feat: memwbregister + tests

FaresAtef1 · Dec 4, 2023 · 80c8ed4 · 80c8ed4
1 parent 7c04663
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diff --git a/MEMWBRegister.vhd b/MEMWBRegister.vhd
@@ -0,0 +1,70 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY MEMWBRegister IS
+    PORT (
+        Clk : IN STD_LOGIC;
+        RST_Reg : IN STD_LOGIC;
+        RTI : IN STD_LOGIC;
+        Register_Write : IN STD_LOGIC;
+        Mem_2PC : IN STD_LOGIC;
+        Mem_2Reg : IN STD_LOGIC;
+        Push_INT_PC : IN STD_LOGIC;
+        Port_Read : IN STD_LOGIC;
+        RST : IN STD_LOGIC;
+        INT : IN STD_LOGIC;
+        Port_Val : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+        Memory_Data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+        ALU_Result : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+        Rdst : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+        -- output ports
+        RTI_Out : OUT STD_LOGIC;
+        Register_Write_Out : OUT STD_LOGIC;
+        Mem_2PC_Out : OUT STD_LOGIC;
+        Mem_2Reg_Out : OUT STD_LOGIC;
+        Push_INT_PC_Out : OUT STD_LOGIC;
+        Port_Read_Out : OUT STD_LOGIC;
+        RST_Out : OUT STD_LOGIC;
+        INT_Out : OUT STD_LOGIC;
+        Port_Val_Out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+        Memory_Data_Out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+        ALU_Result_Out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+        Rdst_Out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
+    );
+
+END MEMWBRegister;
+ARCHITECTURE ArchMEMWBRegister OF MEMWBRegister IS
+BEGIN
+    PROCESS (Clk, RST_Reg)
+    BEGIN
+
+        IF RST_Reg = '1' THEN
+            RTI_Out <= '0';
+            Register_Write_Out <= '0';
+            Mem_2PC_Out <= '0';
+            Mem_2Reg_Out <= '0';
+            Push_INT_PC_Out <= '0';
+            Port_Read_Out <= '0';
+            RST_Out <= '0';
+            INT_Out <= '0';
+            ALU_Result_Out <= (OTHERS => '0');
+            Port_Val_Out<= (OTHERS => '0');
+            Memory_Data_Out <= (OTHERS => '0');
+            Rdst_Out <= (OTHERS => '0');
+        ELSIF RISING_EDGE(Clk) THEN
+            RTI_Out <= RTI;
+            Register_Write_Out <= Register_Write;
+            Mem_2PC_Out <= Mem_2PC;
+            Mem_2Reg_Out <= Mem_2Reg;
+            Push_INT_PC_Out <= Push_INT_PC;
+            Port_Read_Out <= Port_Read;
+            RST_Out <= RST;
+            INT_Out <= INT;
+            ALU_Result_Out <= ALU_Result;
+            Port_Val_Out<= Port_Val;
+            Memory_Data_Out <= Memory_Data;
+            Rdst_Out <= Rdst;
+        END IF;
+    END PROCESS;
+
+END ArchMEMWBRegister;
diff --git a/MEMWBRegisterToDo.do b/MEMWBRegisterToDo.do
@@ -0,0 +1,59 @@
+add wave -position insertpoint  \
+sim:/memwbregister/Clk \
+sim:/memwbregister/RST_Reg \
+sim:/memwbregister/RTI \
+sim:/memwbregister/Register_Write \
+sim:/memwbregister/Mem_2PC \
+sim:/memwbregister/Mem_2Reg \
+sim:/memwbregister/Push_INT_PC \
+sim:/memwbregister/Port_Read \
+sim:/memwbregister/RST \
+sim:/memwbregister/INT \
+sim:/memwbregister/Port_Val \
+sim:/memwbregister/Memory_Data \
+sim:/memwbregister/ALU_Result \
+sim:/memwbregister/Rdst \
+sim:/memwbregister/RTI_Out \
+sim:/memwbregister/Register_Write_Out \
+sim:/memwbregister/Mem_2PC_Out \
+sim:/memwbregister/Mem_2Reg_Out \
+sim:/memwbregister/Push_INT_PC_Out \
+sim:/memwbregister/Port_Read_Out \
+sim:/memwbregister/RST_Out \
+sim:/memwbregister/INT_Out \
+sim:/memwbregister/Port_Val_Out \
+sim:/memwbregister/Memory_Data_Out \
+sim:/memwbregister/ALU_Result_Out \
+sim:/memwbregister/Rdst_Out
+force -freeze sim:/memwbregister/Clk 1 0, 0 {100 ps} -r 200
+force -freeze sim:/memwbregister/RST_Reg 1 0
+run
+force -freeze sim:/memwbregister/RST_Reg 0 0
+force -freeze sim:/memwbregister/RTI 1 0
+force -freeze sim:/memwbregister/Register_Write 0 0
+force -freeze sim:/memwbregister/Mem_2PC 1 0
+force -freeze sim:/memwbregister/Mem_2Reg 0 0
+force -freeze sim:/memwbregister/Push_INT_PC 1 0
+force -freeze sim:/memwbregister/Port_Read 0 0
+force -freeze sim:/memwbregister/RST 1 0
+force -freeze sim:/memwbregister/INT 0 0
+force -freeze sim:/memwbregister/Port_Val 10#20 0
+force -freeze sim:/memwbregister/Memory_Data 10#30 0
+force -freeze sim:/memwbregister/ALU_Result 10#40 0
+force -freeze sim:/memwbregister/Rdst 110 0
+run
+run
+force -freeze sim:/memwbregister/RTI 0 0
+force -freeze sim:/memwbregister/Register_Write 1 0
+force -freeze sim:/memwbregister/Mem_2PC 0 0
+force -freeze sim:/memwbregister/Mem_2Reg 1 0
+force -freeze sim:/memwbregister/Push_INT_PC 0 0
+force -freeze sim:/memwbregister/Port_Read 1 0
+force -freeze sim:/memwbregister/RST 0 0
+force -freeze sim:/memwbregister/INT 1 0
+force -freeze sim:/memwbregister/Port_Val 10#80 0
+force -freeze sim:/memwbregister/Memory_Data 10#90 0
+force -freeze sim:/memwbregister/ALU_Result 10#100 0
+force -freeze sim:/memwbregister/Rdst 001 0
+run
+run