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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,41 @@ | ||
| binaryFile= open("binaryCode.txt",mode="r") | ||
| wavesFile=open("waves.txt",mode="r") | ||
| doFile=open("doFile.txt",mode="w") | ||
| doFile.writelines(["quit -sim","\n","vcom Processor.vhd","\n","vsim -t ns Processor\n"]) | ||
| doFile.writelines([ | ||
| "force -freeze CLK 1 0, 0 {50 ns} -r 100\n", | ||
| "force -freeze PC_Init 1 0 \n", | ||
| "force -freeze Mem_Init 1 0 \n", | ||
| "force -freeze RST_Reg 1 0 \n", | ||
| "force -freeze Init 0 0 \n", | ||
| "force -freeze RST 0 0 \n", | ||
| "force -freeze INT 0 0 \n", | ||
| "force -freeze Port_Input \"1000000100000011\" 0 \n", | ||
| "run 100 ns\n", | ||
| "force -freeze PC_Init 0 0 \n", | ||
| "force -freeze Mem_Init 0 0\n" , | ||
| "run 100 ns\n", | ||
| "force -freeze RST_Reg 0 0 \n", | ||
| "force -freeze Init 1 0 \n" | ||
| ]) | ||
|
|
||
|
|
||
| binaryInstructions=binaryFile.readlines() | ||
| for inst in binaryInstructions: | ||
| doFile.writelines([ | ||
| f"force -freeze IN_Inst \"{inst.strip()}\" 0 ", | ||
| "\n", | ||
| "run 100 ns\n" | ||
| ]) | ||
| waves=wavesFile.readlines() | ||
| doFile.writelines(waves) | ||
| doFile.writelines([ | ||
| "force -freeze PC_Init 1 0 \n", | ||
| "force -freeze Init 0 0 \n", | ||
| "run 100 ns\n" | ||
| "force -freeze PC_Init 0 0 \n", | ||
| ]) | ||
|
|
||
| doFile.writelines([ | ||
| "\n",f"run {100*len(binaryInstructions)} ns" | ||
| ]) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,123 @@ | ||
| add wave -position end sim:/processor/CLK | ||
| add wave -position end sim:/processor/RST | ||
| add wave -position end sim:/processor/INT | ||
| add wave -position end sim:/processor/Init | ||
| add wave -position end sim:/processor/In_Inst | ||
| add wave -position end sim:/processor/PC_Init | ||
| add wave -position end sim:/processor/Mem_Init | ||
| add wave -position end sim:/processor/RST_Reg | ||
| add wave -position end sim:/processor/Port_Input | ||
| add wave -position end sim:/processor/Out_Port_Data | ||
| add wave -position end sim:/processor/RST_Reg_IF | ||
| add wave -position end sim:/processor/INC_PC_IF | ||
| add wave -position end sim:/processor/Immediate_Val_IF | ||
| add wave -position end sim:/processor/Instruction_IF | ||
| add wave -position end sim:/processor/RTI_ID | ||
| add wave -position end sim:/processor/Register_Write_ID | ||
| add wave -position end sim:/processor/Branch_ID | ||
| add wave -position end sim:/processor/Immediate_ID | ||
| add wave -position end sim:/processor/Mem_Read_ID | ||
| add wave -position end sim:/processor/Mem_Write_ID | ||
| add wave -position end sim:/processor/Mem_2Reg_ID | ||
| add wave -position end sim:/processor/Port_Write_ID | ||
| add wave -position end sim:/processor/Port_Read_ID | ||
| add wave -position end sim:/processor/Protect_Write_ID | ||
| add wave -position end sim:/processor/Protect_Val_ID | ||
| add wave -position end sim:/processor/Write_Flag_ID | ||
| add wave -position end sim:/processor/Stack_ID | ||
| add wave -position end sim:/processor/Push_ID | ||
| add wave -position end sim:/processor/Call_ID | ||
| add wave -position end sim:/processor/Mem_2PC_ID | ||
| add wave -position end sim:/processor/Swap_ID | ||
| add wave -position end sim:/processor/RST_ID | ||
| add wave -position end sim:/processor/INT_ID | ||
| add wave -position end sim:/processor/Push_INT_PC_ID | ||
| add wave -position end sim:/processor/Read_Data1_ID | ||
| add wave -position end sim:/processor/Read_Data2_ID | ||
| add wave -position end sim:/processor/INC_PC_ID | ||
| add wave -position end sim:/processor/Op_Code_ID | ||
| add wave -position end sim:/processor/Rdst_ID | ||
| add wave -position end sim:/processor/Rsrc1_ID | ||
| add wave -position end sim:/processor/Rsrc2_ID | ||
| add wave -position end sim:/processor/Inst_Rdst_ID | ||
| add wave -position end sim:/processor/Inst_Rsrc1_ID | ||
| add wave -position end sim:/processor/Inst_Rsrc2_ID | ||
| add wave -position end sim:/processor/Reg0_ID | ||
| add wave -position end sim:/processor/Reg1_ID | ||
| add wave -position end sim:/processor/Reg2_ID | ||
| add wave -position end sim:/processor/Reg3_ID | ||
| add wave -position end sim:/processor/Reg4_ID | ||
| add wave -position end sim:/processor/Reg5_ID | ||
| add wave -position end sim:/processor/Reg6_ID | ||
| add wave -position end sim:/processor/Reg7_ID | ||
| add wave -position end sim:/processor/RTI_EX | ||
| add wave -position end sim:/processor/Register_Write_EX | ||
| add wave -position end sim:/processor/Branch_EX | ||
| add wave -position end sim:/processor/Immediate_EX | ||
| add wave -position end sim:/processor/Mem_Read_EX | ||
| add wave -position end sim:/processor/Mem_Write_EX | ||
| add wave -position end sim:/processor/Mem_2Reg_EX | ||
| add wave -position end sim:/processor/Port_Write_EX | ||
| add wave -position end sim:/processor/Port_Read_EX | ||
| add wave -position end sim:/processor/Protect_Write_EX | ||
| add wave -position end sim:/processor/Write_Flag_EX | ||
| add wave -position end sim:/processor/Stack_EX | ||
| add wave -position end sim:/processor/Push_EX | ||
| add wave -position end sim:/processor/Call_EX | ||
| add wave -position end sim:/processor/Mem_2PC_EX | ||
| add wave -position end sim:/processor/Swap_EX | ||
| add wave -position end sim:/processor/RST_EX | ||
| add wave -position end sim:/processor/INT_EX | ||
| add wave -position end sim:/processor/Push_INT_PC_EX | ||
| add wave -position end sim:/processor/Rdst_EX | ||
| add wave -position end sim:/processor/Rsrc1_EX | ||
| add wave -position end sim:/processor/Rsrc2_EX | ||
| add wave -position end sim:/processor/Flags_EX | ||
| add wave -position end sim:/processor/Read_Data1_EX | ||
| add wave -position end sim:/processor/Read_Data2_EX | ||
| add wave -position end sim:/processor/INC_PC_EX | ||
| add wave -position end sim:/processor/Stack_Pointer_EX | ||
| add wave -position end sim:/processor/ALU_Result_EX | ||
| add wave -position end sim:/processor/Memory_Data_EX | ||
| add wave -position end sim:/processor/Op_Code_EX | ||
| add wave -position end sim:/processor/Protect_Val_EX | ||
| add wave -position end sim:/processor/Protect_State_EX | ||
| add wave -position end sim:/processor/RTI_MEM | ||
| add wave -position end sim:/processor/Register_Write_MEM | ||
| add wave -position end sim:/processor/Mem_2PC_MEM | ||
| add wave -position end sim:/processor/Mem_2Reg_MEM | ||
| add wave -position end sim:/processor/Push_MEM | ||
| add wave -position end sim:/processor/Stack_MEM | ||
| add wave -position end sim:/processor/Push_INT_PC_MEM | ||
| add wave -position end sim:/processor/Call_MEM | ||
| add wave -position end sim:/processor/Mem_Write_MEM | ||
| add wave -position end sim:/processor/Mem_Read_MEM | ||
| add wave -position end sim:/processor/Branch_MEM | ||
| add wave -position end sim:/processor/Port_Write_MEM | ||
| add wave -position end sim:/processor/Port_Read_MEM | ||
| add wave -position end sim:/processor/RST_MEM | ||
| add wave -position end sim:/processor/INT_MEM | ||
| add wave -position end sim:/processor/Protect_State_MEM | ||
| add wave -position end sim:/processor/Stack_Pointer_MEM | ||
| add wave -position end sim:/processor/INC_PC_MEM | ||
| add wave -position end sim:/processor/ALU_Result_MEM | ||
| add wave -position end sim:/processor/Memory_Data_MEM | ||
| add wave -position end sim:/processor/Rdst_MEM | ||
| add wave -position end sim:/processor/Flags_MEM | ||
| add wave -position end sim:/processor/Port_Out | ||
| add wave -position end sim:/processor/Memory_Out | ||
| add wave -position end sim:/processor/Rdst_WB | ||
| add wave -position end sim:/processor/Register_Write_WB | ||
| add wave -position end sim:/processor/RTI_WB | ||
| add wave -position end sim:/processor/INT_WB | ||
| add wave -position end sim:/processor/Push_INT_PC_WB | ||
| add wave -position end sim:/processor/Mem_2PC_WB | ||
| add wave -position end sim:/processor/Mem_2Reg_WB | ||
| add wave -position end sim:/processor/Port_Read_WB | ||
| add wave -position end sim:/processor/RST_WB | ||
| add wave -position end sim:/processor/Memory_Out_WB | ||
| add wave -position end sim:/processor/ALU_Result_WB | ||
| add wave -position end sim:/processor/Port_Out_WB | ||
| add wave -position end sim:/processor/WriteBack_Data | ||
| add wave -position end sim:/processor/EA | ||
| add wave -position end sim:/processor/Immediate_Val_ID |