feat: fetch stage

FaresAtef1 · Dec 3, 2023 · 3207987 · 3207987
1 parent cde42eb
commit 3207987
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Showing 6 changed files with 201 additions and 23 deletions.
diff --git a/FetchStage.vhd b/FetchStage.vhd
@@ -0,0 +1,96 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE std.textio.ALL;
+USE ieee.std_logic_textio.ALL;
+
+ENTITY FetchStage IS
+    PORT (
+        CLK : IN STD_LOGIC;
+        Mem_Out, PC_INC_Decode, PC_INC_Mem, ALU_Res : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- PC_INC is PC + 1 from Decode Stage
+        RDst_Exec : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+        Reset_Mem, Call_Exec, Branch_Exec, Branch_Mem, Mem_2PC, Zero_flag, Init, PC_Init : IN STD_LOGIC;
+        IN_Inst : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+        Inst : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+        Sign_Extend, PC_Inc : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
+END FetchStage;
+
+ARCHITECTURE ArchFetchStage OF FetchStage IS
+    COMPONENT Adder IS
+        GENERIC (n : INTEGER := 8);
+        PORT (
+            First, Second : IN STD_LOGIC_VECTOR(n - 1 DOWNTO 0);
+            CarryIn : STD_LOGIC;
+            Sum : OUT STD_LOGIC_VECTOR(n - 1 DOWNTO 0);
+            CarryOut : OUT STD_LOGIC);
+    END COMPONENT Adder;
+
+    COMPONENT GenericRegister IS
+        GENERIC (
+            Size : INTEGER := 32
+        );
+        PORT (
+            WR_EN : IN STD_LOGIC;
+            RST : IN STD_LOGIC;
+            Data : IN STD_LOGIC_VECTOR(Size - 1 DOWNTO 0);
+            RST_Val : IN STD_LOGIC_VECTOR(Size - 1 DOWNTO 0);
+            Reg_Out : OUT STD_LOGIC_VECTOR(Size - 1 DOWNTO 0)
+        );
+    END COMPONENT GenericRegister;
+
+    COMPONENT PCDecoder IS
+        PORT (
+            Rds : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+            memory : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+            PC_inc : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+            PC_inc_mem : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+            call : IN STD_LOGIC;
+            Zero_Flag : IN STD_LOGIC;
+            mem_to_PC : IN STD_LOGIC;
+            branch : IN STD_LOGIC;
+            prev_branch : IN STD_LOGIC;
+            PC_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
+    END COMPONENT PCDecoder;
+
+    COMPONENT Memory IS
+        GENERIC (
+            bus_width : INTEGER := 16;
+            address_width : INTEGER := 12;
+            slot_width : INTEGER := 16
+        );
+        PORT (
+            RST : IN STD_LOGIC;
+            WR_EN : IN STD_LOGIC;
+            RD_EN : IN STD_LOGIC;
+            Address : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
+            Write_Data : IN STD_LOGIC_VECTOR (bus_width - 1 DOWNTO 0);
+            Read_Data : OUT STD_LOGIC_VECTOR (bus_width - 1 DOWNTO 0));
+    END COMPONENT Memory;
+
+    COMPONENT SignExtend IS
+        PORT (
+            data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+            data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
+    END COMPONENT SignExtend;
+
+    SIGNAL PC : STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SIGNAL PC_Decoder_Out : STD_LOGIC_VECTOR(31 DOWNTO 0);
+    SIGNAL Inst_SIG : STD_LOGIC_VECTOR(15 DOWNTO 0);
+    SIGNAL NOT_Init : STD_LOGIC;
+    SIGNAL NOT_CLK : STD_LOGIC;
+BEGIN
+    NOT_CLK <= NOT CLK;
+    PCD0 : PCDecoder PORT MAP(RDst_Exec, Mem_Out, PC_INC_Decode, PC_INC_Mem, Call_Exec, Zero_flag, Mem_2PC, Branch_Exec, Branch_Mem, PC_Decoder_Out);
+    PC0 : GenericRegister GENERIC MAP(32) PORT MAP('1', PC_Init, PC_Decoder_Out, x"00000000", PC);
+    NOT_Init <= NOT Init;
+    Inst_Mem : Memory GENERIC MAP(
+        bus_width => 16,
+        address_width => 12,
+        slot_width => 16
+    )
+    PORT MAP(Reset_Mem, NOT_CLK, NOT_Init, PC(11 DOWNTO 0), IN_Inst, Inst_SIG);
+    Inst <= Inst_SIG;
+    SE0 : SignExtend PORT MAP(Inst_SIG, Sign_Extend);
+    A0 : Adder GENERIC MAP(32) PORT MAP(PC, X"00000001", '0', PC_Inc, OPEN);
+
+END ArchFetchStage;
diff --git a/FetchStageDo.do b/FetchStageDo.do
@@ -0,0 +1,88 @@
+quit -sim
+vcom FetchStage.vhd
+vsim -t ns FetchStage
+# INPUTS
+add wave -color yellow CLK Mem_Out PC_INC_Decode PC_INC_Mem ALU_Res RDst_Exec Reset_Mem Call_Exec Branch_Exec Branch_Mem Mem_2PC Zero_flag Init PC_Init IN_Inst
+# OUTPUTS
+add wave -color cyan Inst Sign_Extend PC_Inc
+
+# Apply inputs for a specific duration
+force -freeze IN_Inst x"00000001" 0 
+force -freeze PC_Init 0 0 
+force -freeze Init 1 0 
+force -freeze Zero_flag 0 0 
+force -freeze Mem_2PC 0 0 
+force -freeze Branch_Mem 0 0 
+force -freeze Branch_Exec x"0" 0 
+force -freeze Call_Exec x"0" 0 
+force -freeze Reset_Mem x"0" 0 
+force -freeze RDst_Exec x"00000000" 0 
+force -freeze ALU_Res x"00000000" 0 
+force -freeze PC_INC_Mem x"0000000c" 0 
+force -freeze PC_INC_Decode x"00000000" 0 
+force -freeze Mem_Out x"00000000" 0 
+force -freeze CLK 1 0, 0 {50 ns} -r 100
+run 100 ns
+force -freeze PC_INC_Decode x"00000001" 0 
+force -freeze IN_Inst x"00000002" 0 
+
+run 100 ns
+force -freeze PC_INC_Decode x"00000002" 0 
+force -freeze IN_Inst x"00000003" 0 
+
+run 100 ns
+force -freeze PC_INC_Decode x"00000003" 0 
+force -freeze IN_Inst x"00000004" 0 
+
+run 100 ns
+force -freeze Init 0 0 
+force -freeze PC_INC_Decode x"00000000" 0 
+
+run 100 ns
+force -freeze PC_INC_Decode x"00000001" 0 
+
+run 100 ns
+force -freeze Init 0 0 
+force -freeze PC_INC_Decode x"00000002" 0 
+
+run 100 ns
+force -freeze Init 0 0 
+force -freeze PC_INC_Decode x"00000003" 0 
+run 100 ns
+
+force -freeze Init 1 0 
+force -freeze PC_INC_Decode x"0000000b" 0 
+force -freeze IN_Inst x"0000000b" 0 
+
+run 100 ns
+force -freeze PC_INC_Decode x"0000000c" 0 
+force -freeze IN_Inst x"0000000c" 0 
+
+run 100 ns
+
+force -freeze PC_INC_Decode x"0000000d" 0 
+force -freeze IN_Inst x"0000000d" 0 
+force -freeze RDst_Exec x"0000000b" 0 
+run 100 ns
+
+force -freeze Init 0 0 
+force -freeze Call_Exec x"1" 0 
+run 100 ns
+
+force -freeze Call_Exec x"0" 0 
+force -freeze PC_INC_Decode x"000000c" 0 
+run 100 ns
+
+force -freeze PC_INC_Decode x"000000d" 0 
+run 100 ns
+
+force -freeze Branch_Exec 1 0 
+run 100 ns
+
+force -freeze Branch_Exec 0 0 
+force -freeze Mem_2PC 1 0 
+run 100 ns
+
+force -freeze Mem_2PC 0 0 
+force -freeze Branch_Mem 1 0
+run 100 ns
diff --git a/FullAdder.vhd b/FullAdder.vhd
@@ -1,20 +1,16 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
 
-ENTITY FullAdder is 
-	port(A,B,C: IN Std_logic;S,Cout:OUT std_logic);
+ENTITY FullAdder IS
+	PORT (
+		A, B, C : IN STD_LOGIC;
+		S, Cout : OUT STD_LOGIC);
 END ENTITY FullAdder;
-
-
-ARCHITECTURE Arch of FullAdder is
-Signal s1:std_logic;
-begin
+ARCHITECTURE Arch OF FullAdder IS
+	SIGNAL s1 : STD_LOGIC;
+BEGIN
 	s1 <= A XOR B;
 	S <= s1 XOR C;
-	Cout <= (A AND B) XOR (s1 AND C );
-
-
-
-
+	Cout <= (A AND B) XOR (s1 AND C);
 
-end Arch;
+END Arch;
diff --git a/Register.vhd → GenericRegister.vhd b/Register.vhd → GenericRegister.vhd
@@ -9,16 +9,14 @@ ENTITY GenericRegister IS
         WR_EN : IN STD_LOGIC;
         RST : IN STD_LOGIC;
         Data : IN STD_LOGIC_VECTOR(Size - 1 DOWNTO 0);
-        RST_Val : IN STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
+        RST_Val : IN STD_LOGIC_VECTOR(Size - 1 DOWNTO 0);
         Reg_Out : OUT STD_LOGIC_VECTOR(Size - 1 DOWNTO 0)
     );
-
 END GenericRegister;
 
 ARCHITECTURE ArchGenericRegister OF GenericRegister IS
 BEGIN
-Reg_Out <= 
-            RST_Val WHEN RST='1' ELSE
-            Data WHEN WR_EN='1' ;
-
+    Reg_Out <=
+        RST_Val WHEN RST = '1' ELSE
+        Data WHEN WR_EN = '1';
 END ArchGenericRegister;
diff --git a/Memory.vhd b/Memory.vhd
@@ -27,7 +27,7 @@ BEGIN
     PROCESS (WR_EN, RD_EN, Address, Write_Data, RST)
     BEGIN
         IF RST = '1' THEN
-            MemoryArray <= (OTHERS => (OTHERS => '0')); ----------- Zero not U
+            MemoryArray <= (OTHERS => (OTHERS => '0'));
         END IF;
         IF RD_EN = '1' THEN
             rddata : FOR i IN 0 TO (bus_width/slot_width - 1) LOOP

diff --git a/PCDecoder.vhd b/PCDecoder.vhd
@@ -21,7 +21,7 @@ END PCDecoder;
 
 ARCHITECTURE PCDecoderArch OF PCDecoder IS
 BEGIN
-    PROCESS (Rds, PC_inc_mem, memory, PC_inc, call, mem_to_PC, branch, prev_branch)
+    PROCESS (Rds, PC_inc_mem, memory, PC_inc, call, mem_to_PC, branch, prev_branch, Zero_Flag)
     BEGIN
         IF (call = '1') OR (branch = '1') THEN
             PC_out <= Rds;