Updated documentation.

core/ir/encode_api.h

@@ -51,8 +51,38 @@ typedef enum _dr_isa_mode_t {
     DR_ISA_ARM_THUMB,         /**< Thumb (ARM T32). */
     DR_ISA_ARM_A64,           /**< ARM A64 (AArch64). */
     DR_ISA_RV64IMAFDC,        /**< RISC-V (rv64imafdc). */
-    DR_ISA_REGDEPS,           /**< Synthetic ISA for storing
-                                  only register dependencies. */
+    DR_ISA_REGDEPS,
+    /**<
+     * This is a synthetic ISA that has the purpose of preserving register dependencies
+     * and giving hints on the type of operations each instruction is performing.
+     *
+     * For this reason the majority of operations that would normally work on instructions
+     * coming from an actual ISA (e.g., #DR_ISA_AMD64) are not supported.
+     *
+     * Currently we support:
+     * - instr_convert_to_isa_regdeps(), which converts an #instr_t of an actual ISA to a
+     *   #DR_ISA_REGDEPS instruction;
+     * - instr_encode() and instr_encode_to_copy(), to encode an #DR_ISA_REGDEPS #instr_t
+     *   into a sequence of contiguous bytes;
+     * - decode() and decode_from_copy(), to decode an encoded #DR_ISA_REGDEPS instruction
+     *   into an #instr_t.
+     *
+     * A #DR_ISA_REGDEPS #instr_t holds only the encoded information described in the
+     * encoding scheme, which is:
+     * - categories (from #dr_instr_category_t), to indicate the type of operation
+     *   performed (e.g., load, store, floating point math operation, branch, etc.);
+     * - arithmetic flags, with no distinction between different flags, we only report if
+     *   at least one flag was read and/or written;
+     * - number of source and destination register operands;
+     * - operation size;
+     * - list of register operand identifiers, separated in source and destination;
+     * - ISA mode, which is #DR_ISA_REGDEPS.
+     *
+     * Querying additional information (e.g., the instruction opcode) will return the
+     * default value generated by how the instruction was created.  If instr_create() was
+     * used, then zero will be returned.  If the #instr_t was allocated on the stack, then
+     * all values not described above are undefined.
+     */
 } dr_isa_mode_t;
 
 DR_API

core/ir/instr_api.h

@@ -2107,8 +2107,8 @@ DR_API
  * instr_create()).
  * Assumes \p instr_real_isa is a fully-decoded or synthesized instruction of a real ISA
  * with valid operand information.
- * \note \p instr_regdeps_isa will contain the information of a #DR_ISA_REGDEPS synthetic
- * instruction described in #core/ir/isa_regdeps/encoding_common.h.
+ * \note \p instr_regdeps_isa will contain only the information of a #DR_ISA_REGDEPS
+ * synthetic instruction.
  */
 void
 instr_convert_to_isa_regdeps(void *drcontext, instr_t *instr_real_isa,

core/ir/isa_regdeps/encoding_common.h

@@ -33,39 +33,6 @@
 #ifndef _REGDEPS_ENCODING_COMMON_H_
 #define _REGDEPS_ENCODING_COMMON_H_
 
-/**
- * This synthetic ISA (which we call #DR_ISA_REGDEPS) is a made up ISA that has the
- * purpose of preserving register dependencies and giving hints on the type of operations
- * each instruction is performing.
- *
- * For this reason the majority of operations that would normally work on instructions
- * coming from an actual ISA (e.g., #DR_ISA_AMD64) are not supported.
- *
- * Currently we support:
- * - instr_convert_to_isa_regdeps(), which converts an #instr_t of an actual ISA to a
- *   #DR_ISA_REGDEPS instruction;
- * - instr_encode() and instr_encode_to_copy(), to encode an #DR_ISA_REGDEPS #instr_t into
- *   a sequence of contiguous bytes;
- * - decode() and decode_from_copy(), to decode an encoded #DR_ISA_REGDEPS instruction
- *   into an #instr_t.
- *
- * An #DR_ISA_REGDEPS #instr_t holds only the encoded information described in the
- * encoding scheme (see #core/ir/isa_regdeps/encoding_common.h), which is:
- * - categories (from #dr_category_t), to indicate the type of operation performed (e.g.,
- *   a load, a math operation, a floating point math operation, a branch, etc.);
- * - arithmetic flags, with no distinction between different flags, we only report if at
- *   least one flag was read and/or written;
- * - number of source and destination register operands;
- * - operation size;
- * - list of register operand identifiers, separated in source and destination;
- * - ISA mode, which is #DR_ISA_REGDEPS.
- *
- * Querying additional information (e.g., the instruction opcode) will return the default
- * value generated by how the instruction was created.  If instr_create() was used, then
- * zero will be returned.  If the #instr_t was allocated on the stack, then all values not
- * described above are undefined.
- */
-
 /* Here we describe the encoding scheme for the Synthetic ISA that is enforced in decode.c
  * and encode.c.
  *