i#2626 AArch64: Add register FPMR.

FPMR is present only when FEAT_FPMR is implemented. It is then
part of the user-mode execution state and controls the behaviour
of instructions that operate on 8-bit floating-point values.

DR_REG_FPMR is added at the end of the DR_REG_ enum to improve
ABI compatibility.

Change-Id: Ife0bc0239d029ca3f83fe7d6b5ecbbaceebfac5f

core/ir/aarch64/codec.c

@@ -298,6 +298,7 @@ decode_sysreg(uint imm15)
     case 0x5a10: sysreg = DR_REG_NZCV; break;
     case 0x5a20: sysreg = DR_REG_FPCR; break;
     case 0x5a21: sysreg = DR_REG_FPSR; break;
+    case 0x5a22: sysreg = DR_REG_FPMR; break;
     case 0x1808: sysreg = DR_REG_MDCCSR_EL0; break;
     case 0x1820: sysreg = DR_REG_DBGDTR_EL0; break;
     case 0x1828: sysreg = DR_REG_DBGDTRRX_EL0; break;
@@ -433,6 +434,7 @@ encode_sysreg(OUT uint *imm15, opnd_t opnd)
         case DR_REG_NZCV: *imm15 = 0x5a10; break;
         case DR_REG_FPCR: *imm15 = 0x5a20; break;
         case DR_REG_FPSR: *imm15 = 0x5a21; break;
+        case DR_REG_FPMR: *imm15 = 0x5a22; break;
         case DR_REG_MDCCSR_EL0: *imm15 = 0x1808; break;
         case DR_REG_DBGDTR_EL0: *imm15 = 0x1820; break;
         case DR_REG_DBGDTRRX_EL0: *imm15 = 0x1828; break;

core/ir/aarch64/encode.c

@@ -121,6 +121,8 @@ const char *const reg_names[] = {
     "cntvct_el0", "id_aa64isar0_el1", "id_aa64isar1_el1", "id_aa64isar2_el1",
     "id_aa64pfr0_el1", "id_aa64mmfr1_el1", "id_aa64dfr0_el1", "id_aa64zfr0_el1",
     "id_aa64pfr1_el1", "id_aa64mmfr2_el1", "midr_el1", "mpidr_el1", "revidr_el1",
+
+    "fpmr",
 };
 
 
@@ -200,6 +202,8 @@ const reg_id_t dr_reg_fixer[] = { REG_NULL,
     DR_REG_ID_AA64ISAR2_EL1, DR_REG_ID_AA64PFR0_EL1, DR_REG_ID_AA64MMFR1_EL1,
     DR_REG_ID_AA64DFR0_EL1, DR_REG_ID_AA64ZFR0_EL1, DR_REG_ID_AA64PFR1_EL1,
     DR_REG_ID_AA64MMFR2_EL1, DR_REG_MIDR_EL1, DR_REG_MPIDR_EL1, DR_REG_REVIDR_EL1,
+
+    DR_REG_FPMR,
 };
 
 /* Maps real ISA registers to their corresponding virtual DR_ISA_REGDEPS register.
@@ -386,6 +390,8 @@ const reg_id_t d_r_reg_id_to_virtual[] = {
     DR_REG_VIRT206, /* DR_REG_MIDR_EL1 */
     DR_REG_VIRT207, /* DR_REG_MPIDR_EL1 */
     DR_REG_VIRT208, /* DR_REG_REVIDR_EL1 */
+
+    DR_REG_VIRT209, /* DR_REG_FPMR */
 };
 /* clang-format on */
 

core/ir/opnd_api.h

@@ -1059,6 +1059,7 @@ enum {
     DR_REG_MIDR_EL1,         /**< The "midr_el1" register. */
     DR_REG_MPIDR_EL1,        /**< The "mpidr_el1" register. */
     DR_REG_REVIDR_EL1,       /**< The "revidr_el1" register. */
+    DR_REG_FPMR,             /**< The "fpmr" register. */
 #    endif
 
 /* Aliases below here: */
@@ -1115,12 +1116,12 @@ enum {
     /** Thread Pointer/ID Register, Read-Only, EL0. */
     DR_REG_TPIDRRO_EL0 = DR_REG_TPIDRURO,
     /* ARMv7 Thread Registers */
-    DR_REG_CP15_C13_2 = DR_REG_TPIDRURW,        /**< User Read/Write Thread ID Register */
-    DR_REG_CP15_C13_3 = DR_REG_TPIDRURO,        /**< User Read-Only Thread ID Register */
+    DR_REG_CP15_C13_2 = DR_REG_TPIDRURW,  /**< User Read/Write Thread ID Register */
+    DR_REG_CP15_C13_3 = DR_REG_TPIDRURO,  /**< User Read-Only Thread ID Register */
 
 #    ifdef AARCH64
-    DR_REG_LAST_VALID_ENUM = DR_REG_REVIDR_EL1, /**< Last valid register enum */
-    DR_REG_LAST_ENUM = DR_REG_REVIDR_EL1,       /**< Last value of register enums */
+    DR_REG_LAST_VALID_ENUM = DR_REG_FPMR, /**< Last valid register enum */
+    DR_REG_LAST_ENUM = DR_REG_FPMR,       /**< Last value of register enums */
 #    else
     DR_REG_LAST_VALID_ENUM = DR_REG_TPIDRURO, /**< Last valid register enum */
     DR_REG_LAST_ENUM = DR_REG_TPIDRURO,       /**< Last value of register enums */

core/ir/opnd_shared.c

@@ -2780,7 +2780,7 @@ reg_get_size(reg_id_t reg)
     }
     if ((reg >= DR_REG_P0 && reg <= DR_REG_P15) || reg == DR_REG_FFR)
         return OPSZ_SVE_PREDLEN_BYTES;
-    if (reg >= DR_REG_CNTVCT_EL0 && reg <= DR_REG_REVIDR_EL1)
+    if (reg >= DR_REG_CNTVCT_EL0 && reg <= DR_REG_FPMR)
         return OPSZ_8;
     if (reg >= DR_REG_NZCV && reg <= DR_REG_FPSR)
         return OPSZ_8;

suite/tests/api/dis-a64.txt

@@ -31619,6 +31619,7 @@ d53b4201 : mrs    x1, nzcv                : mrs    %nzcv -> %x1
 d53b4402 : mrs    x2, fpcr                : mrs    %fpcr -> %x2
 d53b4423 : mrs    x3, fpsr                : mrs    %fpsr -> %x3
 d53bd044 : mrs    x4, tpidr_el0           : mrs    %tpidr_el0 -> %x4
+d53b4445 : mrs    x5, fpmr                : mrs    %fpmr -> %x5
 d53fffff : mrs    xzr, s3_7_c15_c15_7     : mrs    $0x7fff -> %xzr
 
 # MRS     <Xt>, #<imm> (MRS-R.I-RS_system)
@@ -31741,6 +31742,7 @@ d5380740 : mrs x0, id_aa64mmfr2_el1                  : mrs    %id_aa64mmfr2_el1
 d5380000 : mrs x0, midr_el1                          : mrs    %midr_el1 -> %x0
 d53800a0 : mrs x0, mpidr_el1                         : mrs    %mpidr_el1 -> %x0
 d53800c0 : mrs x0, revidr_el1                        : mrs    %revidr_el1 -> %x0
+d53b4440 : mrs x0, fpmr                              : mrs    %fpmr -> %x0
 
 # MSR     <cond>, #<imm> (MSR-I-SI_system)
 d50040bf : msr SPSel, #0x0                           : msr    %spsel $0x00
@@ -31772,6 +31774,7 @@ d51b4201 : msr    nzcv, x1                : msr    %x1 -> %nzcv
 d51b4402 : msr    fpcr, x2                : msr    %x2 -> %fpcr
 d51b4423 : msr    fpsr, x3                : msr    %x3 -> %fpsr
 d51bd044 : msr    tpidr_el0, x4           : msr    %x4 -> %tpidr_el0
+d51b4445 : msr    fpmr, x5                : msr    %x5 -> %fpmr
 d51fffff : msr    s3_7_c15_c15_7, xzr     : msr    %xzr $0x7fff
 
 # MSR     #<imm>, <Xt> (MSR-I.R-SR_system)
@@ -31789,6 +31792,7 @@ d51b4204 : msr nzcv, x4                              : msr    %x4 -> %nzcv
 d51b4224 : msr daif, x4                              : msr    %x4 -> %daif
 d51b4404 : msr fpcr, x4                              : msr    %x4 -> %fpcr
 d51b4425 : msr fpsr, x5                              : msr    %x5 -> %fpsr
+d51b4445 : msr fpmr, x5                              : msr    %x5 -> %fpmr
 d51b4505 : msr dspsr_el0, x5                         : msr    %x5 -> %dspsr_el0
 d51b4525 : msr dlr_el0, x5                           : msr    %x5 -> %dlr_el0
 d51b9c05 : msr pmcr_el0, x5                          : msr    %x5 -> %pmcr_el0