Skip to content

Commit

Permalink
Add linear and sinc a96
Browse files Browse the repository at this point in the history
  • Loading branch information
DrPeaboss committed Oct 17, 2024
1 parent b1aa810 commit 2946548
Showing 1 changed file with 81 additions and 31 deletions.
112 changes: 81 additions & 31 deletions benches/bench1.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
use simple_src::{sinc::Manager, Convert};
use simple_src::{linear, sinc, Convert};

fn main() {
divan::main();
Expand Down Expand Up @@ -26,6 +26,15 @@ impl ToString for Conv {
}
}

const R44K48K: f64 = 48000.0 / 44100.0;
const R44K96K: f64 = 96000.0 / 44100.0;
const R48K44K: f64 = 44100.0 / 48000.0;
const R48K96K: f64 = 2.0;
const R96K44K: f64 = 44100.0 / 96000.0;
const R96K48K: f64 = 0.5;
const TRANS44K: f64 = 2050.0 / 22050.0;
const TRANS48K: f64 = 4000.0 / 24000.0;

impl Conv {
fn sample_num_10ms(&self) -> usize {
match self {
Expand All @@ -34,31 +43,76 @@ impl Conv {
_ => 960,
}
}

fn ratio(&self) -> f64 {
match self {
Conv::C44k48k => R44K48K,
Conv::C44k96k => R44K96K,
Conv::C48k44k => R48K44K,
Conv::C48k96k => R48K96K,
Conv::C96k44k => R96K44K,
Conv::C96k48k => R96K48K,
}
}

fn trans_width(&self) -> f64 {
match self {
Conv::C48k96k | Conv::C96k48k => TRANS48K,
_ => TRANS44K,
}
}
}

const R44K48K: f64 = 48000.0 / 44100.0;
const R44K96K: f64 = 96000.0 / 44100.0;
const R48K44K: f64 = 44100.0 / 48000.0;
const R48K96K: f64 = 2.0;
const R96K44K: f64 = 44100.0 / 96000.0;
const R96K48K: f64 = 0.5;
const TRANS44K: f64 = 2050.0 / 22050.0;
const TRANS48K: f64 = 4000.0 / 24000.0;
#[divan::bench(
name="0. linear 1s",
args=[Conv::C44k48k, Conv::C44k96k, Conv::C48k44k, Conv::C48k96k, Conv::C96k44k, Conv::C96k48k],
sample_count=1000,
)]
fn linear_1s(bencher: divan::Bencher, conv: &Conv) {
let manager = linear::Manager::new(conv.ratio()).unwrap();
let sample_num = conv.sample_num_10ms() * 100;
bencher.bench_local(move || {
let iter = (0..).map(|x| x as f64).into_iter();
for s in manager.converter().process(iter).take(sample_num) {
divan::black_box(s);
}
})
}

#[divan::bench(
name="1. init a96",
args=[Conv::C44k48k, Conv::C44k96k, Conv::C48k44k, Conv::C48k96k, Conv::C96k44k, Conv::C96k48k]
)]
fn init_a96(conv: &Conv) -> sinc::Manager {
sinc::Manager::new(conv.ratio(), 96.0, 128, conv.trans_width()).unwrap()
}

#[divan::bench(
name="1. proc a96 10ms",
args=[Conv::C44k48k, Conv::C44k96k, Conv::C48k44k, Conv::C48k96k, Conv::C96k44k, Conv::C96k48k],
sample_count=1000,
)]
fn proc_a96_10ms(bencher: divan::Bencher, conv: &Conv) {
let manager = init_a96(conv);
let sample_num = conv.sample_num_10ms();
bencher.bench_local(move || {
let iter = (0..).map(|x| x as f64).into_iter();
for s in manager.converter().process(iter).take(sample_num) {
divan::black_box(s);
}
})
}

#[divan::bench(args=[Conv::C44k48k, Conv::C44k96k, Conv::C48k44k, Conv::C48k96k, Conv::C96k44k, Conv::C96k48k])]
fn init_a120(conv: &Conv) -> Manager {
let m = match conv {
Conv::C44k48k => Manager::new(R44K48K, 120.0, 512, TRANS44K),
Conv::C44k96k => Manager::new(R44K96K, 120.0, 512, TRANS44K),
Conv::C48k44k => Manager::new(R48K44K, 120.0, 512, TRANS44K),
Conv::C48k96k => Manager::new(R48K96K, 120.0, 512, TRANS48K),
Conv::C96k44k => Manager::new(R96K44K, 120.0, 512, TRANS44K),
Conv::C96k48k => Manager::new(R96K48K, 120.0, 512, TRANS48K),
};
m.unwrap()
#[divan::bench(
name="2. init a120",
args=[Conv::C44k48k, Conv::C44k96k, Conv::C48k44k, Conv::C48k96k, Conv::C96k44k, Conv::C96k48k]
)]
fn init_a120(conv: &Conv) -> sinc::Manager {
sinc::Manager::new(conv.ratio(), 120.0, 512, conv.trans_width()).unwrap()
}

#[divan::bench(
name="2. proc a120 10ms",
args=[Conv::C44k48k, Conv::C44k96k, Conv::C48k44k, Conv::C48k96k, Conv::C96k44k, Conv::C96k48k],
sample_count=1000,
)]
Expand All @@ -73,20 +127,16 @@ fn proc_a120_10ms(bencher: divan::Bencher, conv: &Conv) {
})
}

#[divan::bench(args=[Conv::C44k48k, Conv::C44k96k, Conv::C48k44k, Conv::C48k96k, Conv::C96k44k, Conv::C96k48k])]
fn init_a144(conv: &Conv) -> Manager {
let m = match conv {
Conv::C44k48k => Manager::new(R44K48K, 144.0, 2048, TRANS44K),
Conv::C44k96k => Manager::new(R44K96K, 144.0, 2048, TRANS44K),
Conv::C48k44k => Manager::new(R48K44K, 144.0, 2048, TRANS44K),
Conv::C48k96k => Manager::new(R48K96K, 144.0, 2048, TRANS48K),
Conv::C96k44k => Manager::new(R96K44K, 144.0, 2048, TRANS44K),
Conv::C96k48k => Manager::new(R96K48K, 144.0, 2048, TRANS48K),
};
m.unwrap()
#[divan::bench(
name="3. init a144",
args=[Conv::C44k48k, Conv::C44k96k, Conv::C48k44k, Conv::C48k96k, Conv::C96k44k, Conv::C96k48k]
)]
fn init_a144(conv: &Conv) -> sinc::Manager {
sinc::Manager::new(conv.ratio(), 144.0, 2048, conv.trans_width()).unwrap()
}

#[divan::bench(
name="3. proc a144 10ms",
args=[Conv::C44k48k, Conv::C44k96k, Conv::C48k44k, Conv::C48k96k, Conv::C96k44k, Conv::C96k48k],
sample_count=1000,
)]
Expand Down

0 comments on commit 2946548

Please sign in to comment.