10 Bit Potentiometric DAC using 28nm Technology (Synopsys Custom Compiler)

This project aims to deal with a 10 Bit Potentiometric DAC (Digital to Analog Converter) using Synopsys Custom Compiler Tool with a typical Digital Power Supply (VDD) of 1.05V and a typical Analog Voltage Supply (VDDA) of 1.8V using SAED_PDK 28_32nm Technology node.

Table of Contents

• Introduction
• Pre Layout Simulations
  • Tools used
  • Switch
  • 2 bit DAC
  • 3 bit DAC
  • 4 bit DAC
  • 5 bit DAC
  • 6 bit DAC
  • 7 bit DAC
  • 8 bit DAC
  • 9 bit DAC
  • 10 bit DAC
• Results
• Layout
  • Switch Layout
  • 2bit DAC
  • 3bit DAC
  • 4bit DAC
  • 5bit DAC
  • 6bit DAC
  • 7bit DAC
  • 8bit DAC
  • 9bit DAC
  • 10bit DAC
• Future Works
• Contributors
• Acknowledgements
• References

Introduction

• A Digital to Analog Converter (DAC) converts a digital input signal into an analog output signal. The digital signal is represented with a binary code, which is a combination of bits 0 and 1. A Digital to Analog Converter (DAC) consists of a number of binary inputs and a single output. In general, the number of binary inputs of a DAC will be a power of two.

• There are two types of DACs :

  1. Weighted Resistor DAC
  2. R-2R Ladder DAC

Weighted Resistor DAC

• A weighted resistor DAC produces an analog output, which is almost equal to the digital (binary) input by using binary weighted resistors in the inverting adder circuit. In short, a binary weighted resistor DAC is called as weighted resistor DAC.
• The circuit diagram of a 3-bit binary weighted resistor DAC is shown in the following figure :

R-2R Ladder DAC

• The R-2R Ladder DAC overcomes the disadvantages of a binary weighted resistor DAC. As the name suggests, R-2R Ladder DAC produces an analog output, which is almost equal to the digital (binary) input by using a R-2R ladder network in the inverting adder circuit.
• The circuit diagramof a 3-bit R-2R Ladder DAC is shown in the following figure :

• For more information you may wish to visit : Link

Architecture

• The basic idea is to divide the voltage into N different voltage values in the range of VREFH and VREFL- for an N-Bit DAC.
• The design used here to achieve this is the simple resistor string DAC which consists of resistors in series.
• These resistors are then connected to various switches in such a fashion that it routes the exact voltage to the output.
• The problem of the largeness of the circuit is reduced by building hierarchical subcircuits of 10-Bit potentiometric DAC – Switch, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, 7-bit, 8-bit, 9-bit and 10-bit.

Specifications to be met

Pre Layout Simulations

Tools used

• The tools used for the circuit simulations are:

1. Schematic Design : Custom Compiler
2. Symbol Creation : Custom Compiler
3. Simulation : PrimeSim

Switch

• Switching circuits or gates are circuits that perform well-defined logic or arithmetic operations on binary variables.
• Binary variables are two-valued variables expressed as 1's or 0's in algebraic form, or true or false in syllogistic forms, or as high or low voltage, positive or negative remanence (magnetic flux), etc., in circuit forms.
• Circuit switching refers to the mechanism of communications in which a dedicated path with allocated bandwidth is set up on an on-demand basis before the actual communication can take place.

Switch Schematic

Switch Symbol

Switch testbench

Switch Waveform

2 Bit DAC

2 Bit DAC is implemented using 2 switch instances and resistors.

Schematic

Symbol

Testbench

Waveform

3 Bit DAC

3Bit DAC is implemented using 2 2-Bit DACs and 1 switch instance.

Schematic

Symbol

Testbench

Waveform

4 Bit DAC

4Bit DAC is implemented using 2 3-Bit DACs and 1 switch instance.

Schematic

Symbol

Testbench

Waveform

5 Bit DAC

5Bit DAC is implemented using 2 4-Bit DACs and 1 switch instance.

Schematic

Symbol

Testbench

Waveform

6 Bit DAC

6Bit DAC is implemented using 2 5-Bit DACs and 1 switch instance.

Schematic

Symbol

Testbench

Waveform

7 Bit DAC

7Bit DAC is implemented using 2 6-Bit DACs and 1 switch instance.

Schematic

Symbol

Testbench

Waveform

8 Bit DAC

8Bit DAC is implemented using 2 7-Bit DACs and 1 switch instance.

Schematic

Symbol

Testbench

Waveform

9 Bit DAC

9Bit DAC is implemented using 2 8-Bit DACs and 1 switch instance.

Schematic

Symbol

Testbench

Waveform

10 Bit DAC

10Bit DAC is implemented using 2 9-Bit DACs and 1 switch instance.

Schematic

Symbol

Testbench

Waveform

Results

Switch Components and it's value :

Name	Value
D_in	v1 = 0V, v2 = 1.05V, u = 0.1us
Capacitor	1pf
VDDA	1.8V
VSSA	0V
VREFH	1.2V
VREFL	0.8V

2 Bit DAC :

Name	Value
D0, D1	v1 = 0V, v2 = 1.05V, u = 0.1us
Resistor	200ohms
Capacitor	5pf
VDDA	1.8V
VSSA	0V
VREFH	1.8V
VREFL	0V

NOTE :

• For 3 Bit DAC : D0, D1 and D2; For 4 Bit DAC : D0, D1, D2 and D3 and so on.
• For 10 Bit DAC : D0, D1, D2...., D10.
• Other Inputs value remains the same as 2 Bit DAC until 10 Bit DAC.
• For 2 Bit DAC, Number of steps in the output graph = 2^N, i.e, 2^2 = 4 steps.... and so on.
• For a 10 Bit DAC, Number of steps in the output graph = 2^N, i.e, 2^10 = 1024 steps.
• The graph value for DAC ranges from VrefH (1.8V) to VrefL (0V).

Layout

Switch Layout

2Bit DAC

3Bit DAC

4Bit DAC

5Bit DAC

6Bit DAC

7Bit DAC

8Bit DAC

9Bit DAC

10Bit DAC

10.bit.dac.mp4

Future Works

• Need to understand and start with the Layout process.

Contributors

• A Devipriya , B.E (Electronics and Communication Engineering), Bangalore - [email protected]

Acknowledgements

• Kunal Ghosh, Co-Founder of VLSI System Design (VSD) Corp. Pvt. Ltd. - [email protected]
• Muthukrishnan Chinnasamy and Montu Makadia, Semiconductor Fabless Accelerator Lab (SFAL)

References

• Sameer S Durgoji : Link
• Shalini Kanna : Link
• S Skandha Deepsita : Link