mainboard/clevo/adl-p: Enable PCH UART

Fix incorrect native function of PCH UART0 pads. Signed-off-by: Michał Żygowski <[email protected]>
Dasharo · Dec 3, 2024 · 2d4897f · 2d4897f
1 parent 0911762
commit 2d4897f
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Showing 4 changed files with 11 additions and 6 deletions.
diff --git a/src/mainboard/clevo/adl-p/devicetree.cb b/src/mainboard/clevo/adl-p/devicetree.cb
@@ -77,6 +77,9 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
+		device ref uart0 on # BIOS Debug Port
+			register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoPci"
+		end
 		device ref i2c0 on
 			# Touchpad I2C bus
 			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"

diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/gpio.c b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio.c
@@ -419,12 +419,14 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_H10 - GPIO */
 	/* DW0: 0x44000102, DW1: 0x00000000 */
 	/* DW0: (1 << 1) - IGNORED */
-	PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, DEEP, OFF, ACPI),
+	/* PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, DEEP, OFF, ACPI), */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0_RXD */
 
 	/* GPP_H11 - GPIO */
 	/* DW0: 0x44000102, DW1: 0x00000000 */
 	/* DW0: (1 << 1) - IGNORED */
-	PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, DEEP, OFF, ACPI),
+	/* PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, DEEP, OFF, ACPI), */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */
 
 	/* GPP_H12 - DEVSLP0B */
 	/* DW0: 0x44001500, DW1: 0x00000000 */

diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/gpio_early.c b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio_early.c
@@ -4,8 +4,8 @@
 #include <soc/gpio.h>
 
 static const struct pad_config early_gpio_table[] = {
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), // UART0_TX
 };
 
 void mainboard_configure_early_gpios(void)

diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/gpio_early.c b/src/mainboard/clevo/adl-p/variants/nv40pz/gpio_early.c
@@ -6,8 +6,8 @@
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
 	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART2_RXD (actually UART0)
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART2_TXD (actually UART0)
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), // UART0_RXD
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), // UART0_TXD
 };
 
 void mainboard_configure_early_gpios(void)