Created by a 4-Member Team VHDL Project in CPE 016 — Introduction to VHDL | Implemented in VHDL 2008.
Hello! This is a repository dedicated to show the concept and the implementation behind the Clap Lock in VHDL.
The repository is free-of-charge and is under MIT License, so you can fork and make changes without me being notified about it.
Also, keep in mind that, the implementation on this branch is heavily confusing because of how VHDL handles signals and how they make it hard as possible to drive certain signals and things and other such. I'm not sure if I wanna rewrite it, because of the convienience of the IDE such as ModelSim is not so great after all.
And last, but not the least, expect it to be really confusing but it works. We made this project in time interval of 3 DAYS.
In this part of the README, you will learn how to setup from cloning / forking the repository to the simulation process.
In order to get started, as literally, get started, you must have the following materials / software that would help us get through the process of debugging and simulating the system.
- *Visual Studio Code — A Scalable IDE with Multiple Supported Essential Extension and Components for Easy Development and Integration.
- *ModelSim PE Student Edition 10.4a — A 2015 No-Support-For-Student-Edition VHDL Simulation.
Software or materials that has a label of * were my preferrable choice. It is not technically a required software to use. You could use other software that has the same funtionalities. So it depends if you wanna follow the certain materials / software but those are the materials / software that I used after the project making,
If you're using Visual Studio Code, here's a list of extensions that I used for convenience.
- VHDL Formatter by Vinrobot — VHDL Formatter for Visual Studio Code.
- Modern VHDL by rjyoung — This extension add language support for VHDL, based on the 2008 standard. Also includes syntax highlighting of constants, types and functions for the following standard packages:
In this part, I assume that you have the materials / software installed and properly configured. To start off, you have two ways to get this project. By (1) Cloning or (2) Forking.
- Cloning — You replicate the project for your local usage. You do not however inherit the project (unless you're a contributer here) and you don't have the capability to generate PRs to issue with the original repo.
- Forking — You are able to replicate the project and at the same time, you were able to get inheritance of the project. You're allowed to make changes, reflect into your account, and create PR to the original repo.
In this part of the subsection, I'm only going to introduce the setup part in Simulation which is ModelSim. If you have other simulators, please keep in note that you have set the Compiler to VHDL08 Compiler. The default compiler which is VHDL92 does not allow to display output of the signals.
Keep in mind that, you have to set the compiler options from both files. (This is ModelSim Use-Case.)
After setting up the compiler from both files and compiled them. You have to Start the Simulation from (1) clap_lock_vhdl_testbench and (2) Add Waveform to it.
| (1) | (2) |
|---|---|
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Once you were able to set those, its time to adjust the runtime length.
This was done so that, there's a time interval of 1 second per each run command being executed.
And last but not the least, fill in the waveform objects. There are only few selected objects that has to be looked at as other objects weren't useful at all.
Once you hit the run command in the transcript, you have to keep going until you have the following waveform.
The setup is completed! If you want to know more about the runtime of each waveform for every second it runs, please check the documentation. Thanks!
This project was documented in the midst of the progression. Please check the following materials for more information about this project.
Documentation: Time Based Clap Pattern Lock (Legacy Documentation)
Youtube Video (with Simulation and Introduction to the VHDL Programming): Clap Lock VHDL Final Project
Due to time constraints, we're having struggles to add more feature that is very essential to the concept of clap lock.
I, the maintainer, have listed the things that I could have done but decided to postponed it for now.
I promise to have it finished before this year.
- Separate PW_PTRN_RT from Testbench to Module File with INOUT Port Mode.
- Make LED Turn ON (via Process) in Module instead of Testbench, whenever CL_MIC_DTCTR is on.
- Make LED_SEC_BLINK_DISP blink according to changes on CL_RT_CLK.
- Make Type to Remove CL_XX_XX_XX_CODE and retain only CL_XX_XX_XX_DISP.
- Attempt to consolidate redundant iterations to one processor.
- Implement Max With CLAP_WIDTH of 8. (Because we are in 8-bit.) Requires investigation.
- Create Unittests that breaks down the test bench's functionality (from the demo).
- Implement Timer Display for the sake of knowning the nth second for nth pattern by one processor instead of replicating it.
I won't be making such changes (unless if I wanted to in unknown times) in the future because its hard to work with the project. Though I wanna rewrite it as possible but its best to have other things to do than this one, occasionally.
If you're interested on working on this project, please feel free to do it and I'm glad to have someone else to take interest of it. Remember that this is only a concept, but there would still be a room for a change.
Currently, I haven't used any software versioning on this project, just like Semantic Versioning. I won't be doing because it took me 3 days to realize I should've dooe so.
Here are the list of authors who is still taking part of the project.
- Licas, Janrey — Lead Developer and Leader — CodexLink
- Imperial, Justine — Video Editor, Visualizer — No Github Profile
- Jantoc, Janos Angelo — Documentator, Project Initiator — BigBossCodes
- Langaoan, Ronald — Docuemntator, Project Support — AliasBangis
This project is licensed under the MIT License, see the LICENSE.md file for more information.