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refactor(hugr-py): move dfg to own file
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Original file line number | Diff line number | Diff line change |
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from __future__ import annotations | ||
from dataclasses import dataclass | ||
from typing import Sequence, Iterable | ||
from ._hugr import Hugr, Node, Wire, OutPort | ||
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from ._ops import Op, Command, Input, Output, DFG | ||
from hugr.serialization.tys import FunctionType, Type | ||
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@dataclass() | ||
class Dfg: | ||
hugr: Hugr | ||
root: Node | ||
input_node: Node | ||
output_node: Node | ||
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def __init__( | ||
self, input_types: Sequence[Type], output_types: Sequence[Type] | ||
) -> None: | ||
input_types = list(input_types) | ||
output_types = list(output_types) | ||
root_op = DFG(FunctionType(input=input_types, output=output_types)) | ||
self.hugr = Hugr(root_op) | ||
self.root = self.hugr.root | ||
self.input_node = self.hugr.add_node( | ||
Input(input_types), self.root, len(input_types) | ||
) | ||
self.output_node = self.hugr.add_node(Output(output_types), self.root) | ||
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@classmethod | ||
def endo(cls, types: Sequence[Type]) -> Dfg: | ||
return Dfg(types, types) | ||
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def _input_op(self) -> Input: | ||
dop = self.hugr[self.input_node].op | ||
assert isinstance(dop, Input) | ||
return dop | ||
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def inputs(self) -> list[OutPort]: | ||
return [self.input_node.out(i) for i in range(len(self._input_op().types))] | ||
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def add_op(self, op: Op, /, *args: Wire, num_outs: int | None = None) -> Node: | ||
new_n = self.hugr.add_node(op, self.root, num_outs=num_outs) | ||
self._wire_up(new_n, args) | ||
return new_n | ||
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def add(self, com: Command) -> Node: | ||
return self.add_op(com.op, *com.incoming, num_outs=com.op.num_out) | ||
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def insert_nested(self, dfg: Dfg, *args: Wire) -> Node: | ||
mapping = self.hugr.insert_hugr(dfg.hugr, self.root) | ||
self._wire_up(mapping[dfg.root], args) | ||
return mapping[dfg.root] | ||
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def add_nested( | ||
self, | ||
input_types: Sequence[Type], | ||
output_types: Sequence[Type], | ||
*args: Wire, | ||
) -> Dfg: | ||
dfg = self.hugr.add_dfg(input_types, output_types) | ||
self._wire_up(dfg.root, args) | ||
return dfg | ||
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def set_outputs(self, *args: Wire) -> None: | ||
self._wire_up(self.output_node, args) | ||
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def add_state_order(self, src: Node, dst: Node) -> None: | ||
# adds edge to the right of all existing edges | ||
# breaks if further edges are added | ||
self.hugr.add_link( | ||
src.out(self.hugr.num_outgoing(src)), dst.inp(self.hugr.num_incoming(dst)) | ||
) | ||
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def _wire_up(self, node: Node, ports: Iterable[Wire]): | ||
for i, p in enumerate(ports): | ||
src = p.out_port() | ||
self.hugr.add_link(src, node.inp(i)) |
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