refactor: remove module underscores

hugr-py/src/hugr/_cfg.py → hugr-py/src/hugr/cfg.py

@@ -2,14 +2,14 @@
 
 from dataclasses import dataclass
 
-import hugr._ops as ops
-
-from ._dfg import _DfBase
-from ._exceptions import NoSiblingAncestor, NotInSameCfg, MismatchedExit
-from ._hugr import Hugr, ParentBuilder
-from ._node_port import Node, Wire, ToNode
-from ._tys import TypeRow, Type
-import hugr._val as val
+import hugr.ops as ops
+
+from .dfg import _DfBase
+from .exceptions import NoSiblingAncestor, NotInSameCfg, MismatchedExit
+from .hugr import Hugr, ParentBuilder
+from .node_port import Node, Wire, ToNode
+from .tys import TypeRow, Type
+import hugr.val as val
 
 
 class Block(_DfBase[ops.DataflowBlock]):

hugr-py/src/hugr/_cond_loop.py → hugr-py/src/hugr/cond_loop.py

@@ -2,13 +2,13 @@
 
 from dataclasses import dataclass
 
-import hugr._ops as ops
+import hugr.ops as ops
 
-from ._dfg import _DfBase
-from ._hugr import Hugr, ParentBuilder
-from ._node_port import Node, Wire, ToNode
+from .dfg import _DfBase
+from .hugr import Hugr, ParentBuilder
+from .node_port import Node, Wire, ToNode
 
-from ._tys import Sum, TypeRow
+from .tys import Sum, TypeRow
 
 
 class Case(_DfBase[ops.Case]):

hugr-py/src/hugr/_dfg.py → hugr-py/src/hugr/dfg.py

@@ -10,9 +10,9 @@
 
 from typing_extensions import Self
 
-import hugr._ops as ops
-import hugr._val as val
-from hugr._tys import (
+import hugr.ops as ops
+import hugr.val as val
+from hugr.tys import (
     Type,
     TypeRow,
     get_first_sum,
@@ -23,13 +23,13 @@
     ExtensionSet,
 )
 
-from ._exceptions import NoSiblingAncestor
-from ._hugr import Hugr, ParentBuilder
-from ._node_port import Node, OutPort, Wire, ToNode
+from .exceptions import NoSiblingAncestor
+from .hugr import Hugr, ParentBuilder
+from .node_port import Node, OutPort, Wire, ToNode
 
 if TYPE_CHECKING:
-    from ._cfg import Cfg
-    from ._cond_loop import Conditional, If, TailLoop
+    from .cfg import Cfg
+    from .cond_loop import Conditional, If, TailLoop
 
 
 DP = TypeVar("DP", bound=ops.DfParentOp)
@@ -96,7 +96,7 @@ def add_nested(
         self,
         *args: Wire,
     ) -> Dfg:
-        from ._dfg import Dfg
+        from .dfg import Dfg
 
         parent_op = ops.DFG(self._wire_types(args))
         dfg = Dfg.new_nested(parent_op, self.hugr, self.parent_node)
@@ -110,7 +110,7 @@ def add_cfg(
         self,
         *args: Wire,
     ) -> Cfg:
-        from ._cfg import Cfg
+        from .cfg import Cfg
 
         cfg = Cfg.new_nested(self._wire_types(args), self.hugr, self.parent_node)
         self._wire_up(cfg.parent_node, args)
@@ -120,7 +120,7 @@ def insert_cfg(self, cfg: Cfg, *args: Wire) -> Node:
         return self._insert_nested_impl(cfg, *args)
 
     def add_conditional(self, cond: Wire, *args: Wire) -> Conditional:
-        from ._cond_loop import Conditional
+        from .cond_loop import Conditional
 
         args = (cond, *args)
         (sum_, other_inputs) = get_first_sum(self._wire_types(args))
@@ -132,15 +132,15 @@ def insert_conditional(self, cond: Conditional, *args: Wire) -> Node:
         return self._insert_nested_impl(cond, *args)
 
     def add_if(self, cond: Wire, *args: Wire) -> If:
-        from ._cond_loop import If
+        from .cond_loop import If
 
         conditional = self.add_conditional(cond, *args)
         return If(conditional.add_case(1))
 
     def add_tail_loop(
         self, just_inputs: Sequence[Wire], rest: Sequence[Wire]
     ) -> TailLoop:
-        from ._cond_loop import TailLoop
+        from .cond_loop import TailLoop
 
         just_input_types = self._wire_types(just_inputs)
         rest_types = self._wire_types(rest)

hugr-py/src/hugr/_function.py → hugr-py/src/hugr/function.py

@@ -2,13 +2,13 @@
 
 from dataclasses import dataclass
 
-import hugr._ops as ops
-import hugr._val as val
+import hugr.ops as ops
+import hugr.val as val
 
-from ._dfg import _DfBase
-from hugr._node_port import Node
-from ._hugr import Hugr
-from ._tys import TypeRow, TypeParam, PolyFuncType, Type, TypeBound
+from .dfg import _DfBase
+from hugr.node_port import Node
+from .hugr import Hugr
+from .tys import TypeRow, TypeParam, PolyFuncType, Type, TypeBound
 
 
 @dataclass

hugr-py/src/hugr/_hugr.py → hugr-py/src/hugr/hugr.py

@@ -13,15 +13,15 @@
 )
 
 
-from hugr._ops import Op, DataflowOp, Const, Call
-from hugr._tys import Type, Kind, ValueKind
-from hugr._val import Value
-from hugr._node_port import Direction, InPort, OutPort, ToNode, Node, _SubPort
+from hugr.ops import Op, DataflowOp, Const, Call
+from hugr.tys import Type, Kind, ValueKind
+from hugr.val import Value
+from hugr.node_port import Direction, InPort, OutPort, ToNode, Node, _SubPort
 from hugr.serialization.ops import OpType as SerialOp
 from hugr.serialization.serial_hugr import SerialHugr
 from hugr.utils import BiMap
 
-from ._exceptions import ParentBeforeChild
+from .exceptions import ParentBeforeChild
 
 
 @dataclass()

hugr-py/src/hugr/_ops.py → hugr-py/src/hugr/ops.py

@@ -5,13 +5,13 @@
 from hugr.serialization.ops import BaseOp
 import hugr.serialization.ops as sops
 from hugr.utils import ser_it
-import hugr._tys as tys
-from hugr._node_port import Node, InPort, OutPort, Wire
-import hugr._val as val
-from ._exceptions import IncompleteOp
+import hugr.tys as tys
+from hugr.node_port import Node, InPort, OutPort, Wire
+import hugr.val as val
+from .exceptions import IncompleteOp
 
 if TYPE_CHECKING:
-    from hugr._hugr import Hugr
+    from hugr.hugr import Hugr
 
 
 @dataclass
@@ -35,7 +35,7 @@ def port_kind(self, port: InPort | OutPort) -> tys.Kind: ...
 
 
 def _sig_port_type(sig: tys.FunctionType, port: InPort | OutPort) -> tys.Type:
-    from hugr._hugr import Direction
+    from hugr.node_port import Direction
 
     if port.direction == Direction.INCOMING:
         return sig.input[port.offset]