Kindly note: This is a work in progress directory, with reference implementations from Hardware Acceleration RIs at CIE PESU
FPGA Board: Intel Cyclone V DE10 Standard
Tools: Intel Quartus Prime, ModelSim
| Title | Files |
|---|---|
| Accelerator Building Blocks | Pipelined Adder Tree Parallel Prefix Adder - W0_Task Carry Look-Ahead Adder - W0_Task Carry Select Adder - W0_Task Ripple Carry Adder - W0_Task MAC Shift and Add Multiplier - W0_task Division Circuit - W0_task Bitonic Sorter Cordic Accelerator |