Fix filecheck test

AntonLydike · May 14, 2024 · c185f0f · c185f0f
1 parent beaf22e
commit c185f0f
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/riscemu/instructions/RV32F.py b/riscemu/instructions/RV32F.py
@@ -95,7 +95,7 @@ def instruction_fcvt_s_w(self, ins: Instruction):
         | f[rd] = f32_{s32}(x[rs1])
         """
         rd, rs = self.parse_rd_rs(ins)
-        self.regs.set_f(rd, Float32(self.regs.get(rs).signed().value))
+        self.regs.set_f(rd, Float32(self.regs.get(rs).value))
 
     def instruction_fcvt_s_wu(self, ins: Instruction):
         """

diff --git a/test/filecheck/rv32f-conv.asm b/test/filecheck/rv32f-conv.asm
@@ -34,14 +34,14 @@ main:
     fcvt.s.w fa0, a1
     fmv.x.w a1, fa0
     print a1
-// CHECK-NEXT: register a1 contains value 3221225472
+// CHECK-NEXT: register a1 contains value -1073741824
 
     // test fmv.w.x
     li a1, 1073741824
     fmv.w.x fa0, a1
     print.float.s fa0
 // CHECK-NEXT: register fa0 contains value 2.0
-    li a1, 3221225472
+    li a1, -1073741824
     fmv.w.x fa0, a1
     print.float.s fa0
 // CHECK-NEXT: register fa0 contains value -2.0