Feature m instruction set (#48)

* fix jarl argument assertion bug

* fix mulh bug

* implement mulhsu and mulhu

* Fix typos and add codespell pre-commit hook (#45)

* Fix typos

Found via `codespell -L fle,sie`

* Update riscemu/decoder/__main__.py

Co-authored-by: Anton Lydike <[email protected]>

* Remove codespell

---------

Co-authored-by: Anton Lydike <[email protected]>

* Add p2align assembler directive (#46)

* add p2align assembler directive

* black

* add p2align to changelog

* Big cleanup work (#47)

This moves a lot of internal data structures from `types` into `core`, because some imports got confused apparently.

It also adds csr registers, performance improvements, etc.

* release 2.2.0

* fix python publish

* official bump commit

* a bunch of minor fixes

* version bump 2.2.2

* Add support for flen=64 (#49)

Currently still missing a lot of the D extension (all except `fmadd, fmsub, fnmsub, fnmadd, fadd, fsub, fmul, fdiv, fsqrt, fsgnj, fsgnjn, fsgnjx, fmin, fmax, feq, flt, fle, fld, fsd`), missing conversion and move instructions.

This may break some of the float32 stuff, so we should be very careful with this.

* fix a few minor errors

* fix a bug with libc not being found by packaged versions of riscemu

* update pyelftools, add importlib-resources as dependency

* fix issue with importlib.resources not working on python 3.8

* add missing float registers

* update changelog

* Snitch frep extension support (#50)

This patch adds the frep extension to the snitch emulator. Register staggering is not supported currently, but could be added at a later date.

This patch also adds f64 support to the xssr extension.

* release 2.2.4

* fix SimpleInstruction.get_imm and add test

* release 2.2.5

* add filecheck test

* Fix error from merge

* fix filecheck to print unsigned values when needed

---------

Co-authored-by: Kian-Meng Ang <[email protected]>
Co-authored-by: Anton Lydike <[email protected]>

CHANGELOG.md

@@ -5,6 +5,9 @@
  - Feature: Canonicalize register names when parsing, converting e.g. `x0 -> zero` or `fp -> s0`.
  - Feature: Added support for `fcvt.d.w[u]` and `fcvt.w[u].d` instructions
  - BugFix: Fixed that registers were treated as UInt32s instead of Int32 (this may have caused subtle bugs before)
+ - Feature: Added the remainder of the `M` extension
+ - BugFix: Fixed a bug in the overflow behavior of `mulh`
+ - BugFix: Fix faulty length assertion in `jalr`
 
 ## 2.2.5
 

riscemu/instructions/RV32M.py

@@ -5,7 +5,6 @@
 """
 
 from .instruction_set import *
-from riscemu.core.exceptions import INS_NOT_IMPLEMENTED
 
 
 class RV32M(InstructionSet):
@@ -19,13 +18,15 @@ def instruction_mul(self, ins: "Instruction"):
 
     def instruction_mulh(self, ins: "Instruction"):
         rd, rs1, rs2 = self.parse_rd_rs_rs(ins)
-        self.regs.set(rd, (rs1 * rs2) >> 32)
+        self.regs.set(rd, Int32((rs1.signed().value * rs2.signed().value) >> 32))
 
     def instruction_mulhsu(self, ins: "Instruction"):
-        INS_NOT_IMPLEMENTED(ins)
+        rd, rs1, rs2 = self.parse_rd_rs_rs(ins)
+        self.regs.set(rd, Int32((rs1.signed().value * rs2.unsigned_value) >> 32))
 
     def instruction_mulhu(self, ins: "Instruction"):
-        INS_NOT_IMPLEMENTED(ins)
+        rd, rs1, rs2 = self.parse_rd_rs_rs(ins)
+        self.regs.set(rd, UInt32((rs1.unsigned_value * rs2.unsigned_value) >> 32))
 
     def instruction_div(self, ins: "Instruction"):
         rd, rs1, rs2 = self.parse_rd_rs_rs(ins)

test/filecheck/rv32m-conv.asm

@@ -0,0 +1,37 @@
+// RUN: python3 -m riscemu -v %s -o libc | filecheck %s
+
+.text
+
+.globl      main
+main:
+    // test mulh
+    li a1, -1
+    mulh a0, a1, a1
+    print a0
+// CHECK: register a0 contains value 0
+    li a2, 2
+    mulh a0, a1, a2
+    print.uhex a0
+// CHECK-NEXT: register a0 contains value 0xffffffff
+
+    // test mulhu
+    mulhu a0, a1, a2
+    print a0
+// CHECK: register a0 contains value 1
+
+    mulhu a0, a1, a1
+    print.uhex a0
+// CHECK-NEXT: register a0 contains value 0xfffffffe
+
+    // test mulhsu
+    mulhsu a0, a1, a2
+    print.uhex a0
+// CHECK: register a0 contains value 0xffffffff
+
+    mulhsu a0, a2, a1
+    print a0
+// CHECK-NEXT: register a0 contains value 1
+
+    li a0, 0
+    ret
+// CHECK-NEXT: [CPU] Program exited with code 0