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mb/lenovo/optiplex_9030_aio: Add Optiplex 9030 AIO
Built using SMSC555x sources. Boots Linux Mint 20.3 Kernel 5.4. Tested working: - Intel i7-4785T - 2x 4Gb SODIMM DDR3 1600mhz - Audio - Linux Mint 20.3 Kernel 5.4 - SSD - DVD Drive - Boot LED - Ethernet - S3 Resume - Internal Display - USB ports - Intel wifi card Not working: - Fan control - TPM 1.2 Untested: - Internal flashing with flashrom - 2nd NGFF slot - Camera
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amersel
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Jul 8, 2022
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if BOARD_DELL_OPTIPLEX_9030_AIO | ||
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config BOARD_SPECIFIC_OPTIONS | ||
def_bool y | ||
select BOARD_ROMSIZE_KB_12288 | ||
select HAVE_ACPI_RESUME | ||
select HAVE_ACPI_TABLES | ||
select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this | ||
select NORTHBRIDGE_INTEL_HASWELL | ||
select SERIRQ_CONTINUOUS_MODE | ||
select SOUTHBRIDGE_INTEL_LYNXPOINT | ||
select MAINBOARD_USES_IFD_GBE_REGION | ||
select MAINBOARD_HAS_LIBGFXINIT | ||
select HAVE_ACPI_RESUME | ||
select HAVE_ACPI_TABLES | ||
select INTEL_GMA_HAVE_VBT | ||
select SUPERIO_SMSC_SCH555x | ||
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config MAINBOARD_DIR | ||
string | ||
default "dell/optiplex_9030_aio" | ||
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config MAINBOARD_PART_NUMBER | ||
string | ||
default "OptiPlex 9030 AIO" | ||
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config VGA_BIOS_ID | ||
string | ||
default "8086,0412" | ||
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config USBDEBUG_HCD_INDEX # FIXME: check this | ||
int | ||
default 2 | ||
endif |
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config BOARD_DELL_OPTIPLEX_9030_AIO | ||
bool "OptiPlex 9030 AIO" |
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bootblock-y += bootblock.c | ||
bootblock-y += gpio.c | ||
romstage-y += gpio.c | ||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads |
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/* SPDX-License-Identifier: GPL-2.0-only */ | ||
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Method(_WAK, 1) | ||
{ | ||
Return(Package() {0, 0}) | ||
} | ||
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Method(_PTS, 1) | ||
{ | ||
} |
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Category: desktop | ||
ROM protocol: SPI | ||
Flashrom support: n | ||
FIXME: check category, , put ROM package, ROM socketed, Release year |
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/* SPDX-License-Identifier: GPL-2.0-only */ | ||
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#include <arch/io.h> | ||
#include <device/pnp_ops.h> | ||
#include <superio/smsc/sch555x/sch555x.h> | ||
#include <southbridge/intel/lynxpoint/pch.h> | ||
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static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) | ||
{ | ||
// Clear EC-to-Host mailbox | ||
uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); | ||
outb(tmp, SCH555x_EMI_IOBASE + 1); | ||
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// Send address and value to the EC | ||
sch555x_emi_write16(0, (addr1 * 2) | 0x101); | ||
sch555x_emi_write32(4, val | (addr2 << 16)); | ||
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// Wait for acknowledgement message from EC | ||
outb(1, SCH555x_EMI_IOBASE); | ||
size_t timeout = 0; | ||
do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); | ||
} | ||
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struct ec_init_entry { | ||
uint16_t addr; | ||
uint8_t val; | ||
}; | ||
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static void ec_init(void) | ||
{ | ||
/* | ||
* Tables from CORE_PEI | ||
*/ | ||
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static const struct ec_init_entry init_table1[] = { | ||
{0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10}, | ||
{0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10}, | ||
{0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12}, | ||
{0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12}, | ||
{0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10}, | ||
{0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11}, | ||
}; | ||
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for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) | ||
ec_write(2, init_table1[i].addr, init_table1[i].val); | ||
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static const struct ec_init_entry init_table2[] = { | ||
{0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f}, | ||
{0x0083, 0xbb}, {0x0085, 0xd9}, {0x0086, 0x2c}, {0x008a, 0x34}, | ||
{0x008b, 0x60}, {0x0090, 0x5e}, {0x0091, 0x5e}, {0x0092, 0x86}, | ||
{0x0096, 0xa4}, {0x0097, 0xa4}, {0x0098, 0xa4}, {0x009b, 0xa4}, | ||
{0x00a0, 0x0a}, {0x00a1, 0x0a}, {0x00ae, 0x7c}, {0x00af, 0x7c}, | ||
{0x00b0, 0x9e}, {0x00b3, 0x7c}, {0x00b6, 0x08}, {0x00b7, 0x08}, | ||
{0x00ea, 0x64}, {0x00ef, 0xff}, {0x00f8, 0x15}, {0x00f9, 0x00}, | ||
{0x00f0, 0x30}, {0x00fd, 0x01}, {0x01a1, 0x00}, {0x01a2, 0x00}, | ||
{0x01b1, 0x08}, {0x01be, 0x90}, {0x0280, 0x24}, {0x0281, 0x13}, | ||
{0x0282, 0x03}, {0x0283, 0x0a}, {0x0284, 0x80}, {0x0285, 0x03}, | ||
{0x0288, 0x80}, {0x0289, 0x0c}, {0x028a, 0x03}, {0x028b, 0x0a}, | ||
{0x028c, 0x80}, {0x028d, 0x03}, {0x0040, 0x01}, | ||
}; | ||
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for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) | ||
ec_write(1, init_table2[i].addr, init_table2[i].val); | ||
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/* | ||
* Table from PeiHwmInit | ||
*/ | ||
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static const struct ec_init_entry hwm_init_table[] = { | ||
{0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f}, | ||
{0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33}, | ||
{0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff}, | ||
{0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00}, | ||
{0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00}, | ||
{0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80}, | ||
{0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02}, | ||
{0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04}, | ||
{0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50}, | ||
{0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50}, | ||
{0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c}, | ||
{0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd}, | ||
{0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e}, | ||
{0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00}, | ||
{0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff}, | ||
{0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00}, | ||
{0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c}, | ||
{0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02}, | ||
{0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03}, | ||
}; | ||
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for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) | ||
ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); | ||
} | ||
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#define SCH555x_IOBASE 0x2e | ||
#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL) | ||
#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1) | ||
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void mainboard_config_superio(void) | ||
{ | ||
// Super I/O early init will map Runtime and EMI registers | ||
sch555x_early_init(GLOBAL_DEV); | ||
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// Changes LED color among a few other things (extracted from Dell's FW) | ||
outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS); | ||
outb(0x00, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN); | ||
outb(0x18, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN1); | ||
outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); | ||
outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); | ||
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// Magic EC init | ||
ec_init(); | ||
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// Magic EC init is needed for UART1 initialization to work | ||
sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); | ||
} | ||
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chip northbridge/intel/haswell # FIXME: check ec_present, usb_xhci_on_resume, gfx | ||
register "ec_present" = "false" | ||
register "gfx" = "GMA_STATIC_DISPLAYS(0)" | ||
register "gpu_ddi_e_connected" = "1" | ||
register "gpu_dp_b_hotplug" = "0" | ||
register "gpu_dp_c_hotplug" = "0" | ||
register "gpu_dp_d_hotplug" = "0" | ||
register "panel_cfg" = "{ # FIXME: check panel_cfg | ||
.up_delay_ms = 0, | ||
.down_delay_ms = 0, | ||
.cycle_delay_ms = 4294967196, | ||
.backlight_on_delay_ms = 0, | ||
.backlight_off_delay_ms = 0, | ||
.backlight_pwm_hz = 0, | ||
}" | ||
register "usb_xhci_on_resume" = "false" | ||
device cpu_cluster 0x0 on | ||
chip cpu/intel/haswell | ||
device lapic 0x0 on | ||
end | ||
device lapic 0xacac off | ||
end | ||
end | ||
end | ||
device domain 0x0 on | ||
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH | ||
register "docking_supported" = "0" | ||
register "gen1_dec" = "0x007c0a01" | ||
register "gen2_dec" = "0x007c0901" | ||
register "gen3_dec" = "0x003c07e1" | ||
register "gen4_dec" = "0x001c0901" | ||
register "gpe0_en_1" = "0x0" | ||
register "gpe0_en_2" = "0x0" | ||
register "sata_port0_gen3_dtle" = "0x0" | ||
register "sata_port1_gen3_dtle" = "0x0" | ||
register "sata_port_map" = "0x31" # FIXME: check sata ports | ||
device pci 14.0 on # xHCI Controller | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 16.0 off # Management Engine Interface 1 | ||
end | ||
device pci 16.1 off # Management Engine Interface 2 | ||
end | ||
device pci 16.2 off # Management Engine IDE-R | ||
end | ||
device pci 16.3 off # Management Engine KT | ||
end | ||
device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:153a | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1a.0 on # USB2 EHCI #2 | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1b.0 on # High Definition Audio | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1c.0 on # PCIe Port #1 | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1c.1 off # PCIe Port #2 | ||
end | ||
device pci 1c.2 off # PCIe Port #3 | ||
end | ||
device pci 1c.3 off # PCIe Port #4 | ||
end | ||
device pci 1c.4 on # PCIe Port #5 | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1c.5 off # PCIe Port #6 | ||
end | ||
device pci 1c.6 on # PCIe Port #7 | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1c.7 off # PCIe Port #8 | ||
end | ||
device pci 1d.0 on # USB2 EHCI #1 | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1f.0 on # LPC bridge | ||
chip superio/smsc/sch555x | ||
device pnp 2e.0 on # EMI | ||
io 0x60 = 0xa00 | ||
end | ||
device pnp 2e.1 on # 8042 | ||
io 0x60 = 0x60 | ||
irq 0x0f = 0 | ||
irq 0x70 = 1 | ||
irq 0x72 = 12 | ||
end | ||
device pnp 2e.7 on # UART1 | ||
io 0x60 = 0x3f8 | ||
irq 0x0f = 2 | ||
irq 0x70 = 4 | ||
end | ||
device pnp 2e.8 off end # UART2 | ||
device pnp 2e.c on # LPC interface | ||
io 0x60 = 0x2e | ||
end | ||
device pnp 2e.a on # Runtime registers | ||
io 0x60 = 0xa40 | ||
end | ||
device pnp 2e.b off end # Floppy Controller | ||
device pnp 2e.11 off end # Parallel Port | ||
end | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1f.2 on # SATA Controller (AHCI) | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1f.3 on # SMBus | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 1f.5 off # SATA Controller (Legacy) | ||
end | ||
device pci 1f.6 off # Thermal | ||
end | ||
end | ||
device pci 00.0 on # Desktop Host bridge | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 01.0 off # PCIe Bridge for discrete graphics | ||
end | ||
device pci 02.0 on # Internal graphics VGA controller | ||
subsystemid 0x1028 0x0625 | ||
end | ||
device pci 03.0 on # Mini-HD audio | ||
subsystemid 0x1028 0x0625 | ||
end | ||
end | ||
end |
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/* SPDX-License-Identifier: GPL-2.0-only */ | ||
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#include <acpi/acpi.h> | ||
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DefinitionBlock( | ||
"dsdt.aml", | ||
"DSDT", | ||
ACPI_DSDT_REV_2, | ||
OEM_ID, | ||
ACPI_TABLE_CREATOR, | ||
0x20141018 /* OEM revision */ | ||
) | ||
{ | ||
#include <acpi/dsdt_top.asl> | ||
#include "acpi/platform.asl" | ||
#include <cpu/intel/common/acpi/cpu.asl> | ||
#include <southbridge/intel/common/acpi/platform.asl> | ||
/* global NVS and variables. */ | ||
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> | ||
#include <southbridge/intel/common/acpi/sleepstates.asl> | ||
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Device (\_SB.PCI0) | ||
{ | ||
#include <northbridge/intel/haswell/acpi/hostbridge.asl> | ||
/* FIXME: remove this if the board doesn't have backlight. */ | ||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl> | ||
#include <southbridge/intel/lynxpoint/acpi/pch.asl> | ||
} | ||
} |
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-- SPDX-License-Identifier: GPL-2.0-or-later | ||
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with HW.GFX.GMA; | ||
with HW.GFX.GMA.Display_Probing; | ||
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use HW.GFX.GMA; | ||
use HW.GFX.GMA.Display_Probing; | ||
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private package GMA.Mainboard is | ||
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-- FIXME: check this | ||
ports : constant Port_List := | ||
(DP1, | ||
DP2, | ||
DP3, | ||
HDMI1, | ||
HDMI2, | ||
HDMI3, | ||
Analog, | ||
LVDS, | ||
eDP); | ||
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end GMA.Mainboard; |
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