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WIP: SIMD and other goodies #534
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…/accelerate into wip/vector-operations # Conflicts: # src/Data/Array/Accelerate/Trafo/Algebra.hs
Previously we could represent SIMD types (e.g. for complex numbers) but calculations directly in this representation were not possible. User defined (sum and product) types can also be stored in SIMD format through the (generic derivable) SIMD class. Nested SIMD types are not supported. New type classes VOrd and VEq which provide operations from Eq and Ord that compute their result per-lane. Types of member functions of several (otherwise standard H98) classes are changed in order to support SIMD types, in particular Bits.
[ 99 of 112] Compiling Data.Array.Accelerate.Lift ghc: panic! (the 'impossible' happened) (GHC version 8.6.5 for x86_64-unknown-linux): expectJust mkOneConFull CallStack (from HasCallStack): error, called at compiler/utils/Maybes.hs:55:27 in ghc:Maybes expectJust, called at compiler/deSugar/Check.hs:1312:37 in ghc:Check
This should now match the behaviour of the tuple instances
# Conflicts: # .github/workflows/ci-linux.yml # accelerate.cabal # src/Data/Array/Accelerate/AST/Idx.hs # src/Data/Array/Accelerate/Array/Data.hs # src/Data/Array/Accelerate/Classes/RealFrac.hs # src/Data/Array/Accelerate/Classes/RealFrac.hs-boot # src/Data/Array/Accelerate/Data/Complex.hs # src/Data/Array/Accelerate/Language.hs # src/Data/Array/Accelerate/Prelude.hs # src/Data/Array/Accelerate/Sugar/Vec.hs # stack-8.10.yaml # stack-9.2.yaml # stack.yaml
ghc-iserv: munmapForLinker: m32_release_page: Failed to unmap 4096 bytes at ...: Attempt to access invalid address.
- VNum class for horizontal sum/product of a vector - vminimum/vmaximum for horizontal vector min/max reduction - bitreverse - byteswap
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Motivation and context
A while ago @HugoPeters1024 asked something along the lines of "how do I make a SIMD vector of this data type". The answer was "you can't", and so he made a workaround instead that didn't require it.
This patch fixes that infelicity. Now you can:
and then:
will create a 2-wide SIMD-vector-like thing, where internally the usual struct-of-array type of thing is happening to store the ints and floats in their own vector registers.
Of course, just being able to represent SIMD vector data in the language isn't enough, you need to be able to compute with that data as well. Now you can write something like this SIMD-vectorised Mandelbrot computation (adapted from here), where the SIMD width is altered by changing the type:
Description
Since we are making fundamental changes to the internal representation of types, we might as well tick off a bunch of TODOs at the same time. Here is a rough list of changes in this patch, but this has been in progress for a while so I've probably forgotten some stuff.
Int
andWord
nonsense; that gets stripped out at the surface level now-ffloat128
since that needs thequadmath
library installed (gcc/linux x86_64 will have it, other platforms may or may not).bfloat16
or 8-bit floats (which one?) but I'll leave that for nowVEq
,VOrd
,VNum
Ord
instance will do it in the same way as ordering on tuples, whereasVOrd
will do it lane-wise. Similarly,min
will do the tuple-style minimum whereasvmin
will do it lane-wise andvminimum
will give you the minimum element in that vector (i.e. horizontal reduction across the vector) etc. etc.pack
,unpack
,insert
,extract
)FromBool
to convert Bools to and from integral typesVector Float
andVector (Vec 2 Float)
, orVector Bool
(bit vector) andVector Word64
, etc. Works for structured types (pairs, etc.) as well.V2
to construct a 2-wide SIMD vector at both the Haskell value level as well as the Accelerate expression level. I find it useful, but otoh it does hide a bit what is going on, so the type errors can be worse (as usual).There are still TODOs in the code and to an extent the design depends on what code we can eventually generate from it (in progress), but I'm just throwing this up for now to start getting eyes on it.
How has this been tested?
>_>
Types of changes
Checklist