Add new intrinsic for svpmov when lane is zero

To Predicator -  it should have the alias for when the index is not passed.
It defaults the index to zero. According to the spec :
 "The portion index is optional, defaulting to 0 if omitted".[1]
To Vector - remove lane from when the line is zero
  svpmov_lane_z  is now svpmov_z

Adds signed options to svaddqv

[1]https://developer.arm.com/documentation/ddi0602/2023-09/SVE-Instructions/PMOV--to-predicate---Move-predicate-from-vector-

main/acle.md

@@ -9480,7 +9480,7 @@ Unsigned/FP add reduction of quadword vector segments.
 
 ``` c
   // Variants are also available for:
-  // _u16, _u32, _u64,
+  // _s8, _s16, _u16, _s32, _u32, _s64, _u64,
   // _f16, _f32, _f64
   uint8x16_t svaddqv[_u8](svbool_t pg, svuint8_t zn);
   ```
@@ -9614,7 +9614,7 @@ Gather Load Quadword.
    // _u16, _u32, _s32, _u64, _s64
    // _bf16, _f16, _f32, _f64
    svint16_t svld1q_gather_[u64]index[_s16](svbool_t pg, const int16_t *base, svuint64_t index);
-   svint8_t svld1q_gather[_u64base]_index_s8(svbool_t pg, svuint64_t zn, int64_t index);$
+   svint8_t svld1q_gather[_u64base]_index_s8(svbool_t pg, svuint64_t zn, int64_t index);
    ```
 
 #### LD2Q, LD3Q, LD4Q
@@ -9729,16 +9729,20 @@ Transform a predicate-as-counter to a predicate (pair).
 
  ``` c
    // Variants are available for:
-   // _s8, _s16, _u16, _s32, _u32, _s64, _u64
+   // _s8, _u16, _s16, _s32, _u32, _s64, _u64
    svbool_t svpmov_lane[_u8](svuint8_t zn, uint64_t imm);
 
+   // Variants are available for:
+   // _s8, _s16, _u16, _s32, _u32, _s64, _u64
+   svbool_t svpmov[_u8](svuint8_t zn);
+
    // Variants are available for:
    // _s16, _s32, _u32, _s64, _u64
    svuint16_t svpmov_lane[_u16]_m(svuint16_t zd, svbool_t pn, uint64_t imm);
 
    // Variants are also available for:
    // _s8, _u16, _s16, _u32, _s32, _u64, _s64
-   svuint8_t svpmov_lane_u8_z(svbool_t pn);
+   svuint8_t svpmov_u8_z(svbool_t pn);
    ```
 
 #### PSEL