From 359eaaf1d8a7bcc2f467d341dfc3bdf8b57f191a Mon Sep 17 00:00:00 2001 From: Dat Nguyen Duy Date: Wed, 28 Aug 2024 18:30:28 +0700 Subject: [PATCH] board: s32z2xxdc2: allow the code to be executed from code RAM - Trace32 runner: no need to configure TE bit in CFG_CORE register in the cmm start-up script, it can be configured at Zephyr start-up code when required (via SCTRL register) - MPU static regions also needs to be updated for XIP and non-XIP Signed-off-by: Dat Nguyen Duy --- boards/nxp/s32z2xxdc2/Kconfig.defconfig | 13 +++++++++++++ .../s32z2xxdc2_s32z270_rtu0_defconfig | 2 +- .../s32z2xxdc2_s32z270_rtu1_defconfig | 2 +- boards/nxp/s32z2xxdc2/support/startup.cmm | 15 +++------------ soc/nxp/s32/s32ze/mpu_regions.c | 17 +++++++++++------ 5 files changed, 29 insertions(+), 20 deletions(-) diff --git a/boards/nxp/s32z2xxdc2/Kconfig.defconfig b/boards/nxp/s32z2xxdc2/Kconfig.defconfig index 2b5dffc89335a3d..97ece5583f01bae 100644 --- a/boards/nxp/s32z2xxdc2/Kconfig.defconfig +++ b/boards/nxp/s32z2xxdc2/Kconfig.defconfig @@ -30,4 +30,17 @@ config NET_L2_ETHERNET endif # NETWORKING +if XIP +# Offset between CRAM AXIM and CRAM AXIF, code will be downloaded +# over AXIM interface +config BUILD_OUTPUT_ADJUST_LMA + default "-0x47800000" + +config CPU_CORTEX_R52_ICACHE_FLASH_WAY + default 4 + +config CPU_CORTEX_R52_DCACHE_FLASH_WAY + default 1 +endif # XIP + endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1 diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig index c9a84cc2dfebdb6..e498ea985430549 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig @@ -1,7 +1,7 @@ # Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 -CONFIG_XIP=n +CONFIG_XIP=y CONFIG_ISR_STACK_SIZE=512 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig index c9a84cc2dfebdb6..e498ea985430549 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig @@ -1,7 +1,7 @@ # Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 -CONFIG_XIP=n +CONFIG_XIP=y CONFIG_ISR_STACK_SIZE=512 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 diff --git a/boards/nxp/s32z2xxdc2/support/startup.cmm b/boards/nxp/s32z2xxdc2/support/startup.cmm index a0cbca67470e917..ca26d84ae08d04e 100644 --- a/boards/nxp/s32z2xxdc2/support/startup.cmm +++ b/boards/nxp/s32z2xxdc2/support/startup.cmm @@ -20,20 +20,17 @@ ; - Core0 and Core2 (redundancy) operate as a lockstep pair * ; - Core1 and Core3 (redundancy) operate as a lockstep pair * ; default: yes * -; - thumb set to "yes" to select the T32 instruction set at reset * -; default: no * ; * ;******************************************************************************* ENTRY %LINE &args -LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &thumbBit &spltLckBit +LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &spltLckBit &command=STRing.SCANAndExtract("&args","command=","debug") &elfFile=STRing.SCANAndExtract("&args","elfFile=","") &rtu=STRing.SCANAndExtract("&args","rtu=","0") &core=STRing.SCANAndExtract("&args","core=","0") &lockstep=STRing.SCANAndExtract("&args","lockstep=","yes") -&thumb=STRing.SCANAndExtract("&args","thumb=","no") IF ("&elfFile"=="") ( @@ -59,12 +56,6 @@ IF (&core<0||&core>3) ENDDO ) -; select ARMv8 instruction set at reset for all Cortex-R52 cores (CFG_CORE.THUMB bit) -IF ("&thumb"=="yes") - &thumbBit="1" -ELSE - &thumbBit="0" - ; select lock-step or split-lock mode (CFG_CORE.SPLT_LCK bit) IF ("&lockstep"=="yes") &spltLckBit="0" @@ -126,8 +117,8 @@ GOSUB EnableRTU1 ; Init RTU SRAM DO ~~/demo/arm/hardware/s32z27/misc/s32z27_init_rtu&(rtu)_sram.cmm -; Set reset value for TE bit and split-lock mode -Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXx&(thumbBit)x&(spltLckBit) ; CFG_CORE +; Set reset value for split-lock mode +Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXxxx&(spltLckBit) ; CFG_CORE ; Write loop to self instruction Data.Set EAXI:&rtuStartAddr %Long 0xFFFEF7FF diff --git a/soc/nxp/s32/s32ze/mpu_regions.c b/soc/nxp/s32/s32ze/mpu_regions.c index 33c41d362b5da24..bfdee2a67b7ad07 100644 --- a/soc/nxp/s32/s32ze/mpu_regions.c +++ b/soc/nxp/s32/s32ze/mpu_regions.c @@ -11,20 +11,25 @@ #define DEVICE_REGION_END 0x76FFFFFFUL static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("vector", - (uintptr_t)_vector_start, - REGION_RAM_TEXT_ATTR((uintptr_t)_vector_end)), - MPU_REGION_ENTRY("SRAM_TEXT", - (uintptr_t)__text_region_start, + (uintptr_t)__rom_region_start, REGION_RAM_TEXT_ATTR((uintptr_t)__rodata_region_start)), MPU_REGION_ENTRY("SRAM_RODATA", (uintptr_t)__rodata_region_start, - REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)), +#ifdef CONFIG_XIP + REGION_RAM_RO_ATTR(CONFIG_FLASH_BASE_ADDRESS + KB(CONFIG_FLASH_SIZE)) +#else + REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end) +#endif + ), MPU_REGION_ENTRY("SRAM_DATA", +#ifdef CONFIG_XIP + (uintptr_t)_image_ram_start, +#else (uintptr_t)__rom_region_end, +#endif REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)), MPU_REGION_ENTRY("DEVICE",