From 2884d160cb689daf4d338cffa77f7bcc0053a086 Mon Sep 17 00:00:00 2001 From: Vit Stanicek Date: Mon, 27 Nov 2023 15:42:22 +0100 Subject: [PATCH] xtensa: Add nxp_rt600_adsp toolchain Files taken from "nxp_rt600_RI23_11_newlib_linux.tgz" available from https://tensilicatools.com. Signed-off-by: Vit Stanicek --- .github/workflows/ci.yml | 4 + .../xtensa-nxp_rt600_adsp_zephyr-elf.config | 9 + .../binutils/bfd/xtensa-modules.c | 113469 +++++++++++++++ .../binutils/include/xtensa-config.h | 189 + .../gcc/include/xtensa-config.h | 189 + .../gdb/bfd/xtensa-modules.c | 113469 +++++++++++++++ .../gdb/gdb/gdbserver/xtensa-regmap.c | 86 + .../gdb/gdb/gdbserver/xtensa-xtregs.c | 86 + .../gdb/gdb/regformats/reg-xtensa.dat | 91 + .../gdb/gdb/xtensa-config.c | 421 + .../gdb/gdb/xtensa-xtregs.c | 86 + .../gdb/include/xtensa-config.h | 189 + .../xtensa/include/xtensa/config/core-isa.h | 813 + 13 files changed, 229101 insertions(+) create mode 100644 configs/xtensa-nxp_rt600_adsp_zephyr-elf.config create mode 100644 overlays/xtensa_nxp_rt600_adsp/binutils/bfd/xtensa-modules.c create mode 100644 overlays/xtensa_nxp_rt600_adsp/binutils/include/xtensa-config.h create mode 100644 overlays/xtensa_nxp_rt600_adsp/gcc/include/xtensa-config.h create mode 100644 overlays/xtensa_nxp_rt600_adsp/gdb/bfd/xtensa-modules.c create mode 100644 overlays/xtensa_nxp_rt600_adsp/gdb/gdb/gdbserver/xtensa-regmap.c create mode 100644 overlays/xtensa_nxp_rt600_adsp/gdb/gdb/gdbserver/xtensa-xtregs.c create mode 100644 overlays/xtensa_nxp_rt600_adsp/gdb/gdb/regformats/reg-xtensa.dat create mode 100644 overlays/xtensa_nxp_rt600_adsp/gdb/gdb/xtensa-config.c create mode 100644 overlays/xtensa_nxp_rt600_adsp/gdb/gdb/xtensa-xtregs.c create mode 100644 overlays/xtensa_nxp_rt600_adsp/gdb/include/xtensa-config.h create mode 100644 overlays/xtensa_nxp_rt600_adsp/newlib/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 94d21346..ec694429 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -61,6 +61,7 @@ on: - xtensa-nxp_imx8m_adsp_zephyr-elf - xtensa-nxp_imx8ulp_adsp_zephyr-elf - xtensa-nxp_rt500_adsp_zephyr-elf + - xtensa-nxp_rt600_adsp_zephyr-elf - xtensa-sample_controller_zephyr-elf debug: description: 'Debug' @@ -173,6 +174,7 @@ jobs: xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";; xtensa-nxp_imx8ulp_adsp_zephyr-elf) build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf="y";; xtensa-nxp_rt500_adsp_zephyr-elf) build_target_xtensa_nxp_rt500_adsp_zephyr_elf="y";; + xtensa-nxp_rt600_adsp_zephyr-elf) build_target_xtensa_nxp_rt600_adsp_zephyr_elf="y";; xtensa-sample_controller_zephyr-elf) build_target_xtensa_sample_controller_zephyr_elf="y";; esac @@ -213,6 +215,7 @@ jobs: build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y" build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf="y" build_target_xtensa_nxp_rt500_adsp_zephyr_elf="y" + build_target_xtensa_nxp_rt600_adsp_zephyr_elf="y" build_target_xtensa_sample_controller_zephyr_elf="y" fi @@ -293,6 +296,7 @@ jobs: [ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",' [ "${build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8ulp_adsp_zephyr-elf",' [ "${build_target_xtensa_nxp_rt500_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_rt500_adsp_zephyr-elf",' + [ "${build_target_xtensa_nxp_rt600_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_rt600_adsp_zephyr-elf",' [ "${build_target_xtensa_sample_controller_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-sample_controller_zephyr-elf",' MATRIX_TARGETS+=']' diff --git a/configs/xtensa-nxp_rt600_adsp_zephyr-elf.config b/configs/xtensa-nxp_rt600_adsp_zephyr-elf.config new file mode 100644 index 00000000..5007cb9c --- /dev/null +++ b/configs/xtensa-nxp_rt600_adsp_zephyr-elf.config @@ -0,0 +1,9 @@ +CT_CONFIG_VERSION="3" +CT_EXPERIMENTAL=y +CT_OVERLAY_LOCATION="overlays" +CT_OVERLAY_NAME="nxp_rt600_adsp" +CT_ARCH_XTENSA=y +CT_XTENSA_CUSTOM=y +CT_TARGET_VENDOR="nxp_rt600_adsp_zephyr" +CT_TARGET_CFLAGS="-ftls-model=local-exec" +CT_CC_GCC_CONFIG_TLS=n diff --git a/overlays/xtensa_nxp_rt600_adsp/binutils/bfd/xtensa-modules.c b/overlays/xtensa_nxp_rt600_adsp/binutils/bfd/xtensa-modules.c new file mode 100644 index 00000000..069e19f5 --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/binutils/bfd/xtensa-modules.c @@ -0,0 +1,113469 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2023 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "ansidecl.h" +#include +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "MEMCTL", 97, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "PREFCTL", 40, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "AE_OVF_SAR", 240, 1 }, + { "AE_BITHEAD", 241, 1 }, + { "AE_TS_FTS_BU_BP", 242, 1 }, + { "AE_CW_SD_NO", 243, 1 }, + { "AE_CBEGIN0", 246, 1 }, + { "AE_CEND0", 247, 1 }, + { "AE_CBEGIN1", 248, 1 }, + { "AE_CEND1", 249, 1 }, + { "FCR_FSR", -1, 1 }, + { "F64R_LO", 234, 1 }, + { "F64R_HI", 235, 1 }, + { "F64S", 236, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 74 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 249 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "DDR", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "INTERRUPT", 32, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EPS2", 13, 0 }, + { "EPS3", 13, 0 }, + { "EPS4", 13, 0 }, + { "EPS5", 13, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "MEMCTL", 1, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 32, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "PREFCTL", 13, 0 }, + { "CPENABLE", 2, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, + { "AE_CBEGIN0", 32, 0 }, + { "AE_CEND0", 32, 0 }, + { "AE_CBEGIN1", 32, 0 }, + { "AE_CEND1", 32, 0 }, + { "AE_SAR", 14, 0 }, + { "AE_CWRAP", 1, 0 }, + { "AE_BITHEAD", 32, 0 }, + { "AE_BITPTR", 4, 0 }, + { "AE_BITSUSED", 4, 0 }, + { "AE_TABLESIZE", 4, 0 }, + { "AE_FIRST_TS", 4, 0 }, + { "AE_NEXTOFFSET", 27, 0 }, + { "AE_SEARCHDONE", 1, 0 }, + { "RoundMode", 2, 0 }, + { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "F64R", 64, 0 }, + { "F64S", 32, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 83 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_DDR, + STATE_ICOUNT, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_MEMCTL, + STATE_SAR, + STATE_THREADPTR, + STATE_MISC0, + STATE_MISC1, + STATE_ACC, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_PREFCTL, + STATE_CPENABLE, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_AE_OVERFLOW, + STATE_AE_CBEGIN0, + STATE_AE_CEND0, + STATE_AE_CBEGIN1, + STATE_AE_CEND1, + STATE_AE_SAR, + STATE_AE_CWRAP, + STATE_AE_BITHEAD, + STATE_AE_BITPTR, + STATE_AE_BITSUSED, + STATE_AE_TABLESIZE, + STATE_AE_FIRST_TS, + STATE_AE_NEXTOFFSET, + STATE_AE_SEARCHDONE, + STATE_RoundMode, + STATE_InvalidFlag, + STATE_DivZeroFlag, + STATE_OverflowFlag, + STATE_UnderflowFlag, + STATE_InexactFlag, + STATE_F64R, + STATE_F64S, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dfp_fld_op2_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_op2_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dfp_fld_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_dfp_fld_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dfp_fld_op2_3_2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_op2_3_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dfp_fld_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dfp_fld_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_dfp_fld_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dfp_fld_op2_3_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_op2_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_inst_15_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_inst_15_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_inst_7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_inst_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_inst_23_16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_inst_23_16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_inst_7_7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_inst_7_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_inst_4_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_inst_4_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_inst_5_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_inst_5_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_inst_7_6_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_inst_7_6_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_5_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_inst_5_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_13_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_inst_13_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_12_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_inst_12_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_inst_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_inst_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_inst_7_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_inst_7_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_inst_9_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_inst_9_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_9_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_inst_9_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_inst_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_inst_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_inst_19_17_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_inst_19_17_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_inst_19_18_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_inst_19_18_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_7_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_inst_7_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_3_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_inst_3_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_inst16b_15_13_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_ae_fld_inst16b_15_13_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_ae_fld_inst16b_12_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_ae_fld_inst16b_12_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 11) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 11) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 11) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_8_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot3_3_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot3_3_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot3_1_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_1_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_0_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot3_0_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_20_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 11) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot3_7_4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 11) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_13_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 11) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_14_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot3_11_4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot3_11_4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot3_11_11_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot3_11_11_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_slot3_20_15_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 11) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_15_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_20_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 11) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 11) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_14_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 11) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_10_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 11) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_12_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot2_7_4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_7_4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 11) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_8_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_3_2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_3_2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot2_7_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot2_7_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_3_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_8_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_20_4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 11) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot2_20_13_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 11) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_13_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot2_20_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 11) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_19_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_19_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot1_19_9_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_9_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot1_19_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_7_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_slot1_7_6_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_6_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 11) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 11) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_20_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 11) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 11) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_20_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 11) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_20_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 11) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_0_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_0_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_5_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_8_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_11_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_8_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_8_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_7_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_slot0_20_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 11) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 3) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 3) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 24) >> 25); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 10) >> 18); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 10) >> 22); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 10) >> 10); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 10) >> 12); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x3ffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 10) >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 18) >> 18); + return tie_t; +} + +static void +Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 4) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 4) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 10) >> 18); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 10) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 10) >> 10); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 10) >> 16); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 10) >> 14); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 18) >> 18); + return tie_t; +} + +static void +Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 17) >> 23); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 13) >> 13); + return tie_t; +} + +static void +Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 13) >> 13); + return tie_t; +} + +static void +Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_bbi_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_op2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 21) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0) | (tie_t << 4); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_t2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_t4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_s4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_s8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_fhba4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_fhba4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_fhba4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_fhba4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_fhba4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_fhba4_2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_fhba4_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_tp7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_tp7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_tp7_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_tp7_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_osa32_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_osa32_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_ae_fld_osa32_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_osa32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_osa32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_osa64_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa64_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_osa64_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa64_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ae_fld_osa64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_osa64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_imm2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_ae_fld_imm2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_ae_fld_imm2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_imm2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_immls64_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_osa16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_osa16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_osa16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_ls_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_su_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_su_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_su_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_su_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_su_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_av_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_cmpp_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmpp_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_cmpp_v1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmpp_v1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_cmpp_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmpp_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_uu_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_uu_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_uu_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_uu_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_uu_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_cmov_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_cmov_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_cmov_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_cmov_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_cmov_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_cmov_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_cmov_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_cmov_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_pks_d_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_d_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_pks_d_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_d_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_pks_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_pks_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_pks_s_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_s_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_pks_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_shift_d_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_shift_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_shift_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_shift_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_shift_d0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_shift_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_shift_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_shift_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_shift_sd_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_sd_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_shift_sd_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_sd_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_shift_sd_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_sd_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_selimm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_selimm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_selimm_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_selimm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_selimm_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_selimm_n_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_ae_fld_selimm_n_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_rng_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_d1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_d1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d2_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d2_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_d2_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_d2_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_v1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_v1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_acc_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_acc_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_acc_ep_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_acc_ep_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_shift_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_vr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_vr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_cmov_bt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_cmov_bt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_cmov_bt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_cmov_bt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_cmov_arr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_cmov_arr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_cmov_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_cmov_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_brt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_brt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_brt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_brt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vs_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vs_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_mov_i_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_i_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_mov_i_imm4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_i_imm4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vsm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vsm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_20_18_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 11) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_18_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vtm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vtm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_r_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dfp_fld_r_0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dfp_fld_r_0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dfp_fld_r_3_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_s_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_s_0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_s_0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_op2_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_op2_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dfp_fld_op2_1_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_op2_1_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_dfp_fld_op2_2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_op2_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_sigmoid_q15_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_sigmoid_q15_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_sigmoid_q15_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_sigmoid_q15_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_sigmoid_fp32_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_sigmoid_fp32_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_sigmoid_fp32_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_sigmoid_fp32_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_r_disp, + FIELD_r_3, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_r3, + FIELD_rbit2, + FIELD_rhi, + FIELD_t3, + FIELD_tbit2, + FIELD_tlo, + FIELD_w, + FIELD_y, + FIELD_x, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_s8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_ae_fld_fhba4, + FIELD_ae_fld_fhba4_2, + FIELD_ae_fld_tp7, + FIELD_ae_fld_osa32, + FIELD_ae_fld_osa64, + FIELD_ae_fld_imm2, + FIELD_ae_fld_immls64, + FIELD_ae_fld_immls64pos, + FIELD_ae_fld_immls64half, + FIELD_ae_fld_immls32, + FIELD_ae_fld_immls16, + FIELD_ae_fld_osa16, + FIELD_Inst_15_12, + FIELD_Inst_11_8, + FIELD_Inst_7_4, + FIELD_Inst_12, + FIELD_Inst_7, + FIELD_Inst_5_4, + FIELD_Inst_7_6, + FIELD_Inst_19_17, + FIELD_Inst_19_18, + FIELD_Inst_9_8, + FIELD_Inst_4, + FIELD_ae_fld_ls_v, + FIELD_ae_fld_ls_uu, + FIELD_ae_fld_ls_su, + FIELD_ae_fld_ls_av, + FIELD_ae_fld_ls_v1, + FIELD_ae_fld_ls_v2, + FIELD_ae_fld_cmpp_v0, + FIELD_ae_fld_cmpp_v1, + FIELD_ae_fld_cmpp_v, + FIELD_ae_fld_uu_v, + FIELD_ae_fld_uu_uu, + FIELD_ae_fld_dr_to_ar_v0, + FIELD_ae_fld_cmov_v, + FIELD_ae_fld_cmov_v0, + FIELD_ae_fld_pks_d, + FIELD_ae_fld_pks_s, + FIELD_ae_fld_shift_d, + FIELD_ae_fld_shift_d0, + FIELD_ae_fld_shift_sd, + FIELD_ae_fld_dr_to_dr_v, + FIELD_ae_fld_dr_to_dr_v0, + FIELD_ae_fld_dr_to_dr_v1, + FIELD_ae_fld_to_dr_v, + FIELD_ae_fld_to_dr_v0, + FIELD_fld_ae_immls64neg, + FIELD_ae_fld_selimm, + FIELD_ae_fld_selimm_N, + FIELD_fld_ar_to_dr_imm, + FIELD_ae_fld_arth_v, + FIELD_ae_fld_arth_v0, + FIELD_ae_fld_arth_v1, + FIELD_ae_fld_ar_to_dr_v, + FIELD_fld_Inst_23_12, + FIELD_fld_Inst_23_16, + FIELD_fld_Inst_7_7, + FIELD_fld_Inst_11_8, + FIELD_fld_Inst_13_8, + FIELD_fld_Inst_12_8, + FIELD_fld_Inst_9_8, + FIELD_fld_Inst_4_4, + FIELD_fld_Inst_5_4, + FIELD_fld_Inst_7_4, + FIELD_ae_fld_Inst16b_12, + FIELD_ae_fld_Inst16b_15_13, + FIELD_fld_ae4_slot0_7_4, + FIELD_fld_ae2_slot0_11_4, + FIELD_fld_ae2_slot0_7_4, + FIELD_fld_ae4_slot0_27_24, + FIELD_fld_ae2_slot0_11_9, + FIELD_fld_ae2_slot0_28_27, + FIELD_fld_ae4_slot0_27_23, + FIELD_fld_ae2_slot0_11_8, + FIELD_fld_ae5_slot0_21_8, + FIELD_fld_ae4_slot1_13_8, + FIELD_fld_ae3_slot1_19_8, + FIELD_fld_ae4_slot1_13_11, + FIELD_fld_ae5_slot0_3_0, + FIELD_fld_ae3_slot0_3_0, + FIELD_fld_ae3_slot1_3_0, + FIELD_fld_ae2_slot0_3_0, + FIELD_fld_ae2_slot1_3_0, + FIELD_fld_ae_slot0_3_0, + FIELD_fld_ae_slot1_3_0, + FIELD_fld_ae5_slot0_21_12, + FIELD_fld_ae4_slot1_13_12, + FIELD_fld_ae3_slot0_21_12, + FIELD_fld_ae3_slot1_19_12, + FIELD_fld_ae2_slot1_19_12, + FIELD_fld_ae_slot1_19_12, + FIELD_fld_ae5_slot0_21_16, + FIELD_fld_ae3_slot0_21_16, + FIELD_fld_ae3_slot1_19_16, + FIELD_fld_ae2_slot1_19_16, + FIELD_fld_ae_slot1_19_16, + FIELD_fld_ae5_slot0_21_17, + FIELD_fld_ae3_slot0_21_17, + FIELD_fld_ae3_slot1_19_17, + FIELD_fld_ae2_slot0_28_17, + FIELD_fld_ae2_slot1_19_17, + FIELD_fld_ae_slot1_19_17, + FIELD_fld_ae5_slot0_21_20, + FIELD_fld_ae3_slot0_21_20, + FIELD_fld_ae2_slot0_28_20, + FIELD_fld_ae5_slot0_7_4, + FIELD_fld_ae3_slot0_7_4, + FIELD_fld_ae7_slot0_15_0, + FIELD_fld_ae7_slot1_15_0, + FIELD_fld_ae7_slot2_18_0, + FIELD_fld_ae7_slot3_18_0, + FIELD_fld_ae6_slot0_15_0, + FIELD_fld_ae6_slot1_14_0, + FIELD_fld_ae6_slot2_13_0, + FIELD_fld_ae6_slot3_17_0, + FIELD_fld_ae5_slot0_21_0, + FIELD_fld_ae5_slot1_0_0, + FIELD_fld_ae5_slot2_19_0, + FIELD_fld_ae4_slot0_2_0, + FIELD_fld_ae4_slot0_27_3, + FIELD_fld_ae4_slot1_13_0, + FIELD_fld_ae3_slot0_21_0, + FIELD_fld_ae3_slot1_19_0, + FIELD_fld_ae2_slot1_19_0, + FIELD_fld_ae2_slot2_24_0, + FIELD_fld_ae_slot0_20_0, + FIELD_fld_ae_slot1_19_0, + FIELD_fld_ae_slot2_20_0, + FIELD_fld_ae3_slot1_7_4, + FIELD_fld_ae5_slot0_21_13, + FIELD_fld_ae3_slot0_21_13, + FIELD_fld_ae3_slot1_19_13, + FIELD_fld_ae2_slot0_28_13, + FIELD_fld_ae2_slot1_19_13, + FIELD_fld_ae_slot0_20_15, + FIELD_fld_ae_slot1_19_13, + FIELD_fld_ae_slot0_20_13, + FIELD_fld_ae3_slot1_19_4, + FIELD_fld_ae2_slot0_28_4, + FIELD_fld_ae2_slot1_19_4, + FIELD_fld_ae_slot0_20_4, + FIELD_fld_ae_slot1_19_4, + FIELD_fld_ae3_slot1_7_1, + FIELD_fld_ae2_slot1_19_9, + FIELD_fld_ae_slot1_19_9, + FIELD_fld_ae2_slot0_3_2, + FIELD_fld_ae_slot0_3_2, + FIELD_fld_ae2_slot0_0_0, + FIELD_fld_ae_slot0_0_0, + FIELD_fld_ae2_slot0_28_12, + FIELD_fld_ae_slot0_20_12, + FIELD_fld_ae7_slot0_7_4, + FIELD_fld_ae7_slot1_7_4, + FIELD_fld_ae5_slot0_11_8, + FIELD_fld_ae3_slot0_11_8, + FIELD_fld_ae5_slot0_21_6, + FIELD_fld_ae_sem_loads_stores_end, + FIELD_fld_ae2_slot1_7_4, + FIELD_fld_ae_slot1_7_4, + FIELD_fld_ae2_slot0_28_8, + FIELD_fld_ae2_slot1_19_8, + FIELD_fld_ae_slot0_20_8, + FIELD_fld_ae_slot1_19_8, + FIELD_fld_ae6_slot1_14_12, + FIELD_fld_ae6_slot2_3_0, + FIELD_fld_ae_sem_arithmetic_ds, + FIELD_fld_ae6_slot3_17_16, + FIELD_fld_ae_slot3_20_0, + FIELD_fld_ae_sem_rng_d, + FIELD_fld_ae_slot3_3_0, + FIELD_fld_ae3_slot0_8_8, + FIELD_fld_ae_slot0_8_8, + FIELD_fld_ae_slot3_1_0, + FIELD_fld_ae2_slot0_11_0, + FIELD_fld_ae_slot0_11_0, + FIELD_fld_ae2_slot1_7_0, + FIELD_fld_ae_slot0_7_0, + FIELD_fld_ae2_slot0_28_16, + FIELD_fld_ae_slot0_20_16, + FIELD_fld_ae_slot3_20_8, + FIELD_fld_ae2_slot0_9_4, + FIELD_fld_ae_slot0_9_4, + FIELD_fld_ae_sem_mul_x2_S1_d1, + FIELD_fld_ae_sem_mul_x2_S1_d0, + FIELD_fld_ae_sem_mul_x2_S1_q0, + FIELD_fld_ae_sem_mul_x2_S2_d1, + FIELD_fld_ae_sem_mul_x2_S2_d0, + FIELD_fld_ae_sem_mul_x2_S2_q0, + FIELD_fld_ae_sem_mul_x4_d1, + FIELD_fld_ae_sem_mul_x4_d0, + FIELD_fld_ae_sem_mul_x4_q0, + FIELD_fld_ae6_slot2_13_12, + FIELD_fld_ae_sem_mul_x4_q1, + FIELD_fld_ae2_slot2_24_16, + FIELD_fld_ae_sem_mul_x4_d2, + FIELD_fld_ae2_slot2_24_20, + FIELD_fld_ae7_slot2_18_16, + FIELD_fld_ae2_slot2_7_4, + FIELD_fld_ae7_slot3_18_16, + FIELD_fld_ae_sem_mul_x2_S1_d2, + FIELD_fld_ae_sem_mul_x2_S1_v1, + FIELD_fld_ae_sem_mul_x2_S2_d2, + FIELD_fld_ae_sem_mul_x2_S2_v1, + FIELD_fld_ae5_slot2_19_12, + FIELD_fld_ae_slot2_20_12, + FIELD_fld_ae_slot3_20_12, + FIELD_fld_ae5_slot0_21_4, + FIELD_fld_ae_sem_ep_ls_ei, + FIELD_fld_ae3_slot0_3_2, + FIELD_fld_ae3_slot1_3_2, + FIELD_fld_ae_sem_ep_ls_ar_s, + FIELD_fld_ae_sem_ep_ls_eo, + FIELD_fld_ae_slot2_7_0, + FIELD_fld_ae_slot3_11_4, + FIELD_fld_ae_sem_arithmetic_ep, + FIELD_fld_ae_slot2_3_0, + FIELD_fld_ae_sem_arithmetic_ep1, + FIELD_fld_ae_slot2_20_10, + FIELD_fld_ae_sem_mul_x2_S1_acc_ep, + FIELD_fld_ae_slot2_20_14, + FIELD_fld_ae_sem_mul_x2_S2_acc_ep, + FIELD_fld_ae_slot3_20_14, + FIELD_fld_ae_sem_shift_e, + FIELD_fld_ae_slot3_20_16, + FIELD_fld_ae_sem_shift_i8, + FIELD_fld_ae_slot3_11_11, + FIELD_fld_ae_sem_arithmetic_e, + FIELD_fld_ae_slot2_9_8, + FIELD_fld_ae_slot3_7_4, + FIELD_fld_ae_slot2_20_8, + FIELD_fld_ae_slot0_11_8, + FIELD_fld_ae_slot0_11_4, + FIELD_fld_ae_slot3_20_10, + FIELD_fld_ae_slot2_7_4, + FIELD_fld_ae2_slot0_8_4, + FIELD_fld_ae_slot0_8_4, + FIELD_fld_ae5_slot0_7_6, + FIELD_fld_ae3_slot0_5_4, + FIELD_fld_ae3_slot1_7_6, + FIELD_fld_ae2_slot1_7_6, + FIELD_fld_ae_slot1_7_6, + FIELD_fld_ae3_slot0_5_0, + FIELD_fld_ae3_slot0_4_0, + FIELD_fld_ae_slot0_4_0, + FIELD_fld_ae3_slot0_9_8, + FIELD_fld_ae_slot0_9_8, + FIELD_fld_ae7_slot0_15_12, + FIELD_fld_ae7_slot1_15_12, + FIELD_fld_ae5_slot0_5_4, + FIELD_fld_ae5_slot0_21_14, + FIELD_fld_ae3_slot0_7_6, + FIELD_fld_ae3_slot0_21_14, + FIELD_fld_ae7_slot0_7_7, + FIELD_fld_ae7_slot1_7_7, + FIELD_fld_ae6_slot1_7_7, + FIELD_fld_ae5_slot0_7_7, + FIELD_fld_ae3_slot0_5_5, + FIELD_fld_ae3_slot1_7_7, + FIELD_fld_ae2_slot0_4_4, + FIELD_fld_ae2_slot1_7_7, + FIELD_fld_ae_slot0_4_4, + FIELD_fld_ae_slot1_7_7, + FIELD_fld_ae6_slot0_15_12, + FIELD_fld_ae6_slot0_7_7, + FIELD_fld_ae7_slot0_7_6, + FIELD_fld_ae6_slot1_7_6, + FIELD_fld_ae6_slot1_14_6, + FIELD_fld_ae5_slot0_3_2, + FIELD_fld_ae3_slot0_5_2, + FIELD_fld_ae2_slot0_5_2, + FIELD_fld_ae_slot0_5_2, + FIELD_fld_ae3_slot0_21_2, + FIELD_fld_ae2_slot0_5_0, + FIELD_fld_ae_slot3_0_0, + FIELD_fld_ae_slot2_3_2, + FIELD_fld_ae_slot0_7_4, + FIELD_fld_ae2_slot0_7_0, + FIELD_fld_ae2_slot0_7_7, + FIELD_fld_ae_slot0_7_7, + FIELD_fld_ae_slot3_20_13, + FIELD_fld_ae2_slot0_5_4, + FIELD_fld_ae_slot0_5_4, + FIELD_fld_ae_slot3_13_12, + FIELD_fld_ae3_slot0_21_8, + FIELD_fld_ae_slot0_20_14, + FIELD_fld_ae_slot0_5_0, + FIELD_fld_ae3_slot0_21_4, + FIELD_fld_ae_sem_dr_to_ar_vr, + FIELD_fld_ae_sem_cmov_bt, + FIELD_fld_ae_sem_cmov_arr, + FIELD_fld_vfpu2_sem_mov_vt, + FIELD_fld_vfpu2_sem_mov_vr, + FIELD_fld_vfpu2_sem_spfma_vt, + FIELD_fld_vfpu2_sem_spfma_vs, + FIELD_fld_vfpu2_sem_spfma_vr, + FIELD_fld_vfpu2_sem_spmisc_brt, + FIELD_fld_vfpu2_sem_spmisc_vs, + FIELD_fld_vfpu2_sem_spmisc_vr, + FIELD_fld_vfpu2_sem_mov_i_imm4, + FIELD_fld_vfpu2_sem_sp32cvt_vr, + FIELD_fld_vfpu2_sem_sp32cvt_vt, + FIELD_fld_vfpu2_sem_sp32cvt_i_imm5, + FIELD_fld_vfpu2_sem_sp32cvt_arr, + FIELD_fld_ae_slot0_11_11, + FIELD_fld_vfpu2_sem_spmisc_vt, + FIELD_fld_vfpu2_sem_spmisc_vsM, + FIELD_fld_ae_slot2_20_18, + FIELD_fld_vfpu2_sem_spmisc_vtM, + FIELD_fld_vfpu2_sem_spfma_i_imm1, + FIELD_fld_vfpu2_sem_spfma_i_imm3, + FIELD_fld_ae_slot2_20_13, + FIELD_fld_ae_slot3_20_15, + FIELD_fld_ae_slot2_20_15, + FIELD_fld_ae_sem_movfpstate_v, + FIELD_fld_ae_slot2_20_4, + FIELD_dfp_fld_op1, + FIELD_dfp_fld_op2, + FIELD_dfp_fld_r_0, + FIELD_dfp_fld_r_2_1, + FIELD_dfp_fld_r_3, + FIELD_dfp_fld_r_3_1, + FIELD_dfp_fld_s_0, + FIELD_dfp_fld_s_3_1, + FIELD_dfp_fld_op2_0, + FIELD_dfp_fld_op2_1_0, + FIELD_dfp_fld_op2_2, + FIELD_dfp_fld_op2_3, + FIELD_dfp_fld_op2_3_2, + FIELD_dfp_fld_op2_3_1, + FIELD_bitindex, + FIELD_s3to1, + FIELD_fld_SIGMOID_Q15_x, + FIELD_fld_SIGMOID_Q15_y, + FIELD_fld_Inst_3_0, + FIELD_fld_SIGMOID_FP32_x, + FIELD_fld_SIGMOID_FP32_y, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__mr0, + FIELD__mr1, + FIELD__mr2, + FIELD__mr3, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + {"XT_LOADSTORE_UNIT", 2}, + { "mul_function", 1 }, + { "mul_S2_function", 1 }, + { "ae_add32x27", 1 }, + { "ae_shift32x4", 1 }, + { "ae_shift32x5", 1 }, + { "ae_leftshift32x5", 2 }, + { "ae_mulpp_32x32x2_1", 1 }, + { "ae_mulpp_32x32x2_2", 1 } +}; + +enum xtensa_funcUnit_id { + FUNCUNIT_XT_LOADSTORE_UNIT, + FUNCUNIT_mul_function, + FUNCUNIT_mul_S2_function, + FUNCUNIT_ae_add32x27, + FUNCUNIT_ae_shift32x4, + FUNCUNIT_ae_shift32x5, + FUNCUNIT_ae_leftshift32x5, + FUNCUNIT_ae_mulpp_32x32x2_1, + FUNCUNIT_ae_mulpp_32x32x2_2 +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_MR, + REGFILE_BR, + REGFILE_AE_DR, + REGFILE_AE_VALIGN, + REGFILE_AE_EP, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "MR", "m", REGFILE_MR, 32, 4 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "AE_DR", "aed", REGFILE_AE_DR, 64, 16 }, + { "AE_VALIGN", "u", REGFILE_AE_VALIGN, 64, 4 }, + { "AE_EP", "aep", REGFILE_AE_EP, 8, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "ERI_RD_Out", 14, 0, 0, 'o' }, + { "ERI_RD_In", 32, 0, 1, 'i' }, + { "ERI_RD_Rdy", 1, 0, 0, 'i' }, + { "ERI_WR_Out", 46, 0, 2, 'o' }, + { "ERI_WR_In", 1, 0, 3, 'i' }, + { "IMPWIRE", 32, 0, 4, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In, + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table bitmask8 */ +static const unsigned CONST_TBL_bitmask8_0[] = { + 0 & 0xff, + 0x1 & 0xff, + 0x3 & 0xff, + 0x7 & 0xff, + 0xf & 0xff, + 0x1f & 0xff, + 0x3f & 0xff, + 0x7f & 0xff, + 0 +}; + +/* constant table ae_ripimmtable */ +static const unsigned CONST_TBL_ae_ripimmtable_0[] = { + 0xffffffe0, + 0xffffffe8, + 0xfffffff0, + 0xfffffff8, + 0 +}; + +/* constant table ae_slai72table */ +static const unsigned CONST_TBL_ae_slai72table_0[] = { + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0 +}; + +/* constant table ae_seliencode */ +static const unsigned CONST_TBL_ae_seliencode_0[] = { + 0x4e5 & 0xfff, + 0x65 & 0xfff, + 0x77 & 0xfff, + 0x4f7 & 0xfff, + 0x72e & 0xfff, + 0x29c & 0xfff, + 0xaf & 0xfff, + 0xa6 & 0xfff, + 0x2ef & 0xfff, + 0x10d & 0xfff, + 0x599 & 0xfff, + 0x59f & 0xfff, + 0xb3e & 0xfff, + 0x18f & 0xfff, + 0x51d & 0xfff, + 0xa6 & 0xfff, + 0 +}; + +/* constant table xd_recip0_table128_8 */ +static const unsigned CONST_TBL_xd_recip0_table128_8_0[] = { + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf5 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf0 & 0xff, + 0xee & 0xff, + 0xed & 0xff, + 0xeb & 0xff, + 0xe9 & 0xff, + 0xe8 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xde & 0xff, + 0xdd & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd1 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb1 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xad & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa4 & 0xff, + 0xa3 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0 +}; + +/* constant table xd_rsqrt0_table128_8 */ +static const unsigned CONST_TBL_xd_rsqrt0_table128_8_0[] = { + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x80 & 0xff, + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf6 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf1 & 0xff, + 0xef & 0xff, + 0xed & 0xff, + 0xec & 0xff, + 0xea & 0xff, + 0xe9 & 0xff, + 0xe7 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xdf & 0xff, + 0xdd & 0xff, + 0xdc & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd6 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd2 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xce & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc9 & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc3 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0 +}; + +/* constant table vfpu2_table_mulmux */ +static const unsigned CONST_TBL_vfpu2_table_mulmux_0[] = { + 0xe & 0x3f, + 0x1e & 0x3f, + 0 +}; + +/* constant table vfpu2_table_maddmux */ +static const unsigned CONST_TBL_vfpu2_table_maddmux_0[] = { + 0xe & 0x3f, + 0x21 & 0x3f, + 0x3e & 0x3f, + 0x11 & 0x3f, + 0x1e & 0x3f, + 0x1 & 0x3f, + 0x2e & 0x3f, + 0x31 & 0x3f, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_MR_0_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +OperandSem_opnd_sem_MR_0_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_decode (uint32 *valp) +{ + unsigned immr_out_0; + unsigned immr_in_0; + immr_in_0 = *valp & 0xf; + immr_out_0 = immr_in_0; + *valp = immr_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_encode (uint32 *valp) +{ + unsigned immr_in_0; + unsigned immr_out_0; + immr_out_0 = *valp; + immr_in_0 = (immr_out_0 & 0xf); + *valp = immr_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_12_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_entry_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = ((0 << 4) | uimm4x16_in_0) << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = ((0 << 4) | uimmrx4_in_0) << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_1_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_2_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_3_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_5_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_imms_decode (uint32 *valp) +{ + unsigned imms_out_0; + unsigned imms_in_0; + imms_in_0 = *valp & 0xf; + imms_out_0 = imms_in_0; + *valp = imms_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_encode (uint32 *valp) +{ + unsigned imms_in_0; + unsigned imms_out_0; + imms_out_0 = *valp; + imms_in_0 = imms_out_0 & 0xf; + *valp = imms_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_out_0; + unsigned xt_wbr18_label_in_0; + xt_wbr18_label_in_0 = *valp & 0x3ffff; + xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); + *valp = xt_wbr18_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_label_in_0; + unsigned xt_wbr18_label_out_0; + xt_wbr18_label_out_0 = *valp; + xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64neg_decode (uint32 *valp) +{ + unsigned ae_immls64neg_out_0; + unsigned ae_immls64neg_in_0; + ae_immls64neg_in_0 = *valp & 0x3; + ae_immls64neg_out_0 = CONST_TBL_ae_ripimmtable_0[ae_immls64neg_in_0 & 0x3]; + *valp = ae_immls64neg_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64neg_encode (uint32 *valp) +{ + unsigned ae_immls64neg_in_0; + unsigned ae_immls64neg_out_0; + ae_immls64neg_out_0 = *valp; + ae_immls64neg_in_0 = (((ae_immls64neg_out_0 == (CONST_TBL_ae_ripimmtable_0[0]))) ? 0 : (((ae_immls64neg_out_0 == (CONST_TBL_ae_ripimmtable_0[1]))) ? 0x1 : (((ae_immls64neg_out_0 == (CONST_TBL_ae_ripimmtable_0[2]))) ? 0x2 : 0x3))) & 0x3; + *valp = ae_immls64neg_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64half_decode (uint32 *valp) +{ + unsigned ae_immls64half_out_0; + unsigned ae_immls64half_in_0; + ae_immls64half_in_0 = *valp & 0x7; + ae_immls64half_out_0 = (((int) ae_immls64half_in_0 << 29) >> 29) << 3; + *valp = ae_immls64half_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64half_encode (uint32 *valp) +{ + unsigned ae_immls64half_in_0; + unsigned ae_immls64half_out_0; + ae_immls64half_out_0 = *valp; + ae_immls64half_in_0 = ((ae_immls64half_out_0 >> 3) & 0x7); + *valp = ae_immls64half_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) +{ + unsigned ae_ohba_out_0; + unsigned ae_ohba_in_0; + ae_ohba_in_0 = *valp & 0xf; + ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); + *valp = ae_ohba_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) +{ + unsigned ae_ohba_in_0; + unsigned ae_ohba_out_0; + ae_ohba_out_0 = *valp; + ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); + *valp = ae_ohba_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_opnd_tp7_decode (uint32 *valp) +{ + unsigned ae_opnd_tp7_out_0; + unsigned ae_opnd_tp7_in_0; + ae_opnd_tp7_in_0 = *valp & 0xf; + ae_opnd_tp7_out_0 = ae_opnd_tp7_in_0 + 0x7; + *valp = ae_opnd_tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_opnd_tp7_encode (uint32 *valp) +{ + unsigned ae_opnd_tp7_in_0; + unsigned ae_opnd_tp7_out_0; + ae_opnd_tp7_out_0 = *valp; + ae_opnd_tp7_in_0 = (ae_opnd_tp7_out_0 - 0x7) & 0xf; + *valp = ae_opnd_tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_imm2_decode (uint32 *valp) +{ + unsigned ae_imm2_out_0; + unsigned ae_imm2_in_0; + ae_imm2_in_0 = *valp & 0x3; + ae_imm2_out_0 = (0 << 2) | ae_imm2_in_0; + *valp = ae_imm2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_imm2_encode (uint32 *valp) +{ + unsigned ae_imm2_in_0; + unsigned ae_imm2_out_0; + ae_imm2_out_0 = *valp; + ae_imm2_in_0 = (ae_imm2_out_0 & 0x3); + *valp = ae_imm2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa32_decode (uint32 *valp) +{ + unsigned ae_osa32_out_0; + unsigned ae_osa32_in_0; + ae_osa32_in_0 = *valp & 0x1f; + ae_osa32_out_0 = (0 << 5) | ae_osa32_in_0; + *valp = ae_osa32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa32_encode (uint32 *valp) +{ + unsigned ae_osa32_in_0; + unsigned ae_osa32_out_0; + ae_osa32_out_0 = *valp; + ae_osa32_in_0 = (ae_osa32_out_0 & 0x1f); + *valp = ae_osa32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa64_decode (uint32 *valp) +{ + unsigned ae_osa64_out_0; + unsigned ae_osa64_in_0; + ae_osa64_in_0 = *valp & 0x3f; + ae_osa64_out_0 = (0 << 6) | ae_osa64_in_0; + *valp = ae_osa64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa64_encode (uint32 *valp) +{ + unsigned ae_osa64_in_0; + unsigned ae_osa64_out_0; + ae_osa64_out_0 = *valp; + ae_osa64_in_0 = (ae_osa64_out_0 & 0x3f); + *valp = ae_osa64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64_decode (uint32 *valp) +{ + unsigned ae_immls64_out_0; + unsigned ae_immls64_in_0; + ae_immls64_in_0 = *valp & 0xf; + ae_immls64_out_0 = (((int) ae_immls64_in_0 << 28) >> 28) << 3; + *valp = ae_immls64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64_encode (uint32 *valp) +{ + unsigned ae_immls64_in_0; + unsigned ae_immls64_out_0; + ae_immls64_out_0 = *valp; + ae_immls64_in_0 = ((ae_immls64_out_0 >> 3) & 0xf); + *valp = ae_immls64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64pos_decode (uint32 *valp) +{ + unsigned ae_immls64pos_out_0; + unsigned ae_immls64pos_in_0; + ae_immls64pos_in_0 = *valp & 0x7; + ae_immls64pos_out_0 = ((0 << 3) | ae_immls64pos_in_0) << 3; + *valp = ae_immls64pos_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64pos_encode (uint32 *valp) +{ + unsigned ae_immls64pos_in_0; + unsigned ae_immls64pos_out_0; + ae_immls64pos_out_0 = *valp; + ae_immls64pos_in_0 = ((ae_immls64pos_out_0 >> 3) & 0x7); + *valp = ae_immls64pos_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls32_decode (uint32 *valp) +{ + unsigned ae_immls32_out_0; + unsigned ae_immls32_in_0; + ae_immls32_in_0 = *valp & 0xf; + ae_immls32_out_0 = (((int) ae_immls32_in_0 << 28) >> 28) << 2; + *valp = ae_immls32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls32_encode (uint32 *valp) +{ + unsigned ae_immls32_in_0; + unsigned ae_immls32_out_0; + ae_immls32_out_0 = *valp; + ae_immls32_in_0 = ((ae_immls32_out_0 >> 2) & 0xf); + *valp = ae_immls32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls16_decode (uint32 *valp) +{ + unsigned ae_immls16_out_0; + unsigned ae_immls16_in_0; + ae_immls16_in_0 = *valp & 0xf; + ae_immls16_out_0 = (((int) ae_immls16_in_0 << 28) >> 28) << 1; + *valp = ae_immls16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls16_encode (uint32 *valp) +{ + unsigned ae_immls16_in_0; + unsigned ae_immls16_out_0; + ae_immls16_out_0 = *valp; + ae_immls16_in_0 = ((ae_immls16_out_0 >> 1) & 0xf); + *valp = ae_immls16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa16_decode (uint32 *valp) +{ + unsigned ae_osa16_out_0; + unsigned ae_osa16_in_0; + ae_osa16_in_0 = *valp & 0xf; + ae_osa16_out_0 = (0 << 4) | ae_osa16_in_0; + *valp = ae_osa16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa16_encode (uint32 *valp) +{ + unsigned ae_osa16_in_0; + unsigned ae_osa16_out_0; + ae_osa16_out_0 = *valp; + ae_osa16_in_0 = (ae_osa16_out_0 & 0xf); + *valp = ae_osa16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_selimm_N_decode (uint32 *valp) +{ + unsigned ae_selimm_N_out_0; + unsigned ae_selimm_N_in_0; + ae_selimm_N_in_0 = *valp & 0x3; + ae_selimm_N_out_0 = (0 << 2) | ae_selimm_N_in_0; + *valp = ae_selimm_N_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_selimm_N_encode (uint32 *valp) +{ + unsigned ae_selimm_N_in_0; + unsigned ae_selimm_N_out_0; + ae_selimm_N_out_0 = *valp; + ae_selimm_N_in_0 = (ae_selimm_N_out_0 & 0x3); + *valp = ae_selimm_N_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_movi_imm_decode (uint32 *valp) +{ + unsigned movi_imm_out_0; + unsigned movi_imm_in_0; + movi_imm_in_0 = *valp & 0x3f; + movi_imm_out_0 = ((((-(( ( ((((movi_imm_in_0 >> 4) & 0x3)) | 0xfffffffc)) == 0xffffffff))) & 0x3ffffff)) << 6) | movi_imm_in_0; + *valp = movi_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_movi_imm_encode (uint32 *valp) +{ + unsigned movi_imm_in_0; + unsigned movi_imm_out_0; + movi_imm_out_0 = *valp; + movi_imm_in_0 = (movi_imm_out_0 & 0x3f); + *valp = movi_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_decode (uint32 *valp) +{ + unsigned ae_uimm2x2_out_0; + unsigned ae_uimm2x2_in_0; + ae_uimm2x2_in_0 = *valp & 0x1; + ae_uimm2x2_out_0 = (0 << 2) | (ae_uimm2x2_in_0 << 1) | 0; + *valp = ae_uimm2x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_encode (uint32 *valp) +{ + unsigned ae_uimm2x2_in_0; + unsigned ae_uimm2x2_out_0; + ae_uimm2x2_out_0 = *valp; + ae_uimm2x2_in_0 = (((ae_uimm2x2_out_0 >> 1) & 1)) & 0x1; + *valp = ae_uimm2x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_out_0; + unsigned opnd_ae_sem_shift_i8_in_0; + opnd_ae_sem_shift_i8_in_0 = *valp & 0x7; + opnd_ae_sem_shift_i8_out_0 = CONST_TBL_ae_slai72table_0[opnd_ae_sem_shift_i8_in_0 & 0x7]; + *valp = opnd_ae_sem_shift_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_in_0; + unsigned opnd_ae_sem_shift_i8_out_0; + opnd_ae_sem_shift_i8_out_0 = *valp; + switch (opnd_ae_sem_shift_i8_out_0) + { + case 0x1: opnd_ae_sem_shift_i8_in_0 = 0; break; + case 0x2: opnd_ae_sem_shift_i8_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_shift_i8_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_shift_i8_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_shift_i8_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_shift_i8_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_shift_i8_in_0 = 0x6; break; + default: opnd_ae_sem_shift_i8_in_0 = 0x7; break; + } + *valp = opnd_ae_sem_shift_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa2_decode (uint32 *valp) +{ + unsigned ae_osa2_out_0; + unsigned ae_osa2_in_0; + ae_osa2_in_0 = *valp & 0x1; + ae_osa2_out_0 = (0 << 1) | ae_osa2_in_0; + *valp = ae_osa2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa2_encode (uint32 *valp) +{ + unsigned ae_osa2_in_0; + unsigned ae_osa2_out_0; + ae_osa2_out_0 = *valp; + ae_osa2_in_0 = (((ae_osa2_out_0 >> 0) & 1)) & 0x1; + *valp = ae_osa2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa8_decode (uint32 *valp) +{ + unsigned ae_osa8_out_0; + unsigned ae_osa8_in_0; + ae_osa8_in_0 = *valp & 0x7; + ae_osa8_out_0 = (0 << 3) | ae_osa8_in_0; + *valp = ae_osa8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa8_encode (uint32 *valp) +{ + unsigned ae_osa8_in_0; + unsigned ae_osa8_out_0; + ae_osa8_out_0 = *valp; + ae_osa8_in_0 = (ae_osa8_out_0 & 0x7); + *valp = ae_osa8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_2_decode (uint32 *valp) +{ + unsigned dfp_fld_op2_2_out_0; + unsigned dfp_fld_op2_2_in_0; + dfp_fld_op2_2_in_0 = *valp & 0x1; + dfp_fld_op2_2_out_0 = (0 << 1) | dfp_fld_op2_2_in_0; + *valp = dfp_fld_op2_2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_2_encode (uint32 *valp) +{ + unsigned dfp_fld_op2_2_in_0; + unsigned dfp_fld_op2_2_out_0; + dfp_fld_op2_2_out_0 = *valp; + dfp_fld_op2_2_in_0 = (((dfp_fld_op2_2_out_0 >> 0) & 1)) & 0x1; + *valp = dfp_fld_op2_2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_1_0_decode (uint32 *valp) +{ + unsigned dfp_fld_op2_1_0_out_0; + unsigned dfp_fld_op2_1_0_in_0; + dfp_fld_op2_1_0_in_0 = *valp & 0x3; + dfp_fld_op2_1_0_out_0 = (0 << 2) | dfp_fld_op2_1_0_in_0; + *valp = dfp_fld_op2_1_0_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_1_0_encode (uint32 *valp) +{ + unsigned dfp_fld_op2_1_0_in_0; + unsigned dfp_fld_op2_1_0_out_0; + dfp_fld_op2_1_0_out_0 = *valp; + dfp_fld_op2_1_0_in_0 = (dfp_fld_op2_1_0_out_0 & 0x3); + *valp = dfp_fld_op2_1_0_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_decode (uint32 *valp) +{ + unsigned dfp_fld_op2_out_0; + unsigned dfp_fld_op2_in_0; + dfp_fld_op2_in_0 = *valp & 0xf; + dfp_fld_op2_out_0 = (0 << 4) | dfp_fld_op2_in_0; + *valp = dfp_fld_op2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_encode (uint32 *valp) +{ + unsigned dfp_fld_op2_in_0; + unsigned dfp_fld_op2_out_0; + dfp_fld_op2_out_0 = *valp; + dfp_fld_op2_in_0 = (dfp_fld_op2_out_0 & 0xf); + *valp = dfp_fld_op2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_decode (uint32 *valp) +{ + unsigned bitindex_out_0; + unsigned bitindex_in_0; + bitindex_in_0 = *valp & 0x1f; + bitindex_out_0 = (0 << 5) | bitindex_in_0; + *valp = bitindex_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_encode (uint32 *valp) +{ + unsigned bitindex_in_0; + unsigned bitindex_out_0; + bitindex_out_0 = *valp; + bitindex_in_0 = (bitindex_out_0 & 0x1f); + *valp = bitindex_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa, + -1, 0 }, + { "immr", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode, + 0, 0, + -1, 0 }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0, + -1, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0, + -1, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0, + 0, 31 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0, + 0, 31 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode, + 0, 0, + 0, 31 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode, + 0, 0, + 0, 31 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode, + 0, 0, + 0, 31 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0, + -1, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0, + -1, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0, + -1, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa, + -1, 0 }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0, + -1, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0, + -1, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0, + -1, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0, + -1, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0, + -1, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0, + -1, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0, + -1, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0, + -1, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0, + -1, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0, + -1, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0, + -1, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0, + -1, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0, + -1, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0, + -1, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa, + -1, 0 }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa, + -1, 0 }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa, + -1, 0 }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa, + -1, 0 }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa, + -1, 0 }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0, + -1, 0 }, + { "mx", FIELD_x, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, + 0, 0, + 0, 3 }, + { "my", FIELD_y, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, + 0, 0, + 0, 3 }, + { "mw", FIELD_w, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, + 0, 0, + 0, 3 }, + { "mr0", FIELD__mr0, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, + 0, 0, + 0, 3 }, + { "mr1", FIELD__mr1, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, + 0, 0, + 0, 3 }, + { "mr2", FIELD__mr2, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, + 0, 0, + 0, 3 }, + { "mr3", FIELD__mr3, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, + 0, 0, + 0, 3 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "imms1", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0, + -1, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa, + -1, 0 }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa, + -1, 0 }, + { "ae_immls64neg", FIELD_fld_ae_immls64neg, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls64neg_encode, OperandSem_opnd_sem_ae_immls64neg_decode, + 0, 0, + -1, 0 }, + { "ae_immls64half", FIELD_ae_fld_immls64half, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls64half_encode, OperandSem_opnd_sem_ae_immls64half_decode, + 0, 0, + -1, 0 }, + { "ae_ohba", FIELD_ae_fld_fhba4, -1, 0, + 0, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, + 0, 0, + -1, 0 }, + { "ae_ohba2", FIELD_ae_fld_fhba4_2, -1, 0, + 0, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, + 0, 0, + -1, 0 }, + { "ae_opnd_tp7", FIELD_ae_fld_tp7, -1, 0, + 0, + OperandSem_opnd_sem_ae_opnd_tp7_encode, OperandSem_opnd_sem_ae_opnd_tp7_decode, + 0, 0, + -1, 0 }, + { "ae_imm2", FIELD_ae_fld_imm2, -1, 0, + 0, + OperandSem_opnd_sem_ae_imm2_encode, OperandSem_opnd_sem_ae_imm2_decode, + 0, 0, + -1, 0 }, + { "ae_osa32", FIELD_ae_fld_osa32, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa32_encode, OperandSem_opnd_sem_ae_osa32_decode, + 0, 0, + -1, 0 }, + { "ae_osa64", FIELD_ae_fld_osa64, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa64_encode, OperandSem_opnd_sem_ae_osa64_decode, + 0, 0, + -1, 0 }, + { "ae_immls64", FIELD_ae_fld_immls64, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls64_encode, OperandSem_opnd_sem_ae_immls64_decode, + 0, 0, + -1, 0 }, + { "ae_immls64pos", FIELD_ae_fld_immls64pos, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls64pos_encode, OperandSem_opnd_sem_ae_immls64pos_decode, + 0, 0, + -1, 0 }, + { "ae_immls32", FIELD_ae_fld_immls32, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls32_encode, OperandSem_opnd_sem_ae_immls32_decode, + 0, 0, + -1, 0 }, + { "ae_immls16", FIELD_ae_fld_immls16, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls16_encode, OperandSem_opnd_sem_ae_immls16_decode, + 0, 0, + -1, 0 }, + { "ae_osa16", FIELD_ae_fld_osa16, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa16_encode, OperandSem_opnd_sem_ae_osa16_decode, + 0, 0, + -1, 0 }, + { "ae_selimm", FIELD_ae_fld_selimm, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa16_encode, OperandSem_opnd_sem_ae_osa16_decode, + 0, 0, + -1, 0 }, + { "ae_selimm.N", FIELD_ae_fld_selimm_N, -1, 0, + 0, + OperandSem_opnd_sem_ae_selimm_N_encode, OperandSem_opnd_sem_ae_selimm_N_decode, + 0, 0, + -1, 0 }, + { "movi_imm", FIELD_fld_ar_to_dr_imm, -1, 0, + 0, + OperandSem_opnd_sem_movi_imm_encode, OperandSem_opnd_sem_movi_imm_decode, + 0, 0, + -1, 0 }, + { "ae_arth_v", FIELD_ae_fld_arth_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_arth_v0", FIELD_ae_fld_arth_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_arth_v1", FIELD_ae_fld_arth_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ar_to_dr_v", FIELD_ae_fld_ar_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_to_dr_v", FIELD_ae_fld_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_to_dr_v0", FIELD_ae_fld_to_dr_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_dr_to_dr_v", FIELD_ae_fld_dr_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_dr_to_dr_v0", FIELD_ae_fld_dr_to_dr_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_dr_to_dr_v1", FIELD_ae_fld_dr_to_dr_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_v", FIELD_ae_fld_ls_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_av", FIELD_ae_fld_ls_av, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_v1", FIELD_ae_fld_ls_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_v2", FIELD_ae_fld_ls_v2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_uu", FIELD_ae_fld_ls_uu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "ae_ls_su", FIELD_ae_fld_ls_su, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "ae_uu_v", FIELD_ae_fld_uu_v, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "ae_uu_uu", FIELD_ae_fld_uu_uu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "ae_dr_to_ar_v0", FIELD_ae_fld_dr_to_ar_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_cmov_v", FIELD_ae_fld_cmov_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_cmov_v0", FIELD_ae_fld_cmov_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_pks_d", FIELD_ae_fld_pks_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_pks_s", FIELD_ae_fld_pks_s, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_shift_d", FIELD_ae_fld_shift_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_shift_d0", FIELD_ae_fld_shift_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_shift_sd", FIELD_ae_fld_shift_sd, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_uimm2x2", FIELD_ae_fld_Inst16b_12, -1, 0, + 0, + OperandSem_opnd_sem_ae_uimm2x2_encode, OperandSem_opnd_sem_ae_uimm2x2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_d1", FIELD_fld_ae_sem_mul_x2_S1_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_d0", FIELD_fld_ae_sem_mul_x2_S1_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_q0", FIELD_fld_ae_sem_mul_x2_S1_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_d1", FIELD_fld_ae_sem_mul_x2_S2_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_d0", FIELD_fld_ae_sem_mul_x2_S2_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_q0", FIELD_fld_ae_sem_mul_x2_S2_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_d1", FIELD_fld_ae_sem_mul_x4_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_d0", FIELD_fld_ae_sem_mul_x4_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_q0", FIELD_fld_ae_sem_mul_x4_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_q1", FIELD_fld_ae_sem_mul_x4_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_d2", FIELD_fld_ae_sem_mul_x4_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_d2", FIELD_fld_ae_sem_mul_x2_S1_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_v1", FIELD_fld_ae_sem_mul_x2_S1_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_d2", FIELD_fld_ae_sem_mul_x2_S2_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_v1", FIELD_fld_ae_sem_mul_x2_S2_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_ep_ls_ei", FIELD_fld_ae_sem_ep_ls_ei, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_ep_ls_ar_s", FIELD_fld_ae_sem_ep_ls_ar_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_ep_ls_eo", FIELD_fld_ae_sem_ep_ls_eo, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_mul_x2_S1_acc_ep", FIELD_fld_ae_sem_mul_x2_S1_acc_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_mul_x2_S2_acc_ep", FIELD_fld_ae_sem_mul_x2_S2_acc_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_cmov_bt", FIELD_fld_ae_sem_cmov_bt, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_cmov_arr", FIELD_fld_ae_sem_cmov_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_vfpu2_sem_mov_vt", FIELD_fld_vfpu2_sem_mov_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_mov_vr", FIELD_fld_vfpu2_sem_mov_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spfma_vt", FIELD_fld_vfpu2_sem_spfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spfma_vs", FIELD_fld_vfpu2_sem_spfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spfma_vr", FIELD_fld_vfpu2_sem_spfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spmisc_brt", FIELD_fld_vfpu2_sem_spmisc_brt, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spmisc_vs", FIELD_fld_vfpu2_sem_spmisc_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spmisc_vr", FIELD_fld_vfpu2_sem_spmisc_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_mov_i_imm4", FIELD_fld_vfpu2_sem_mov_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa16_encode, OperandSem_opnd_sem_ae_osa16_decode, + 0, 0, + -1, 0 }, + { "opnd_vfpu2_sem_spmisc_vt", FIELD_fld_vfpu2_sem_spmisc_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spmisc_vtM", FIELD_fld_vfpu2_sem_spmisc_vtM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_sp32cvt_vr", FIELD_fld_vfpu2_sem_sp32cvt_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_sp32cvt_vt", FIELD_fld_vfpu2_sem_sp32cvt_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_sp32cvt_i_imm5", FIELD_fld_vfpu2_sem_sp32cvt_i_imm5, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa32_encode, OperandSem_opnd_sem_ae_osa32_decode, + 0, 0, + -1, 0 }, + { "opnd_vfpu2_sem_sp32cvt_arr", FIELD_fld_vfpu2_sem_sp32cvt_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_vfpu2_sem_spmisc_vsM", FIELD_fld_vfpu2_sem_spmisc_vsM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spfma_i_imm1", FIELD_fld_vfpu2_sem_spfma_i_imm1, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa2_encode, OperandSem_opnd_sem_ae_osa2_decode, + 0, 0, + -1, 0 }, + { "opnd_vfpu2_sem_spfma_i_imm3", FIELD_fld_vfpu2_sem_spfma_i_imm3, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa8_encode, OperandSem_opnd_sem_ae_osa8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "dfp_fld_op2_2", FIELD_dfp_fld_op2_2, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_op2_1_0", FIELD_dfp_fld_op2_1_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_1_0_encode, OperandSem_opnd_sem_dfp_fld_op2_1_0_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_r_0", FIELD_dfp_fld_r_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_r_2_1", FIELD_dfp_fld_r_2_1, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_1_0_encode, OperandSem_opnd_sem_dfp_fld_op2_1_0_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_op2", FIELD_dfp_fld_op2, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_encode, OperandSem_opnd_sem_dfp_fld_op2_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_op2_0", FIELD_dfp_fld_op2_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_s_0", FIELD_dfp_fld_s_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0, + -1, 0 }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, + 0, 0, + -1, 0 }, + { "opnd_SIGMOID_Q15_x", FIELD_fld_SIGMOID_Q15_x, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_SIGMOID_Q15_y", FIELD_fld_SIGMOID_Q15_y, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_SIGMOID_FP32_x", FIELD_fld_SIGMOID_FP32_x, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_SIGMOID_FP32_y", FIELD_fld_SIGMOID_FP32_y, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 }, + { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, + { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, + { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, + { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_fhba4", FIELD_ae_fld_fhba4, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_fhba4_2", FIELD_ae_fld_fhba4_2, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_tp7", FIELD_ae_fld_tp7, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_osa32", FIELD_ae_fld_osa32, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_osa64", FIELD_ae_fld_osa64, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_imm2", FIELD_ae_fld_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls64", FIELD_ae_fld_immls64, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls64pos", FIELD_ae_fld_immls64pos, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls64half", FIELD_ae_fld_immls64half, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls32", FIELD_ae_fld_immls32, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls16", FIELD_ae_fld_immls16, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_osa16", FIELD_ae_fld_osa16, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_15_12", FIELD_Inst_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_11_8", FIELD_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_7_4", FIELD_Inst_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_12", FIELD_Inst_12, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_7", FIELD_Inst_7, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_5_4", FIELD_Inst_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_7_6", FIELD_Inst_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_19_17", FIELD_Inst_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_19_18", FIELD_Inst_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_9_8", FIELD_Inst_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_4", FIELD_Inst_4, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_v", FIELD_ae_fld_ls_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_uu", FIELD_ae_fld_ls_uu, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_su", FIELD_ae_fld_ls_su, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_av", FIELD_ae_fld_ls_av, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_v1", FIELD_ae_fld_ls_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_v2", FIELD_ae_fld_ls_v2, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmpp_v0", FIELD_ae_fld_cmpp_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmpp_v1", FIELD_ae_fld_cmpp_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmpp_v", FIELD_ae_fld_cmpp_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_uu_v", FIELD_ae_fld_uu_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_uu_uu", FIELD_ae_fld_uu_uu, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_dr_to_ar_v0", FIELD_ae_fld_dr_to_ar_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmov_v", FIELD_ae_fld_cmov_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmov_v0", FIELD_ae_fld_cmov_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_pks_d", FIELD_ae_fld_pks_d, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_pks_s", FIELD_ae_fld_pks_s, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_shift_d", FIELD_ae_fld_shift_d, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_shift_d0", FIELD_ae_fld_shift_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_shift_sd", FIELD_ae_fld_shift_sd, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_dr_to_dr_v", FIELD_ae_fld_dr_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_dr_to_dr_v0", FIELD_ae_fld_dr_to_dr_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_dr_to_dr_v1", FIELD_ae_fld_dr_to_dr_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_to_dr_v", FIELD_ae_fld_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_to_dr_v0", FIELD_ae_fld_to_dr_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_immls64neg", FIELD_fld_ae_immls64neg, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_selimm", FIELD_ae_fld_selimm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_selimm.N", FIELD_ae_fld_selimm_N, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ar_to_dr_imm", FIELD_fld_ar_to_dr_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_arth_v", FIELD_ae_fld_arth_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_arth_v0", FIELD_ae_fld_arth_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_arth_v1", FIELD_ae_fld_arth_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ar_to_dr_v", FIELD_ae_fld_ar_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_16", FIELD_fld_Inst_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_7", FIELD_fld_Inst_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_11_8", FIELD_fld_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_13_8", FIELD_fld_Inst_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_8", FIELD_fld_Inst_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_9_8", FIELD_fld_Inst_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_4_4", FIELD_fld_Inst_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_5_4", FIELD_fld_Inst_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_4", FIELD_fld_Inst_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_12", FIELD_ae_fld_Inst16b_12, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_15_13", FIELD_ae_fld_Inst16b_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_7_4", FIELD_fld_ae4_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_4", FIELD_fld_ae2_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_4", FIELD_fld_ae2_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_27_24", FIELD_fld_ae4_slot0_27_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_9", FIELD_fld_ae2_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_27", FIELD_fld_ae2_slot0_28_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_27_23", FIELD_fld_ae4_slot0_27_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_8", FIELD_fld_ae2_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_8", FIELD_fld_ae5_slot0_21_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_13_8", FIELD_fld_ae4_slot1_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_8", FIELD_fld_ae3_slot1_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_13_11", FIELD_fld_ae4_slot1_13_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_0", FIELD_fld_ae5_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_0", FIELD_fld_ae3_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_0", FIELD_fld_ae3_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_3_0", FIELD_fld_ae2_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_0", FIELD_fld_ae2_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_0", FIELD_fld_ae_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_0", FIELD_fld_ae_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_12", FIELD_fld_ae5_slot0_21_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_13_12", FIELD_fld_ae4_slot1_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_12", FIELD_fld_ae3_slot0_21_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_12", FIELD_fld_ae3_slot1_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_12", FIELD_fld_ae2_slot1_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_12", FIELD_fld_ae_slot1_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_16", FIELD_fld_ae5_slot0_21_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_16", FIELD_fld_ae3_slot0_21_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_16", FIELD_fld_ae3_slot1_19_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_16", FIELD_fld_ae2_slot1_19_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_16", FIELD_fld_ae_slot1_19_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_17", FIELD_fld_ae5_slot0_21_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_17", FIELD_fld_ae3_slot0_21_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_17", FIELD_fld_ae3_slot1_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_17", FIELD_fld_ae2_slot0_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_17", FIELD_fld_ae2_slot1_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_17", FIELD_fld_ae_slot1_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_20", FIELD_fld_ae5_slot0_21_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_20", FIELD_fld_ae3_slot0_21_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_20", FIELD_fld_ae2_slot0_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_4", FIELD_fld_ae5_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_4", FIELD_fld_ae3_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_15_0", FIELD_fld_ae7_slot0_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_15_0", FIELD_fld_ae7_slot1_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_18_0", FIELD_fld_ae7_slot2_18_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_18_0", FIELD_fld_ae7_slot3_18_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_15_0", FIELD_fld_ae6_slot0_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_0", FIELD_fld_ae6_slot1_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_13_0", FIELD_fld_ae6_slot2_13_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_17_0", FIELD_fld_ae6_slot3_17_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_0", FIELD_fld_ae5_slot0_21_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot1_0_0", FIELD_fld_ae5_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_19_0", FIELD_fld_ae5_slot2_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_2_0", FIELD_fld_ae4_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_27_3", FIELD_fld_ae4_slot0_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_13_0", FIELD_fld_ae4_slot1_13_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_0", FIELD_fld_ae3_slot0_21_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_0", FIELD_fld_ae3_slot1_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_0", FIELD_fld_ae2_slot1_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_0", FIELD_fld_ae2_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_0", FIELD_fld_ae_slot0_20_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_0", FIELD_fld_ae_slot1_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_0", FIELD_fld_ae_slot2_20_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_4", FIELD_fld_ae3_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_13", FIELD_fld_ae5_slot0_21_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_13", FIELD_fld_ae3_slot0_21_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_13", FIELD_fld_ae3_slot1_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_13", FIELD_fld_ae2_slot0_28_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_13", FIELD_fld_ae2_slot1_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_15", FIELD_fld_ae_slot0_20_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_13", FIELD_fld_ae_slot1_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_13", FIELD_fld_ae_slot0_20_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_4", FIELD_fld_ae3_slot1_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_4", FIELD_fld_ae2_slot0_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_4", FIELD_fld_ae2_slot1_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_4", FIELD_fld_ae_slot0_20_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_4", FIELD_fld_ae_slot1_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_1", FIELD_fld_ae3_slot1_7_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_9", FIELD_fld_ae2_slot1_19_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_9", FIELD_fld_ae_slot1_19_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_3_2", FIELD_fld_ae2_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_2", FIELD_fld_ae_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_0_0", FIELD_fld_ae2_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_0_0", FIELD_fld_ae_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_12", FIELD_fld_ae2_slot0_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_12", FIELD_fld_ae_slot0_20_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_4", FIELD_fld_ae7_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_4", FIELD_fld_ae7_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_8", FIELD_fld_ae5_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_8", FIELD_fld_ae3_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_6", FIELD_fld_ae5_slot0_21_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_4", FIELD_fld_ae2_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_4", FIELD_fld_ae_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_8", FIELD_fld_ae2_slot0_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_8", FIELD_fld_ae2_slot1_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_8", FIELD_fld_ae_slot0_20_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_8", FIELD_fld_ae_slot1_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_12", FIELD_fld_ae6_slot1_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_3_0", FIELD_fld_ae6_slot2_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_17_16", FIELD_fld_ae6_slot3_17_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_0", FIELD_fld_ae_slot3_20_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_3_0", FIELD_fld_ae_slot3_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_8_8", FIELD_fld_ae3_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_8_8", FIELD_fld_ae_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_1_0", FIELD_fld_ae_slot3_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_0", FIELD_fld_ae2_slot0_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_0", FIELD_fld_ae_slot0_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_0", FIELD_fld_ae2_slot1_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_0", FIELD_fld_ae_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_16", FIELD_fld_ae2_slot0_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_16", FIELD_fld_ae_slot0_20_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_8", FIELD_fld_ae_slot3_20_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_9_4", FIELD_fld_ae2_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_4", FIELD_fld_ae_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_d1", FIELD_fld_ae_sem_mul_x2_S1_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_d0", FIELD_fld_ae_sem_mul_x2_S1_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_q0", FIELD_fld_ae_sem_mul_x2_S1_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_d1", FIELD_fld_ae_sem_mul_x2_S2_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_d0", FIELD_fld_ae_sem_mul_x2_S2_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_q0", FIELD_fld_ae_sem_mul_x2_S2_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_d1", FIELD_fld_ae_sem_mul_x4_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_d0", FIELD_fld_ae_sem_mul_x4_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_q0", FIELD_fld_ae_sem_mul_x4_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_13_12", FIELD_fld_ae6_slot2_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_q1", FIELD_fld_ae_sem_mul_x4_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_16", FIELD_fld_ae2_slot2_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_d2", FIELD_fld_ae_sem_mul_x4_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_20", FIELD_fld_ae2_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_18_16", FIELD_fld_ae7_slot2_18_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_7_4", FIELD_fld_ae2_slot2_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_18_16", FIELD_fld_ae7_slot3_18_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_d2", FIELD_fld_ae_sem_mul_x2_S1_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_v1", FIELD_fld_ae_sem_mul_x2_S1_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_d2", FIELD_fld_ae_sem_mul_x2_S2_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_v1", FIELD_fld_ae_sem_mul_x2_S2_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_19_12", FIELD_fld_ae5_slot2_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_12", FIELD_fld_ae_slot2_20_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_12", FIELD_fld_ae_slot3_20_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_4", FIELD_fld_ae5_slot0_21_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_ep_ls_ei", FIELD_fld_ae_sem_ep_ls_ei, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_2", FIELD_fld_ae3_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_2", FIELD_fld_ae3_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_ep_ls_ar_s", FIELD_fld_ae_sem_ep_ls_ar_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_ep_ls_eo", FIELD_fld_ae_sem_ep_ls_eo, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_7_0", FIELD_fld_ae_slot2_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_11_4", FIELD_fld_ae_slot3_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_3_0", FIELD_fld_ae_slot2_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_10", FIELD_fld_ae_slot2_20_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_acc_ep", FIELD_fld_ae_sem_mul_x2_S1_acc_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_14", FIELD_fld_ae_slot2_20_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_acc_ep", FIELD_fld_ae_sem_mul_x2_S2_acc_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_14", FIELD_fld_ae_slot3_20_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_16", FIELD_fld_ae_slot3_20_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_11_11", FIELD_fld_ae_slot3_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_8", FIELD_fld_ae_slot2_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_7_4", FIELD_fld_ae_slot3_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_8", FIELD_fld_ae_slot2_20_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_8", FIELD_fld_ae_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_4", FIELD_fld_ae_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_10", FIELD_fld_ae_slot3_20_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_7_4", FIELD_fld_ae_slot2_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_8_4", FIELD_fld_ae2_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_8_4", FIELD_fld_ae_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_6", FIELD_fld_ae5_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_4", FIELD_fld_ae3_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_6", FIELD_fld_ae3_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_6", FIELD_fld_ae2_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_6", FIELD_fld_ae_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_0", FIELD_fld_ae3_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_0", FIELD_fld_ae3_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_0", FIELD_fld_ae_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_8", FIELD_fld_ae3_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_8", FIELD_fld_ae_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_15_12", FIELD_fld_ae7_slot0_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_15_12", FIELD_fld_ae7_slot1_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_5_4", FIELD_fld_ae5_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_14", FIELD_fld_ae5_slot0_21_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_6", FIELD_fld_ae3_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_14", FIELD_fld_ae3_slot0_21_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_7", FIELD_fld_ae7_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_7", FIELD_fld_ae7_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_7_7", FIELD_fld_ae6_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_7", FIELD_fld_ae5_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_5", FIELD_fld_ae3_slot0_5_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_7", FIELD_fld_ae3_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_4_4", FIELD_fld_ae2_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_7", FIELD_fld_ae2_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_4", FIELD_fld_ae_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_7", FIELD_fld_ae_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_15_12", FIELD_fld_ae6_slot0_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_7", FIELD_fld_ae6_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_6", FIELD_fld_ae7_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_7_6", FIELD_fld_ae6_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_6", FIELD_fld_ae6_slot1_14_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_2", FIELD_fld_ae5_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_2", FIELD_fld_ae3_slot0_5_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_5_2", FIELD_fld_ae2_slot0_5_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_2", FIELD_fld_ae_slot0_5_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_2", FIELD_fld_ae3_slot0_21_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_5_0", FIELD_fld_ae2_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_0_0", FIELD_fld_ae_slot3_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_3_2", FIELD_fld_ae_slot2_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_4", FIELD_fld_ae_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_0", FIELD_fld_ae2_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_7", FIELD_fld_ae2_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_7", FIELD_fld_ae_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_13", FIELD_fld_ae_slot3_20_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_5_4", FIELD_fld_ae2_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_4", FIELD_fld_ae_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_13_12", FIELD_fld_ae_slot3_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_8", FIELD_fld_ae3_slot0_21_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_14", FIELD_fld_ae_slot0_20_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_0", FIELD_fld_ae_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_4", FIELD_fld_ae3_slot0_21_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_cmov_bt", FIELD_fld_ae_sem_cmov_bt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_cmov_arr", FIELD_fld_ae_sem_cmov_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_mov_vt", FIELD_fld_vfpu2_sem_mov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_mov_vr", FIELD_fld_vfpu2_sem_mov_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_vt", FIELD_fld_vfpu2_sem_spfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_vs", FIELD_fld_vfpu2_sem_spfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_vr", FIELD_fld_vfpu2_sem_spfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_brt", FIELD_fld_vfpu2_sem_spmisc_brt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vs", FIELD_fld_vfpu2_sem_spmisc_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vr", FIELD_fld_vfpu2_sem_spmisc_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_mov_i_imm4", FIELD_fld_vfpu2_sem_mov_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_sp32cvt_vr", FIELD_fld_vfpu2_sem_sp32cvt_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_sp32cvt_vt", FIELD_fld_vfpu2_sem_sp32cvt_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_sp32cvt_i_imm5", FIELD_fld_vfpu2_sem_sp32cvt_i_imm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_sp32cvt_arr", FIELD_fld_vfpu2_sem_sp32cvt_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_11", FIELD_fld_ae_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vt", FIELD_fld_vfpu2_sem_spmisc_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vsM", FIELD_fld_vfpu2_sem_spmisc_vsM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_18", FIELD_fld_ae_slot2_20_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vtM", FIELD_fld_vfpu2_sem_spmisc_vtM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_i_imm1", FIELD_fld_vfpu2_sem_spfma_i_imm1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_i_imm3", FIELD_fld_vfpu2_sem_spfma_i_imm3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_13", FIELD_fld_ae_slot2_20_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_15", FIELD_fld_ae_slot3_20_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_15", FIELD_fld_ae_slot2_20_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_4", FIELD_fld_ae_slot2_20_4, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op1", FIELD_dfp_fld_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_r_3", FIELD_dfp_fld_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_r_3_1", FIELD_dfp_fld_r_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_s_3_1", FIELD_dfp_fld_s_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op2_3", FIELD_dfp_fld_op2_3, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op2_3_2", FIELD_dfp_fld_op2_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op2_3_1", FIELD_dfp_fld_op2_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_SIGMOID_Q15_x", FIELD_fld_SIGMOID_Q15_x, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_SIGMOID_Q15_y", FIELD_fld_SIGMOID_Q15_y, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_3_0", FIELD_fld_Inst_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_SIGMOID_FP32_x", FIELD_fld_SIGMOID_FP32_x, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_SIGMOID_FP32_y", FIELD_fld_SIGMOID_FP32_y, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_immr, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_immt, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_mx, + OPERAND_my, + OPERAND_mw, + OPERAND_mr0, + OPERAND_mr1, + OPERAND_mr2, + OPERAND_mr3, + OPERAND_imms, + OPERAND_imms1, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_ae_immls64neg, + OPERAND_ae_immls64half, + OPERAND_ae_ohba, + OPERAND_ae_ohba2, + OPERAND_ae_opnd_tp7, + OPERAND_ae_imm2, + OPERAND_ae_osa32, + OPERAND_ae_osa64, + OPERAND_ae_immls64, + OPERAND_ae_immls64pos, + OPERAND_ae_immls32, + OPERAND_ae_immls16, + OPERAND_ae_osa16, + OPERAND_ae_selimm, + OPERAND_ae_selimm_N, + OPERAND_movi_imm, + OPERAND_ae_arth_v, + OPERAND_ae_arth_v0, + OPERAND_ae_arth_v1, + OPERAND_ae_ar_to_dr_v, + OPERAND_ae_to_dr_v, + OPERAND_ae_to_dr_v0, + OPERAND_ae_dr_to_dr_v, + OPERAND_ae_dr_to_dr_v0, + OPERAND_ae_dr_to_dr_v1, + OPERAND_ae_ls_v, + OPERAND_ae_ls_av, + OPERAND_ae_ls_v1, + OPERAND_ae_ls_v2, + OPERAND_ae_ls_uu, + OPERAND_ae_ls_su, + OPERAND_ae_uu_v, + OPERAND_ae_uu_uu, + OPERAND_ae_dr_to_ar_v0, + OPERAND_ae_cmov_v, + OPERAND_ae_cmov_v0, + OPERAND_ae_pks_d, + OPERAND_ae_pks_s, + OPERAND_ae_shift_d, + OPERAND_ae_shift_d0, + OPERAND_ae_shift_sd, + OPERAND_ae_uimm2x2, + OPERAND_opnd_ae_sem_loads_stores_end, + OPERAND_opnd_ae_sem_arithmetic_ds, + OPERAND_opnd_ae_sem_rng_d, + OPERAND_opnd_ae_sem_mul_x2_S1_d1, + OPERAND_opnd_ae_sem_mul_x2_S1_d0, + OPERAND_opnd_ae_sem_mul_x2_S1_q0, + OPERAND_opnd_ae_sem_mul_x2_S2_d1, + OPERAND_opnd_ae_sem_mul_x2_S2_d0, + OPERAND_opnd_ae_sem_mul_x2_S2_q0, + OPERAND_opnd_ae_sem_mul_x4_d1, + OPERAND_opnd_ae_sem_mul_x4_d0, + OPERAND_opnd_ae_sem_mul_x4_q0, + OPERAND_opnd_ae_sem_mul_x4_q1, + OPERAND_opnd_ae_sem_mul_x4_d2, + OPERAND_opnd_ae_sem_mul_x2_S1_d2, + OPERAND_opnd_ae_sem_mul_x2_S1_v1, + OPERAND_opnd_ae_sem_mul_x2_S2_d2, + OPERAND_opnd_ae_sem_mul_x2_S2_v1, + OPERAND_opnd_ae_sem_ep_ls_ei, + OPERAND_opnd_ae_sem_ep_ls_ar_s, + OPERAND_opnd_ae_sem_ep_ls_eo, + OPERAND_opnd_ae_sem_arithmetic_ep, + OPERAND_opnd_ae_sem_arithmetic_ep1, + OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep, + OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep, + OPERAND_opnd_ae_sem_shift_e, + OPERAND_opnd_ae_sem_shift_i8, + OPERAND_opnd_ae_sem_arithmetic_e, + OPERAND_opnd_ae_sem_dr_to_ar_vr, + OPERAND_opnd_ae_sem_cmov_bt, + OPERAND_opnd_ae_sem_cmov_arr, + OPERAND_opnd_vfpu2_sem_mov_vt, + OPERAND_opnd_vfpu2_sem_mov_vr, + OPERAND_opnd_vfpu2_sem_spfma_vt, + OPERAND_opnd_vfpu2_sem_spfma_vs, + OPERAND_opnd_vfpu2_sem_spfma_vr, + OPERAND_opnd_vfpu2_sem_spmisc_brt, + OPERAND_opnd_vfpu2_sem_spmisc_vs, + OPERAND_opnd_vfpu2_sem_spmisc_vr, + OPERAND_opnd_vfpu2_sem_mov_i_imm4, + OPERAND_opnd_vfpu2_sem_spmisc_vt, + OPERAND_opnd_vfpu2_sem_spmisc_vtM, + OPERAND_opnd_vfpu2_sem_sp32cvt_vr, + OPERAND_opnd_vfpu2_sem_sp32cvt_vt, + OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5, + OPERAND_opnd_vfpu2_sem_sp32cvt_arr, + OPERAND_opnd_vfpu2_sem_spmisc_vsM, + OPERAND_opnd_vfpu2_sem_spfma_i_imm1, + OPERAND_opnd_vfpu2_sem_spfma_i_imm3, + OPERAND_opnd_ae_sem_movfpstate_v, + OPERAND_dfp_fld_op2_2, + OPERAND_dfp_fld_op2_1_0, + OPERAND_dfp_fld_r_0, + OPERAND_dfp_fld_r_2_1, + OPERAND_dfp_fld_op2, + OPERAND_dfp_fld_op2_0, + OPERAND_dfp_fld_s_0, + OPERAND_bitindex, + OPERAND_opnd_SIGMOID_Q15_x, + OPERAND_opnd_SIGMOID_Q15_y, + OPERAND_opnd_SIGMOID_FP32_x, + OPERAND_opnd_SIGMOID_FP32_y, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_r_disp, + OPERAND_r_3, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_r3, + OPERAND_rbit2, + OPERAND_rhi, + OPERAND_t3, + OPERAND_tbit2, + OPERAND_tlo, + OPERAND_w, + OPERAND_y, + OPERAND_x, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_s8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_ae_fld_fhba4, + OPERAND_ae_fld_fhba4_2, + OPERAND_ae_fld_tp7, + OPERAND_ae_fld_osa32, + OPERAND_ae_fld_osa64, + OPERAND_ae_fld_imm2, + OPERAND_ae_fld_immls64, + OPERAND_ae_fld_immls64pos, + OPERAND_ae_fld_immls64half, + OPERAND_ae_fld_immls32, + OPERAND_ae_fld_immls16, + OPERAND_ae_fld_osa16, + OPERAND_Inst_15_12, + OPERAND_Inst_11_8, + OPERAND_Inst_7_4, + OPERAND_Inst_12, + OPERAND_Inst_7, + OPERAND_Inst_5_4, + OPERAND_Inst_7_6, + OPERAND_Inst_19_17, + OPERAND_Inst_19_18, + OPERAND_Inst_9_8, + OPERAND_Inst_4, + OPERAND_ae_fld_ls_v, + OPERAND_ae_fld_ls_uu, + OPERAND_ae_fld_ls_su, + OPERAND_ae_fld_ls_av, + OPERAND_ae_fld_ls_v1, + OPERAND_ae_fld_ls_v2, + OPERAND_ae_fld_cmpp_v0, + OPERAND_ae_fld_cmpp_v1, + OPERAND_ae_fld_cmpp_v, + OPERAND_ae_fld_uu_v, + OPERAND_ae_fld_uu_uu, + OPERAND_ae_fld_dr_to_ar_v0, + OPERAND_ae_fld_cmov_v, + OPERAND_ae_fld_cmov_v0, + OPERAND_ae_fld_pks_d, + OPERAND_ae_fld_pks_s, + OPERAND_ae_fld_shift_d, + OPERAND_ae_fld_shift_d0, + OPERAND_ae_fld_shift_sd, + OPERAND_ae_fld_dr_to_dr_v, + OPERAND_ae_fld_dr_to_dr_v0, + OPERAND_ae_fld_dr_to_dr_v1, + OPERAND_ae_fld_to_dr_v, + OPERAND_ae_fld_to_dr_v0, + OPERAND_fld_ae_immls64neg, + OPERAND_ae_fld_selimm, + OPERAND_ae_fld_selimm_N, + OPERAND_fld_ar_to_dr_imm, + OPERAND_ae_fld_arth_v, + OPERAND_ae_fld_arth_v0, + OPERAND_ae_fld_arth_v1, + OPERAND_ae_fld_ar_to_dr_v, + OPERAND_fld_Inst_23_12, + OPERAND_fld_Inst_23_16, + OPERAND_fld_Inst_7_7, + OPERAND_fld_Inst_11_8, + OPERAND_fld_Inst_13_8, + OPERAND_fld_Inst_12_8, + OPERAND_fld_Inst_9_8, + OPERAND_fld_Inst_4_4, + OPERAND_fld_Inst_5_4, + OPERAND_fld_Inst_7_4, + OPERAND_ae_fld_Inst16b_12, + OPERAND_ae_fld_Inst16b_15_13, + OPERAND_fld_ae4_slot0_7_4, + OPERAND_fld_ae2_slot0_11_4, + OPERAND_fld_ae2_slot0_7_4, + OPERAND_fld_ae4_slot0_27_24, + OPERAND_fld_ae2_slot0_11_9, + OPERAND_fld_ae2_slot0_28_27, + OPERAND_fld_ae4_slot0_27_23, + OPERAND_fld_ae2_slot0_11_8, + OPERAND_fld_ae5_slot0_21_8, + OPERAND_fld_ae4_slot1_13_8, + OPERAND_fld_ae3_slot1_19_8, + OPERAND_fld_ae4_slot1_13_11, + OPERAND_fld_ae5_slot0_3_0, + OPERAND_fld_ae3_slot0_3_0, + OPERAND_fld_ae3_slot1_3_0, + OPERAND_fld_ae2_slot0_3_0, + OPERAND_fld_ae2_slot1_3_0, + OPERAND_fld_ae_slot0_3_0, + OPERAND_fld_ae_slot1_3_0, + OPERAND_fld_ae5_slot0_21_12, + OPERAND_fld_ae4_slot1_13_12, + OPERAND_fld_ae3_slot0_21_12, + OPERAND_fld_ae3_slot1_19_12, + OPERAND_fld_ae2_slot1_19_12, + OPERAND_fld_ae_slot1_19_12, + OPERAND_fld_ae5_slot0_21_16, + OPERAND_fld_ae3_slot0_21_16, + OPERAND_fld_ae3_slot1_19_16, + OPERAND_fld_ae2_slot1_19_16, + OPERAND_fld_ae_slot1_19_16, + OPERAND_fld_ae5_slot0_21_17, + OPERAND_fld_ae3_slot0_21_17, + OPERAND_fld_ae3_slot1_19_17, + OPERAND_fld_ae2_slot0_28_17, + OPERAND_fld_ae2_slot1_19_17, + OPERAND_fld_ae_slot1_19_17, + OPERAND_fld_ae5_slot0_21_20, + OPERAND_fld_ae3_slot0_21_20, + OPERAND_fld_ae2_slot0_28_20, + OPERAND_fld_ae5_slot0_7_4, + OPERAND_fld_ae3_slot0_7_4, + OPERAND_fld_ae7_slot0_15_0, + OPERAND_fld_ae7_slot1_15_0, + OPERAND_fld_ae7_slot2_18_0, + OPERAND_fld_ae7_slot3_18_0, + OPERAND_fld_ae6_slot0_15_0, + OPERAND_fld_ae6_slot1_14_0, + OPERAND_fld_ae6_slot2_13_0, + OPERAND_fld_ae6_slot3_17_0, + OPERAND_fld_ae5_slot0_21_0, + OPERAND_fld_ae5_slot1_0_0, + OPERAND_fld_ae5_slot2_19_0, + OPERAND_fld_ae4_slot0_2_0, + OPERAND_fld_ae4_slot0_27_3, + OPERAND_fld_ae4_slot1_13_0, + OPERAND_fld_ae3_slot0_21_0, + OPERAND_fld_ae3_slot1_19_0, + OPERAND_fld_ae2_slot1_19_0, + OPERAND_fld_ae2_slot2_24_0, + OPERAND_fld_ae_slot0_20_0, + OPERAND_fld_ae_slot1_19_0, + OPERAND_fld_ae_slot2_20_0, + OPERAND_fld_ae3_slot1_7_4, + OPERAND_fld_ae5_slot0_21_13, + OPERAND_fld_ae3_slot0_21_13, + OPERAND_fld_ae3_slot1_19_13, + OPERAND_fld_ae2_slot0_28_13, + OPERAND_fld_ae2_slot1_19_13, + OPERAND_fld_ae_slot0_20_15, + OPERAND_fld_ae_slot1_19_13, + OPERAND_fld_ae_slot0_20_13, + OPERAND_fld_ae3_slot1_19_4, + OPERAND_fld_ae2_slot0_28_4, + OPERAND_fld_ae2_slot1_19_4, + OPERAND_fld_ae_slot0_20_4, + OPERAND_fld_ae_slot1_19_4, + OPERAND_fld_ae3_slot1_7_1, + OPERAND_fld_ae2_slot1_19_9, + OPERAND_fld_ae_slot1_19_9, + OPERAND_fld_ae2_slot0_3_2, + OPERAND_fld_ae_slot0_3_2, + OPERAND_fld_ae2_slot0_0_0, + OPERAND_fld_ae_slot0_0_0, + OPERAND_fld_ae2_slot0_28_12, + OPERAND_fld_ae_slot0_20_12, + OPERAND_fld_ae7_slot0_7_4, + OPERAND_fld_ae7_slot1_7_4, + OPERAND_fld_ae5_slot0_11_8, + OPERAND_fld_ae3_slot0_11_8, + OPERAND_fld_ae5_slot0_21_6, + OPERAND_fld_ae_sem_loads_stores_end, + OPERAND_fld_ae2_slot1_7_4, + OPERAND_fld_ae_slot1_7_4, + OPERAND_fld_ae2_slot0_28_8, + OPERAND_fld_ae2_slot1_19_8, + OPERAND_fld_ae_slot0_20_8, + OPERAND_fld_ae_slot1_19_8, + OPERAND_fld_ae6_slot1_14_12, + OPERAND_fld_ae6_slot2_3_0, + OPERAND_fld_ae_sem_arithmetic_ds, + OPERAND_fld_ae6_slot3_17_16, + OPERAND_fld_ae_slot3_20_0, + OPERAND_fld_ae_sem_rng_d, + OPERAND_fld_ae_slot3_3_0, + OPERAND_fld_ae3_slot0_8_8, + OPERAND_fld_ae_slot0_8_8, + OPERAND_fld_ae_slot3_1_0, + OPERAND_fld_ae2_slot0_11_0, + OPERAND_fld_ae_slot0_11_0, + OPERAND_fld_ae2_slot1_7_0, + OPERAND_fld_ae_slot0_7_0, + OPERAND_fld_ae2_slot0_28_16, + OPERAND_fld_ae_slot0_20_16, + OPERAND_fld_ae_slot3_20_8, + OPERAND_fld_ae2_slot0_9_4, + OPERAND_fld_ae_slot0_9_4, + OPERAND_fld_ae_sem_mul_x2_S1_d1, + OPERAND_fld_ae_sem_mul_x2_S1_d0, + OPERAND_fld_ae_sem_mul_x2_S1_q0, + OPERAND_fld_ae_sem_mul_x2_S2_d1, + OPERAND_fld_ae_sem_mul_x2_S2_d0, + OPERAND_fld_ae_sem_mul_x2_S2_q0, + OPERAND_fld_ae_sem_mul_x4_d1, + OPERAND_fld_ae_sem_mul_x4_d0, + OPERAND_fld_ae_sem_mul_x4_q0, + OPERAND_fld_ae6_slot2_13_12, + OPERAND_fld_ae_sem_mul_x4_q1, + OPERAND_fld_ae2_slot2_24_16, + OPERAND_fld_ae_sem_mul_x4_d2, + OPERAND_fld_ae2_slot2_24_20, + OPERAND_fld_ae7_slot2_18_16, + OPERAND_fld_ae2_slot2_7_4, + OPERAND_fld_ae7_slot3_18_16, + OPERAND_fld_ae_sem_mul_x2_S1_d2, + OPERAND_fld_ae_sem_mul_x2_S1_v1, + OPERAND_fld_ae_sem_mul_x2_S2_d2, + OPERAND_fld_ae_sem_mul_x2_S2_v1, + OPERAND_fld_ae5_slot2_19_12, + OPERAND_fld_ae_slot2_20_12, + OPERAND_fld_ae_slot3_20_12, + OPERAND_fld_ae5_slot0_21_4, + OPERAND_fld_ae_sem_ep_ls_ei, + OPERAND_fld_ae3_slot0_3_2, + OPERAND_fld_ae3_slot1_3_2, + OPERAND_fld_ae_sem_ep_ls_ar_s, + OPERAND_fld_ae_sem_ep_ls_eo, + OPERAND_fld_ae_slot2_7_0, + OPERAND_fld_ae_slot3_11_4, + OPERAND_fld_ae_sem_arithmetic_ep, + OPERAND_fld_ae_slot2_3_0, + OPERAND_fld_ae_sem_arithmetic_ep1, + OPERAND_fld_ae_slot2_20_10, + OPERAND_fld_ae_sem_mul_x2_S1_acc_ep, + OPERAND_fld_ae_slot2_20_14, + OPERAND_fld_ae_sem_mul_x2_S2_acc_ep, + OPERAND_fld_ae_slot3_20_14, + OPERAND_fld_ae_sem_shift_e, + OPERAND_fld_ae_slot3_20_16, + OPERAND_fld_ae_sem_shift_i8, + OPERAND_fld_ae_slot3_11_11, + OPERAND_fld_ae_sem_arithmetic_e, + OPERAND_fld_ae_slot2_9_8, + OPERAND_fld_ae_slot3_7_4, + OPERAND_fld_ae_slot2_20_8, + OPERAND_fld_ae_slot0_11_8, + OPERAND_fld_ae_slot0_11_4, + OPERAND_fld_ae_slot3_20_10, + OPERAND_fld_ae_slot2_7_4, + OPERAND_fld_ae2_slot0_8_4, + OPERAND_fld_ae_slot0_8_4, + OPERAND_fld_ae5_slot0_7_6, + OPERAND_fld_ae3_slot0_5_4, + OPERAND_fld_ae3_slot1_7_6, + OPERAND_fld_ae2_slot1_7_6, + OPERAND_fld_ae_slot1_7_6, + OPERAND_fld_ae3_slot0_5_0, + OPERAND_fld_ae3_slot0_4_0, + OPERAND_fld_ae_slot0_4_0, + OPERAND_fld_ae3_slot0_9_8, + OPERAND_fld_ae_slot0_9_8, + OPERAND_fld_ae7_slot0_15_12, + OPERAND_fld_ae7_slot1_15_12, + OPERAND_fld_ae5_slot0_5_4, + OPERAND_fld_ae5_slot0_21_14, + OPERAND_fld_ae3_slot0_7_6, + OPERAND_fld_ae3_slot0_21_14, + OPERAND_fld_ae7_slot0_7_7, + OPERAND_fld_ae7_slot1_7_7, + OPERAND_fld_ae6_slot1_7_7, + OPERAND_fld_ae5_slot0_7_7, + OPERAND_fld_ae3_slot0_5_5, + OPERAND_fld_ae3_slot1_7_7, + OPERAND_fld_ae2_slot0_4_4, + OPERAND_fld_ae2_slot1_7_7, + OPERAND_fld_ae_slot0_4_4, + OPERAND_fld_ae_slot1_7_7, + OPERAND_fld_ae6_slot0_15_12, + OPERAND_fld_ae6_slot0_7_7, + OPERAND_fld_ae7_slot0_7_6, + OPERAND_fld_ae6_slot1_7_6, + OPERAND_fld_ae6_slot1_14_6, + OPERAND_fld_ae5_slot0_3_2, + OPERAND_fld_ae3_slot0_5_2, + OPERAND_fld_ae2_slot0_5_2, + OPERAND_fld_ae_slot0_5_2, + OPERAND_fld_ae3_slot0_21_2, + OPERAND_fld_ae2_slot0_5_0, + OPERAND_fld_ae_slot3_0_0, + OPERAND_fld_ae_slot2_3_2, + OPERAND_fld_ae_slot0_7_4, + OPERAND_fld_ae2_slot0_7_0, + OPERAND_fld_ae2_slot0_7_7, + OPERAND_fld_ae_slot0_7_7, + OPERAND_fld_ae_slot3_20_13, + OPERAND_fld_ae2_slot0_5_4, + OPERAND_fld_ae_slot0_5_4, + OPERAND_fld_ae_slot3_13_12, + OPERAND_fld_ae3_slot0_21_8, + OPERAND_fld_ae_slot0_20_14, + OPERAND_fld_ae_slot0_5_0, + OPERAND_fld_ae3_slot0_21_4, + OPERAND_fld_ae_sem_dr_to_ar_vr, + OPERAND_fld_ae_sem_cmov_bt, + OPERAND_fld_ae_sem_cmov_arr, + OPERAND_fld_vfpu2_sem_mov_vt, + OPERAND_fld_vfpu2_sem_mov_vr, + OPERAND_fld_vfpu2_sem_spfma_vt, + OPERAND_fld_vfpu2_sem_spfma_vs, + OPERAND_fld_vfpu2_sem_spfma_vr, + OPERAND_fld_vfpu2_sem_spmisc_brt, + OPERAND_fld_vfpu2_sem_spmisc_vs, + OPERAND_fld_vfpu2_sem_spmisc_vr, + OPERAND_fld_vfpu2_sem_mov_i_imm4, + OPERAND_fld_vfpu2_sem_sp32cvt_vr, + OPERAND_fld_vfpu2_sem_sp32cvt_vt, + OPERAND_fld_vfpu2_sem_sp32cvt_i_imm5, + OPERAND_fld_vfpu2_sem_sp32cvt_arr, + OPERAND_fld_ae_slot0_11_11, + OPERAND_fld_vfpu2_sem_spmisc_vt, + OPERAND_fld_vfpu2_sem_spmisc_vsM, + OPERAND_fld_ae_slot2_20_18, + OPERAND_fld_vfpu2_sem_spmisc_vtM, + OPERAND_fld_vfpu2_sem_spfma_i_imm1, + OPERAND_fld_vfpu2_sem_spfma_i_imm3, + OPERAND_fld_ae_slot2_20_13, + OPERAND_fld_ae_slot3_20_15, + OPERAND_fld_ae_slot2_20_15, + OPERAND_fld_ae_sem_movfpstate_v, + OPERAND_fld_ae_slot2_20_4, + OPERAND_dfp_fld_op1, + OPERAND_dfp_fld_r_3, + OPERAND_dfp_fld_r_3_1, + OPERAND_dfp_fld_s_3_1, + OPERAND_dfp_fld_op2_3, + OPERAND_dfp_fld_op2_3_2, + OPERAND_dfp_fld_op2_3_1, + OPERAND_s3to1, + OPERAND_fld_SIGMOID_Q15_x, + OPERAND_fld_SIGMOID_Q15_y, + OPERAND_fld_Inst_3_0, + OPERAND_fld_SIGMOID_FP32_x, + OPERAND_fld_SIGMOID_FP32_y +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSEXCM }, 'o' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32h_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpfb_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpdngrd_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERI_RAW_INTERLOCK }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERI_RAW_INTERLOCK }, 'o' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_1_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_3_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_sext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_clamps16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ITER_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2_1_0 }, 'i' }, + { { OPERAND_dfp_fld_op2_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ITER_stateArgs[] = { + { { STATE_F64R }, 'm' }, + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64RND_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2_1_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64RND_stateArgs[] = { + { { STATE_F64R }, 'm' }, + { { STATE_F64S }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ADDC_F64SUBC_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dfp_fld_r_2_1 }, 'i' }, + { { OPERAND_dfp_fld_r_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ADDC_F64SUBC_stateArgs[] = { + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64SIG_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPL_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPL_stateArgs[] = { + { { STATE_F64S }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPH_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPH_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_F64R }, 'o' }, + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64NORM_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64NORM_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64SEXP_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RF64R_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_dfp_fld_s_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RF64R_stateArgs[] = { + { { STATE_F64R }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WF64R_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_r_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WF64R_stateArgs[] = { + { { STATE_F64R }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_lo_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_lo_stateArgs[] = { + { { STATE_F64R }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_lo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_lo_stateArgs[] = { + { { STATE_F64R }, 'm' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_hi_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_hi_stateArgs[] = { + { { STATE_F64R }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_hi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_hi_stateArgs[] = { + { { STATE_F64R }, 'm' } +}; + +static xtensa_arg_internal Iclass_rur_f64s_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64s_stateArgs[] = { + { { STATE_F64S }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64s_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64s_stateArgs[] = { + { { STATE_F64S }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64neg }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64half }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_args[] = { + { { OPERAND_ae_uu_uu }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_args[] = { + { { OPERAND_ae_ls_su }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_args[] = { + { { OPERAND_ae_uu_uu }, 'o' }, + { { OPERAND_ae_uu_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_args[] = { + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_args[] = { + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDICIRC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_end }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_args[] = { + { { OPERAND_ae_ls_v2 }, 'i' }, + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_args[] = { + { { OPERAND_ae_ls_v2 }, 'i' }, + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDBRBA32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BITSWAP_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG3_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG2_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG1_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_args[] = { + { { OPERAND_opnd_ae_sem_rng_d }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ae_selimm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ae_selimm_N }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB4_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB2_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_args[] = { + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_movi_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_shift_sd }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_shift_sd }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_shift_sd }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_shift_sd }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' }, + { { OPERAND_ae_arth_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' }, + { { OPERAND_ae_arth_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_args[] = { + { { OPERAND_ae_pks_d }, 'm' }, + { { OPERAND_ae_pks_s }, 'i' }, + { { OPERAND_ae_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_args[] = { + { { OPERAND_ae_pks_d }, 'm' }, + { { OPERAND_ae_pks_s }, 'i' }, + { { OPERAND_ae_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_args[] = { + { { OPERAND_ae_pks_d }, 'm' }, + { { OPERAND_ae_pks_s }, 'i' }, + { { OPERAND_ae_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_args[] = { + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_args[] = { + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHA32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_opnd_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ae_sem_ep_ls_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_args[] = { + { { OPERAND_opnd_ae_sem_ep_ls_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_ep_ls_ar_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_args[] = { + { { OPERAND_opnd_ae_sem_ep_ls_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_ep_ls_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_e }, 'i' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_e }, 'o' }, + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_e }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16SI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16UI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16I_N_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_arr }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_arr }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_mov_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_mov_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_mov_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_mov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SIGMOID_Q15_args[] = { + { { OPERAND_opnd_SIGMOID_Q15_y }, 'o' }, + { { OPERAND_opnd_SIGMOID_Q15_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_SIGMOID_FP32_args[] = { + { { OPERAND_opnd_SIGMOID_FP32_y }, 'o' }, + { { OPERAND_opnd_SIGMOID_FP32_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_SIGMOID_FP32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 1, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 1, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 1, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32h_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 16, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_dcache_dyn_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpfb_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_bpfnxt */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpdngrd_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_bpfctl */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prefctl_args, + 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_prefctl_args, + 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_prefctl_args, + 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 2, Iclass_xt_iclass_wb15_0_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_1_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_2_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_3_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_ae_ovf_sar_args, + 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ovf_sar_args, + 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_bithead_args, + 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_bithead_args, + 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ts_fts_bu_bp_args, + 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ts_fts_bu_bp_args, + 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cw_sd_no_args, + 4, Iclass_rur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cw_sd_no_args, + 4, Iclass_wur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin0_args, + 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin0_args, + 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend0_args, + 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend0_args, + 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin1_args, + 2, Iclass_rur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin1_args, + 2, Iclass_wur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend1_args, + 2, Iclass_rur_ae_cend1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend1_args, + 2, Iclass_wur_ae_cend1_stateArgs, 0, 0 }, + { 2, Iclass_ic_sext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_zext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_clamps16_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_fcr_args, + 2, Iclass_rur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fcr_args, + 2, Iclass_wur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_rur_fsr_args, + 6, Iclass_rur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fsr_args, + 6, Iclass_wur_fsr_stateArgs, 0, 0 }, + { 5, Iclass_iclass_F64ITER_args, + 2, Iclass_iclass_F64ITER_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64RND_args, + 2, Iclass_iclass_F64RND_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64ADDC_F64SUBC_args, + 1, Iclass_iclass_F64ADDC_F64SUBC_stateArgs, 0, 0 }, + { 2, Iclass_iclass_F64SIG_args, + 0, 0, 0, 0 }, + { 3, Iclass_iclass_F64CMPL_args, + 1, Iclass_iclass_F64CMPL_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64CMPH_args, + 3, Iclass_iclass_F64CMPH_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64NORM_args, + 2, Iclass_iclass_F64NORM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_F64SEXP_args, + 0, 0, 0, 0 }, + { 2, Iclass_iclass_RF64R_args, + 1, Iclass_iclass_RF64R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_WF64R_args, + 1, Iclass_iclass_WF64R_stateArgs, 0, 0 }, + { 1, Iclass_rur_f64r_lo_args, + 1, Iclass_rur_f64r_lo_stateArgs, 0, 0 }, + { 1, Iclass_wur_f64r_lo_args, + 1, Iclass_wur_f64r_lo_stateArgs, 0, 0 }, + { 1, Iclass_rur_f64r_hi_args, + 1, Iclass_rur_f64r_hi_stateArgs, 0, 0 }, + { 1, Iclass_wur_f64r_hi_args, + 1, Iclass_wur_f64r_hi_stateArgs, 0, 0 }, + { 1, Iclass_rur_f64s_args, + 1, Iclass_rur_f64s_stateArgs, 0, 0 }, + { 1, Iclass_wur_f64s_args, + 1, Iclass_wur_f64s_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 1, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 1, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_OVERFLOW_args, + 2, Iclass_RUR_AE_OVERFLOW_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_OVERFLOW_args, + 2, Iclass_WUR_AE_OVERFLOW_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_SAR_args, + 2, Iclass_RUR_AE_SAR_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_SAR_args, + 2, Iclass_WUR_AE_SAR_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_BITPTR_args, + 2, Iclass_RUR_AE_BITPTR_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_BITPTR_args, + 2, Iclass_WUR_AE_BITPTR_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_BITSUSED_args, + 2, Iclass_RUR_AE_BITSUSED_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_BITSUSED_args, + 2, Iclass_WUR_AE_BITSUSED_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_TABLESIZE_args, + 2, Iclass_RUR_AE_TABLESIZE_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_TABLESIZE_args, + 2, Iclass_WUR_AE_TABLESIZE_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_FIRST_TS_args, + 2, Iclass_RUR_AE_FIRST_TS_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_FIRST_TS_args, + 2, Iclass_WUR_AE_FIRST_TS_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_NEXTOFFSET_args, + 2, Iclass_RUR_AE_NEXTOFFSET_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_NEXTOFFSET_args, + 2, Iclass_WUR_AE_NEXTOFFSET_stateArgs, 0, 0 }, + { 1, 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Iclass_AE_S32X2_RIC1_args, + 3, Iclass_AE_S32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_X_args, + 1, Iclass_AE_S32X2_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_XP_args, + 1, Iclass_AE_S32X2_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_I_args, + 2, Iclass_AE_S32X2RNG_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_IP_args, + 2, Iclass_AE_S32X2RNG_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_X_args, + 2, Iclass_AE_S32X2RNG_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_XP_args, + 2, Iclass_AE_S32X2RNG_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XC_args, + 3, Iclass_AE_S16X4_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XC1_args, + 3, Iclass_AE_S16X4_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_I_args, + 1, Iclass_AE_S16X4_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_IP_args, + 1, Iclass_AE_S16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_X_args, + 1, Iclass_AE_S16X4_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XP_args, + 1, Iclass_AE_S16X4_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_XC_args, + 3, Iclass_AE_S16M_L_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_XC1_args, + 3, Iclass_AE_S16M_L_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_I_args, + 1, Iclass_AE_S16M_L_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_IU_args, + 1, Iclass_AE_S16M_L_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_X_args, + 1, Iclass_AE_S16M_L_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_XU_args, + 1, Iclass_AE_S16M_L_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_XC_args, + 3, Iclass_AE_S32F24_L_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_XC1_args, + 3, Iclass_AE_S32F24_L_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_I_args, + 1, Iclass_AE_S32F24_L_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_IP_args, + 1, Iclass_AE_S32F24_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_X_args, + 1, Iclass_AE_S32F24_L_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_XP_args, + 1, Iclass_AE_S32F24_L_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_XC_args, + 3, Iclass_AE_S32_L_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_XC1_args, + 3, Iclass_AE_S32_L_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_I_args, + 1, Iclass_AE_S32_L_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_IP_args, + 1, Iclass_AE_S32_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_X_args, + 1, Iclass_AE_S32_L_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_XP_args, + 1, Iclass_AE_S32_L_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_XC_args, + 3, Iclass_AE_S16_0_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_XC1_args, + 3, Iclass_AE_S16_0_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_I_args, + 1, Iclass_AE_S16_0_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_IP_args, + 1, Iclass_AE_S16_0_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_X_args, + 1, Iclass_AE_S16_0_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_XP_args, + 1, Iclass_AE_S16_0_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XC_args, + 3, Iclass_AE_S64_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XC1_args, + 3, Iclass_AE_S64_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_I_args, + 1, Iclass_AE_S64_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_IP_args, + 1, Iclass_AE_S64_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_X_args, + 1, Iclass_AE_S64_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XP_args, + 1, Iclass_AE_S64_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_XC_args, + 3, Iclass_AE_S32M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_I_args, + 1, Iclass_AE_S32M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_IU_args, + 1, Iclass_AE_S32M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_X_args, + 1, Iclass_AE_S32M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_XU_args, + 1, Iclass_AE_S32M_XU_stateArgs, 0, 0 }, + { 1, Iclass_AE_ZALIGN64_args, + 1, Iclass_AE_ZALIGN64_stateArgs, 0, 0 }, + { 3, Iclass_AE_LALIGN64_I_args, + 1, Iclass_AE_LALIGN64_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_SALIGN64_I_args, + 1, Iclass_AE_SALIGN64_I_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVALIGN_args, + 1, Iclass_AE_MOVALIGN_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA64_PP_args, + 1, Iclass_AE_LA64_PP_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC_args, + 3, Iclass_AE_LA24POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC_args, + 3, Iclass_AE_LA24X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC_args, + 3, Iclass_AE_LA32X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC_args, + 3, Iclass_AE_LA16X4POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC_args, + 3, Iclass_AE_LA24NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC_args, + 3, Iclass_AE_LA24X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC_args, + 3, Iclass_AE_LA32X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC_args, + 3, Iclass_AE_LA16X4NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC1_args, + 3, Iclass_AE_LA24POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC1_args, + 3, Iclass_AE_LA24X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC1_args, + 3, Iclass_AE_LA32X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC1_args, + 3, Iclass_AE_LA16X4POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC1_args, + 3, Iclass_AE_LA24NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC1_args, + 3, Iclass_AE_LA24X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC1_args, + 3, Iclass_AE_LA32X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC1_args, + 3, Iclass_AE_LA16X4NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64POS_FP_args, + 1, Iclass_AE_SA64POS_FP_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64NEG_FP_args, + 1, Iclass_AE_SA64NEG_FP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC_args, + 3, Iclass_AE_LA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC1_args, + 3, Iclass_AE_LA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IP_args, + 1, Iclass_AE_LA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIP_args, + 1, Iclass_AE_LA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC_args, + 3, Iclass_AE_LA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC1_args, + 3, Iclass_AE_LA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC_args, + 3, Iclass_AE_LA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC1_args, + 3, Iclass_AE_LA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IP_args, + 1, Iclass_AE_LA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIP_args, + 1, Iclass_AE_LA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC_args, + 3, Iclass_AE_LA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC1_args, + 3, Iclass_AE_LA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC_args, + 3, Iclass_AE_LA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC1_args, + 3, Iclass_AE_LA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IP_args, + 1, Iclass_AE_LA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIP_args, + 1, Iclass_AE_LA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC_args, + 3, Iclass_AE_LA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC1_args, + 3, Iclass_AE_LA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC_args, + 3, Iclass_AE_LA24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC1_args, + 3, Iclass_AE_LA24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IP_args, + 1, Iclass_AE_LA24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIP_args, + 1, Iclass_AE_LA24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC_args, + 3, Iclass_AE_LA24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC1_args, + 3, Iclass_AE_LA24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC_args, + 3, Iclass_AE_LA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC1_args, + 3, Iclass_AE_LA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IP_args, + 1, Iclass_AE_LA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIP_args, + 1, Iclass_AE_LA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC_args, + 3, Iclass_AE_LA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC1_args, + 3, Iclass_AE_LA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC_args, + 3, Iclass_AE_SA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC1_args, + 3, Iclass_AE_SA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IP_args, + 1, Iclass_AE_SA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIP_args, + 1, Iclass_AE_SA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC_args, + 3, Iclass_AE_SA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC1_args, + 3, Iclass_AE_SA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC_args, + 3, Iclass_AE_SA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC1_args, + 3, Iclass_AE_SA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IP_args, + 1, Iclass_AE_SA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIP_args, + 1, Iclass_AE_SA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC_args, + 3, Iclass_AE_SA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC1_args, + 3, Iclass_AE_SA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC_args, + 3, Iclass_AE_SA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC1_args, + 3, Iclass_AE_SA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IP_args, + 1, Iclass_AE_SA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIP_args, + 1, Iclass_AE_SA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC_args, + 3, Iclass_AE_SA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC1_args, + 3, Iclass_AE_SA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC_args, + 3, Iclass_AE_SA24_L_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC1_args, + 3, Iclass_AE_SA24_L_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IP_args, + 1, Iclass_AE_SA24_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIP_args, + 1, Iclass_AE_SA24_L_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC_args, + 3, Iclass_AE_SA24_L_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC1_args, + 3, Iclass_AE_SA24_L_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC_args, + 3, Iclass_AE_SA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC1_args, + 3, Iclass_AE_SA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IP_args, + 1, Iclass_AE_SA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIP_args, + 1, Iclass_AE_SA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC_args, + 3, Iclass_AE_SA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC1_args, + 3, Iclass_AE_SA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDICIRC_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC1_args, + 3, Iclass_AE_ADDCIRC_XC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC_args, + 3, Iclass_AE_ADDCIRC_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_I_args, + 2, Iclass_AE_S32RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_IP_args, + 2, Iclass_AE_S32RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_X_args, + 2, Iclass_AE_S32RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XP_args, + 2, Iclass_AE_S32RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC_args, + 4, Iclass_AE_S32RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC1_args, + 4, Iclass_AE_S32RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_I_args, + 2, Iclass_AE_S24RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_IP_args, + 2, Iclass_AE_S24RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_X_args, + 2, Iclass_AE_S24RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XP_args, + 2, Iclass_AE_S24RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC_args, + 4, Iclass_AE_S24RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC1_args, + 4, Iclass_AE_S24RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RA64S_IP_args, + 2, Iclass_AE_S32X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24X2RA64S_IP_args, + 2, Iclass_AE_S24X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDBRBA32_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_BITSWAP_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MUL32JS_args, + 1, Iclass_AE_MUL32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32S_args, + 2, Iclass_AE_ADDANDSUB32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_args, + 2, Iclass_AE_ADDANDSUBRNG32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDRNG32_args, + 2, Iclass_AE_ADDRNG32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBRNG32_args, + 2, Iclass_AE_SUBRNG32_stateArgs, 0, 0 }, + { 0, 0 /* AE_CALCRNG3 */, + 2, Iclass_AE_CALCRNG3_stateArgs, 0, 0 }, + { 0, 0 /* AE_CALCRNG2 */, + 2, Iclass_AE_CALCRNG2_stateArgs, 0, 0 }, + { 0, 0 /* AE_CALCRNG1 */, + 2, Iclass_AE_CALCRNG1_stateArgs, 0, 0 }, + { 1, Iclass_AE_RNG32X2_args, + 2, Iclass_AE_RNG32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_args, + 1, Iclass_AE_SEL16I_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_N_args, + 1, Iclass_AE_SEL16I_N_stateArgs, 0, 0 }, + { 2, Iclass_AE_SHORTSWAP_args, + 1, Iclass_AE_SHORTSWAP_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAB4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVBA1X2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB4_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVT16X4_args, + 1, Iclass_AE_MOVT16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF16X4_args, + 1, Iclass_AE_MOVF16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT32X2_args, + 1, Iclass_AE_MOVT32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF32X2_args, + 1, Iclass_AE_MOVF32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVSARA7X2_args, + 2, Iclass_AE_MOVSARA7X2_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVSARD7_args, + 2, Iclass_AE_MOVSARD7_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVASAR_args, + 2, Iclass_AE_MOVASAR_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA32X2_args, + 1, Iclass_AE_MOVDA32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA32_args, + 1, Iclass_AE_MOVDA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA16X2_args, + 1, Iclass_AE_MOVDA16X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA16_args, + 1, Iclass_AE_MOVDA16_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVI_args, + 1, Iclass_AE_MOVI_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24A32X2_args, + 1, Iclass_AE_TRUNCP24A32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SAT16X4_args, + 2, Iclass_AE_SAT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_32_args, + 1, Iclass_AE_CVT32X2F16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_10_args, + 1, Iclass_AE_CVT32X2F16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_32_args, + 1, Iclass_AE_SEXT32X2D16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_10_args, + 1, Iclass_AE_SEXT32X2D16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_L_args, + 1, Iclass_AE_CVTA32F24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_H_args, + 1, Iclass_AE_CVTA32F24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LL_args, + 1, Iclass_AE_CVTP24A16X2_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LH_args, + 1, Iclass_AE_CVTP24A16X2_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HL_args, + 1, Iclass_AE_CVTP24A16X2_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HH_args, + 1, Iclass_AE_CVTP24A16X2_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24Q48X2_args, + 1, Iclass_AE_TRUNCP24Q48X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32X2F64S_args, + 2, Iclass_AE_TRUNCA32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32X2F64S_args, + 2, Iclass_AE_TRUNCI32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32F64S_L_args, + 2, Iclass_AE_TRUNCA32F64S_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32F64S_L_args, + 2, Iclass_AE_TRUNCI32F64S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCP16_args, + 1, Iclass_AE_TRUNCP16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SSYM_args, + 2, Iclass_AE_ROUND32X2F64SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SASYM_args, + 2, Iclass_AE_ROUND32X2F64SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SSYM_args, + 2, Iclass_AE_ROUND32X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SASYM_args, + 2, Iclass_AE_ROUND32X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SSYM_args, + 2, Iclass_AE_ROUND16X4F32SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SASYM_args, + 2, Iclass_AE_ROUND16X4F32SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SSYM_args, + 2, Iclass_AE_ROUND24X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SASYM_args, + 2, Iclass_AE_ROUND24X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2SYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2ASYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS32S_args, + 2, Iclass_AE_MINABS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS32S_args, + 2, Iclass_AE_MAXABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24SYM_args, + 2, Iclass_AE_ROUNDSP16F24SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24ASYM_args, + 2, Iclass_AE_ROUNDSP16F24ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOV_args, + 1, Iclass_AE_MOV_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT64_args, + 1, Iclass_AE_MOVT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF64_args, + 1, Iclass_AE_MOVF64_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56A32S_args, + 1, Iclass_AE_CVTQ56A32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48A32_args, + 1, Iclass_AE_CVT48A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64A32_args, + 1, Iclass_AE_CVT64A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_L_args, + 1, Iclass_AE_CVTQ56P32S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_H_args, + 1, Iclass_AE_CVTQ56P32S_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64F32_H_args, + 1, Iclass_AE_CVT64F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_L_args, + 1, Iclass_AE_CVT48F32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_H_args, + 1, Iclass_AE_CVT48F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT48S_args, + 2, Iclass_AE_SAT48S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SATQ56S_args, + 2, Iclass_AE_SATQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT24S_args, + 2, Iclass_AE_SAT24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCQ32_args, + 1, Iclass_AE_TRUNCQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS64S_args, + 2, Iclass_AE_MINABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS64S_args, + 2, Iclass_AE_MAXABS64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48SYM_args, + 2, Iclass_AE_ROUNDSQ32F48SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48ASYM_args, + 2, Iclass_AE_ROUNDSQ32F48ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA32Q48_args, + 1, Iclass_AE_TRUNCA32Q48_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_L_args, + 1, Iclass_AE_MOVAD32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_H_args, + 1, Iclass_AE_MOVAD32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_3_args, + 1, Iclass_AE_MOVAD16_3_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_2_args, + 1, Iclass_AE_MOVAD16_2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_1_args, + 1, Iclass_AE_MOVAD16_1_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_0_args, + 1, Iclass_AE_MOVAD16_0_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRA64_32_args, + 1, Iclass_AE_SRA64_32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR32_args, + 2, Iclass_AE_PKSR32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR24_args, + 2, Iclass_AE_PKSR24_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSRF32_args, + 2, Iclass_AE_PKSRF32_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_L_args, + 1, Iclass_AE_TRUNCA16P24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_H_args, + 1, Iclass_AE_TRUNCA16P24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_args, + 1, Iclass_AE_ADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB32_args, + 1, Iclass_AE_SUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32_args, + 1, Iclass_AE_ADDSUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBADD32_args, + 1, Iclass_AE_SUBADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD16_args, + 1, Iclass_AE_ADD16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB16_args, + 1, Iclass_AE_SUB16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_HL_LH_args, + 1, Iclass_AE_ADD32_HL_LH_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32_args, + 1, Iclass_AE_NEG32_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS32_args, + 1, Iclass_AE_ABS32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD24S_args, + 2, Iclass_AE_ADD24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB24S_args, + 2, Iclass_AE_SUB24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32S_args, + 2, Iclass_AE_ADD32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB32S_args, + 2, Iclass_AE_SUB32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32S_args, + 2, Iclass_AE_ADDSUB32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBADD32S_args, + 2, Iclass_AE_SUBADD32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD16S_args, + 2, Iclass_AE_ADD16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB16S_args, + 2, Iclass_AE_SUB16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32S_HL_LH_args, + 2, Iclass_AE_ADD32S_HL_LH_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG24S_args, + 2, Iclass_AE_NEG24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS24S_args, + 2, Iclass_AE_ABS24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32S_args, + 1, Iclass_AE_NEG32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS32S_args, + 1, Iclass_AE_ABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG16S_args, + 1, Iclass_AE_NEG16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS16S_args, + 1, Iclass_AE_ABS16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT16_args, + 1, Iclass_AE_LT16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE16_args, + 1, Iclass_AE_LE16_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ16_args, + 1, Iclass_AE_EQ16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT32_args, + 1, Iclass_AE_LT32_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE32_args, + 1, Iclass_AE_LE32_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ32_args, + 1, Iclass_AE_EQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN32_args, + 1, Iclass_AE_MIN32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX32_args, + 1, Iclass_AE_MAX32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD64_args, + 1, Iclass_AE_ADD64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB64_args, + 1, Iclass_AE_SUB64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG64_args, + 1, Iclass_AE_NEG64_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS64_args, + 1, Iclass_AE_ABS64_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSQ56S_args, + 2, Iclass_AE_ADDSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBSQ56S_args, + 2, Iclass_AE_SUBSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD64S_args, + 2, Iclass_AE_ADD64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB64S_args, + 2, Iclass_AE_SUB64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEGSQ56S_args, + 2, Iclass_AE_NEGSQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABSSQ56S_args, + 2, Iclass_AE_ABSSQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG64S_args, + 2, Iclass_AE_NEG64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS64S_args, + 2, Iclass_AE_ABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_AND_args, + 1, Iclass_AE_AND_stateArgs, 0, 0 }, + { 3, Iclass_AE_NAND_args, + 1, Iclass_AE_NAND_stateArgs, 0, 0 }, + { 3, Iclass_AE_OR_args, + 1, Iclass_AE_OR_stateArgs, 0, 0 }, + { 3, Iclass_AE_XOR_args, + 1, Iclass_AE_XOR_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI24_args, + 1, Iclass_AE_SLAI24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI24_args, + 1, Iclass_AE_SRLI24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI24_args, + 1, Iclass_AE_SRAI24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS24_args, + 2, Iclass_AE_SLAS24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS24_args, + 2, Iclass_AE_SRLS24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS24_args, + 2, Iclass_AE_SRAS24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16_args, + 1, Iclass_AE_SRAI16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16R_args, + 1, Iclass_AE_SRAI16R_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI32_args, + 1, Iclass_AE_SLAI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI32_args, + 1, Iclass_AE_SRLI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32_args, + 1, Iclass_AE_SRAI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32R_args, + 1, Iclass_AE_SRAI32R_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS32_args, + 2, Iclass_AE_SLAS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS32_args, + 2, Iclass_AE_SRLS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS32_args, + 2, Iclass_AE_SRAS32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA32_args, + 1, Iclass_AE_SLAA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA32_args, + 1, Iclass_AE_SRLA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32_args, + 1, Iclass_AE_SRAA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI16S_args, + 2, Iclass_AE_SLAI16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA16S_args, + 2, Iclass_AE_SLAA16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16S_args, + 2, Iclass_AE_SRAA16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16RS_args, + 2, Iclass_AE_SRAA16RS_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI24S_args, + 2, Iclass_AE_SLAI24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS24S_args, + 3, Iclass_AE_SLAS24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI32S_args, + 2, Iclass_AE_SLAI32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS32S_args, + 3, Iclass_AE_SLAS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA32S_args, + 2, Iclass_AE_SLAA32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32S_args, + 2, Iclass_AE_SRAA32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32RS_args, + 2, Iclass_AE_SRAA32RS_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLASQ56_args, + 2, Iclass_AE_SLASQ56_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLSQ56_args, + 2, Iclass_AE_SRLSQ56_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRASQ56_args, + 2, Iclass_AE_SRASQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAAQ56_args, + 1, Iclass_AE_SLAAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLAQ56_args, + 1, Iclass_AE_SRLAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAAQ56_args, + 1, Iclass_AE_SRAAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI64_args, + 1, Iclass_AE_SLAI64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI64_args, + 1, Iclass_AE_SRLI64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI64_args, + 1, Iclass_AE_SRAI64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS64_args, + 2, Iclass_AE_SLAS64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS64_args, + 2, Iclass_AE_SRLS64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS64_args, + 2, Iclass_AE_SRAS64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA64_args, + 1, Iclass_AE_SLAA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA64_args, + 1, Iclass_AE_SRLA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA64_args, + 1, Iclass_AE_SRAA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAISQ56S_args, + 2, Iclass_AE_SLAISQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLASSQ56S_args, + 3, Iclass_AE_SLASSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAASQ56S_args, + 2, Iclass_AE_SLAASQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI64S_args, + 2, Iclass_AE_SLAI64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS64S_args, + 3, Iclass_AE_SLAS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA64S_args, + 2, Iclass_AE_SLAA64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT64_args, + 1, Iclass_AE_LT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE64_args, + 1, Iclass_AE_LE64_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ64_args, + 1, Iclass_AE_EQ64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX64_args, + 1, Iclass_AE_MAX64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN64_args, + 1, Iclass_AE_MIN64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSA64_args, + 1, Iclass_AE_NSA64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSAZ16_0_args, + 1, Iclass_AE_NSAZ16_0_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSAZ32_L_args, + 1, Iclass_AE_NSAZ32_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_LL_args, + 2, Iclass_AE_MULS32F48P16S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_LL_args, + 2, Iclass_AE_MULF32S_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_LL_args, + 1, Iclass_AE_MUL32_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_LL_S2_args, + 2, Iclass_AE_MULF32S_LL_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_LL_S2_args, + 1, Iclass_AE_MUL32_LL_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_LL_S2_args, + 2, Iclass_AE_MULS32F48P16S_LL_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_LL_args, + 1, Iclass_AE_MULF32R_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_LL_args, + 1, Iclass_AE_MULF32RA_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_LL_S2_args, + 1, Iclass_AE_MULF32RA_LL_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_LL_S2_args, + 1, Iclass_AE_MULF32R_LL_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_LH_args, + 2, Iclass_AE_MULS32F48P16S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_LH_args, + 2, Iclass_AE_MULF32S_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_LH_args, + 1, Iclass_AE_MUL32_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_LH_S2_args, + 2, Iclass_AE_MULF32S_LH_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_LH_S2_args, + 1, Iclass_AE_MUL32_LH_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_LH_S2_args, + 2, Iclass_AE_MULS32F48P16S_LH_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_LH_args, + 1, Iclass_AE_MULF32R_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_LH_args, + 1, Iclass_AE_MULF32RA_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32RA_LH_S2_args, + 1, Iclass_AE_MULF32RA_LH_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32R_LH_S2_args, + 1, Iclass_AE_MULF32R_LH_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULS32F48P16S_HH_args, + 2, Iclass_AE_MULS32F48P16S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_HH_args, + 2, Iclass_AE_MULF32S_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL32_HH_args, + 1, Iclass_AE_MUL32_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULF32S_HH_S2_args, + 2, Iclass_AE_MULF32S_HH_S2_stateArgs, 0, 0 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Iclass_AE_MULAC32_args, + 1, Iclass_AE_MULAC32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFC24RA_args, + 1, Iclass_AE_MULAFC24RA_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFC32RAS_args, + 2, Iclass_AE_MULAFC32RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC32X16_L_args, + 1, Iclass_AE_MULAC32X16_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFC32X16RAS_L_args, + 2, Iclass_AE_MULAFC32X16RAS_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC32X16_H_args, + 1, Iclass_AE_MULAC32X16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFC32X16RAS_H_args, + 2, Iclass_AE_MULAFC32X16RAS_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF16X4SS_args, + 2, Iclass_AE_MULF16X4SS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF16X4SS_args, + 2, Iclass_AE_MULAF16X4SS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF16X4SS_args, + 2, Iclass_AE_MULSF16X4SS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL16X4_args, + 1, Iclass_AE_MUL16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA16X4_args, + 1, Iclass_AE_MULA16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS16X4_args, + 1, Iclass_AE_MULS16X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X2S_FIR_H_args, + 2, Iclass_AE_MULFD32X2S_FIR_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X2RA_FIR_H_args, + 1, Iclass_AE_MULFD32X2RA_FIR_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X2S_FIR_L_args, + 2, Iclass_AE_MULFD32X2S_FIR_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X2RA_FIR_L_args, + 1, Iclass_AE_MULFD32X2RA_FIR_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X16X2_FIR_HH_args, + 1, Iclass_AE_MULFD32X16X2_FIR_HH_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X16X2_FIR_HL_args, + 1, Iclass_AE_MULFD32X16X2_FIR_HL_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X16X2_FIR_LH_args, + 1, Iclass_AE_MULFD32X16X2_FIR_LH_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X16X2_FIR_LL_args, + 1, Iclass_AE_MULFD32X16X2_FIR_LL_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X2S_FIR_H_args, + 2, Iclass_AE_MULAFD32X2S_FIR_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X2RA_FIR_H_args, + 1, Iclass_AE_MULAFD32X2RA_FIR_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X2S_FIR_L_args, + 2, Iclass_AE_MULAFD32X2S_FIR_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X2RA_FIR_L_args, + 1, Iclass_AE_MULAFD32X2RA_FIR_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X16X2_FIR_HH_args, + 1, Iclass_AE_MULAFD32X16X2_FIR_HH_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X16X2_FIR_HL_args, + 1, Iclass_AE_MULAFD32X16X2_FIR_HL_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X16X2_FIR_LH_args, + 1, Iclass_AE_MULAFD32X16X2_FIR_LH_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X16X2_FIR_LL_args, + 1, Iclass_AE_MULAFD32X16X2_FIR_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAFQ32X16_args, + 1, Iclass_AE_MULZAAAAFQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAFQ32X16_args, + 1, Iclass_AE_MULAAAAFQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAFQ32X16_S2_args, + 1, Iclass_AE_MULZAAAAFQ32X16_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAFQ32X16_S2_args, + 1, Iclass_AE_MULAAAAFQ32X16_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAQ32X16_args, + 1, Iclass_AE_MULZAAAAQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAQ32X16_args, + 1, Iclass_AE_MULAAAAQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAQ32X16_S2_args, + 1, Iclass_AE_MULZAAAAQ32X16_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAQ32X16_S2_args, + 1, Iclass_AE_MULAAAAQ32X16_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL16_00_args, + 1, Iclass_AE_MUL16_00_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA16_00_args, + 1, Iclass_AE_MULA16_00_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL16_00_S2_args, + 1, Iclass_AE_MUL16_00_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA16_00_S2_args, + 1, Iclass_AE_MULA16_00_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAAAQ16_args, + 1, Iclass_AE_MULZAAAAQ16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAAAQ16_args, + 1, Iclass_AE_MULAAAAQ16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAAAQ16_S2_args, + 1, Iclass_AE_MULZAAAAQ16_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAAAQ16_S2_args, + 1, Iclass_AE_MULAAAAQ16_S2_stateArgs, 0, 0 }, + { 2, Iclass_AE_DIV64D32_H_args, + 1, Iclass_AE_DIV64D32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_DIV64D32_L_args, + 1, Iclass_AE_DIV64D32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_SHA32_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_VLDL32T_args, + 5, Iclass_AE_VLDL32T_stateArgs, 0, 0 }, + { 3, Iclass_AE_VLDL16T_args, + 5, Iclass_AE_VLDL16T_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDL16C_args, + 8, Iclass_AE_VLDL16C_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDL16C_IP_args, + 8, Iclass_AE_VLDL16C_IP_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDL16C_IC_args, + 11, Iclass_AE_VLDL16C_IC_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDL16C_IC1_args, + 11, Iclass_AE_VLDL16C_IC1_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDSHT_args, + 6, Iclass_AE_VLDSHT_stateArgs, 0, 0 }, + { 2, Iclass_AE_LB_args, + 3, Iclass_AE_LB_stateArgs, 0, 0 }, + { 2, Iclass_AE_LBI_args, + 3, Iclass_AE_LBI_stateArgs, 0, 0 }, + { 3, Iclass_AE_LBK_args, + 3, Iclass_AE_LBK_stateArgs, 0, 0 }, + { 3, Iclass_AE_LBKI_args, + 3, Iclass_AE_LBKI_stateArgs, 0, 0 }, + { 2, Iclass_AE_LBS_args, + 3, Iclass_AE_LBS_stateArgs, 0, 0 }, + { 2, Iclass_AE_LBSI_args, + 3, Iclass_AE_LBSI_stateArgs, 0, 0 }, + { 2, Iclass_AE_DB_args, + 3, Iclass_AE_DB_stateArgs, 0, 0 }, + { 2, Iclass_AE_DBI_args, + 3, Iclass_AE_DBI_stateArgs, 0, 0 }, + { 2, Iclass_AE_DB_IC_args, + 6, Iclass_AE_DB_IC_stateArgs, 0, 0 }, + { 2, Iclass_AE_DBI_IC_args, + 6, Iclass_AE_DBI_IC_stateArgs, 0, 0 }, + { 2, Iclass_AE_DB_IC1_args, + 6, Iclass_AE_DB_IC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_DBI_IC1_args, + 6, Iclass_AE_DBI_IC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_DB_IP_args, + 3, Iclass_AE_DB_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_DBI_IP_args, + 3, Iclass_AE_DBI_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_VLEL32T_args, + 3, Iclass_AE_VLEL32T_stateArgs, 0, 0 }, + { 3, Iclass_AE_VLEL16T_args, + 3, Iclass_AE_VLEL16T_stateArgs, 0, 0 }, + { 2, Iclass_AE_SB_args, + 4, Iclass_AE_SB_stateArgs, 0, 0 }, + { 3, Iclass_AE_SBI_args, + 3, Iclass_AE_SBI_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLES16C_args, + 5, Iclass_AE_VLES16C_stateArgs, 0, 0 }, + { 1, Iclass_AE_SBF_args, + 3, Iclass_AE_SBF_stateArgs, 0, 0 }, + { 2, Iclass_AE_SB_IC_args, + 7, Iclass_AE_SB_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SBI_IC_args, + 6, Iclass_AE_SBI_IC_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLES16C_IC_args, + 8, Iclass_AE_VLES16C_IC_stateArgs, 0, 0 }, + { 1, Iclass_AE_SBF_IC_args, + 6, Iclass_AE_SBF_IC_stateArgs, 0, 0 }, + { 2, Iclass_AE_SB_IC1_args, + 7, Iclass_AE_SB_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SBI_IC1_args, + 6, Iclass_AE_SBI_IC1_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLES16C_IC1_args, + 8, Iclass_AE_VLES16C_IC1_stateArgs, 0, 0 }, + { 1, Iclass_AE_SBF_IC1_args, + 6, Iclass_AE_SBF_IC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_SB_IP_args, + 4, Iclass_AE_SB_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SBI_IP_args, + 3, Iclass_AE_SBI_IP_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLES16C_IP_args, + 5, Iclass_AE_VLES16C_IP_stateArgs, 0, 0 }, + { 1, Iclass_AE_SBF_IP_args, + 3, Iclass_AE_SBF_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SEXT32_args, + 1, Iclass_AE_SEXT32_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAE_args, + 1, Iclass_AE_MOVAE_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVEA_args, + 1, Iclass_AE_MOVEA_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVEEP_args, + 1, Iclass_AE_MOVEEP_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT72_args, + 1, Iclass_AE_SEXT72_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADD72_args, + 1, Iclass_AE_ADD72_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUB72_args, + 1, Iclass_AE_SUB72_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD72X64_args, + 1, Iclass_AE_ADD72X64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB72X64_args, + 1, Iclass_AE_SUB72X64_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32EP_HH_args, + 1, Iclass_AE_MUL32EP_HH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32EP_HH_S2_args, + 1, Iclass_AE_MUL32EP_HH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32EP_HH_args, + 1, Iclass_AE_MULA32EP_HH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32EP_HH_args, + 1, Iclass_AE_MULS32EP_HH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32EP_HH_S2_args, + 1, Iclass_AE_MULA32EP_HH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32EP_HH_S2_args, + 1, Iclass_AE_MULS32EP_HH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAD32EP_HH_LL_args, + 1, Iclass_AE_MULZAAD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZSSD32EP_HH_LL_args, + 1, Iclass_AE_MULZSSD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32EP_HH_LL_args, + 1, Iclass_AE_MULAAD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSSD32EP_HH_LL_args, + 1, Iclass_AE_MULSSD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAD32EP_HH_LL_S2_args, + 1, Iclass_AE_MULZAAD32EP_HH_LL_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZSSD32EP_HH_LL_S2_args, + 1, Iclass_AE_MULZSSD32EP_HH_LL_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32EP_HH_LL_S2_args, + 1, Iclass_AE_MULAAD32EP_HH_LL_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSSD32EP_HH_LL_S2_args, + 1, Iclass_AE_MULSSD32EP_HH_LL_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32USEP_HL_LH_args, + 1, Iclass_AE_MULAAD32USEP_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32USEP_HL_LH_S2_args, + 1, Iclass_AE_MULAAD32USEP_HL_LH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAD32USEP_HL_LH_args, + 1, Iclass_AE_MULZAAD32USEP_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAD32USEP_HL_LH_S2_args, + 1, Iclass_AE_MULZAAD32USEP_HL_LH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32USEP_LH_args, + 1, Iclass_AE_MUL32USEP_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32USEP_LH_args, + 1, Iclass_AE_MULA32USEP_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32USEP_LL_args, + 1, Iclass_AE_MUL32USEP_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32USEP_LL_args, + 1, Iclass_AE_MULA32USEP_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_SRAI72_args, + 1, Iclass_AE_SRAI72_stateArgs, 0, 0 }, + { 4, Iclass_AE_SLAI72_args, + 1, Iclass_AE_SLAI72_stateArgs, 0, 0 }, + { 3, Iclass_AE_SAT64S_args, + 2, Iclass_AE_SAT64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16SI_N_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_L16UI_N_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_S16I_N_args, + 0, 0, 0, 0 }, + { 1, Iclass_AE_MOVFCRFSRV_args, + 7, Iclass_AE_MOVFCRFSRV_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVVFCRFSR_args, + 7, Iclass_AE_MOVVFCRFSR_stateArgs, 0, 0 }, + { 2, Iclass_RFR_args, + 1, Iclass_RFR_stateArgs, 0, 0 }, + { 2, Iclass_WFR_args, + 1, Iclass_WFR_stateArgs, 0, 0 }, + { 3, Iclass_MOVT_S_args, + 1, Iclass_MOVT_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVF_S_args, + 1, Iclass_MOVF_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVEQZ_S_args, + 1, Iclass_MOVEQZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVNEZ_S_args, + 1, Iclass_MOVNEZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVGEZ_S_args, + 1, Iclass_MOVGEZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVLTZ_S_args, + 1, Iclass_MOVLTZ_S_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC_S_args, + 3, Iclass_TRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC_S_args, + 3, Iclass_UTRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC_SX2_args, + 3, Iclass_TRUNC_SX2_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC_SX2_args, + 3, Iclass_UTRUNC_SX2_stateArgs, 0, 0 }, + { 2, Iclass_FICEIL_S_args, + 2, Iclass_FICEIL_S_stateArgs, 0, 0 }, + { 2, Iclass_FIFLOOR_S_args, + 2, Iclass_FIFLOOR_S_stateArgs, 0, 0 }, + { 2, Iclass_FIROUND_S_args, + 2, Iclass_FIROUND_S_stateArgs, 0, 0 }, + { 2, Iclass_FITRUNC_S_args, + 2, Iclass_FITRUNC_S_stateArgs, 0, 0 }, + { 2, Iclass_FIRINT_S_args, + 4, Iclass_FIRINT_S_stateArgs, 0, 0 }, + { 2, Iclass_CVTSF16_L_args, + 2, Iclass_CVTSF16_L_stateArgs, 0, 0 }, + { 2, Iclass_CVTSF16_H_args, + 2, Iclass_CVTSF16_H_stateArgs, 0, 0 }, + { 2, Iclass_CVTF16S_L_args, + 6, Iclass_CVTF16S_L_stateArgs, 0, 0 }, + { 2, Iclass_CVTF16S_H_args, + 6, Iclass_CVTF16S_H_stateArgs, 0, 0 }, + { 2, Iclass_ABS_S_args, + 1, Iclass_ABS_S_stateArgs, 0, 0 }, + { 3, Iclass_MUL_S_args, + 6, Iclass_MUL_S_stateArgs, 0, 0 }, + { 3, Iclass_MADD_S_args, + 6, Iclass_MADD_S_stateArgs, 0, 0 }, + { 3, Iclass_MSUB_S_args, + 6, Iclass_MSUB_S_stateArgs, 0, 0 }, + { 3, Iclass_MSUBN_S_args, + 1, Iclass_MSUBN_S_stateArgs, 0, 0 }, + { 3, Iclass_MADDN_S_args, + 1, Iclass_MADDN_S_stateArgs, 0, 0 }, + { 3, Iclass_ADD_S_args, + 6, Iclass_ADD_S_stateArgs, 0, 0 }, + { 3, Iclass_SUB_S_args, + 6, Iclass_SUB_S_stateArgs, 0, 0 }, + { 2, Iclass_NEG_S_args, + 1, Iclass_NEG_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_S_args, + 3, Iclass_FLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_S_args, + 3, Iclass_UFLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_SX2_args, + 3, Iclass_FLOAT_SX2_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_SX2_args, + 3, Iclass_UFLOAT_SX2_stateArgs, 0, 0 }, + { 3, Iclass_OLE_S_args, + 2, Iclass_OLE_S_stateArgs, 0, 0 }, + { 3, Iclass_OLT_S_args, + 2, Iclass_OLT_S_stateArgs, 0, 0 }, + { 3, Iclass_OEQ_S_args, + 2, Iclass_OEQ_S_stateArgs, 0, 0 }, + { 3, Iclass_UN_S_args, + 2, Iclass_UN_S_stateArgs, 0, 0 }, + { 3, Iclass_ULE_S_args, + 2, Iclass_ULE_S_stateArgs, 0, 0 }, + { 3, Iclass_ULT_S_args, + 2, Iclass_ULT_S_stateArgs, 0, 0 }, + { 3, Iclass_UEQ_S_args, + 2, Iclass_UEQ_S_stateArgs, 0, 0 }, + { 2, Iclass_CONST_S_args, + 1, Iclass_CONST_S_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_S_args, + 1, Iclass_NEXP01_S_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_S_args, + 2, Iclass_MKSADJ_S_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_S_args, + 3, Iclass_MKDADJ_S_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_S_args, + 1, Iclass_DIV0_S_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_S_args, + 1, Iclass_SQRT0_S_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_S_args, + 3, Iclass_RECIP0_S_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_S_args, + 3, Iclass_RSQRT0_S_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_S_args, + 5, Iclass_DIVN_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXP_S_args, + 1, Iclass_ADDEXP_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXPM_S_args, + 1, Iclass_ADDEXPM_S_stateArgs, 0, 0 }, + { 3, Iclass_MIN_S_args, + 2, Iclass_MIN_S_stateArgs, 0, 0 }, + { 3, Iclass_MAX_S_args, + 2, Iclass_MAX_S_stateArgs, 0, 0 }, + { 4, Iclass_MULMUX_S_args, + 6, Iclass_MULMUX_S_stateArgs, 0, 0 }, + { 4, Iclass_MADDMUX_S_args, + 6, Iclass_MADDMUX_S_stateArgs, 0, 0 }, + { 2, Iclass_CONJC_S_args, + 1, Iclass_CONJC_S_stateArgs, 0, 0 }, + { 2, Iclass_SIGMOID_Q15_args, + 0, 0, 0, 0 }, + { 2, Iclass_SIGMOID_FP32_args, + 1, Iclass_SIGMOID_FP32_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_mul32h, + ICLASS_xt_iclass_mac16_aa, + ICLASS_xt_iclass_mac16_ad, + ICLASS_xt_iclass_mac16_da, + ICLASS_xt_iclass_mac16_dd, + ICLASS_xt_iclass_mac16a_aa, + ICLASS_xt_iclass_mac16a_ad, + ICLASS_xt_iclass_mac16a_da, + ICLASS_xt_iclass_mac16a_dd, + ICLASS_xt_iclass_mac16al_da, + ICLASS_xt_iclass_mac16al_dd, + ICLASS_xt_iclass_mac16_l, + ICLASS_xt_iclass_rsr_m0, + ICLASS_xt_iclass_wsr_m0, + ICLASS_xt_iclass_xsr_m0, + ICLASS_xt_iclass_rsr_m1, + ICLASS_xt_iclass_wsr_m1, + ICLASS_xt_iclass_xsr_m1, + ICLASS_xt_iclass_rsr_m2, + ICLASS_xt_iclass_wsr_m2, + ICLASS_xt_iclass_xsr_m2, + ICLASS_xt_iclass_rsr_m3, + ICLASS_xt_iclass_wsr_m3, + ICLASS_xt_iclass_xsr_m3, + ICLASS_xt_iclass_rsr_acclo, + ICLASS_xt_iclass_wsr_acclo, + ICLASS_xt_iclass_xsr_acclo, + ICLASS_xt_iclass_rsr_acchi, + ICLASS_xt_iclass_wsr_acchi, + ICLASS_xt_iclass_xsr_acchi, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_dyn, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dpfb, + ICLASS_xt_iclass_bpfnxt, + ICLASS_xt_iclass_dpdngrd, + ICLASS_xt_iclass_bpfctl, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_rsr_prefctl, + ICLASS_xt_iclass_wsr_prefctl, + ICLASS_xt_iclass_xsr_prefctl, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_xt_iclass_wb15_0, + ICLASS_xt_iclass_wb15_1, + ICLASS_xt_iclass_wb15_2, + ICLASS_xt_iclass_wb15_3, + ICLASS_xt_iclass_wb15_4, + ICLASS_rur_ae_ovf_sar, + ICLASS_wur_ae_ovf_sar, + ICLASS_rur_ae_bithead, + ICLASS_wur_ae_bithead, + ICLASS_rur_ae_ts_fts_bu_bp, + ICLASS_wur_ae_ts_fts_bu_bp, + ICLASS_rur_ae_cw_sd_no, + ICLASS_wur_ae_cw_sd_no, + ICLASS_rur_ae_cbegin0, + ICLASS_wur_ae_cbegin0, + ICLASS_rur_ae_cend0, + ICLASS_wur_ae_cend0, + ICLASS_rur_ae_cbegin1, + ICLASS_wur_ae_cbegin1, + ICLASS_rur_ae_cend1, + ICLASS_wur_ae_cend1, + ICLASS_ic_sext16, + ICLASS_ic_zext16, + ICLASS_ic_clamps16, + ICLASS_rur_fcr, + ICLASS_wur_fcr, + ICLASS_rur_fsr, + ICLASS_wur_fsr, + ICLASS_iclass_F64ITER, + ICLASS_iclass_F64RND, + ICLASS_iclass_F64ADDC_F64SUBC, + ICLASS_iclass_F64SIG, + ICLASS_iclass_F64CMPL, + ICLASS_iclass_F64CMPH, + ICLASS_iclass_F64NORM, + ICLASS_iclass_F64SEXP, + ICLASS_iclass_RF64R, + ICLASS_iclass_WF64R, + ICLASS_rur_f64r_lo, + ICLASS_wur_f64r_lo, + ICLASS_rur_f64r_hi, + ICLASS_wur_f64r_hi, + ICLASS_rur_f64s, + ICLASS_wur_f64s, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE, + ICLASS_RUR_AE_OVERFLOW, + ICLASS_WUR_AE_OVERFLOW, + ICLASS_RUR_AE_SAR, + ICLASS_WUR_AE_SAR, + ICLASS_RUR_AE_BITPTR, + ICLASS_WUR_AE_BITPTR, + ICLASS_RUR_AE_BITSUSED, + ICLASS_WUR_AE_BITSUSED, + ICLASS_RUR_AE_TABLESIZE, + ICLASS_WUR_AE_TABLESIZE, + ICLASS_RUR_AE_FIRST_TS, + ICLASS_WUR_AE_FIRST_TS, + ICLASS_RUR_AE_NEXTOFFSET, + ICLASS_WUR_AE_NEXTOFFSET, + ICLASS_RUR_AE_SEARCHDONE, + ICLASS_WUR_AE_SEARCHDONE, + ICLASS_RUR_AE_CWRAP, + ICLASS_WUR_AE_CWRAP, + ICLASS_AE_L8X4F_I, + ICLASS_AE_L8X4F_IP, + ICLASS_AE_L16M_XC, + ICLASS_AE_L16M_XC1, + ICLASS_AE_L16M_I, + ICLASS_AE_L16M_IU, + ICLASS_AE_L16M_X, + ICLASS_AE_L16M_XU, + ICLASS_AE_L16_XC, + ICLASS_AE_L16_XC1, + ICLASS_AE_L16_I, + ICLASS_AE_L16_IP, + ICLASS_AE_L16_X, + ICLASS_AE_L16_XP, + ICLASS_AE_L32F24_XC, + ICLASS_AE_L32F24_XC1, + ICLASS_AE_L32F24_I, + ICLASS_AE_L32F24_IP, + ICLASS_AE_L32F24_X, + ICLASS_AE_L32F24_XP, + ICLASS_AE_L32_XC, + ICLASS_AE_L32_XC1, + ICLASS_AE_L32_I, + ICLASS_AE_L32_IP, + ICLASS_AE_L32_X, + ICLASS_AE_L32_XP, + ICLASS_AE_L32M_XC, + ICLASS_AE_L32M_I, + ICLASS_AE_L32M_IU, + ICLASS_AE_L32M_X, + ICLASS_AE_L32M_XU, + ICLASS_AE_L16X2M_XC, + ICLASS_AE_L16X2M_XC1, + ICLASS_AE_L16X2M_I, + ICLASS_AE_L16X2M_IU, + ICLASS_AE_L16X2M_X, + ICLASS_AE_L16X2M_XU, + ICLASS_AE_L32X2F24_XC, + ICLASS_AE_L32X2F24_XC1, + ICLASS_AE_L32X2F24_I, + ICLASS_AE_L32X2F24_IP, + ICLASS_AE_L32X2F24_RIP, + ICLASS_AE_L32X2F24_RI, + ICLASS_AE_L32X2F24_RIC, + ICLASS_AE_L32X2F24_RIC1, + ICLASS_AE_L32X2F24_X, + ICLASS_AE_L32X2F24_XP, + ICLASS_AE_L32X2_XC, + ICLASS_AE_L32X2_XC1, + ICLASS_AE_L32X2_I, + ICLASS_AE_L32X2_IP, + ICLASS_AE_L32X2_RIC, + ICLASS_AE_L32X2_RIC1, + ICLASS_AE_L32X2_X, + ICLASS_AE_L32X2_XP, + ICLASS_AE_L16X4_XC, + ICLASS_AE_L16X4_XC1, + ICLASS_AE_L16X4_I, + ICLASS_AE_L16X4_IP, + ICLASS_AE_L16X4_X, + ICLASS_AE_L16X4_XP, + ICLASS_AE_L64_XC, + ICLASS_AE_L64_XC1, + ICLASS_AE_L64_I, + ICLASS_AE_L64_IP, + ICLASS_AE_L64_X, + ICLASS_AE_L64_XP, + ICLASS_AE_S16X2M_XC, + ICLASS_AE_S16X2M_XC1, + ICLASS_AE_S16X2M_I, + ICLASS_AE_S16X2M_IU, + ICLASS_AE_S16X2M_X, + ICLASS_AE_S16X2M_XU, + ICLASS_AE_S32X2F24_XC, + ICLASS_AE_S32X2F24_XC1, + ICLASS_AE_S32X2F24_I, + ICLASS_AE_S32X2F24_IP, + ICLASS_AE_S32X2F24_RIP, + ICLASS_AE_S32X2F24_RIC, + ICLASS_AE_S32X2F24_RIC1, + ICLASS_AE_S32X2F24_X, + ICLASS_AE_S32X2F24_XP, + ICLASS_AE_S32X2_XC, + ICLASS_AE_S32X2_XC1, + ICLASS_AE_S32X2_I, + ICLASS_AE_S32X2_IP, + ICLASS_AE_S32X2_RIC, + ICLASS_AE_S32X2_RIC1, + ICLASS_AE_S32X2_X, + ICLASS_AE_S32X2_XP, + ICLASS_AE_S32X2RNG_I, + ICLASS_AE_S32X2RNG_IP, + ICLASS_AE_S32X2RNG_X, + ICLASS_AE_S32X2RNG_XP, + ICLASS_AE_S16X4_XC, + ICLASS_AE_S16X4_XC1, + ICLASS_AE_S16X4_I, + ICLASS_AE_S16X4_IP, + ICLASS_AE_S16X4_X, + ICLASS_AE_S16X4_XP, + ICLASS_AE_S16M_L_XC, + ICLASS_AE_S16M_L_XC1, + ICLASS_AE_S16M_L_I, + ICLASS_AE_S16M_L_IU, + ICLASS_AE_S16M_L_X, + ICLASS_AE_S16M_L_XU, + ICLASS_AE_S32F24_L_XC, + ICLASS_AE_S32F24_L_XC1, + ICLASS_AE_S32F24_L_I, + ICLASS_AE_S32F24_L_IP, + ICLASS_AE_S32F24_L_X, + ICLASS_AE_S32F24_L_XP, + ICLASS_AE_S32_L_XC, + ICLASS_AE_S32_L_XC1, + ICLASS_AE_S32_L_I, + ICLASS_AE_S32_L_IP, + ICLASS_AE_S32_L_X, + ICLASS_AE_S32_L_XP, + ICLASS_AE_S16_0_XC, + ICLASS_AE_S16_0_XC1, + ICLASS_AE_S16_0_I, + ICLASS_AE_S16_0_IP, + ICLASS_AE_S16_0_X, + ICLASS_AE_S16_0_XP, + ICLASS_AE_S64_XC, + ICLASS_AE_S64_XC1, + ICLASS_AE_S64_I, + ICLASS_AE_S64_IP, + ICLASS_AE_S64_X, + ICLASS_AE_S64_XP, + ICLASS_AE_S32M_XC, + ICLASS_AE_S32M_I, + ICLASS_AE_S32M_IU, + ICLASS_AE_S32M_X, + ICLASS_AE_S32M_XU, + ICLASS_AE_ZALIGN64, + ICLASS_AE_LALIGN64_I, + ICLASS_AE_SALIGN64_I, + ICLASS_AE_MOVALIGN, + ICLASS_AE_LA64_PP, + ICLASS_AE_LA24POS_PC, + ICLASS_AE_LA24X2POS_PC, + ICLASS_AE_LA32X2POS_PC, + ICLASS_AE_LA16X4POS_PC, + ICLASS_AE_LA24NEG_PC, + ICLASS_AE_LA24X2NEG_PC, + ICLASS_AE_LA32X2NEG_PC, + ICLASS_AE_LA16X4NEG_PC, + ICLASS_AE_LA24POS_PC1, + ICLASS_AE_LA24X2POS_PC1, + ICLASS_AE_LA32X2POS_PC1, + ICLASS_AE_LA16X4POS_PC1, + ICLASS_AE_LA24NEG_PC1, + ICLASS_AE_LA24X2NEG_PC1, + ICLASS_AE_LA32X2NEG_PC1, + ICLASS_AE_LA16X4NEG_PC1, + ICLASS_AE_SA64POS_FP, + ICLASS_AE_SA64NEG_FP, + ICLASS_AE_LA32X2_IC, + ICLASS_AE_LA32X2_IC1, + ICLASS_AE_LA32X2_IP, + ICLASS_AE_LA32X2_RIP, + ICLASS_AE_LA32X2_RIC, + ICLASS_AE_LA32X2_RIC1, + ICLASS_AE_LA16X4_IC, + ICLASS_AE_LA16X4_IC1, + ICLASS_AE_LA16X4_IP, + ICLASS_AE_LA16X4_RIP, + ICLASS_AE_LA16X4_RIC, + ICLASS_AE_LA16X4_RIC1, + ICLASS_AE_LA32X2F24_IC, + ICLASS_AE_LA32X2F24_IC1, + ICLASS_AE_LA32X2F24_IP, + ICLASS_AE_LA32X2F24_RIP, + ICLASS_AE_LA32X2F24_RIC, + ICLASS_AE_LA32X2F24_RIC1, + ICLASS_AE_LA24_IC, + ICLASS_AE_LA24_IC1, + ICLASS_AE_LA24_IP, + ICLASS_AE_LA24_RIP, + ICLASS_AE_LA24_RIC, + ICLASS_AE_LA24_RIC1, + ICLASS_AE_LA24X2_IC, + ICLASS_AE_LA24X2_IC1, + ICLASS_AE_LA24X2_IP, + ICLASS_AE_LA24X2_RIP, + ICLASS_AE_LA24X2_RIC, + ICLASS_AE_LA24X2_RIC1, + ICLASS_AE_SA32X2_IC, + ICLASS_AE_SA32X2_IC1, + ICLASS_AE_SA32X2_IP, + ICLASS_AE_SA32X2_RIP, + ICLASS_AE_SA32X2_RIC, + ICLASS_AE_SA32X2_RIC1, + ICLASS_AE_SA16X4_IC, + ICLASS_AE_SA16X4_IC1, + ICLASS_AE_SA16X4_IP, + ICLASS_AE_SA16X4_RIP, + ICLASS_AE_SA16X4_RIC, + ICLASS_AE_SA16X4_RIC1, + ICLASS_AE_SA32X2F24_IC, + ICLASS_AE_SA32X2F24_IC1, + ICLASS_AE_SA32X2F24_IP, + ICLASS_AE_SA32X2F24_RIP, + ICLASS_AE_SA32X2F24_RIC, + ICLASS_AE_SA32X2F24_RIC1, + ICLASS_AE_SA24_L_IC, + ICLASS_AE_SA24_L_IC1, + ICLASS_AE_SA24_L_IP, + ICLASS_AE_SA24_L_RIP, + ICLASS_AE_SA24_L_RIC, + ICLASS_AE_SA24_L_RIC1, + ICLASS_AE_SA24X2_IC, + ICLASS_AE_SA24X2_IC1, + ICLASS_AE_SA24X2_IP, + ICLASS_AE_SA24X2_RIP, + ICLASS_AE_SA24X2_RIC, + ICLASS_AE_SA24X2_RIC1, + ICLASS_AE_ADDICIRC, + ICLASS_AE_ADDCIRC_XC1, + ICLASS_AE_ADDCIRC_XC, + ICLASS_AE_S32RA64S_I, + ICLASS_AE_S32RA64S_IP, + ICLASS_AE_S32RA64S_X, + ICLASS_AE_S32RA64S_XP, + ICLASS_AE_S32RA64S_XC, + ICLASS_AE_S32RA64S_XC1, + ICLASS_AE_S24RA64S_I, + ICLASS_AE_S24RA64S_IP, + ICLASS_AE_S24RA64S_X, + ICLASS_AE_S24RA64S_XP, + ICLASS_AE_S24RA64S_XC, + ICLASS_AE_S24RA64S_XC1, + ICLASS_AE_S32X2RA64S_IP, + ICLASS_AE_S24X2RA64S_IP, + ICLASS_AE_ADDBRBA32, + ICLASS_AE_BITSWAP, + ICLASS_AE_MUL32JS, + ICLASS_AE_ADDANDSUB32S, + ICLASS_AE_ADDANDSUBRNG32, + ICLASS_AE_ADDRNG32, + ICLASS_AE_SUBRNG32, + ICLASS_AE_CALCRNG3, + ICLASS_AE_CALCRNG2, + ICLASS_AE_CALCRNG1, + ICLASS_AE_RNG32X2, + ICLASS_AE_SEL16I, + ICLASS_AE_SEL16I_N, + ICLASS_AE_SHORTSWAP, + ICLASS_AE_MOVAB4, + ICLASS_AE_MOVAB2, + ICLASS_AE_MOVAB, + ICLASS_AE_MOVBA, + ICLASS_AE_MOVBA1X2, + ICLASS_AE_MOVBA4, + ICLASS_AE_MOVBA2, + ICLASS_AE_MOVB2, + ICLASS_AE_MOVB4, + ICLASS_AE_MOVT16X4, + ICLASS_AE_MOVF16X4, + ICLASS_AE_MOVT32X2, + ICLASS_AE_MOVF32X2, + ICLASS_AE_MOVSARA7X2, + ICLASS_AE_MOVSARD7, + ICLASS_AE_MOVASAR, + ICLASS_AE_MOVDA32X2, + ICLASS_AE_MOVDA32, + ICLASS_AE_MOVDA16X2, + ICLASS_AE_MOVDA16, + ICLASS_AE_MOVI, + ICLASS_AE_TRUNCP24A32X2, + ICLASS_AE_SAT16X4, + ICLASS_AE_CVT32X2F16_32, + ICLASS_AE_CVT32X2F16_10, + ICLASS_AE_SEXT32X2D16_32, + ICLASS_AE_SEXT32X2D16_10, + ICLASS_AE_CVTA32F24S_L, + ICLASS_AE_CVTA32F24S_H, + ICLASS_AE_CVTP24A16X2_LL, + ICLASS_AE_CVTP24A16X2_LH, + ICLASS_AE_CVTP24A16X2_HL, + ICLASS_AE_CVTP24A16X2_HH, + ICLASS_AE_TRUNCP24Q48X2, + ICLASS_AE_TRUNCA32X2F64S, + ICLASS_AE_TRUNCI32X2F64S, + ICLASS_AE_TRUNCA32F64S_L, + ICLASS_AE_TRUNCI32F64S_L, + ICLASS_AE_TRUNCP16, + ICLASS_AE_ROUND32X2F64SSYM, + ICLASS_AE_ROUND32X2F64SASYM, + ICLASS_AE_ROUND32X2F48SSYM, + ICLASS_AE_ROUND32X2F48SASYM, + ICLASS_AE_ROUND16X4F32SSYM, + ICLASS_AE_ROUND16X4F32SASYM, + ICLASS_AE_ROUND24X2F48SSYM, + ICLASS_AE_ROUND24X2F48SASYM, + ICLASS_AE_ROUNDSP16Q48X2SYM, + ICLASS_AE_ROUNDSP16Q48X2ASYM, + ICLASS_AE_MINABS32S, + ICLASS_AE_MAXABS32S, + ICLASS_AE_ROUNDSP16F24SYM, + ICLASS_AE_ROUNDSP16F24ASYM, + ICLASS_AE_MOV, + ICLASS_AE_MOVT64, + ICLASS_AE_MOVF64, + ICLASS_AE_CVTQ56A32S, + ICLASS_AE_CVT48A32, + ICLASS_AE_CVT64A32, + ICLASS_AE_CVTQ56P32S_L, + ICLASS_AE_CVTQ56P32S_H, + ICLASS_AE_CVT64F32_H, + ICLASS_AE_CVT48F32_L, + ICLASS_AE_CVT48F32_H, + ICLASS_AE_SAT48S, + ICLASS_AE_SATQ56S, + ICLASS_AE_SAT24S, + ICLASS_AE_TRUNCQ32, + ICLASS_AE_MINABS64S, + ICLASS_AE_MAXABS64S, + ICLASS_AE_ROUNDSQ32F48SYM, + ICLASS_AE_ROUNDSQ32F48ASYM, + ICLASS_AE_TRUNCA32Q48, + ICLASS_AE_MOVAD32_L, + ICLASS_AE_MOVAD32_H, + ICLASS_AE_MOVAD16_3, + ICLASS_AE_MOVAD16_2, + ICLASS_AE_MOVAD16_1, + ICLASS_AE_MOVAD16_0, + ICLASS_AE_SRA64_32, + ICLASS_AE_PKSR32, + ICLASS_AE_PKSR24, + ICLASS_AE_PKSRF32, + ICLASS_AE_TRUNCA16P24S_L, + ICLASS_AE_TRUNCA16P24S_H, + ICLASS_AE_ADD32, + ICLASS_AE_SUB32, + ICLASS_AE_ADDSUB32, + ICLASS_AE_SUBADD32, + ICLASS_AE_ADD16, + ICLASS_AE_SUB16, + ICLASS_AE_ADD32_HL_LH, + ICLASS_AE_NEG32, + ICLASS_AE_ABS32, + ICLASS_AE_ADD24S, + ICLASS_AE_SUB24S, + ICLASS_AE_ADD32S, + ICLASS_AE_SUB32S, + ICLASS_AE_ADDSUB32S, + ICLASS_AE_SUBADD32S, + ICLASS_AE_ADD16S, + ICLASS_AE_SUB16S, + ICLASS_AE_ADD32S_HL_LH, + ICLASS_AE_NEG24S, + ICLASS_AE_ABS24S, + ICLASS_AE_NEG32S, + ICLASS_AE_ABS32S, + ICLASS_AE_NEG16S, + ICLASS_AE_ABS16S, + ICLASS_AE_LT16, + ICLASS_AE_LE16, + ICLASS_AE_EQ16, + ICLASS_AE_LT32, + ICLASS_AE_LE32, + ICLASS_AE_EQ32, + ICLASS_AE_MIN32, + ICLASS_AE_MAX32, + ICLASS_AE_ADD64, + ICLASS_AE_SUB64, + ICLASS_AE_NEG64, + ICLASS_AE_ABS64, + ICLASS_AE_ADDSQ56S, + ICLASS_AE_SUBSQ56S, + ICLASS_AE_ADD64S, + ICLASS_AE_SUB64S, + ICLASS_AE_NEGSQ56S, + ICLASS_AE_ABSSQ56S, + ICLASS_AE_NEG64S, + ICLASS_AE_ABS64S, + ICLASS_AE_AND, + ICLASS_AE_NAND, + ICLASS_AE_OR, + ICLASS_AE_XOR, + ICLASS_AE_SLAI24, + ICLASS_AE_SRLI24, + ICLASS_AE_SRAI24, + ICLASS_AE_SLAS24, + ICLASS_AE_SRLS24, + ICLASS_AE_SRAS24, + ICLASS_AE_SRAI16, + ICLASS_AE_SRAI16R, + ICLASS_AE_SLAI32, + ICLASS_AE_SRLI32, + ICLASS_AE_SRAI32, + ICLASS_AE_SRAI32R, + ICLASS_AE_SLAS32, + ICLASS_AE_SRLS32, + ICLASS_AE_SRAS32, + ICLASS_AE_SLAA32, + ICLASS_AE_SRLA32, + ICLASS_AE_SRAA32, + ICLASS_AE_SLAI16S, + ICLASS_AE_SLAA16S, + ICLASS_AE_SRAA16S, + ICLASS_AE_SRAA16RS, + ICLASS_AE_SLAI24S, + ICLASS_AE_SLAS24S, + ICLASS_AE_SLAI32S, + ICLASS_AE_SLAS32S, + ICLASS_AE_SLAA32S, + ICLASS_AE_SRAA32S, + ICLASS_AE_SRAA32RS, + ICLASS_AE_SLASQ56, + ICLASS_AE_SRLSQ56, + ICLASS_AE_SRASQ56, + ICLASS_AE_SLAAQ56, + ICLASS_AE_SRLAQ56, + ICLASS_AE_SRAAQ56, + ICLASS_AE_SLAI64, + ICLASS_AE_SRLI64, + ICLASS_AE_SRAI64, + ICLASS_AE_SLAS64, + ICLASS_AE_SRLS64, + ICLASS_AE_SRAS64, + ICLASS_AE_SLAA64, + ICLASS_AE_SRLA64, + ICLASS_AE_SRAA64, + ICLASS_AE_SLAISQ56S, + ICLASS_AE_SLASSQ56S, + ICLASS_AE_SLAASQ56S, + ICLASS_AE_SLAI64S, + ICLASS_AE_SLAS64S, + ICLASS_AE_SLAA64S, + ICLASS_AE_LT64, + ICLASS_AE_LE64, + ICLASS_AE_EQ64, + ICLASS_AE_MAX64, + ICLASS_AE_MIN64, + ICLASS_AE_NSA64, + ICLASS_AE_NSAZ16_0, + ICLASS_AE_NSAZ32_L, + ICLASS_AE_MULS32F48P16S_LL, + ICLASS_AE_MULF32S_LL, + ICLASS_AE_MUL32_LL, + ICLASS_AE_MULF32S_LL_S2, + ICLASS_AE_MUL32_LL_S2, + ICLASS_AE_MULS32F48P16S_LL_S2, + ICLASS_AE_MULF32R_LL, + ICLASS_AE_MULF32RA_LL, + ICLASS_AE_MULF32RA_LL_S2, + ICLASS_AE_MULF32R_LL_S2, + ICLASS_AE_MULS32F48P16S_LH, + ICLASS_AE_MULF32S_LH, + ICLASS_AE_MUL32_LH, + ICLASS_AE_MULF32S_LH_S2, + ICLASS_AE_MUL32_LH_S2, + ICLASS_AE_MULS32F48P16S_LH_S2, + ICLASS_AE_MULF32R_LH, + ICLASS_AE_MULF32RA_LH, + ICLASS_AE_MULF32RA_LH_S2, + ICLASS_AE_MULF32R_LH_S2, + ICLASS_AE_MULS32F48P16S_HH, + ICLASS_AE_MULF32S_HH, + ICLASS_AE_MUL32_HH, + ICLASS_AE_MULF32S_HH_S2, + ICLASS_AE_MUL32_HH_S2, + ICLASS_AE_MULS32F48P16S_HH_S2, + ICLASS_AE_MULF32R_HH, + ICLASS_AE_MULF32RA_HH, + ICLASS_AE_MULF32RA_HH_S2, + ICLASS_AE_MULF32R_HH_S2, + ICLASS_AE_MULAS32F48P16S_LL, + ICLASS_AE_MULAF32S_LL, + ICLASS_AE_MULA32_LL, + ICLASS_AE_MULAF32S_LL_S2, + ICLASS_AE_MULA32_LL_S2, + ICLASS_AE_MULAS32F48P16S_LL_S2, + ICLASS_AE_MULAF32R_LL, + ICLASS_AE_MULAF32RA_LL, + ICLASS_AE_MULAF32RA_LL_S2, + ICLASS_AE_MULAF32R_LL_S2, + ICLASS_AE_MULAS32F48P16S_LH, + ICLASS_AE_MULAF32S_LH, + ICLASS_AE_MULA32_LH, + ICLASS_AE_MULAF32S_LH_S2, + ICLASS_AE_MULA32_LH_S2, + ICLASS_AE_MULAS32F48P16S_LH_S2, + ICLASS_AE_MULAF32R_LH, + ICLASS_AE_MULAF32RA_LH, + ICLASS_AE_MULAF32RA_LH_S2, + ICLASS_AE_MULAF32R_LH_S2, + ICLASS_AE_MULAS32F48P16S_HH, + ICLASS_AE_MULAF32S_HH, + ICLASS_AE_MULA32_HH, + ICLASS_AE_MULAF32S_HH_S2, + ICLASS_AE_MULA32_HH_S2, + ICLASS_AE_MULAS32F48P16S_HH_S2, + ICLASS_AE_MULAF32R_HH, + ICLASS_AE_MULAF32RA_HH, + ICLASS_AE_MULAF32RA_HH_S2, + ICLASS_AE_MULAF32R_HH_S2, + ICLASS_AE_MULSS32F48P16S_LL, + ICLASS_AE_MULSF32S_LL, + ICLASS_AE_MULS32_LL, + ICLASS_AE_MULSF32S_LL_S2, + ICLASS_AE_MULS32_LL_S2, + ICLASS_AE_MULSS32F48P16S_LL_S2, + ICLASS_AE_MULSF32R_LL, + ICLASS_AE_MULSF32RA_LL, + ICLASS_AE_MULSF32RA_LL_S2, + ICLASS_AE_MULSF32R_LL_S2, + ICLASS_AE_MULSS32F48P16S_LH, + ICLASS_AE_MULSF32S_LH, + ICLASS_AE_MULS32_LH, + ICLASS_AE_MULSF32S_LH_S2, + ICLASS_AE_MULS32_LH_S2, + ICLASS_AE_MULSS32F48P16S_LH_S2, + ICLASS_AE_MULSF32R_LH, + ICLASS_AE_MULSF32RA_LH, + ICLASS_AE_MULSF32RA_LH_S2, + ICLASS_AE_MULSF32R_LH_S2, + ICLASS_AE_MULSS32F48P16S_HH, + ICLASS_AE_MULSF32S_HH, + ICLASS_AE_MULS32_HH, + ICLASS_AE_MULSF32S_HH_S2, + ICLASS_AE_MULS32_HH_S2, + ICLASS_AE_MULSS32F48P16S_HH_S2, + ICLASS_AE_MULSF32R_HH, + ICLASS_AE_MULSF32RA_HH, + ICLASS_AE_MULSF32RA_HH_S2, + ICLASS_AE_MULSF32R_HH_S2, + ICLASS_AE_MUL32U_LL, + ICLASS_AE_MULA32U_LL, + ICLASS_AE_MULS32U_LL, + ICLASS_AE_MULF16SS_33, + ICLASS_AE_MULF16SS_33_S2, + ICLASS_AE_MULF16SS_22, + ICLASS_AE_MULF16SS_22_S2, + ICLASS_AE_MULF16SS_32, + ICLASS_AE_MULF16SS_32_S2, + ICLASS_AE_MULF16SS_21, + ICLASS_AE_MULF16SS_21_S2, + ICLASS_AE_MULF16SS_31, + ICLASS_AE_MULF16SS_31_S2, + ICLASS_AE_MULF16SS_30, + ICLASS_AE_MULF16SS_30_S2, + ICLASS_AE_MULF16SS_10, + ICLASS_AE_MULF16SS_10_S2, + ICLASS_AE_MULF16SS_20, + ICLASS_AE_MULF16SS_20_S2, + ICLASS_AE_MULF16SS_11, + ICLASS_AE_MULF16SS_11_S2, + ICLASS_AE_MULF16SS_00, + ICLASS_AE_MULF16SS_00_S2, + ICLASS_AE_MULSF16SS_33, + ICLASS_AE_MULSF16SS_33_S2, + ICLASS_AE_MULSF16SS_22, + ICLASS_AE_MULSF16SS_22_S2, + ICLASS_AE_MULSF16SS_32, + ICLASS_AE_MULSF16SS_32_S2, + ICLASS_AE_MULSF16SS_21, + ICLASS_AE_MULSF16SS_21_S2, + ICLASS_AE_MULSF16SS_31, + ICLASS_AE_MULSF16SS_31_S2, + ICLASS_AE_MULSF16SS_30, + ICLASS_AE_MULSF16SS_30_S2, + ICLASS_AE_MULSF16SS_10, + ICLASS_AE_MULSF16SS_10_S2, + ICLASS_AE_MULSF16SS_20, + ICLASS_AE_MULSF16SS_20_S2, + ICLASS_AE_MULSF16SS_11, + ICLASS_AE_MULSF16SS_11_S2, + ICLASS_AE_MULSF16SS_00, + ICLASS_AE_MULSF16SS_00_S2, + ICLASS_AE_MULAF16SS_33, + ICLASS_AE_MULAF16SS_33_S2, + ICLASS_AE_MULAF16SS_22, + ICLASS_AE_MULAF16SS_22_S2, + ICLASS_AE_MULAF16SS_32, + ICLASS_AE_MULAF16SS_32_S2, + ICLASS_AE_MULAF16SS_21, + ICLASS_AE_MULAF16SS_21_S2, + ICLASS_AE_MULAF16SS_31, + ICLASS_AE_MULAF16SS_31_S2, + ICLASS_AE_MULAF16SS_30, + ICLASS_AE_MULAF16SS_30_S2, + ICLASS_AE_MULAF16SS_10, + ICLASS_AE_MULAF16SS_10_S2, + ICLASS_AE_MULAF16SS_20, + ICLASS_AE_MULAF16SS_20_S2, + ICLASS_AE_MULAF16SS_11, + ICLASS_AE_MULAF16SS_11_S2, + ICLASS_AE_MULAF16SS_00, + ICLASS_AE_MULAF16SS_00_S2, + ICLASS_AE_MULAAFD16SS_33_22, + ICLASS_AE_MULAAFD16SS_33_22_S2, + ICLASS_AE_MULAAFD16SS_13_02, + ICLASS_AE_MULAAFD16SS_13_02_S2, + ICLASS_AE_MULAAFD16SS_11_00, + ICLASS_AE_MULAAFD16SS_11_00_S2, + ICLASS_AE_MULSSFD16SS_33_22, + ICLASS_AE_MULSSFD16SS_33_22_S2, + ICLASS_AE_MULSSFD16SS_13_02, + ICLASS_AE_MULSSFD16SS_13_02_S2, + ICLASS_AE_MULSSFD16SS_11_00, + ICLASS_AE_MULSSFD16SS_11_00_S2, + ICLASS_AE_MULZAAFD16SS_33_22, + ICLASS_AE_MULZAAFD16SS_33_22_S2, + ICLASS_AE_MULZAAFD16SS_13_02, + ICLASS_AE_MULZAAFD16SS_13_02_S2, + ICLASS_AE_MULZAAFD16SS_11_00, + ICLASS_AE_MULZAAFD16SS_11_00_S2, + ICLASS_AE_MULZSSFD16SS_33_22, + ICLASS_AE_MULZSSFD16SS_33_22_S2, + ICLASS_AE_MULZSSFD16SS_13_02, + ICLASS_AE_MULZSSFD16SS_13_02_S2, + ICLASS_AE_MULZSSFD16SS_11_00, + ICLASS_AE_MULZSSFD16SS_11_00_S2, + ICLASS_AE_MULF48Q32SP16S_L, + ICLASS_AE_MULF48Q32SP16S_L_S2, + ICLASS_AE_MULF48Q32SP16U_L, + ICLASS_AE_MULF48Q32SP16U_L_S2, + ICLASS_AE_MULQ32SP16S_L, + ICLASS_AE_MULQ32SP16S_L_S2, + ICLASS_AE_MULQ32SP16U_L, + ICLASS_AE_MULQ32SP16U_L_S2, + ICLASS_AE_MULAF48Q32SP16S_L, + ICLASS_AE_MULAF48Q32SP16S_L_S2, + ICLASS_AE_MULAF48Q32SP16U_L, + ICLASS_AE_MULAF48Q32SP16U_L_S2, + ICLASS_AE_MULAQ32SP16S_L, + ICLASS_AE_MULAQ32SP16S_L_S2, + ICLASS_AE_MULAQ32SP16U_L, + ICLASS_AE_MULAQ32SP16U_L_S2, + ICLASS_AE_MULSF48Q32SP16S_L, + ICLASS_AE_MULSF48Q32SP16S_L_S2, + ICLASS_AE_MULSF48Q32SP16U_L, + ICLASS_AE_MULSF48Q32SP16U_L_S2, + ICLASS_AE_MULSQ32SP16S_L, + ICLASS_AE_MULSQ32SP16S_L_S2, + ICLASS_AE_MULSQ32SP16U_L, + ICLASS_AE_MULSQ32SP16U_L_S2, + ICLASS_AE_MULFP24X2RA, + ICLASS_AE_MULFP24X2R, + ICLASS_AE_MULFP24X2RA_S2, + ICLASS_AE_MULFP24X2R_S2, + ICLASS_AE_MULAFP24X2RA, + ICLASS_AE_MULAFP24X2R, + ICLASS_AE_MULAFP24X2RA_S2, + ICLASS_AE_MULAFP24X2R_S2, + ICLASS_AE_MULSFP24X2RA, + ICLASS_AE_MULSFP24X2R, + ICLASS_AE_MULSFP24X2RA_S2, + ICLASS_AE_MULSFP24X2R_S2, + ICLASS_AE_MULZAAFD32S_HH_LL, + ICLASS_AE_MULZAAFD32RA_HH_LL, + ICLASS_AE_MULZAAD32_HH_LL, + ICLASS_AE_MULZAAFD32S_HH_LL_S2, + ICLASS_AE_MULZAAFD32RA_HH_LL_S2, + ICLASS_AE_MULZAAD32_HH_LL_S2, + ICLASS_AE_MULZAAFD32S_HL_LH, + ICLASS_AE_MULZAAFD32RA_HL_LH, + ICLASS_AE_MULZAAD32_HL_LH, + ICLASS_AE_MULZAAFD32S_HL_LH_S2, + ICLASS_AE_MULZAAFD32RA_HL_LH_S2, + ICLASS_AE_MULZAAD32_HL_LH_S2, + ICLASS_AE_MULZASFD32S_HH_LL, + ICLASS_AE_MULZASFD32RA_HH_LL, + ICLASS_AE_MULZASD32_HH_LL, + ICLASS_AE_MULZASFD32S_HH_LL_S2, + ICLASS_AE_MULZASFD32RA_HH_LL_S2, + ICLASS_AE_MULZASD32_HH_LL_S2, + ICLASS_AE_MULZASFD32S_HL_LH, + ICLASS_AE_MULZASFD32RA_HL_LH, + ICLASS_AE_MULZASD32_HL_LH, + ICLASS_AE_MULZASFD32S_HL_LH_S2, + ICLASS_AE_MULZASFD32RA_HL_LH_S2, + ICLASS_AE_MULZASD32_HL_LH_S2, + ICLASS_AE_MULZSAFD32S_HH_LL, + ICLASS_AE_MULZSAFD32RA_HH_LL, + ICLASS_AE_MULZSAD32_HH_LL, + ICLASS_AE_MULZSAFD32S_HH_LL_S2, + ICLASS_AE_MULZSAFD32RA_HH_LL_S2, + ICLASS_AE_MULZSAD32_HH_LL_S2, + ICLASS_AE_MULZSSFD32S_HH_LL, + ICLASS_AE_MULZSSFD32RA_HH_LL, + ICLASS_AE_MULZSSD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HH_LL_S2, + ICLASS_AE_MULZSSFD32RA_HH_LL_S2, + ICLASS_AE_MULZSSD32_HH_LL_S2, + ICLASS_AE_MULZSSFD32S_HL_LH, + ICLASS_AE_MULZSSFD32RA_HL_LH, + ICLASS_AE_MULZSSD32_HL_LH, + ICLASS_AE_MULZSSFD32S_HL_LH_S2, + ICLASS_AE_MULZSSFD32RA_HL_LH_S2, + ICLASS_AE_MULZSSD32_HL_LH_S2, + ICLASS_AE_MULAAFD32S_HH_LL, + ICLASS_AE_MULAAFD32RA_HH_LL, + ICLASS_AE_MULAAD32_HH_LL, + ICLASS_AE_MULAAFD32S_HH_LL_S2, + ICLASS_AE_MULAAFD32RA_HH_LL_S2, + ICLASS_AE_MULAAD32_HH_LL_S2, + ICLASS_AE_MULAAFD32S_HL_LH, + ICLASS_AE_MULAAFD32RA_HL_LH, + ICLASS_AE_MULAAD32_HL_LH, + ICLASS_AE_MULAAFD32S_HL_LH_S2, + ICLASS_AE_MULAAFD32RA_HL_LH_S2, + ICLASS_AE_MULAAD32_HL_LH_S2, + ICLASS_AE_MULASFD32S_HH_LL, + ICLASS_AE_MULASFD32RA_HH_LL, + ICLASS_AE_MULASD32_HH_LL, + ICLASS_AE_MULASFD32S_HH_LL_S2, + ICLASS_AE_MULASFD32RA_HH_LL_S2, + ICLASS_AE_MULASD32_HH_LL_S2, + ICLASS_AE_MULASFD32S_HL_LH, + ICLASS_AE_MULASFD32RA_HL_LH, + ICLASS_AE_MULASD32_HL_LH, + ICLASS_AE_MULASFD32S_HL_LH_S2, + ICLASS_AE_MULASFD32RA_HL_LH_S2, + ICLASS_AE_MULASD32_HL_LH_S2, + ICLASS_AE_MULSAFD32S_HH_LL, + ICLASS_AE_MULSAFD32RA_HH_LL, + ICLASS_AE_MULSAD32_HH_LL, + ICLASS_AE_MULSAFD32S_HH_LL_S2, + ICLASS_AE_MULSAFD32RA_HH_LL_S2, + ICLASS_AE_MULSAD32_HH_LL_S2, + ICLASS_AE_MULSSFD32S_HH_LL, + ICLASS_AE_MULSSFD32RA_HH_LL, + ICLASS_AE_MULSSD32_HH_LL, + ICLASS_AE_MULSSFD32S_HH_LL_S2, + ICLASS_AE_MULSSFD32RA_HH_LL_S2, + ICLASS_AE_MULSSD32_HH_LL_S2, + ICLASS_AE_MULSSFD32S_HL_LH, + ICLASS_AE_MULSSFD32RA_HL_LH, + ICLASS_AE_MULSSD32_HL_LH, + ICLASS_AE_MULSSFD32S_HL_LH_S2, + ICLASS_AE_MULSSFD32RA_HL_LH_S2, + ICLASS_AE_MULSSD32_HL_LH_S2, + ICLASS_AE_MULF32X16_L0, + ICLASS_AE_MUL32X16_L0, + ICLASS_AE_MULF32X16_L0_S2, + ICLASS_AE_MUL32X16_L0_S2, + ICLASS_AE_MULF32X16_L1, + ICLASS_AE_MUL32X16_L1, + ICLASS_AE_MULF32X16_L1_S2, + ICLASS_AE_MUL32X16_L1_S2, + ICLASS_AE_MULF32X16_L2, + ICLASS_AE_MUL32X16_L2, + ICLASS_AE_MULF32X16_L2_S2, + ICLASS_AE_MUL32X16_L2_S2, + ICLASS_AE_MULF32X16_L3, + ICLASS_AE_MUL32X16_L3, + ICLASS_AE_MULF32X16_L3_S2, + ICLASS_AE_MUL32X16_L3_S2, + ICLASS_AE_MULF32X16_H0, + ICLASS_AE_MUL32X16_H0, + ICLASS_AE_MULF32X16_H0_S2, + ICLASS_AE_MUL32X16_H0_S2, + ICLASS_AE_MULF32X16_H1, + ICLASS_AE_MUL32X16_H1, + ICLASS_AE_MULF32X16_H1_S2, + ICLASS_AE_MUL32X16_H1_S2, + ICLASS_AE_MULF32X16_H2, + ICLASS_AE_MUL32X16_H2, + ICLASS_AE_MULF32X16_H2_S2, + ICLASS_AE_MUL32X16_H2_S2, + ICLASS_AE_MULF32X16_H3, + ICLASS_AE_MUL32X16_H3, + ICLASS_AE_MULF32X16_H3_S2, + ICLASS_AE_MUL32X16_H3_S2, + ICLASS_AE_MULAF32X16_L0, + ICLASS_AE_MULA32X16_L0, + ICLASS_AE_MULAF32X16_L0_S2, + ICLASS_AE_MULA32X16_L0_S2, + ICLASS_AE_MULAF32X16_L1, + ICLASS_AE_MULA32X16_L1, + ICLASS_AE_MULAF32X16_L1_S2, + ICLASS_AE_MULA32X16_L1_S2, + ICLASS_AE_MULAF32X16_L2, + ICLASS_AE_MULA32X16_L2, + ICLASS_AE_MULAF32X16_L2_S2, + ICLASS_AE_MULA32X16_L2_S2, + ICLASS_AE_MULAF32X16_L3, + ICLASS_AE_MULA32X16_L3, + ICLASS_AE_MULAF32X16_L3_S2, + ICLASS_AE_MULA32X16_L3_S2, + ICLASS_AE_MULAF32X16_H0, + ICLASS_AE_MULA32X16_H0, + ICLASS_AE_MULAF32X16_H0_S2, + ICLASS_AE_MULA32X16_H0_S2, + ICLASS_AE_MULAF32X16_H1, + ICLASS_AE_MULA32X16_H1, + ICLASS_AE_MULAF32X16_H1_S2, + ICLASS_AE_MULA32X16_H1_S2, + ICLASS_AE_MULAF32X16_H2, + ICLASS_AE_MULA32X16_H2, + ICLASS_AE_MULAF32X16_H2_S2, + ICLASS_AE_MULA32X16_H2_S2, + ICLASS_AE_MULAF32X16_H3, + ICLASS_AE_MULA32X16_H3, + ICLASS_AE_MULAF32X16_H3_S2, + ICLASS_AE_MULA32X16_H3_S2, + ICLASS_AE_MULSF32X16_L0, + ICLASS_AE_MULS32X16_L0, + ICLASS_AE_MULSF32X16_L0_S2, + ICLASS_AE_MULS32X16_L0_S2, + ICLASS_AE_MULSF32X16_L1, + ICLASS_AE_MULS32X16_L1, + ICLASS_AE_MULSF32X16_L1_S2, + ICLASS_AE_MULS32X16_L1_S2, + ICLASS_AE_MULSF32X16_L2, + ICLASS_AE_MULS32X16_L2, + ICLASS_AE_MULSF32X16_L2_S2, + ICLASS_AE_MULS32X16_L2_S2, + ICLASS_AE_MULSF32X16_L3, + ICLASS_AE_MULS32X16_L3, + ICLASS_AE_MULSF32X16_L3_S2, + ICLASS_AE_MULS32X16_L3_S2, + ICLASS_AE_MULSF32X16_H0, + ICLASS_AE_MULS32X16_H0, + ICLASS_AE_MULSF32X16_H0_S2, + ICLASS_AE_MULS32X16_H0_S2, + ICLASS_AE_MULSF32X16_H1, + ICLASS_AE_MULS32X16_H1, + ICLASS_AE_MULSF32X16_H1_S2, + ICLASS_AE_MULS32X16_H1_S2, + ICLASS_AE_MULSF32X16_H2, + ICLASS_AE_MULS32X16_H2, + ICLASS_AE_MULSF32X16_H2_S2, + ICLASS_AE_MULS32X16_H2_S2, + ICLASS_AE_MULSF32X16_H3, + ICLASS_AE_MULS32X16_H3, + ICLASS_AE_MULSF32X16_H3_S2, + ICLASS_AE_MULS32X16_H3_S2, + ICLASS_AE_MULAAFD32X16_H3_L2, + ICLASS_AE_MULAAD32X16_H3_L2, + ICLASS_AE_MULAAFD32X16_H3_L2_S2, + ICLASS_AE_MULAAD32X16_H3_L2_S2, + ICLASS_AE_MULAAFD32X16_H1_L0, + ICLASS_AE_MULAAD32X16_H1_L0, + ICLASS_AE_MULAAFD32X16_H1_L0_S2, + ICLASS_AE_MULAAD32X16_H1_L0_S2, + ICLASS_AE_MULASFD32X16_H3_L2, + ICLASS_AE_MULASD32X16_H3_L2, + ICLASS_AE_MULASFD32X16_H3_L2_S2, + ICLASS_AE_MULASD32X16_H3_L2_S2, + ICLASS_AE_MULASFD32X16_H1_L0, + ICLASS_AE_MULASD32X16_H1_L0, + ICLASS_AE_MULASFD32X16_H1_L0_S2, + ICLASS_AE_MULASD32X16_H1_L0_S2, + ICLASS_AE_MULSAFD32X16_H3_L2, + ICLASS_AE_MULSAD32X16_H3_L2, + ICLASS_AE_MULSAFD32X16_H3_L2_S2, + ICLASS_AE_MULSAD32X16_H3_L2_S2, + ICLASS_AE_MULSAFD32X16_H1_L0, + ICLASS_AE_MULSAD32X16_H1_L0, + ICLASS_AE_MULSAFD32X16_H1_L0_S2, + ICLASS_AE_MULSAD32X16_H1_L0_S2, + ICLASS_AE_MULSSFD32X16_H3_L2, + ICLASS_AE_MULSSD32X16_H3_L2, + ICLASS_AE_MULSSFD32X16_H3_L2_S2, + ICLASS_AE_MULSSD32X16_H3_L2_S2, + ICLASS_AE_MULSSFD32X16_H1_L0, + ICLASS_AE_MULSSD32X16_H1_L0, + ICLASS_AE_MULSSFD32X16_H1_L0_S2, + ICLASS_AE_MULSSD32X16_H1_L0_S2, + ICLASS_AE_MULZAAFD32X16_H3_L2, + ICLASS_AE_MULZAAD32X16_H3_L2, + ICLASS_AE_MULZAAFD32X16_H3_L2_S2, + ICLASS_AE_MULZAAD32X16_H3_L2_S2, + ICLASS_AE_MULZAAFD32X16_H1_L0, + ICLASS_AE_MULZAAD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H1_L0_S2, + ICLASS_AE_MULZAAD32X16_H1_L0_S2, + ICLASS_AE_MULZASFD32X16_H3_L2, + ICLASS_AE_MULZASD32X16_H3_L2, + ICLASS_AE_MULZASFD32X16_H3_L2_S2, + ICLASS_AE_MULZASD32X16_H3_L2_S2, + ICLASS_AE_MULZASFD32X16_H1_L0, + ICLASS_AE_MULZASD32X16_H1_L0, + ICLASS_AE_MULZASFD32X16_H1_L0_S2, + ICLASS_AE_MULZASD32X16_H1_L0_S2, + ICLASS_AE_MULZSAFD32X16_H3_L2, + ICLASS_AE_MULZSAD32X16_H3_L2, + ICLASS_AE_MULZSAFD32X16_H3_L2_S2, + ICLASS_AE_MULZSAD32X16_H3_L2_S2, + ICLASS_AE_MULZSAFD32X16_H1_L0, + ICLASS_AE_MULZSAD32X16_H1_L0, + ICLASS_AE_MULZSAFD32X16_H1_L0_S2, + ICLASS_AE_MULZSAD32X16_H1_L0_S2, + ICLASS_AE_MULZSSFD32X16_H3_L2, + ICLASS_AE_MULZSSD32X16_H3_L2, + ICLASS_AE_MULZSSFD32X16_H3_L2_S2, + ICLASS_AE_MULZSSD32X16_H3_L2_S2, + ICLASS_AE_MULZSSFD32X16_H1_L0, + ICLASS_AE_MULZSSD32X16_H1_L0, + ICLASS_AE_MULZSSFD32X16_H1_L0_S2, + ICLASS_AE_MULZSSD32X16_H1_L0_S2, + ICLASS_AE_MULZAAFD32X16_H2_L3, + ICLASS_AE_MULZAAFD32X16_H0_L1, + ICLASS_AE_MULAAFD32X16_H2_L3, + ICLASS_AE_MULAAFD32X16_H0_L1, + ICLASS_AE_MULZAAD32X16_H2_L3, + ICLASS_AE_MULZAAD32X16_H0_L1, + ICLASS_AE_MULAAD32X16_H2_L3, + ICLASS_AE_MULAAD32X16_H0_L1, + ICLASS_AE_MULZAAFD32X16_H2_L3_S2, + ICLASS_AE_MULZAAFD32X16_H0_L1_S2, + ICLASS_AE_MULAAFD32X16_H2_L3_S2, + ICLASS_AE_MULAAFD32X16_H0_L1_S2, + ICLASS_AE_MULZAAD32X16_H2_L3_S2, + ICLASS_AE_MULZAAD32X16_H0_L1_S2, + ICLASS_AE_MULAAD32X16_H2_L3_S2, + ICLASS_AE_MULAAD32X16_H0_L1_S2, + ICLASS_AE_MULP32X16X2_H, + ICLASS_AE_MULFP32X16X2RS_H, + ICLASS_AE_MULFP32X16X2RAS_H, + ICLASS_AE_MULFP32X16X2S_H, + ICLASS_AE_MULFP32X16X2S_H_S2, + ICLASS_AE_MULP32X16X2_H_S2, + ICLASS_AE_MULFP32X16X2RS_H_S2, + ICLASS_AE_MULFP32X16X2RAS_H_S2, + ICLASS_AE_MULP32X16X2_L, + ICLASS_AE_MULFP32X16X2RS_L, + ICLASS_AE_MULFP32X16X2RAS_L, + ICLASS_AE_MULFP32X16X2S_L, + ICLASS_AE_MULFP32X16X2S_L_S2, + ICLASS_AE_MULP32X16X2_L_S2, + ICLASS_AE_MULFP32X16X2RS_L_S2, + ICLASS_AE_MULFP32X16X2RAS_L_S2, + ICLASS_AE_MULAP32X16X2_H, + ICLASS_AE_MULAFP32X16X2RS_H, + ICLASS_AE_MULAFP32X16X2RAS_H, + ICLASS_AE_MULAFP32X16X2S_H, + ICLASS_AE_MULAFP32X16X2S_H_S2, + ICLASS_AE_MULAP32X16X2_H_S2, + ICLASS_AE_MULAFP32X16X2RS_H_S2, + ICLASS_AE_MULAFP32X16X2RAS_H_S2, + ICLASS_AE_MULAP32X16X2_L, + ICLASS_AE_MULAFP32X16X2RS_L, + ICLASS_AE_MULAFP32X16X2RAS_L, + ICLASS_AE_MULAFP32X16X2S_L, + ICLASS_AE_MULAFP32X16X2S_L_S2, + ICLASS_AE_MULAP32X16X2_L_S2, + ICLASS_AE_MULAFP32X16X2RS_L_S2, + ICLASS_AE_MULAFP32X16X2RAS_L_S2, + ICLASS_AE_MULSP32X16X2_H, + ICLASS_AE_MULSFP32X16X2RS_H, + ICLASS_AE_MULSFP32X16X2RAS_H, + ICLASS_AE_MULSFP32X16X2S_H, + ICLASS_AE_MULSFP32X16X2S_H_S2, + ICLASS_AE_MULSP32X16X2_H_S2, + ICLASS_AE_MULSFP32X16X2RS_H_S2, + ICLASS_AE_MULSFP32X16X2RAS_H_S2, + ICLASS_AE_MULSP32X16X2_L, + ICLASS_AE_MULSFP32X16X2RS_L, + ICLASS_AE_MULSFP32X16X2RAS_L, + ICLASS_AE_MULSFP32X16X2S_L, + ICLASS_AE_MULSFP32X16X2S_L_S2, + ICLASS_AE_MULSP32X16X2_L_S2, + ICLASS_AE_MULSFP32X16X2RS_L_S2, + ICLASS_AE_MULSFP32X16X2RAS_L_S2, + ICLASS_AE_MULP32X2, + ICLASS_AE_MULFP32X2RS, + ICLASS_AE_MULFP32X2RAS, + ICLASS_AE_MULP32X2_S2, + ICLASS_AE_MULFP32X2RS_S2, + ICLASS_AE_MULFP32X2RAS_S2, + ICLASS_AE_MULAP32X2, + ICLASS_AE_MULAFP32X2RS, + ICLASS_AE_MULAFP32X2RAS, + ICLASS_AE_MULAP32X2_S2, + ICLASS_AE_MULAFP32X2RS_S2, + ICLASS_AE_MULAFP32X2RAS_S2, + ICLASS_AE_MULSP32X2, + ICLASS_AE_MULSFP32X2RS, + ICLASS_AE_MULSFP32X2RAS, + ICLASS_AE_MULSP32X2_S2, + ICLASS_AE_MULSFP32X2RS_S2, + ICLASS_AE_MULSFP32X2RAS_S2, + ICLASS_AE_MULFP16X4S, + ICLASS_AE_MULFP16X4RAS, + ICLASS_AE_MULC32, + ICLASS_AE_MULFC24RA, + ICLASS_AE_MULFC32RAS, + ICLASS_AE_MULC32X16_L, + ICLASS_AE_MULFC32X16RAS_L, + ICLASS_AE_MULC32X16_H, + ICLASS_AE_MULFC32X16RAS_H, + ICLASS_AE_MULAC32, + ICLASS_AE_MULAFC24RA, + ICLASS_AE_MULAFC32RAS, + ICLASS_AE_MULAC32X16_L, + ICLASS_AE_MULAFC32X16RAS_L, + ICLASS_AE_MULAC32X16_H, + ICLASS_AE_MULAFC32X16RAS_H, + ICLASS_AE_MULF16X4SS, + ICLASS_AE_MULAF16X4SS, + ICLASS_AE_MULSF16X4SS, + ICLASS_AE_MUL16X4, + ICLASS_AE_MULA16X4, + ICLASS_AE_MULS16X4, + ICLASS_AE_MULFD32X2S_FIR_H, + ICLASS_AE_MULFD32X2RA_FIR_H, + ICLASS_AE_MULFD32X2S_FIR_L, + ICLASS_AE_MULFD32X2RA_FIR_L, + ICLASS_AE_MULFD32X16X2_FIR_HH, + ICLASS_AE_MULFD32X16X2_FIR_HL, + ICLASS_AE_MULFD32X16X2_FIR_LH, + ICLASS_AE_MULFD32X16X2_FIR_LL, + ICLASS_AE_MULAFD32X2S_FIR_H, + ICLASS_AE_MULAFD32X2RA_FIR_H, + ICLASS_AE_MULAFD32X2S_FIR_L, + ICLASS_AE_MULAFD32X2RA_FIR_L, + ICLASS_AE_MULAFD32X16X2_FIR_HH, + ICLASS_AE_MULAFD32X16X2_FIR_HL, + ICLASS_AE_MULAFD32X16X2_FIR_LH, + ICLASS_AE_MULAFD32X16X2_FIR_LL, + ICLASS_AE_MULZAAAAFQ32X16, + ICLASS_AE_MULAAAAFQ32X16, + ICLASS_AE_MULZAAAAFQ32X16_S2, + ICLASS_AE_MULAAAAFQ32X16_S2, + ICLASS_AE_MULZAAAAQ32X16, + ICLASS_AE_MULAAAAQ32X16, + ICLASS_AE_MULZAAAAQ32X16_S2, + ICLASS_AE_MULAAAAQ32X16_S2, + ICLASS_AE_MUL16_00, + ICLASS_AE_MULA16_00, + ICLASS_AE_MUL16_00_S2, + ICLASS_AE_MULA16_00_S2, + ICLASS_AE_MULZAAAAQ16, + ICLASS_AE_MULAAAAQ16, + ICLASS_AE_MULZAAAAQ16_S2, + ICLASS_AE_MULAAAAQ16_S2, + ICLASS_AE_DIV64D32_H, + ICLASS_AE_DIV64D32_L, + ICLASS_AE_SHA32, + ICLASS_AE_VLDL32T, + ICLASS_AE_VLDL16T, + ICLASS_AE_VLDL16C, + ICLASS_AE_VLDL16C_IP, + ICLASS_AE_VLDL16C_IC, + ICLASS_AE_VLDL16C_IC1, + ICLASS_AE_VLDSHT, + ICLASS_AE_LB, + ICLASS_AE_LBI, + ICLASS_AE_LBK, + ICLASS_AE_LBKI, + ICLASS_AE_LBS, + ICLASS_AE_LBSI, + ICLASS_AE_DB, + ICLASS_AE_DBI, + ICLASS_AE_DB_IC, + ICLASS_AE_DBI_IC, + ICLASS_AE_DB_IC1, + ICLASS_AE_DBI_IC1, + ICLASS_AE_DB_IP, + ICLASS_AE_DBI_IP, + ICLASS_AE_VLEL32T, + ICLASS_AE_VLEL16T, + ICLASS_AE_SB, + ICLASS_AE_SBI, + ICLASS_AE_VLES16C, + ICLASS_AE_SBF, + ICLASS_AE_SB_IC, + ICLASS_AE_SBI_IC, + ICLASS_AE_VLES16C_IC, + ICLASS_AE_SBF_IC, + ICLASS_AE_SB_IC1, + ICLASS_AE_SBI_IC1, + ICLASS_AE_VLES16C_IC1, + ICLASS_AE_SBF_IC1, + ICLASS_AE_SB_IP, + ICLASS_AE_SBI_IP, + ICLASS_AE_VLES16C_IP, + ICLASS_AE_SBF_IP, + ICLASS_AE_SEXT32, + ICLASS_AE_MOVAE, + ICLASS_AE_MOVEA, + ICLASS_AE_MOVEEP, + ICLASS_AE_SEXT72, + ICLASS_AE_ADD72, + ICLASS_AE_SUB72, + ICLASS_AE_ADD72X64, + ICLASS_AE_SUB72X64, + ICLASS_AE_MUL32EP_HH, + ICLASS_AE_MUL32EP_HH_S2, + ICLASS_AE_MULA32EP_HH, + ICLASS_AE_MULS32EP_HH, + ICLASS_AE_MULA32EP_HH_S2, + ICLASS_AE_MULS32EP_HH_S2, + ICLASS_AE_MULZAAD32EP_HH_LL, + ICLASS_AE_MULZSSD32EP_HH_LL, + ICLASS_AE_MULAAD32EP_HH_LL, + ICLASS_AE_MULSSD32EP_HH_LL, + ICLASS_AE_MULZAAD32EP_HH_LL_S2, + ICLASS_AE_MULZSSD32EP_HH_LL_S2, + ICLASS_AE_MULAAD32EP_HH_LL_S2, + ICLASS_AE_MULSSD32EP_HH_LL_S2, + ICLASS_AE_MULAAD32USEP_HL_LH, + ICLASS_AE_MULAAD32USEP_HL_LH_S2, + ICLASS_AE_MULZAAD32USEP_HL_LH, + ICLASS_AE_MULZAAD32USEP_HL_LH_S2, + ICLASS_AE_MUL32USEP_LH, + ICLASS_AE_MULA32USEP_LH, + ICLASS_AE_MUL32USEP_LL, + ICLASS_AE_MULA32USEP_LL, + ICLASS_AE_SRAI72, + ICLASS_AE_SLAI72, + ICLASS_AE_SAT64S, + ICLASS_AE_L16SI_N, + ICLASS_AE_L16UI_N, + ICLASS_AE_S16I_N, + ICLASS_AE_MOVFCRFSRV, + ICLASS_AE_MOVVFCRFSR, + ICLASS_RFR, + ICLASS_WFR, + ICLASS_MOVT_S, + ICLASS_MOVF_S, + ICLASS_MOVEQZ_S, + ICLASS_MOVNEZ_S, + ICLASS_MOVGEZ_S, + ICLASS_MOVLTZ_S, + ICLASS_TRUNC_S, + ICLASS_UTRUNC_S, + ICLASS_TRUNC_SX2, + ICLASS_UTRUNC_SX2, + ICLASS_FICEIL_S, + ICLASS_FIFLOOR_S, + ICLASS_FIROUND_S, + ICLASS_FITRUNC_S, + ICLASS_FIRINT_S, + ICLASS_CVTSF16_L, + ICLASS_CVTSF16_H, + ICLASS_CVTF16S_L, + ICLASS_CVTF16S_H, + ICLASS_ABS_S, + ICLASS_MUL_S, + ICLASS_MADD_S, + ICLASS_MSUB_S, + ICLASS_MSUBN_S, + ICLASS_MADDN_S, + ICLASS_ADD_S, + ICLASS_SUB_S, + ICLASS_NEG_S, + ICLASS_FLOAT_S, + ICLASS_UFLOAT_S, + ICLASS_FLOAT_SX2, + ICLASS_UFLOAT_SX2, + ICLASS_OLE_S, + ICLASS_OLT_S, + ICLASS_OEQ_S, + ICLASS_UN_S, + ICLASS_ULE_S, + ICLASS_ULT_S, + ICLASS_UEQ_S, + ICLASS_CONST_S, + ICLASS_NEXP01_S, + ICLASS_MKSADJ_S, + ICLASS_MKDADJ_S, + ICLASS_DIV0_S, + ICLASS_SQRT0_S, + ICLASS_RECIP0_S, + ICLASS_RSQRT0_S, + ICLASS_DIVN_S, + ICLASS_ADDEXP_S, + ICLASS_ADDEXPM_S, + ICLASS_MIN_S, + ICLASS_MAX_S, + ICLASS_MULMUX_S, + ICLASS_MADDMUX_S, + ICLASS_CONJC_S, + ICLASS_SIGMOID_Q15, + ICLASS_SIGMOID_FP32 +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_addi_n_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_l32i_n_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_mov_n_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340800; +} + +static void +Opcode_mov_n_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200; +} + +static void +Opcode_mov_n_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260900; +} + +static void +Opcode_mov_n_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_mov_n_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800; +} + +static void +Opcode_mov_n_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278200; +} + +static void +Opcode_mov_n_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba500; +} + +static void +Opcode_mov_n_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7300; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_movi_n_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10140000; +} + +static void +Opcode_addi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_addi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10150000; +} + +static void +Opcode_addmi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_addmi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_addmi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_addmi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_addmi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10244000; +} + +static void +Opcode_add_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_add_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_add_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_add_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_add_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_add_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10245000; +} + +static void +Opcode_addx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_addx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5000; +} + +static void +Opcode_addx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_addx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5000; +} + +static void +Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_addx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10246000; +} + +static void +Opcode_addx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_addx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_addx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_addx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_addx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10247000; +} + +static void +Opcode_addx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_addx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7000; +} + +static void +Opcode_addx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_addx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7000; +} + +static void +Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_addx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10314000; +} + +static void +Opcode_sub_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_sub_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000; +} + +static void +Opcode_sub_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_sub_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000; +} + +static void +Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_sub_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10315000; +} + +static void +Opcode_subx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_subx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4000; +} + +static void +Opcode_subx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_subx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000; +} + +static void +Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_subx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10316000; +} + +static void +Opcode_subx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_subx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5000; +} + +static void +Opcode_subx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_subx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4000; +} + +static void +Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_subx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10317000; +} + +static void +Opcode_subx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_subx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6000; +} + +static void +Opcode_subx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_subx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5000; +} + +static void +Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_subx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10249000; +} + +static void +Opcode_and_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_and_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_and_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_and_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10312000; +} + +static void +Opcode_or_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000; +} + +static void +Opcode_or_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_or_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000; +} + +static void +Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_or_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10318000; +} + +static void +Opcode_xor_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7000; +} + +static void +Opcode_xor_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_xor_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6000; +} + +static void +Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_xor_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; +} + +static void +Opcode_extui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_extui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10170000; +} + +static void +Opcode_l16ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l16ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_l16ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l16ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_l16ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10160000; +} + +static void +Opcode_l16si_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l16si_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l16si_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l16si_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l16si_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10180000; +} + +static void +Opcode_l32i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_l32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_l32i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_l32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l32i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_l32r_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_l32r_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10190000; +} + +static void +Opcode_l8ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_l8ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_l8ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_l8ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_l8ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000c0; +} + +static void +Opcode_loop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_loop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_loopgtz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300020; +} + +static void +Opcode_loopgtz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250040; +} + +static void +Opcode_loopgtz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260010; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300060; +} + +static void +Opcode_loopnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250080; +} + +static void +Opcode_loopnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260020; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101d0000; +} + +static void +Opcode_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024e000; +} + +static void +Opcode_moveqz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_moveqz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_moveqz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_moveqz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd000; +} + +static void +Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_moveqz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024f000; +} + +static void +Opcode_movgez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_movgez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cf000; +} + +static void +Opcode_movgez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_movgez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_movgez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10310000; +} + +static void +Opcode_movltz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_movltz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_movltz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_movltz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cf000; +} + +static void +Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_movltz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10311000; +} + +static void +Opcode_movnez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_movnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000; +} + +static void +Opcode_movnez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_movnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_movnez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342000; +} + +static void +Opcode_abs_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_abs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268000; +} + +static void +Opcode_abs_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3000; +} + +static void +Opcode_abs_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c000; +} + +static void +Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_abs_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342001; +} + +static void +Opcode_neg_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7002; +} + +static void +Opcode_neg_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268002; +} + +static void +Opcode_neg_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3003; +} + +static void +Opcode_neg_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c001; +} + +static void +Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0003; +} + +static void +Opcode_neg_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6003; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d35; +} + +static void +Opcode_nop_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe57d0; +} + +static void +Opcode_nop_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11400a0; +} + +static void +Opcode_nop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b74; +} + +static void +Opcode_nop_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3016; +} + +static void +Opcode_nop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000040; +} + +static void +Opcode_nop_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3900; +} + +static void +Opcode_nop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27b205; +} + +static void +Opcode_nop_Slot_ae5_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf9000; +} + +static void +Opcode_nop_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_nop_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c0; +} + +static void +Opcode_nop_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001; +} + +static void +Opcode_nop_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_nop_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa090; +} + +static void +Opcode_nop_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010; +} + +static void +Opcode_nop_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_nop_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c15; +} + +static void +Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1670; +} + +static void +Opcode_nop_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176011; +} + +static void +Opcode_nop_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b1d; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101a0000; +} + +static void +Opcode_s16i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_s16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101b0000; +} + +static void +Opcode_s32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_s32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101c0000; +} + +static void +Opcode_s8i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_s8i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssa8b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103320d0; +} + +static void +Opcode_ssa8b_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe52d0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2020; +} + +static void +Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1907f0; +} + +static void +Opcode_ssa8b_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1270; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103330d0; +} + +static void +Opcode_ssa8l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe53d0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2030; +} + +static void +Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1917f0; +} + +static void +Opcode_ssa8l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1370; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103340d0; +} + +static void +Opcode_ssl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe54d0; +} + +static void +Opcode_ssl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2120; +} + +static void +Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1927b0; +} + +static void +Opcode_ssl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1470; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103350d0; +} + +static void +Opcode_ssr_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe55d0; +} + +static void +Opcode_ssr_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2130; +} + +static void +Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1927f0; +} + +static void +Opcode_ssr_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1570; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300d0; +} + +static void +Opcode_ssai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50d0; +} + +static void +Opcode_ssai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3006; +} + +static void +Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1907b0; +} + +static void +Opcode_ssai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1070; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d020; +} + +static void +Opcode_sll_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4080; +} + +static void +Opcode_sll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256010; +} + +static void +Opcode_sll_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1080; +} + +static void +Opcode_sll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277080; +} + +static void +Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda020; +} + +static void +Opcode_sll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5080; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10313000; +} + +static void +Opcode_src_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_src_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_src_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342003; +} + +static void +Opcode_sra_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7003; +} + +static void +Opcode_sra_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268003; +} + +static void +Opcode_sra_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3004; +} + +static void +Opcode_sra_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c002; +} + +static void +Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0004; +} + +static void +Opcode_sra_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6004; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342004; +} + +static void +Opcode_srl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7004; +} + +static void +Opcode_srl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268004; +} + +static void +Opcode_srl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3005; +} + +static void +Opcode_srl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c003; +} + +static void +Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0006; +} + +static void +Opcode_srl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6005; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10240000; +} + +static void +Opcode_slli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_slli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_slli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_slli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_slli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10242000; +} + +static void +Opcode_srai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_srai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_srai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_srai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_srai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031f000; +} + +static void +Opcode_srli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_srli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241000; +} + +static void +Opcode_srli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000; +} + +static void +Opcode_srli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251000; +} + +static void +Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_srli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20000; +} + +static void +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770004; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750004; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760004; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740004; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730004; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710004; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720004; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370004; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350004; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360004; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340004; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670004; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660004; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640004; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270004; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250004; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240004; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790004; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0004; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0004; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0004; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0004; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0004; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0004; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390004; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0004; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0004; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0004; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0004; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0004; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0004; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690004; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0004; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0004; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0004; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0004; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0004; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0004; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290004; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0004; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0004; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0004; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0004; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0004; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0004; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0004; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590004; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490004; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0004; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0004; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0004; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0004; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90004; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0004; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900004; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800004; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612000; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32100; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132100; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612100; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32200; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132200; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612200; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32300; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132300; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612300; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611000; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31100; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131100; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611100; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10320000; +} + +static void +Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_andbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10321000; +} + +static void +Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10322000; +} + +static void +Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_orbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10323000; +} + +static void +Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_xorb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10324000; +} + +static void +Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_all4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341e00; +} + +static void +Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1004; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_any4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341e04; +} + +static void +Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1404; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_all8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341e08; +} + +static void +Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1804; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_any8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341e09; +} + +static void +Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1805; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10319000; +} + +static void +Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_movt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031a000; +} + +static void +Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7082; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfm_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193000; +} + +static void +Opcode_dpfm_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340200; +} + +static void +Opcode_dpfm_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb200; +} + +static void +Opcode_dpfm_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x197000; +} + +static void +Opcode_dpfm_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340300; +} + +static void +Opcode_dpfm_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb600; +} + +static void +Opcode_dpfr_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_dpfr_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340400; +} + +static void +Opcode_dpfr_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bba00; +} + +static void +Opcode_dpfr_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x195000; +} + +static void +Opcode_dpfr_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340500; +} + +static void +Opcode_dpfr_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbe00; +} + +static void +Opcode_dpfw_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_dpfw_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340600; +} + +static void +Opcode_dpfw_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba100; +} + +static void +Opcode_dpfw_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_dpfw_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340700; +} + +static void +Opcode_dpfw_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb100; +} + +static void +Opcode_pfnxt_f_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3430; +} + +static void +Opcode_dhi_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_dhwbi_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_dhwb_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_pfend_a_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3030; +} + +static void +Opcode_pfend_o_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3130; +} + +static void +Opcode_pfwait_a_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3230; +} + +static void +Opcode_pfwait_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3330; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32800; +} + +static void +Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132800; +} + +static void +Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612800; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031b000; +} + +static void +Opcode_clamps_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_clamps_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8000; +} + +static void +Opcode_clamps_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_clamps_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7000; +} + +static void +Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_clamps_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024a000; +} + +static void +Opcode_max_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_max_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_max_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_max_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_max_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024b000; +} + +static void +Opcode_maxu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_maxu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb000; +} + +static void +Opcode_maxu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_maxu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a1000; +} + +static void +Opcode_maxu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024c000; +} + +static void +Opcode_min_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_min_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_min_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_min_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb000; +} + +static void +Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_min_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024d000; +} + +static void +Opcode_minu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_minu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd000; +} + +static void +Opcode_minu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_minu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a3000; +} + +static void +Opcode_minu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031c000; +} + +static void +Opcode_sext_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_sext_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d9000; +} + +static void +Opcode_sext_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_sext_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8000; +} + +static void +Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_sext_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_beqz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; +} + +static void +Opcode_beqz_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000000; +} + +static void +Opcode_bgez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; +} + +static void +Opcode_bgez_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000010; +} + +static void +Opcode_bltz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004a0; +} + +static void +Opcode_bltz_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000020; +} + +static void +Opcode_bnez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004e0; +} + +static void +Opcode_bnez_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000030; +} + +static void +Opcode_beqi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_beqi_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_bgei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; +} + +static void +Opcode_bgei_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_blti_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; +} + +static void +Opcode_blti_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; +} + +static void +Opcode_bnei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; +} + +static void +Opcode_bnei_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9800000; +} + +static void +Opcode_bgeui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; +} + +static void +Opcode_bgeui_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5800000; +} + +static void +Opcode_bltui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; +} + +static void +Opcode_bltui_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800000; +} + +static void +Opcode_bbci_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_bbsi_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ball_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_ball_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_bany_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_bany_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_bbc_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; +} + +static void +Opcode_bbc_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_bbs_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; +} + +static void +Opcode_bbs_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800000; +} + +static void +Opcode_beq_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_beq_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4800000; +} + +static void +Opcode_bgeu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_bgeu_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_bge_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; +} + +static void +Opcode_bge_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800000; +} + +static void +Opcode_bltu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; +} + +static void +Opcode_bltu_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_blt_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_blt_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800000; +} + +static void +Opcode_bnall_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_bnall_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000000; +} + +static void +Opcode_bne_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; +} + +static void +Opcode_bne_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; +} + +static void +Opcode_bnone_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; +} + +static void +Opcode_bnone_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800000; +} + +static void +Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f00; +} + +static void +Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f000; +} + +static void +Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f10; +} + +static void +Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f100; +} + +static void +Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f20; +} + +static void +Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f200; +} + +static void +Opcode_rur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f30; +} + +static void +Opcode_wur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f300; +} + +static void +Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f60; +} + +static void +Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f600; +} + +static void +Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f70; +} + +static void +Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f700; +} + +static void +Opcode_rur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f80; +} + +static void +Opcode_wur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f800; +} + +static void +Opcode_rur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f90; +} + +static void +Opcode_wur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f900; +} + +static void +Opcode_ae_sext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d; +} + +static void +Opcode_ae_zext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900d; +} + +static void +Opcode_ae_clamps16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00d; +} + +static void +Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e80; +} + +static void +Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e800; +} + +static void +Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e90; +} + +static void +Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e900; +} + +static void +Opcode_f64iter_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000; +} + +static void +Opcode_f64rnd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_f64addc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb0000; +} + +static void +Opcode_f64subc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb8000; +} + +static void +Opcode_f64sig_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_f64cmpl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0000; +} + +static void +Opcode_f64cmph_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_f64norm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0000; +} + +static void +Opcode_f64sexp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_rf64r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbce00; +} + +static void +Opcode_wf64r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_rur_f64r_lo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30ea0; +} + +static void +Opcode_wur_f64r_lo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3ea00; +} + +static void +Opcode_rur_f64r_hi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30eb0; +} + +static void +Opcode_wur_f64r_hi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3eb00; +} + +static void +Opcode_rur_f64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30ec0; +} + +static void +Opcode_wur_f64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3ec00; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ea04; +} + +static void +Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67eb04; +} + +static void +Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ec04; +} + +static void +Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ed04; +} + +static void +Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ee04; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269601; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c00b; +} + +static void +Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ef04; +} + +static void +Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f004; +} + +static void +Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f104; +} + +static void +Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f204; +} + +static void +Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f304; +} + +static void +Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f404; +} + +static void +Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f504; +} + +static void +Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f604; +} + +static void +Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f704; +} + +static void +Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f804; +} + +static void +Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f904; +} + +static void +Opcode_rur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fa04; +} + +static void +Opcode_wur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fb04; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0200; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22d000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140200; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0600; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22e000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140600; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250400; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250800; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1db000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_l16m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10004; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0100; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x221000; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_l16m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_l16m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20004; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0500; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x222000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x232000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250000; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1db000; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_l16m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d9000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0c00; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_l16m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30004; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250c00; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dd000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0600; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250700; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5000; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_l16_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6000; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0b00; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250b00; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0f00; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_l16_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00004; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0300; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x225000; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_l16_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x235000; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_l16_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40004; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0700; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x226000; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_l16_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x236000; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130700; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250300; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4000; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_l16_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5000; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0700; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250f00; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6000; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_l16_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8000; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_l32f24_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb50004; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260400; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0800; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260800; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0c00; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_l32f24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb60004; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0b00; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x227000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x237000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130b00; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_l32f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70004; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0f00; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130f00; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0400; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260c00; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_l32_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0004; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270000; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f4000; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_l32_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f9000; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100400; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270400; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100800; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_l32_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0004; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0800; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22b000; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ae_l32_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b000; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140800; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_l32_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe0004; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0c00; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000; +} + +static void +Opcode_ae_l32_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140c00; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_l32_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf0004; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260f00; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3000; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_l32_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f8000; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270800; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5000; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_l32_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fb000; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100c00; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260600; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0a00; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l32m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80004; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0000; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x229000; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_l32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x239000; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_l32m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90004; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0400; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22a000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140400; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_l32m_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0004; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260200; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_l32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed000; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0600; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_l32m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0004; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260a00; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0e00; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250600; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1df000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0e00; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250a00; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1df000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_l16x2m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80004; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0900; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x223000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x233000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130900; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb90004; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0d00; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130d00; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_l16x2m_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0004; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250200; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dd000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0a00; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0004; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250e00; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0100; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40004; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260100; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0500; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260500; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0900; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50004; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0010; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244040; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254010; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0010; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0084; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0600; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242020; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170e10; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0014; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0900; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260040; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170110; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0a00; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262080; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170100; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330700; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40e0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2560d0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10e0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770b0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0870; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50e0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330740; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40f0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770c0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c08b0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50f0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc60004; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260e00; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0100; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc70004; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260900; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0d00; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_l32x2_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00004; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260300; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0700; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260700; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0b00; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_l32x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10004; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0090; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0020; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244080; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254020; +} + +static void +Opcode_ae_l32x2_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180090; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0020; +} + +static void +Opcode_ae_l32x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0084; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0e00; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243020; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170500; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4080; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330780; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257010; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10f0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770d0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c08f0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0060; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103307c0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5010; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770e0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c30; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0070; +} + +static void +Opcode_ae_l32x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20004; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260d00; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f4000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30004; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260b00; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f7000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0f00; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250500; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0900; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250900; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e3000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0d00; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_l16x4_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0004; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0010; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180010; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_l16x4_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900084; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0200; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260080; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170e00; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250100; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0500; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_l16x4_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0004; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250d00; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e3000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270200; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f7000; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_l64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fd000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100600; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270600; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fe000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100a00; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_l64_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf0004; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00d0; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0030; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2440c0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000; +} + +static void +Opcode_ae_l64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254030; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800d0; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0030; +} + +static void +Opcode_ae_l64_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460004; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0030; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248000; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000; +} + +static void +Opcode_ae_l64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258000; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180030; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0040; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270c00; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6000; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_l64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc000; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100200; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270a00; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f8000; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_l64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ff000; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100e00; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270300; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fd000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x205000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100700; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270700; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206000; +} + +static void +Opcode_ae_s16x2m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80004; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0100; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140100; +} + +static void +Opcode_ae_s16x2m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd90004; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0500; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x232000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140500; +} + +static void +Opcode_ae_s16x2m_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda0004; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270d00; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100300; +} + +static void +Opcode_ae_s16x2m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb0004; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270b00; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fe000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x207000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100b00; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0004; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290e00; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x212000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120e00; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290100; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x221000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120100; +} + +static void +Opcode_ae_s32x2f24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed0004; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00b0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248080; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258020; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800b0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620084; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0610; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251020; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265080; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8080; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170d00; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330850; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257090; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c070; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0cf0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330050; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257050; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770f0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c70; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330450; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c030; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0cb0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee0004; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290a00; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x211000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21f000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120a00; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef0004; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290500; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x213000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x222000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120500; +} + +static void +Opcode_ae_s32x2_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80004; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290700; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x217000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x226000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120700; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290b00; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x227000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120b00; +} + +static void +Opcode_ae_s32x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90004; +} + +static void +Opcode_ae_s32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ae_s32x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620004; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0e10; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x253020; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267080; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9080; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170700; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330c50; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2570d0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0b0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1903b0; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330090; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0f0; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1903f0; +} + +static void +Opcode_ae_s32x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0004; +} + +static void +Opcode_ae_s32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290300; +} + +static void +Opcode_ae_s32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x225000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120300; +} + +static void +Opcode_ae_s32x2_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0004; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290f00; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120f00; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00f0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2480c0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258030; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800f0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0a10; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252020; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266080; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170300; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290900; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x223000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120900; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290d00; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x215000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120d00; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x209000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280400; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110400; +} + +static void +Opcode_ae_s16x4_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0004; +} + +static void +Opcode_ae_s16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0070; +} + +static void +Opcode_ae_s16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248040; +} + +static void +Opcode_ae_s16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258010; +} + +static void +Opcode_ae_s16x4_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180070; +} + +static void +Opcode_ae_s16x4_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800084; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0210; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250020; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264080; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170900; +} + +static void +Opcode_ae_s16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270f00; +} + +static void +Opcode_ae_s16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ff000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100f00; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280800; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x201000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20b000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110800; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270100; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x201000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100500; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270500; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100900; +} + +static void +Opcode_ae_s16m_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd50004; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0a00; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22f000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140a00; +} + +static void +Opcode_ae_s16m_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd60004; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0e00; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140e00; +} + +static void +Opcode_ae_s16m_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70004; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270e00; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f9000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100100; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270900; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fb000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x203000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100d00; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280300; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x209000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x215000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110300; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280700; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110700; +} + +static void +Opcode_ae_s32f24_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde0004; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0f00; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140f00; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf0004; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x239000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x249000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280d00; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110d00; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280b00; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x217000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110b00; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0400; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21a000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22a000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0800; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22b000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130800; +} + +static void +Opcode_ae_s32_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00004; +} + +static void +Opcode_ae_s32_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0a00; +} + +static void +Opcode_ae_s32_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24f000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a00; +} + +static void +Opcode_ae_s32_l_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe10004; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0e00; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e00; +} + +static void +Opcode_ae_s32_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20004; +} + +static void +Opcode_ae_s32_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x219000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x229000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_s32_l_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30004; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0c00; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21b000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280200; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x203000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110200; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280600; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110600; +} + +static void +Opcode_ae_s16_0_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20004; +} + +static void +Opcode_ae_s16_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0900; +} + +static void +Opcode_ae_s16_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x233000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140900; +} + +static void +Opcode_ae_s16_0_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30004; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0d00; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140d00; +} + +static void +Opcode_ae_s16_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280c00; +} + +static void +Opcode_ae_s16_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110c00; +} + +static void +Opcode_ae_s16_0_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40004; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280a00; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110a00; +} + +static void +Opcode_ae_s64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0600; +} + +static void +Opcode_ae_s64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21d000; +} + +static void +Opcode_ae_s64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22e000; +} + +static void +Opcode_ae_s64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130600; +} + +static void +Opcode_ae_s64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0a00; +} + +static void +Opcode_ae_s64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22f000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130a00; +} + +static void +Opcode_ae_s64_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10004; +} + +static void +Opcode_ae_s64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300040; +} + +static void +Opcode_ae_s64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c040; +} + +static void +Opcode_ae_s64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c010; +} + +static void +Opcode_ae_s64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190040; +} + +static void +Opcode_ae_s64_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20004; +} + +static void +Opcode_ae_s64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300080; +} + +static void +Opcode_ae_s64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c080; +} + +static void +Opcode_ae_s64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c020; +} + +static void +Opcode_ae_s64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190080; +} + +static void +Opcode_ae_s64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0200; +} + +static void +Opcode_ae_s64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_ae_s64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22d000; +} + +static void +Opcode_ae_s64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_ae_s64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0e00; +} + +static void +Opcode_ae_s64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21e000; +} + +static void +Opcode_ae_s64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_ae_s64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130e00; +} + +static void +Opcode_ae_s32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x219000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_s32m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40004; +} + +static void +Opcode_ae_s32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0400; +} + +static void +Opcode_ae_s32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a000; +} + +static void +Opcode_ae_s32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24a000; +} + +static void +Opcode_ae_s32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150400; +} + +static void +Opcode_ae_s32m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50004; +} + +static void +Opcode_ae_s32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0800; +} + +static void +Opcode_ae_s32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24b000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150800; +} + +static void +Opcode_ae_s32m_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe60004; +} + +static void +Opcode_ae_s32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280f00; +} + +static void +Opcode_ae_s32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20b000; +} + +static void +Opcode_ae_s32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ae_s32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110f00; +} + +static void +Opcode_ae_s32m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe70004; +} + +static void +Opcode_ae_s32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290400; +} + +static void +Opcode_ae_s32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21a000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120400; +} + +static void +Opcode_ae_zalign64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x281304; +} + +static void +Opcode_ae_zalign64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d34; +} + +static void +Opcode_ae_zalign64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b34; +} + +static void +Opcode_ae_zalign64_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27b204; +} + +static void +Opcode_ae_zalign64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c14; +} + +static void +Opcode_ae_lalign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032a020; +} + +static void +Opcode_ae_lalign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264000; +} + +static void +Opcode_ae_lalign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278000; +} + +static void +Opcode_ae_lalign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8020; +} + +static void +Opcode_ae_salign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032b020; +} + +static void +Opcode_ae_salign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264400; +} + +static void +Opcode_ae_salign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278100; +} + +static void +Opcode_ae_salign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9020; +} + +static void +Opcode_ae_movalign_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280304; +} + +static void +Opcode_ae_movalign_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d30; +} + +static void +Opcode_ae_movalign_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b30; +} + +static void +Opcode_ae_movalign_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27b200; +} + +static void +Opcode_ae_movalign_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c04; +} + +static void +Opcode_ae_la64_pp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7720c4; +} + +static void +Opcode_ae_la64_pp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d00; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b00; +} + +static void +Opcode_ae_la64_pp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a300; +} + +static void +Opcode_ae_la64_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb020; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341a20; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260330; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279280; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf020; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341b20; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260720; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279380; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd410; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7710c4; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341c20; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260730; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a280; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf410; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341920; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260320; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278380; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be420; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341a00; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260310; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279200; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341b00; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260700; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279300; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc410; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341c00; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260710; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a200; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be410; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341900; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260300; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278300; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc420; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341a30; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2792c0; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf030; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341b30; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2793c0; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd430; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341c30; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a2c0; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf430; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341930; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2783c0; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf420; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341a10; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279240; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf010; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341b10; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279340; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc430; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341c10; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a240; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be430; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341910; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278340; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd420; +} + +static void +Opcode_ae_sa64pos_fp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7730c4; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d20; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b10; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a380; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb820; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d10; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b20; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a340; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb420; +} + +static void +Opcode_ae_la32x2_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0084; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032c010; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256030; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0c0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9040; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0500; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d010; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d080; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9080; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0900; +} + +static void +Opcode_ae_la32x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00c4; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032e010; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257020; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d0c0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90c0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0d00; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10329020; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258020; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f080; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0b00; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032f010; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257030; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e080; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0300; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10328020; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e0c0; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0700; +} + +static void +Opcode_ae_la16x4_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370084; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10325000; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261020; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261040; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170510; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10325010; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262040; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8040; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170910; +} + +static void +Opcode_ae_la16x4_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3700c4; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10325020; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261010; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263040; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170d10; +} + +static void +Opcode_ae_la16x4_rip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350084; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10327000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266040; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6040; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170b10; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10325030; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261030; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264040; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170310; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10326000; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265040; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170710; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0004; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032e000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254030; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2690c0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c00; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032f000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a080; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0200; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0044; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10328010; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x255020; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a0c0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6080; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0600; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032b010; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256020; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c080; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60c0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0100; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10329010; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x255030; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b080; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0a00; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032a010; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b0c0; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0e00; +} + +static void +Opcode_ae_la24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10328000; +} + +static void +Opcode_ae_la24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263020; +} + +static void +Opcode_ae_la24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d040; +} + +static void +Opcode_ae_la24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170730; +} + +static void +Opcode_ae_la24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10329000; +} + +static void +Opcode_ae_la24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e040; +} + +static void +Opcode_ae_la24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170b30; +} + +static void +Opcode_ae_la24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032a000; +} + +static void +Opcode_ae_la24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263010; +} + +static void +Opcode_ae_la24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f040; +} + +static void +Opcode_ae_la24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170f30; +} + +static void +Opcode_ae_la24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d000; +} + +static void +Opcode_ae_la24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254020; +} + +static void +Opcode_ae_la24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269080; +} + +static void +Opcode_ae_la24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0800; +} + +static void +Opcode_ae_la24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032b000; +} + +static void +Opcode_ae_la24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263030; +} + +static void +Opcode_ae_la24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268080; +} + +static void +Opcode_ae_la24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_la24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032c000; +} + +static void +Opcode_ae_la24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680c0; +} + +static void +Opcode_ae_la24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0400; +} + +static void +Opcode_ae_la24x2_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0004; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10326010; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262020; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267040; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170f10; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10327010; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268040; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170130; +} + +static void +Opcode_ae_la24x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0044; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10326020; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262010; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269040; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170530; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10327030; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263000; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c040; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170330; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10327020; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262030; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a040; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170930; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10326030; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b040; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170d30; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330500; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251010; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2750c0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0e10; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330900; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276000; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0110; +} + +static void +Opcode_ae_sa32x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00c4; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330d00; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252010; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276040; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0510; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330a00; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254010; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277000; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0310; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330200; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x253010; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276080; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0910; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330600; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2760c0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0d10; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0d00; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258030; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f0c0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0f00; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0920; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270000; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0020; +} + +static void +Opcode_ae_sa16x4_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0084; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0d20; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x259020; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270040; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0420; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0b00; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a020; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271000; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0220; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0300; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x259030; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270080; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0820; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0700; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700c0; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c20; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0f30; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e030; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274040; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0410; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330000; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274080; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0810; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f00c4; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330400; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25f020; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2740c0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c10; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330100; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250010; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275080; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0a10; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330800; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25f030; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275000; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0210; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330c00; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275040; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0610; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0530; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c030; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2720c0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0d20; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0930; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273000; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0320; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0d30; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25d020; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273040; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0720; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0b30; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e020; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274000; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0010; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0330; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25d030; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273080; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0b20; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0730; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2730c0; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0f20; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0f00; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a030; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271040; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0620; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0320; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271080; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0a20; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0720; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25b020; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2710c0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0e20; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0130; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c020; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272080; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0920; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0b20; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25b030; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272000; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0120; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0f20; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272040; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0520; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031e000; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0050; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0050; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb400; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7100; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0c00; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c00; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0200; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d000; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24d000; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150200; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290800; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e000; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21b000; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120800; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290600; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21e000; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120600; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290c00; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f000; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120c00; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290200; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21d000; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120200; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0300; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x235000; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x245000; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140300; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0700; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x236000; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x246000; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140700; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280e00; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x205000; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110e00; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd0004; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280900; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x207000; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x213000; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110900; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280100; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206000; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x211000; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110100; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280500; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x212000; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110500; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0600; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e000; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24e000; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150600; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30004; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0b00; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x237000; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x247000; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140b00; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10248000; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_addbrba32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_ae_addbrba32_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342002; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7001; +} + +static void +Opcode_ae_bitswap_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3001; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0002; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6001; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_addrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187000; +} + +static void +Opcode_ae_subrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_ae_calcrng3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b19; +} + +static void +Opcode_ae_calcrng2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b15; +} + +static void +Opcode_ae_calcrng1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b11; +} + +static void +Opcode_ae_rng32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b00; +} + +static void +Opcode_ae_sel16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00004; +} + +static void +Opcode_ae_sel16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; +} + +static void +Opcode_ae_sel16i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_ae_shortswap_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73a00; +} + +static void +Opcode_ae_movab4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0814; +} + +static void +Opcode_ae_movab4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258010; +} + +static void +Opcode_ae_movab4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000a; +} + +static void +Opcode_ae_movab2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0804; +} + +static void +Opcode_ae_movab2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800f; +} + +static void +Opcode_ae_movab2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0008; +} + +static void +Opcode_ae_movab_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260804; +} + +static void +Opcode_ae_movab_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800d; +} + +static void +Opcode_ae_movab_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0007; +} + +static void +Opcode_ae_movba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0804; +} + +static void +Opcode_ae_movba_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268005; +} + +static void +Opcode_ae_movba_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0005; +} + +static void +Opcode_ae_movba1x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_ae_movba1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba000; +} + +static void +Opcode_ae_movba4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241704; +} + +static void +Opcode_ae_movba4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269001; +} + +static void +Opcode_ae_movba4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1002; +} + +static void +Opcode_ae_movba2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240704; +} + +static void +Opcode_ae_movba2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269000; +} + +static void +Opcode_ae_movba2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_ae_movb2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680804; +} + +static void +Opcode_ae_movb2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26801f; +} + +static void +Opcode_ae_movb4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0834; +} + +static void +Opcode_ae_movb4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26811f; +} + +static void +Opcode_ae_movt16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330300; +} + +static void +Opcode_ae_movt16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0f10; +} + +static void +Opcode_ae_movt16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5001; +} + +static void +Opcode_ae_movf16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330e00; +} + +static void +Opcode_ae_movf16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0b10; +} + +static void +Opcode_ae_movf16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_ae_movt32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0014; +} + +static void +Opcode_ae_movt32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0500; +} + +static void +Opcode_ae_movt32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170f00; +} + +static void +Opcode_ae_movt32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4001; +} + +static void +Opcode_ae_movf32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0014; +} + +static void +Opcode_ae_movf32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0100; +} + +static void +Opcode_ae_movf32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170b00; +} + +static void +Opcode_ae_movf32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbc00; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7200; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a6; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe56d0; +} + +static void +Opcode_ae_movsard7_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269a01; +} + +static void +Opcode_ae_movsard7_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c10b; +} + +static void +Opcode_ae_movsard7_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d004a; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342006; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7005; +} + +static void +Opcode_ae_movasar_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e002a; +} + +static void +Opcode_ae_movda32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150004; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0400; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_ae_movda32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0034; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032e060; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40d0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256090; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10d0; +} + +static void +Opcode_ae_movda32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770a0; +} + +static void +Opcode_ae_movda32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0830; +} + +static void +Opcode_ae_movda32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50d0; +} + +static void +Opcode_ae_movda16x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140004; +} + +static void +Opcode_ae_movda16_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0024; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032e020; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40c0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256050; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10c0; +} + +static void +Opcode_ae_movda16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277090; +} + +static void +Opcode_ae_movda16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190df0; +} + +static void +Opcode_ae_movda16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50c0; +} + +static void +Opcode_ae_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0084; +} + +static void +Opcode_ae_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032c020; +} + +static void +Opcode_ae_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4040; +} + +static void +Opcode_ae_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x255010; +} + +static void +Opcode_ae_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1040; +} + +static void +Opcode_ae_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277040; +} + +static void +Opcode_ae_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0710; +} + +static void +Opcode_ae_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5040; +} + +static void +Opcode_ae_movi_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174800; +} + +static void +Opcode_ae_movi_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031d000; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0800; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_ae_sat16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19d000; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a2; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6400; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0002; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73900; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72900; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0014; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a4; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6c00; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0004; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a3; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6b00; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0003; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a00; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330022; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5030; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0002; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330020; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5020; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130004; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120004; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110004; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100004; +} + +static void +Opcode_ae_truncp24q48x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0004; +} + +static void +Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00004; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10130000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101f0000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10120000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101e0000; +} + +static void +Opcode_ae_truncp16_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0004; +} + +static void +Opcode_ae_truncp16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70e0; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160900; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x197000; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193000; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160500; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160100; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x195000; +} + +static void +Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c000; +} + +static void +Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_ae_minabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_ae_maxabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18d000; +} + +static void +Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6500; +} + +static void +Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6400; +} + +static void +Opcode_ae_mov_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0014; +} + +static void +Opcode_ae_mov_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a1; +} + +static void +Opcode_ae_mov_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6a00; +} + +static void +Opcode_ae_mov_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800e; +} + +static void +Opcode_ae_mov_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2010; +} + +static void +Opcode_ae_mov_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c00a; +} + +static void +Opcode_ae_mov_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0001; +} + +static void +Opcode_ae_mov_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_ae_mov_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a00; +} + +static void +Opcode_ae_movt64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600004; +} + +static void +Opcode_ae_movt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0c00; +} + +static void +Opcode_ae_movt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170a00; +} + +static void +Opcode_ae_movt64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_ae_movf64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0800; +} + +static void +Opcode_ae_movf64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170600; +} + +static void +Opcode_ae_movf64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d0e0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40b0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10b0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1909f0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50b0; +} + +static void +Opcode_ae_cvt48a32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0014; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d060; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4090; +} + +static void +Opcode_ae_cvt48a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1090; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1901f0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5090; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d0a0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40a0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10a0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1905f0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50a0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0034; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006f; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6900; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d000a; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70d0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0024; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006d; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6800; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0008; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70c0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006e; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6700; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c7; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70b0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006c; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6600; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c5; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70a0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006b; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6500; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0087; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7090; +} + +static void +Opcode_ae_sat48s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0a04; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175e00; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7070; +} + +static void +Opcode_ae_satq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7080; +} + +static void +Opcode_ae_sat24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7060; +} + +static void +Opcode_ae_truncq32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0024; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0048; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70f0; +} + +static void +Opcode_ae_minabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_ae_maxabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7050; +} + +static void +Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7040; +} + +static void +Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250034; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330029; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50c0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0081; +} + +static void +Opcode_ae_movad32_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500c4; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330027; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5090; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800c; +} + +static void +Opcode_ae_movad32_l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c009; +} + +static void +Opcode_ae_movad32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c2; +} + +static void +Opcode_ae_movad32_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500b4; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330025; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5080; +} + +static void +Opcode_ae_movad32_h_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800b; +} + +static void +Opcode_ae_movad32_h_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c008; +} + +static void +Opcode_ae_movad32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c0; +} + +static void +Opcode_ae_movad16_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500a4; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330026; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5070; +} + +static void +Opcode_ae_movad16_3_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800a; +} + +static void +Opcode_ae_movad16_3_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c007; +} + +static void +Opcode_ae_movad16_3_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0082; +} + +static void +Opcode_ae_movad16_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250094; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330024; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5060; +} + +static void +Opcode_ae_movad16_2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268009; +} + +static void +Opcode_ae_movad16_2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c006; +} + +static void +Opcode_ae_movad16_2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0080; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330023; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5050; +} + +static void +Opcode_ae_movad16_1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268008; +} + +static void +Opcode_ae_movad16_1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c005; +} + +static void +Opcode_ae_movad16_1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0042; +} + +static void +Opcode_ae_movad16_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250084; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330021; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5040; +} + +static void +Opcode_ae_movad16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268007; +} + +static void +Opcode_ae_movad16_0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c004; +} + +static void +Opcode_ae_movad16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0040; +} + +static void +Opcode_ae_sra64_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230070; +} + +static void +Opcode_ae_sra64_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0070; +} + +static void +Opcode_ae_pksr32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270204; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0030; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x173004; +} + +static void +Opcode_ae_pksr24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260204; +} + +static void +Opcode_ae_pksr24_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x173000; +} + +static void +Opcode_ae_pksrf32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680104; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0430; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x173008; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250024; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0043; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250014; +} + +static void +Opcode_ae_add32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300004; +} + +static void +Opcode_ae_add32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0d00; +} + +static void +Opcode_ae_add32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252000; +} + +static void +Opcode_ae_add32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150d00; +} + +static void +Opcode_ae_add32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e000; +} + +static void +Opcode_ae_add32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181000; +} + +static void +Opcode_ae_sub32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0004; +} + +static void +Opcode_ae_sub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0d00; +} + +static void +Opcode_ae_sub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160b00; +} + +static void +Opcode_ae_sub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000; +} + +static void +Opcode_ae_sub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a1000; +} + +static void +Opcode_ae_addsub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0800; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160800; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189000; +} + +static void +Opcode_ae_subadd32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0f00; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170800; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_ae_add16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0100; +} + +static void +Opcode_ae_add16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150100; +} + +static void +Opcode_ae_add16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b000; +} + +static void +Opcode_ae_add16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_ae_sub16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0100; +} + +static void +Opcode_ae_sub16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160d00; +} + +static void +Opcode_ae_sub16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ae_sub16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19e000; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0b00; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150b00; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ae_neg32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341400; +} + +static void +Opcode_ae_neg32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1baf00; +} + +static void +Opcode_ae_neg32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175300; +} + +static void +Opcode_ae_neg32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb030; +} + +static void +Opcode_ae_abs32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340b00; +} + +static void +Opcode_ae_abs32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb900; +} + +static void +Opcode_ae_abs32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174e00; +} + +static void +Opcode_ae_abs32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba010; +} + +static void +Opcode_ae_add24s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320004; +} + +static void +Opcode_ae_add24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0900; +} + +static void +Opcode_ae_add24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150900; +} + +static void +Opcode_ae_add24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d000; +} + +static void +Opcode_ae_add24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_sub24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0900; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160700; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ae_add32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400004; +} + +static void +Opcode_ae_add32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0300; +} + +static void +Opcode_ae_add32s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x253000; +} + +static void +Opcode_ae_add32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150300; +} + +static void +Opcode_ae_add32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f000; +} + +static void +Opcode_ae_add32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ae_sub32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0004; +} + +static void +Opcode_ae_sub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0300; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160f00; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_ae_addsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0c00; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160c00; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x157000; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ae_subadd32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0000; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170c00; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161000; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_ae_add16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330004; +} + +static void +Opcode_ae_add16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0500; +} + +static void +Opcode_ae_add16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150500; +} + +static void +Opcode_ae_add16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c000; +} + +static void +Opcode_ae_add16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f000; +} + +static void +Opcode_ae_sub16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0004; +} + +static void +Opcode_ae_sub16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0500; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160300; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f000; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0700; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150700; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183000; +} + +static void +Opcode_ae_neg24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341300; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbb00; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175200; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb020; +} + +static void +Opcode_ae_abs24s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0104; +} + +static void +Opcode_ae_abs24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340a00; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba900; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174d00; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9010; +} + +static void +Opcode_ae_neg32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0704; +} + +static void +Opcode_ae_neg32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341500; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbf00; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175600; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_ae_abs32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0304; +} + +static void +Opcode_ae_abs32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340c00; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bad00; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174f00; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb010; +} + +static void +Opcode_ae_neg16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0604; +} + +static void +Opcode_ae_neg16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341200; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bab00; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175d00; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba030; +} + +static void +Opcode_ae_abs16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0204; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340900; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb500; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174c00; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8010; +} + +static void +Opcode_ae_lt16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330010; +} + +static void +Opcode_ae_lt16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1901b0; +} + +static void +Opcode_ae_le16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e03d0; +} + +static void +Opcode_ae_le16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1902f0; +} + +static void +Opcode_ae_eq16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e01d0; +} + +static void +Opcode_ae_eq16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900f0; +} + +static void +Opcode_ae_lt32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x541004; +} + +static void +Opcode_ae_lt32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0190; +} + +static void +Opcode_ae_lt32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900b0; +} + +static void +Opcode_ae_le32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0150; +} + +static void +Opcode_ae_le32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190170; +} + +static void +Opcode_ae_eq32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540004; +} + +static void +Opcode_ae_eq32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0110; +} + +static void +Opcode_ae_eq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190070; +} + +static void +Opcode_ae_min32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530004; +} + +static void +Opcode_ae_min32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0a00; +} + +static void +Opcode_ae_min32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160a00; +} + +static void +Opcode_ae_min32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18f000; +} + +static void +Opcode_ae_max32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520004; +} + +static void +Opcode_ae_max32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0200; +} + +static void +Opcode_ae_max32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160200; +} + +static void +Opcode_ae_max32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b000; +} + +static void +Opcode_ae_add64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310004; +} + +static void +Opcode_ae_add64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0f00; +} + +static void +Opcode_ae_add64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f00; +} + +static void +Opcode_ae_add64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ae_add64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x185000; +} + +static void +Opcode_ae_sub64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d0004; +} + +static void +Opcode_ae_sub64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0700; +} + +static void +Opcode_ae_sub64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_sub64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d000; +} + +static void +Opcode_ae_sub64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a3000; +} + +static void +Opcode_ae_neg64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0504; +} + +static void +Opcode_ae_neg64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341600; +} + +static void +Opcode_ae_neg64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_ae_neg64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175700; +} + +static void +Opcode_ae_neg64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7010; +} + +static void +Opcode_ae_abs64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270804; +} + +static void +Opcode_ae_abs64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340d00; +} + +static void +Opcode_ae_abs64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbd00; +} + +static void +Opcode_ae_abs64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175100; +} + +static void +Opcode_ae_abs64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8020; +} + +static void +Opcode_ae_addsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0400; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160400; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155000; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ae_subsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0400; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170200; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ae_add64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x153000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ae_sub64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0b00; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170400; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_ae_negsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341800; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175b00; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7030; +} + +static void +Opcode_ae_abssq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340f00; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb300; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175900; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9020; +} + +static void +Opcode_ae_neg64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341700; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175a00; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7020; +} + +static void +Opcode_ae_abs64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340e00; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba300; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175500; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8030; +} + +static void +Opcode_ae_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410004; +} + +static void +Opcode_ae_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300030; +} + +static void +Opcode_ae_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190050; +} + +static void +Opcode_ae_and_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_ae_nand_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300070; +} + +static void +Opcode_ae_nand_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190090; +} + +static void +Opcode_ae_nand_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_ae_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160004; +} + +static void +Opcode_ae_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000b0; +} + +static void +Opcode_ae_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900d0; +} + +static void +Opcode_ae_or_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_ae_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0004; +} + +static void +Opcode_ae_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000f0; +} + +static void +Opcode_ae_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190030; +} + +static void +Opcode_ae_xor_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_ae_slai24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940004; +} + +static void +Opcode_ae_slai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220020; +} + +static void +Opcode_ae_slai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0020; +} + +static void +Opcode_ae_slai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000; +} + +static void +Opcode_ae_srli24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230080; +} + +static void +Opcode_ae_srli24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0080; +} + +static void +Opcode_ae_srli24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66000; +} + +static void +Opcode_ae_srai24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0004; +} + +static void +Opcode_ae_srai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220030; +} + +static void +Opcode_ae_srai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0030; +} + +static void +Opcode_ae_srai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_ae_slas24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240b04; +} + +static void +Opcode_ae_slas24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002b; +} + +static void +Opcode_ae_slas24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0083; +} + +static void +Opcode_ae_slas24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6600; +} + +static void +Opcode_ae_srls24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330067; +} + +static void +Opcode_ae_srls24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0007; +} + +static void +Opcode_ae_srls24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72800; +} + +static void +Opcode_ae_sras24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240e04; +} + +static void +Opcode_ae_sras24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330063; +} + +static void +Opcode_ae_sras24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0086; +} + +static void +Opcode_ae_sras24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6e00; +} + +static void +Opcode_ae_srai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300090; +} + +static void +Opcode_ae_srai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900e0; +} + +static void +Opcode_ae_srai16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_ae_srai16r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000d0; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190010; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_ae_slai32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960004; +} + +static void +Opcode_ae_slai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220010; +} + +static void +Opcode_ae_slai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0010; +} + +static void +Opcode_ae_slai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ae_srli32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920004; +} + +static void +Opcode_ae_srli32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230020; +} + +static void +Opcode_ae_srli32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0020; +} + +static void +Opcode_ae_srli32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a000; +} + +static void +Opcode_ae_srai32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e0004; +} + +static void +Opcode_ae_srai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102200b0; +} + +static void +Opcode_ae_srai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00b0; +} + +static void +Opcode_ae_srai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e000; +} + +static void +Opcode_ae_srai32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230000; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62000; +} + +static void +Opcode_ae_slas32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002e; +} + +static void +Opcode_ae_slas32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c3; +} + +static void +Opcode_ae_slas32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6800; +} + +static void +Opcode_ae_srls32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330068; +} + +static void +Opcode_ae_srls32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0045; +} + +static void +Opcode_ae_srls32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73800; +} + +static void +Opcode_ae_sras32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330064; +} + +static void +Opcode_ae_sras32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c4; +} + +static void +Opcode_ae_sras32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6f00; +} + +static void +Opcode_ae_slaa32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200004; +} + +static void +Opcode_ae_slaa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300e0; +} + +static void +Opcode_ae_slaa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00e0; +} + +static void +Opcode_ae_srla32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0060; +} + +static void +Opcode_ae_srla32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180060; +} + +static void +Opcode_ae_sraa32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70004; +} + +static void +Opcode_ae_sraa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0000; +} + +static void +Opcode_ae_sraa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_slai16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300050; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900a0; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_ae_slaa16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230004; +} + +static void +Opcode_ae_slaa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300a0; +} + +static void +Opcode_ae_slaa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00a0; +} + +static void +Opcode_ae_sraa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300f0; +} + +static void +Opcode_ae_sraa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00f0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300b0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00b0; +} + +static void +Opcode_ae_slai24s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980004; +} + +static void +Opcode_ae_slai24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102200a0; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00a0; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000; +} + +static void +Opcode_ae_slas24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002c; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c1; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6700; +} + +static void +Opcode_ae_slai32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0004; +} + +static void +Opcode_ae_slai32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220090; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0090; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a000; +} + +static void +Opcode_ae_slas32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002d; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0004; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6900; +} + +static void +Opcode_ae_slaa32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50004; +} + +static void +Opcode_ae_slaa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230010; +} + +static void +Opcode_ae_slaa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0010; +} + +static void +Opcode_ae_sraa32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820004; +} + +static void +Opcode_ae_sraa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0080; +} + +static void +Opcode_ae_sraa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180080; +} + +static void +Opcode_ae_sraa32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0040; +} + +static void +Opcode_ae_sraa32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180040; +} + +static void +Opcode_ae_slasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240c04; +} + +static void +Opcode_ae_slasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330062; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0046; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6c00; +} + +static void +Opcode_ae_srlsq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330069; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0085; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71900; +} + +static void +Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240f04; +} + +static void +Opcode_ae_srasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330065; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0005; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71800; +} + +static void +Opcode_ae_slaaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210004; +} + +static void +Opcode_ae_slaaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300d0; +} + +static void +Opcode_ae_slaaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00d0; +} + +static void +Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610004; +} + +static void +Opcode_ae_srlaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00e0; +} + +static void +Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800e0; +} + +static void +Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910004; +} + +static void +Opcode_ae_sraaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0020; +} + +static void +Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180020; +} + +static void +Opcode_ae_slai64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880004; +} + +static void +Opcode_ae_slai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210000; +} + +static void +Opcode_ae_slai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ae_slai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ae_srli64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220000; +} + +static void +Opcode_ae_srli64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_srli64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ae_srai64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0004; +} + +static void +Opcode_ae_srai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210030; +} + +static void +Opcode_ae_srai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0030; +} + +static void +Opcode_ae_srai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53000; +} + +static void +Opcode_ae_slas64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002f; +} + +static void +Opcode_ae_slas64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0006; +} + +static void +Opcode_ae_slas64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6a00; +} + +static void +Opcode_ae_srls64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006a; +} + +static void +Opcode_ae_srls64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0047; +} + +static void +Opcode_ae_srls64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70900; +} + +static void +Opcode_ae_sras64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330066; +} + +static void +Opcode_ae_sras64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c6; +} + +static void +Opcode_ae_sras64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70800; +} + +static void +Opcode_ae_slaa64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220004; +} + +static void +Opcode_ae_slaa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230050; +} + +static void +Opcode_ae_slaa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0050; +} + +static void +Opcode_ae_srla64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00a0; +} + +static void +Opcode_ae_srla64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800a0; +} + +static void +Opcode_ae_sraa64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810004; +} + +static void +Opcode_ae_sraa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00c0; +} + +static void +Opcode_ae_sraa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800c0; +} + +static void +Opcode_ae_slaisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210010; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0010; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52000; +} + +static void +Opcode_ae_slassq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330061; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0084; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6d00; +} + +static void +Opcode_ae_slaasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60004; +} + +static void +Opcode_ae_slaasq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230030; +} + +static void +Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0030; +} + +static void +Opcode_ae_slai64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210020; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0020; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x51000; +} + +static void +Opcode_ae_slas64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240d04; +} + +static void +Opcode_ae_slas64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330060; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0044; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6b00; +} + +static void +Opcode_ae_slaa64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230090; +} + +static void +Opcode_ae_slaa64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0090; +} + +static void +Opcode_ae_lt64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510004; +} + +static void +Opcode_ae_lt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300010; +} + +static void +Opcode_ae_lt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190060; +} + +static void +Opcode_ae_le64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500004; +} + +static void +Opcode_ae_le64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000e0; +} + +static void +Opcode_ae_le64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190020; +} + +static void +Opcode_ae_eq64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000a0; +} + +static void +Opcode_ae_eq64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900c0; +} + +static void +Opcode_ae_max64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0600; +} + +static void +Opcode_ae_max64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160600; +} + +static void +Opcode_ae_max64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ae_min64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0e00; +} + +static void +Opcode_ae_min64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160e00; +} + +static void +Opcode_ae_min64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ae_nsa64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500d4; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330028; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50a0; +} + +static void +Opcode_ae_nsa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0001; +} + +static void +Opcode_ae_nsaz16_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500e4; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0003; +} + +static void +Opcode_ae_nsaz32_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500f4; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002a; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50b0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0041; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0010; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b000; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080050; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_mul32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600c0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000; +} + +static void +Opcode_ae_mulf32s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_mul32_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79000; +} + +static void +Opcode_ae_muls32f48p16s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff000; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080020; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c000; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f0070; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_ae_mulf32ra_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_mulf32r_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0000; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a000; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080040; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_mul32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600b0; +} + +static void +Opcode_ae_mul32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43000; +} + +static void +Opcode_ae_mulf32s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_mul32_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78000; +} + +static void +Opcode_ae_muls32f48p16s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080010; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b000; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f0060; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_ae_mulf32ra_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_mulf32r_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900f0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79000; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080030; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d000; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_mul32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600a0; +} + +static void +Opcode_ae_mul32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000; +} + +static void +Opcode_ae_mulf32s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_mul32_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77000; +} + +static void +Opcode_ae_muls32f48p16s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfd000; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a000; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f0050; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_ae_mulf32ra_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_mulf32r_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0050; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e000; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150050; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76000; +} + +static void +Opcode_ae_mula32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070090; +} + +static void +Opcode_ae_mula32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x51000; +} + +static void +Opcode_ae_mulaf32s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_ae_mula32_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85000; +} + +static void +Opcode_ae_mulas32f48p16s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140060; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f000; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73000; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130070; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ae_mulaf32ra_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_ae_mulaf32r_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0040; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d000; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91000; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150040; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75000; +} + +static void +Opcode_ae_mula32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070080; +} + +static void +Opcode_ae_mula32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ae_mulaf32s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_ae_mula32_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000; +} + +static void +Opcode_ae_mulas32f48p16s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140050; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72000; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130060; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f000; +} + +static void +Opcode_ae_mulaf32ra_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_ae_mulaf32r_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b0070; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140070; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74000; +} + +static void +Opcode_ae_mula32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070070; +} + +static void +Opcode_ae_mula32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f000; +} + +static void +Opcode_ae_mulaf32s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_ae_mula32_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83000; +} + +static void +Opcode_ae_mulas32f48p16s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140040; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d000; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71000; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130050; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e000; +} + +static void +Opcode_ae_mulaf32ra_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_ae_mulaf32r_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0080; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d000; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00c0; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93000; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1000; +} + +static void +Opcode_ae_muls32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00d0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87000; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_mulsf32s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124000; +} + +static void +Opcode_ae_muls32_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a000; +} + +static void +Opcode_ae_mulss32f48p16s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0090; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0060; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000; +} + +static void +Opcode_ae_mulsf32ra_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e000; +} + +static void +Opcode_ae_mulsf32r_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x121000; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0070; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00b0; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_muls32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00c0; +} + +static void +Opcode_ae_muls32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_mulsf32s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123000; +} + +static void +Opcode_ae_muls32_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109000; +} + +static void +Opcode_ae_mulss32f48p16s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0080; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0050; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000; +} + +static void +Opcode_ae_mulsf32ra_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d000; +} + +static void +Opcode_ae_mulsf32r_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0060; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b000; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00a0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91000; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef000; +} + +static void +Opcode_ae_muls32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00b0; +} + +static void +Opcode_ae_muls32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85000; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_mulsf32s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x122000; +} + +static void +Opcode_ae_muls32_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ae_mulss32f48p16s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0070; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0040; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000; +} + +static void +Opcode_ae_mulsf32ra_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c000; +} + +static void +Opcode_ae_mulsf32r_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f000; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060010; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600e0; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0020; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c000; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_ae_mulf16ss_33_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_ae_mulf16ss_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_ae_mulf16ss_32_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_ae_mulf16ss_21_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_ae_mulf16ss_31_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_ae_mulf16ss_30_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_ae_mulf16ss_10_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ae_mulf16ss_20_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_ae_mulf16ss_11_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f0040; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59000; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_ae_mulf16ss_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ae_mulsf16ss_33_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b000; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_mulsf16ss_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x117000; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_mulsf16ss_32_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a000; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_mulsf16ss_21_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x116000; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_mulsf16ss_31_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x119000; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_mulsf16ss_30_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_mulsf16ss_10_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x113000; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_mulsf16ss_20_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x115000; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_mulsf16ss_11_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x114000; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0030; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_mulsf16ss_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x112000; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d000; +} + +static void +Opcode_ae_mulaf16ss_33_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69000; +} + +static void +Opcode_ae_mulaf16ss_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c000; +} + +static void +Opcode_ae_mulaf16ss_32_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68000; +} + +static void +Opcode_ae_mulaf16ss_21_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b000; +} + +static void +Opcode_ae_mulaf16ss_31_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a000; +} + +static void +Opcode_ae_mulaf16ss_30_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000; +} + +static void +Opcode_ae_mulaf16ss_10_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67000; +} + +static void +Opcode_ae_mulaf16ss_20_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66000; +} + +static void +Opcode_ae_mulaf16ss_11_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130040; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000; +} + +static void +Opcode_ae_mulaf16ss_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100070; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23000; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b000; +} + +static void +Opcode_ae_mulaafd16ss_33_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100060; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22000; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a000; +} + +static void +Opcode_ae_mulaafd16ss_13_02_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100050; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21000; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59000; +} + +static void +Opcode_ae_mulaafd16ss_11_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00f0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x114000; +} + +static void +Opcode_ae_mulssfd16ss_33_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147000; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00e0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x113000; +} + +static void +Opcode_ae_mulssfd16ss_13_02_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x146000; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00d0; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x112000; +} + +static void +Opcode_ae_mulssfd16ss_11_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145000; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00f0; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124000; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x157000; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00e0; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123000; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00d0; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x122000; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155000; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100d0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x177000; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100c0; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143000; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100b0; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142000; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175000; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800e0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68000; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_mulf48q32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800f0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69000; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_mulf48q32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900d0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77000; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_mulq32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb000; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900e0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78000; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_mulq32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1170060; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f000; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1170070; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b0050; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a000; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000; +} + +static void +Opcode_ae_mulaq32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b0060; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b000; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000; +} + +static void +Opcode_ae_mulaq32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0050; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d000; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0060; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb000; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e000; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0040; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109000; +} + +static void +Opcode_ae_mulsq32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0050; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a000; +} + +static void +Opcode_ae_mulsq32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d000; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090010; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b000; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090000; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a000; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_mulfp24x2ra_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000; +} + +static void +Opcode_ae_mulfp24x2r_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef000; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180050; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180040; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81000; +} + +static void +Opcode_ae_mulafp24x2ra_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_mulafp24x2r_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0080; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfd000; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0070; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000; +} + +static void +Opcode_ae_mulsfp24x2ra_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f000; +} + +static void +Opcode_ae_mulsfp24x2r_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0020; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127000; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0000; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x125000; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00b0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ae_mulzaad32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x153000; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0030; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0010; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126000; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00c0; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x121000; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000; +} + +static void +Opcode_ae_mulzaad32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00e0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133000; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00c0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00a0; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f000; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ae_mulzasd32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00f0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134000; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00d0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00b0; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x167000; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x165000; +} + +static void +Opcode_ae_mulzasd32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x163000; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000c0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000b0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000a0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16d000; +} + +static void +Opcode_ae_mulzsad32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120080; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147000; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100e0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145000; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110090; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ae_mulzssd32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x173000; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120090; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100f0; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x146000; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100a0; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141000; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000; +} + +static void +Opcode_ae_mulzssd32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110060; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110040; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c000; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700f0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f000; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57000; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_mulaad32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110070; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110050; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d000; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100040; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58000; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93000; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91000; +} + +static void +Opcode_ae_mulaad32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e0040; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55000; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d0060; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53000; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d0040; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x51000; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_mulasd32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e0050; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56000; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d0070; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54000; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d0050; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52000; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_mulasd32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0000; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00f0; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00e0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f000; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e000; +} + +static void +Opcode_ae_mulsad32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d000; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0020; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x117000; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0000; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x115000; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00b0; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a000; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ae_mulssd32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143000; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0030; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0010; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x116000; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00c0; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x111000; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b000; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x149000; +} + +static void +Opcode_ae_mulssd32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800a0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060060; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_ae_mulf32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ae_mul32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d000; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800b0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060070; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_ae_mulf32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000; +} + +static void +Opcode_ae_mul32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74000; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800c0; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66000; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060080; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_mulf32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000; +} + +static void +Opcode_ae_mul32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75000; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800d0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67000; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060090; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41000; +} + +static void +Opcode_ae_mulf32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000; +} + +static void +Opcode_ae_mul32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76000; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080060; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060020; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_ae_mulf32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_mul32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f000; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080070; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61000; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060030; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_ae_mulf32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_mul32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61000; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080080; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62000; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060040; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_ae_mulf32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_mul32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080090; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63000; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060050; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_ae_mulf32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_mul32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69000; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1160060; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37000; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b000; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070030; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b000; +} + +static void +Opcode_ae_mulaf32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_mula32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f000; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1160070; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c000; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070040; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_ae_mulaf32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_mula32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1170040; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d000; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070050; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d000; +} + +static void +Opcode_ae_mulaf32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_mula32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81000; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1170050; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e000; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070060; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e000; +} + +static void +Opcode_ae_mulaf32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_mula32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150060; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33000; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77000; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600f0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47000; +} + +static void +Opcode_ae_mulaf32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_mula32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b000; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150070; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78000; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070000; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ae_mulaf32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_mula32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c000; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1160040; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35000; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79000; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070010; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x49000; +} + +static void +Opcode_ae_mulaf32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_mula32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d000; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1160050; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a000; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070020; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a000; +} + +static void +Opcode_ae_mulaf32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_mula32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e000; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0010; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0070; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81000; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_mulsf32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x129000; +} + +static void +Opcode_ae_muls32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104000; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0020; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7000; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0080; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_mulsf32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a000; +} + +static void +Opcode_ae_muls32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105000; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0030; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0090; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83000; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_mulsf32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b000; +} + +static void +Opcode_ae_muls32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106000; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0040; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf9000; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00a0; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_mulsf32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c000; +} + +static void +Opcode_ae_muls32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107000; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00d0; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0030; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d000; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_mulsf32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x125000; +} + +static void +Opcode_ae_muls32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00e0; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3000; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0040; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e000; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_mulsf32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126000; +} + +static void +Opcode_ae_muls32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101000; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00f0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0050; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f000; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_mulsf32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127000; +} + +static void +Opcode_ae_muls32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102000; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf5000; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0060; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_mulsf32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_muls32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120070; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b000; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63000; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700e0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56000; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120050; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29000; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61000; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700c0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54000; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e0070; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58000; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0070; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e0060; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57000; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0060; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f000; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93000; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0020; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x111000; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0010; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b000; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0050; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a000; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00a0; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f000; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d000; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142000; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0040; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x119000; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0090; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e000; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c000; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141000; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0070; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c000; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00a0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f000; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f000; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0050; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a000; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0080; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d000; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d000; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100090; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0090; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e000; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161000; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100080; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135000; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0080; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d000; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000e0; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d000; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b000; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000d0; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137000; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16f000; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200b0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a000; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110080; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d000; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200a0; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x149000; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000f0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171000; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0060; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b000; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0040; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x129000; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120060; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a000; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62000; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120040; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0090; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e000; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0070; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c000; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700d0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d000; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55000; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700b0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b000; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53000; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f000; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87000; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900a0; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74000; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090040; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e000; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090020; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c000; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090060; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_mulfp32x16x2s_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ae_mulp32x16x2_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900b0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75000; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090050; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f000; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090030; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090070; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71000; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_mulfp32x16x2s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf5000; +} + +static void +Opcode_ae_mulp32x16x2_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf9000; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1000; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a0060; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47000; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1190040; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85000; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180060; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83000; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1190060; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43000; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87000; +} + +static void +Opcode_ae_mulafp32x16x2s_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_mulap32x16x2_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a0070; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1190050; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180070; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1190070; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ae_mulafp32x16x2s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_mulap32x16x2_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0010; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00b0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0090; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00d0; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102000; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135000; +} + +static void +Opcode_ae_mulsp32x16x2_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0020; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00c0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00a0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff000; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00e0; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_ae_mulsp32x16x2_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_ae_mulp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900c0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76000; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090090; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73000; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090080; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72000; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_mulp32x2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000; +} + +static void +Opcode_ae_mulfp32x2rs_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7000; +} + +static void +Opcode_ae_mulfp32x2ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000; +} + +static void +Opcode_ae_mulap32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b0040; +} + +static void +Opcode_ae_mulap32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x49000; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a0050; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a0040; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x45000; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000; +} + +static void +Opcode_ae_mulap32x2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_mulafp32x2rs_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_mulafp32x2ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0030; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0000; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105000; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00f0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104000; +} + +static void +Opcode_ae_mulsp32x2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_ae_mulsfp32x2rs_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ae_mulsfp32x2ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137000; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171000; +} + +static void +Opcode_ae_mulc32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300b0; +} + +static void +Opcode_ae_mulc32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300e0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf5000; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16d000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300f0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300d0; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140090; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300c0; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3000; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140080; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16f000; +} + +static void +Opcode_ae_mulac32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200c0; +} + +static void +Opcode_ae_mulac32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x163000; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200f0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130080; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef000; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x167000; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200e0; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x165000; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300a0; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1000; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200d0; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130090; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ae_mulf16x4ss_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1030000; +} + +static void +Opcode_ae_mulaf16x4ss_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020000; +} + +static void +Opcode_ae_mulsf16x4ss_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050000; +} + +static void +Opcode_ae_mul16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_mula16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1010000; +} + +static void +Opcode_ae_muls16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100020; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulzaaaafq32x16_s2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mulaaaafq32x16_s2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100030; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100010; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_mulzaaaaq32x16_s2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulaaaaq32x16_s2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_mul16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060000; +} + +static void +Opcode_ae_mul16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_ae_mula16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600d0; +} + +static void +Opcode_ae_mula16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x45000; +} + +static void +Opcode_ae_mul16_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e000; +} + +static void +Opcode_ae_mula16_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a000; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0060; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b000; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700a0; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52000; +} + +static void +Opcode_ae_mulzaaaaq16_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e000; +} + +static void +Opcode_ae_mulaaaaq16_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000; +} + +static void +Opcode_ae_div64d32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341000; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba700; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9030; +} + +static void +Opcode_ae_div64d32_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0404; +} + +static void +Opcode_ae_div64d32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341100; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb700; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba020; +} + +static void +Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360084; +} + +static void +Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0004; +} + +static void +Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0004; +} + +static void +Opcode_ae_vldl16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e064; +} + +static void +Opcode_ae_vldl16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x259010; +} + +static void +Opcode_ae_vldl16c_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e084; +} + +static void +Opcode_ae_vldl16c_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e074; +} + +static void +Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a3c0; +} + +static void +Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x341004; +} + +static void +Opcode_ae_vldsht_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269201; +} + +static void +Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690204; +} + +static void +Opcode_ae_lb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268001; +} + +static void +Opcode_ae_lb_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3002; +} + +static void +Opcode_ae_lb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0001; +} + +static void +Opcode_ae_lb_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6002; +} + +static void +Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690304; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268006; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000; +} + +static void +Opcode_ae_lbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0009; +} + +static void +Opcode_ae_lbi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1060; +} + +static void +Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830004; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce0004; +} + +static void +Opcode_ae_lbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690604; +} + +static void +Opcode_ae_lbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690704; +} + +static void +Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x774004; +} + +static void +Opcode_ae_db_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260100; +} + +static void +Opcode_ae_db_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb800; +} + +static void +Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x775004; +} + +static void +Opcode_ae_dbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260d00; +} + +static void +Opcode_ae_dbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc400; +} + +static void +Opcode_ae_db_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x776004; +} + +static void +Opcode_ae_dbi_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x777004; +} + +static void +Opcode_ae_db_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b4004; +} + +static void +Opcode_ae_dbi_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x744004; +} + +static void +Opcode_ae_db_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x778004; +} + +static void +Opcode_ae_dbi_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x779004; +} + +static void +Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00004; +} + +static void +Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10004; +} + +static void +Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77a004; +} + +static void +Opcode_ae_sb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260500; +} + +static void +Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630004; +} + +static void +Opcode_ae_sbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21f000; +} + +static void +Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e004; +} + +static void +Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e014; +} + +static void +Opcode_ae_sb_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77b004; +} + +static void +Opcode_ae_sbi_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560004; +} + +static void +Opcode_ae_vles16c_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e024; +} + +static void +Opcode_ae_sbf_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e034; +} + +static void +Opcode_ae_sb_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a4004; +} + +static void +Opcode_ae_sbi_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0004; +} + +static void +Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a3d0; +} + +static void +Opcode_ae_sbf_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e0c4; +} + +static void +Opcode_ae_sb_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77c004; +} + +static void +Opcode_ae_sbi_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570004; +} + +static void +Opcode_ae_vles16c_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e044; +} + +static void +Opcode_ae_sbf_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e054; +} + +static void +Opcode_ae_sext32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170004; +} + +static void +Opcode_ae_sext32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_ae_movae_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260f00; +} + +static void +Opcode_ae_movae_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4100; +} + +static void +Opcode_ae_movea_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260f04; +} + +static void +Opcode_ae_movea_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4104; +} + +static void +Opcode_ae_moveep_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176010; +} + +static void +Opcode_ae_moveep_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b01; +} + +static void +Opcode_ae_sext72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300c; +} + +static void +Opcode_ae_add72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ae_sub72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f000; +} + +static void +Opcode_ae_add72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ae_sub72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174400; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul32ep_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mula32ep_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000; +} + +static void +Opcode_ae_muls32ep_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000; +} + +static void +Opcode_ae_srai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_slai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175000; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_ae_l16si_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d; +} + +static void +Opcode_ae_l16ui_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d; +} + +static void +Opcode_ae_s16i_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600d; +} + +static void +Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f700; +} + +static void +Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f710; +} + +static void +Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0040; +} + +static void +Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0050; +} + +static void +Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb0000; +} + +static void +Opcode_movt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0d00; +} + +static void +Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0000; +} + +static void +Opcode_movf_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0300; +} + +static void +Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b0000; +} + +static void +Opcode_moveqz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0400; +} + +static void +Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b0000; +} + +static void +Opcode_movnez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0b00; +} + +static void +Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0000; +} + +static void +Opcode_movgez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0700; +} + +static void +Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0000; +} + +static void +Opcode_movltz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0900; +} + +static void +Opcode_trunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0200; +} + +static void +Opcode_utrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0100; +} + +static void +Opcode_trunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1034a000; +} + +static void +Opcode_utrunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10346000; +} + +static void +Opcode_ficeil_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343001; +} + +static void +Opcode_fifloor_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343003; +} + +static void +Opcode_firound_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343002; +} + +static void +Opcode_fitrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343000; +} + +static void +Opcode_firint_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343004; +} + +static void +Opcode_cvtsf16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343007; +} + +static void +Opcode_cvtsf16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343005; +} + +static void +Opcode_cvtf16s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342007; +} + +static void +Opcode_cvtf16s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342005; +} + +static void +Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0010; +} + +static void +Opcode_abs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176080; +} + +static void +Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_mul_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11800d0; +} + +static void +Opcode_mul_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb000; +} + +static void +Opcode_mul_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d000; +} + +static void +Opcode_mul_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_madd_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11500a0; +} + +static void +Opcode_madd_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfd000; +} + +static void +Opcode_madd_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000; +} + +static void +Opcode_madd_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_msub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150090; +} + +static void +Opcode_msub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000; +} + +static void +Opcode_msub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_msub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_msubn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_maddn_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_maddn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_add_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150080; +} + +static void +Opcode_add_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000; +} + +static void +Opcode_add_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000; +} + +static void +Opcode_add_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_sub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11900d0; +} + +static void +Opcode_sub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000; +} + +static void +Opcode_sub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_sub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0060; +} + +static void +Opcode_neg_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176090; +} + +static void +Opcode_neg_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c00; +} + +static void +Opcode_float_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0800; +} + +static void +Opcode_ufloat_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0a00; +} + +static void +Opcode_float_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10348000; +} + +static void +Opcode_ufloat_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10344000; +} + +static void +Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ole_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0f10; +} + +static void +Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_olt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0010; +} + +static void +Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0000; +} + +static void +Opcode_oeq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0f00; +} + +static void +Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_const_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0030; +} + +static void +Opcode_const_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f600; +} + +static void +Opcode_nexp01_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f200; +} + +static void +Opcode_mksadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f100; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300f; +} + +static void +Opcode_div0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f000; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f500; +} + +static void +Opcode_recip0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f300; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f400; +} + +static void +Opcode_divn_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_addexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300e; +} + +static void +Opcode_addexpm_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300d; +} + +static void +Opcode_min_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_max_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x177000; +} + +static void +Opcode_mulmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_mulmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_conjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175f00; +} + +static void +Opcode_sigmoid_q15_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60100; +} + +static void +Opcode_sigmoid_fp32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addi_n_Slot_ae4_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32i_n_Slot_ae4_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0, Opcode_mov_n_Slot_ae_slot1_encode, Opcode_mov_n_Slot_ae_slot0_encode, 0, Opcode_mov_n_Slot_ae2_slot1_encode, Opcode_mov_n_Slot_ae2_slot0_encode, Opcode_mov_n_Slot_ae3_slot1_encode, Opcode_mov_n_Slot_ae3_slot0_encode, Opcode_mov_n_Slot_ae4_slot1_encode, 0, 0, 0, Opcode_mov_n_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movi_n_Slot_ae4_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, 0, 0, Opcode_addi_Slot_ae_slot1_encode, Opcode_addi_Slot_ae_slot0_encode, 0, Opcode_addi_Slot_ae2_slot1_encode, Opcode_addi_Slot_ae2_slot0_encode, Opcode_addi_Slot_ae3_slot1_encode, Opcode_addi_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, 0, 0, Opcode_addmi_Slot_ae_slot1_encode, Opcode_addmi_Slot_ae_slot0_encode, 0, Opcode_addmi_Slot_ae2_slot1_encode, Opcode_addmi_Slot_ae2_slot0_encode, Opcode_addmi_Slot_ae3_slot1_encode, Opcode_addmi_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addmi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, 0, 0, Opcode_add_Slot_ae_slot1_encode, Opcode_add_Slot_ae_slot0_encode, 0, Opcode_add_Slot_ae2_slot1_encode, Opcode_add_Slot_ae2_slot0_encode, Opcode_add_Slot_ae3_slot1_encode, Opcode_add_Slot_ae3_slot0_encode, Opcode_add_Slot_ae4_slot1_encode, 0, 0, 0, Opcode_add_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, 0, 0, Opcode_addx2_Slot_ae_slot1_encode, Opcode_addx2_Slot_ae_slot0_encode, 0, Opcode_addx2_Slot_ae2_slot1_encode, Opcode_addx2_Slot_ae2_slot0_encode, Opcode_addx2_Slot_ae3_slot1_encode, Opcode_addx2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, 0, 0, Opcode_addx4_Slot_ae_slot1_encode, Opcode_addx4_Slot_ae_slot0_encode, 0, Opcode_addx4_Slot_ae2_slot1_encode, Opcode_addx4_Slot_ae2_slot0_encode, Opcode_addx4_Slot_ae3_slot1_encode, Opcode_addx4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, 0, 0, Opcode_addx8_Slot_ae_slot1_encode, Opcode_addx8_Slot_ae_slot0_encode, 0, Opcode_addx8_Slot_ae2_slot1_encode, Opcode_addx8_Slot_ae2_slot0_encode, Opcode_addx8_Slot_ae3_slot1_encode, Opcode_addx8_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, 0, 0, Opcode_sub_Slot_ae_slot1_encode, Opcode_sub_Slot_ae_slot0_encode, 0, Opcode_sub_Slot_ae2_slot1_encode, Opcode_sub_Slot_ae2_slot0_encode, Opcode_sub_Slot_ae3_slot1_encode, Opcode_sub_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_sub_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, 0, 0, Opcode_subx2_Slot_ae_slot1_encode, Opcode_subx2_Slot_ae_slot0_encode, 0, Opcode_subx2_Slot_ae2_slot1_encode, Opcode_subx2_Slot_ae2_slot0_encode, Opcode_subx2_Slot_ae3_slot1_encode, Opcode_subx2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_subx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, 0, 0, Opcode_subx4_Slot_ae_slot1_encode, Opcode_subx4_Slot_ae_slot0_encode, 0, Opcode_subx4_Slot_ae2_slot1_encode, Opcode_subx4_Slot_ae2_slot0_encode, Opcode_subx4_Slot_ae3_slot1_encode, Opcode_subx4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_subx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, 0, 0, Opcode_subx8_Slot_ae_slot1_encode, Opcode_subx8_Slot_ae_slot0_encode, 0, Opcode_subx8_Slot_ae2_slot1_encode, Opcode_subx8_Slot_ae2_slot0_encode, Opcode_subx8_Slot_ae3_slot1_encode, Opcode_subx8_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_subx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, 0, 0, Opcode_and_Slot_ae_slot1_encode, Opcode_and_Slot_ae_slot0_encode, 0, Opcode_and_Slot_ae2_slot1_encode, Opcode_and_Slot_ae2_slot0_encode, Opcode_and_Slot_ae3_slot1_encode, Opcode_and_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_and_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, 0, 0, Opcode_or_Slot_ae_slot1_encode, Opcode_or_Slot_ae_slot0_encode, 0, Opcode_or_Slot_ae2_slot1_encode, Opcode_or_Slot_ae2_slot0_encode, Opcode_or_Slot_ae3_slot1_encode, Opcode_or_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_or_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, 0, 0, Opcode_xor_Slot_ae_slot1_encode, Opcode_xor_Slot_ae_slot0_encode, 0, Opcode_xor_Slot_ae2_slot1_encode, Opcode_xor_Slot_ae2_slot0_encode, Opcode_xor_Slot_ae3_slot1_encode, Opcode_xor_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_xor_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, 0, 0, Opcode_extui_Slot_ae_slot1_encode, 0, 0, Opcode_extui_Slot_ae2_slot1_encode, Opcode_extui_Slot_ae2_slot0_encode, Opcode_extui_Slot_ae3_slot1_encode, Opcode_extui_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_extui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, 0, 0, Opcode_l16ui_Slot_ae_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae2_slot1_encode, Opcode_l16ui_Slot_ae2_slot0_encode, Opcode_l16ui_Slot_ae3_slot1_encode, Opcode_l16ui_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l16ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, 0, 0, Opcode_l16si_Slot_ae_slot1_encode, Opcode_l16si_Slot_ae_slot0_encode, 0, Opcode_l16si_Slot_ae2_slot1_encode, Opcode_l16si_Slot_ae2_slot0_encode, Opcode_l16si_Slot_ae3_slot1_encode, Opcode_l16si_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l16si_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, 0, 0, Opcode_l32i_Slot_ae_slot1_encode, Opcode_l32i_Slot_ae_slot0_encode, 0, Opcode_l32i_Slot_ae2_slot1_encode, Opcode_l32i_Slot_ae2_slot0_encode, Opcode_l32i_Slot_ae3_slot1_encode, Opcode_l32i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32r_Slot_ae2_slot0_encode, 0, Opcode_l32r_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l32r_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, 0, 0, Opcode_l8ui_Slot_ae_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae2_slot1_encode, Opcode_l8ui_Slot_ae2_slot0_encode, Opcode_l8ui_Slot_ae3_slot1_encode, Opcode_l8ui_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l8ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loop_Slot_ae2_slot0_encode, 0, Opcode_loop_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_loop_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopgtz_Slot_ae2_slot0_encode, 0, Opcode_loopgtz_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_loopgtz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopnez_Slot_ae2_slot0_encode, 0, Opcode_loopnez_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_loopnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, 0, 0, Opcode_movi_Slot_ae_slot1_encode, Opcode_movi_Slot_ae_slot0_encode, 0, Opcode_movi_Slot_ae2_slot1_encode, Opcode_movi_Slot_ae2_slot0_encode, Opcode_movi_Slot_ae3_slot1_encode, Opcode_movi_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, 0, 0, Opcode_moveqz_Slot_ae_slot1_encode, Opcode_moveqz_Slot_ae_slot0_encode, 0, Opcode_moveqz_Slot_ae2_slot1_encode, Opcode_moveqz_Slot_ae2_slot0_encode, Opcode_moveqz_Slot_ae3_slot1_encode, Opcode_moveqz_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_moveqz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, 0, 0, Opcode_movgez_Slot_ae_slot1_encode, Opcode_movgez_Slot_ae_slot0_encode, 0, Opcode_movgez_Slot_ae2_slot1_encode, Opcode_movgez_Slot_ae2_slot0_encode, Opcode_movgez_Slot_ae3_slot1_encode, Opcode_movgez_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_movgez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, 0, 0, Opcode_movltz_Slot_ae_slot1_encode, Opcode_movltz_Slot_ae_slot0_encode, 0, Opcode_movltz_Slot_ae2_slot1_encode, Opcode_movltz_Slot_ae2_slot0_encode, Opcode_movltz_Slot_ae3_slot1_encode, Opcode_movltz_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_movltz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, 0, 0, Opcode_movnez_Slot_ae_slot1_encode, Opcode_movnez_Slot_ae_slot0_encode, 0, Opcode_movnez_Slot_ae2_slot1_encode, Opcode_movnez_Slot_ae2_slot0_encode, Opcode_movnez_Slot_ae3_slot1_encode, Opcode_movnez_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_movnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, 0, 0, Opcode_abs_Slot_ae_slot1_encode, Opcode_abs_Slot_ae_slot0_encode, 0, Opcode_abs_Slot_ae2_slot1_encode, Opcode_abs_Slot_ae2_slot0_encode, Opcode_abs_Slot_ae3_slot1_encode, Opcode_abs_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_abs_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, 0, 0, Opcode_neg_Slot_ae_slot1_encode, Opcode_neg_Slot_ae_slot0_encode, 0, Opcode_neg_Slot_ae2_slot1_encode, Opcode_neg_Slot_ae2_slot0_encode, Opcode_neg_Slot_ae3_slot1_encode, Opcode_neg_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_neg_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot3_encode, Opcode_nop_Slot_ae_slot2_encode, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode, Opcode_nop_Slot_ae2_slot2_encode, Opcode_nop_Slot_ae2_slot1_encode, Opcode_nop_Slot_ae2_slot0_encode, Opcode_nop_Slot_ae3_slot1_encode, Opcode_nop_Slot_ae3_slot0_encode, Opcode_nop_Slot_ae4_slot1_encode, Opcode_nop_Slot_ae4_slot0_encode, Opcode_nop_Slot_ae5_slot2_encode, Opcode_nop_Slot_ae5_slot1_encode, Opcode_nop_Slot_ae5_slot0_encode, Opcode_nop_Slot_ae6_slot3_encode, Opcode_nop_Slot_ae6_slot2_encode, Opcode_nop_Slot_ae6_slot1_encode, Opcode_nop_Slot_ae6_slot0_encode, Opcode_nop_Slot_ae7_slot3_encode, Opcode_nop_Slot_ae7_slot2_encode, Opcode_nop_Slot_ae7_slot1_encode, Opcode_nop_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode, 0, 0, Opcode_s16i_Slot_ae2_slot0_encode, 0, Opcode_s16i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_s16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode, 0, 0, Opcode_s32i_Slot_ae2_slot0_encode, 0, Opcode_s32i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_s32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s8i_Slot_ae2_slot0_encode, 0, Opcode_s8i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_s8i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot1_encode, Opcode_ssa8b_Slot_ae_slot0_encode, 0, Opcode_ssa8b_Slot_ae2_slot1_encode, Opcode_ssa8b_Slot_ae2_slot0_encode, Opcode_ssa8b_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot1_encode, Opcode_ssa8l_Slot_ae_slot0_encode, 0, Opcode_ssa8l_Slot_ae2_slot1_encode, Opcode_ssa8l_Slot_ae2_slot0_encode, Opcode_ssa8l_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssl_Slot_ae_slot1_encode, Opcode_ssl_Slot_ae_slot0_encode, 0, Opcode_ssl_Slot_ae2_slot1_encode, Opcode_ssl_Slot_ae2_slot0_encode, Opcode_ssl_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssr_Slot_ae_slot1_encode, Opcode_ssr_Slot_ae_slot0_encode, 0, Opcode_ssr_Slot_ae2_slot1_encode, Opcode_ssr_Slot_ae2_slot0_encode, Opcode_ssr_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssai_Slot_ae_slot1_encode, Opcode_ssai_Slot_ae_slot0_encode, 0, Opcode_ssai_Slot_ae2_slot1_encode, Opcode_ssai_Slot_ae2_slot0_encode, Opcode_ssai_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, 0, 0, Opcode_sll_Slot_ae_slot1_encode, Opcode_sll_Slot_ae_slot0_encode, 0, Opcode_sll_Slot_ae2_slot1_encode, Opcode_sll_Slot_ae2_slot0_encode, Opcode_sll_Slot_ae3_slot1_encode, Opcode_sll_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_sll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, 0, 0, Opcode_src_Slot_ae_slot1_encode, Opcode_src_Slot_ae_slot0_encode, 0, Opcode_src_Slot_ae2_slot1_encode, Opcode_src_Slot_ae2_slot0_encode, Opcode_src_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, 0, 0, Opcode_sra_Slot_ae_slot1_encode, Opcode_sra_Slot_ae_slot0_encode, 0, Opcode_sra_Slot_ae2_slot1_encode, Opcode_sra_Slot_ae2_slot0_encode, Opcode_sra_Slot_ae3_slot1_encode, Opcode_sra_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_sra_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, 0, 0, Opcode_srl_Slot_ae_slot1_encode, Opcode_srl_Slot_ae_slot0_encode, 0, Opcode_srl_Slot_ae2_slot1_encode, Opcode_srl_Slot_ae2_slot0_encode, Opcode_srl_Slot_ae3_slot1_encode, Opcode_srl_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_srl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, 0, 0, Opcode_slli_Slot_ae_slot1_encode, Opcode_slli_Slot_ae_slot0_encode, 0, Opcode_slli_Slot_ae2_slot1_encode, Opcode_slli_Slot_ae2_slot0_encode, Opcode_slli_Slot_ae3_slot1_encode, Opcode_slli_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_slli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, 0, 0, Opcode_srai_Slot_ae_slot1_encode, Opcode_srai_Slot_ae_slot0_encode, 0, Opcode_srai_Slot_ae2_slot1_encode, Opcode_srai_Slot_ae2_slot0_encode, Opcode_srai_Slot_ae3_slot1_encode, Opcode_srai_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_srai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, 0, 0, Opcode_srli_Slot_ae_slot1_encode, Opcode_srli_Slot_ae_slot0_encode, 0, Opcode_srli_Slot_ae2_slot1_encode, Opcode_srli_Slot_ae2_slot0_encode, Opcode_srli_Slot_ae3_slot1_encode, Opcode_srli_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_srli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { + Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { + Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode, 0, 0, Opcode_andb_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode, 0, 0, Opcode_andbc_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode, 0, 0, Opcode_orb_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode, 0, 0, Opcode_orbc_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode, 0, 0, Opcode_xorb_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode, 0, 0, Opcode_all4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode, 0, 0, Opcode_any4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode, 0, 0, Opcode_all8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode, 0, 0, Opcode_any8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode, 0, 0, Opcode_movf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode, 0, 0, Opcode_movt_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { + Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfm_b_encode_fns[] = { + Opcode_dpfm_b_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfm_b_Slot_ae_slot0_encode, 0, 0, Opcode_dpfm_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfm_bf_encode_fns[] = { + Opcode_dpfm_bf_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfm_bf_Slot_ae_slot0_encode, 0, 0, Opcode_dpfm_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_b_encode_fns[] = { + Opcode_dpfr_b_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfr_b_Slot_ae_slot0_encode, 0, 0, Opcode_dpfr_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_bf_encode_fns[] = { + Opcode_dpfr_bf_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfr_bf_Slot_ae_slot0_encode, 0, 0, Opcode_dpfr_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_b_encode_fns[] = { + Opcode_dpfw_b_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfw_b_Slot_ae_slot0_encode, 0, 0, Opcode_dpfw_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_bf_encode_fns[] = { + Opcode_dpfw_bf_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfw_bf_Slot_ae_slot0_encode, 0, 0, Opcode_dpfw_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfnxt_f_encode_fns[] = { + Opcode_pfnxt_f_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_b_encode_fns[] = { + Opcode_dhi_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_b_encode_fns[] = { + Opcode_dhwbi_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_b_encode_fns[] = { + Opcode_dhwb_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfend_a_encode_fns[] = { + Opcode_pfend_a_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfend_o_encode_fns[] = { + Opcode_pfend_o_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfwait_a_encode_fns[] = { + Opcode_pfwait_a_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfwait_r_encode_fns[] = { + Opcode_pfwait_r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { + Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { + Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { + Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, 0, 0, Opcode_clamps_Slot_ae_slot1_encode, Opcode_clamps_Slot_ae_slot0_encode, 0, Opcode_clamps_Slot_ae2_slot1_encode, Opcode_clamps_Slot_ae2_slot0_encode, Opcode_clamps_Slot_ae3_slot1_encode, Opcode_clamps_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_clamps_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, 0, 0, Opcode_max_Slot_ae_slot1_encode, Opcode_max_Slot_ae_slot0_encode, 0, Opcode_max_Slot_ae2_slot1_encode, Opcode_max_Slot_ae2_slot0_encode, Opcode_max_Slot_ae3_slot1_encode, Opcode_max_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_max_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, 0, 0, Opcode_maxu_Slot_ae_slot1_encode, Opcode_maxu_Slot_ae_slot0_encode, 0, Opcode_maxu_Slot_ae2_slot1_encode, Opcode_maxu_Slot_ae2_slot0_encode, Opcode_maxu_Slot_ae3_slot1_encode, Opcode_maxu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_maxu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, 0, 0, Opcode_min_Slot_ae_slot1_encode, Opcode_min_Slot_ae_slot0_encode, 0, Opcode_min_Slot_ae2_slot1_encode, Opcode_min_Slot_ae2_slot0_encode, Opcode_min_Slot_ae3_slot1_encode, Opcode_min_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_min_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, 0, 0, Opcode_minu_Slot_ae_slot1_encode, Opcode_minu_Slot_ae_slot0_encode, 0, Opcode_minu_Slot_ae2_slot1_encode, Opcode_minu_Slot_ae2_slot0_encode, Opcode_minu_Slot_ae3_slot1_encode, Opcode_minu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_minu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, 0, 0, Opcode_sext_Slot_ae_slot1_encode, Opcode_sext_Slot_ae_slot0_encode, 0, Opcode_sext_Slot_ae2_slot1_encode, Opcode_sext_Slot_ae2_slot0_encode, Opcode_sext_Slot_ae3_slot1_encode, Opcode_sext_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_sext_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_beqz_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bgez_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bltz_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bnez_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_beqi_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bgei_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_blti_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bnei_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bgeui_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bltui_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bbci_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bbsi_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_ball_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bany_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bbc_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bbs_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_beq_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bgeu_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bge_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bltu_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_blt_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bnall_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bne_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bnone_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { + Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { + Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { + Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { + Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cw_sd_no_encode_fns[] = { + Opcode_rur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cw_sd_no_encode_fns[] = { + Opcode_wur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { + Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { + Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { + Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { + Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin1_encode_fns[] = { + Opcode_rur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin1_encode_fns[] = { + Opcode_wur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend1_encode_fns[] = { + Opcode_rur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend1_encode_fns[] = { + Opcode_wur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext16_encode_fns[] = { + 0, 0, Opcode_ae_sext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext16_encode_fns[] = { + 0, 0, Opcode_ae_zext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_clamps16_encode_fns[] = { + 0, 0, Opcode_ae_clamps16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { + Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { + Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { + Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { + Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64iter_encode_fns[] = { + Opcode_f64iter_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64rnd_encode_fns[] = { + Opcode_f64rnd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64addc_encode_fns[] = { + Opcode_f64addc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64subc_encode_fns[] = { + Opcode_f64subc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64sig_encode_fns[] = { + Opcode_f64sig_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64cmpl_encode_fns[] = { + Opcode_f64cmpl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64cmph_encode_fns[] = { + Opcode_f64cmph_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64norm_encode_fns[] = { + Opcode_f64norm_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64sexp_encode_fns[] = { + Opcode_f64sexp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rf64r_encode_fns[] = { + Opcode_rf64r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wf64r_encode_fns[] = { + Opcode_wf64r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_f64r_lo_encode_fns[] = { + Opcode_rur_f64r_lo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_f64r_lo_encode_fns[] = { + Opcode_wur_f64r_lo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_f64r_hi_encode_fns[] = { + Opcode_rur_f64r_hi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_f64r_hi_encode_fns[] = { + Opcode_wur_f64r_hi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_f64s_encode_fns[] = { + Opcode_rur_f64s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_f64s_encode_fns[] = { + Opcode_wur_f64s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { + Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { + Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { + Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { + Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { + Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { + Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { + Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { + Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { + Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { + Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { + Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { + Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { + Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { + Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { + Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { + Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cwrap_encode_fns[] = { + Opcode_rur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cwrap_encode_fns[] = { + Opcode_wur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_i_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae_slot0_encode, 0, Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_ip_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae_slot1_encode, Opcode_ae_l16m_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_xc_Slot_ae2_slot1_encode, Opcode_ae_l16m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode, Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_i_encode_fns[] = { + Opcode_ae_l16m_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16m_i_Slot_ae_slot1_encode, Opcode_ae_l16m_i_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_i_Slot_ae2_slot1_encode, Opcode_ae_l16m_i_Slot_ae2_slot0_encode, Opcode_ae_l16m_i_Slot_ae3_slot1_encode, Opcode_ae_l16m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_iu_encode_fns[] = { + Opcode_ae_l16m_iu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae_slot1_encode, Opcode_ae_l16m_iu_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_iu_Slot_ae2_slot1_encode, Opcode_ae_l16m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16m_x_Slot_ae_slot1_encode, Opcode_ae_l16m_x_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_x_Slot_ae2_slot1_encode, Opcode_ae_l16m_x_Slot_ae2_slot0_encode, Opcode_ae_l16m_x_Slot_ae3_slot1_encode, Opcode_ae_l16m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xu_encode_fns[] = { + Opcode_ae_l16m_xu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae_slot1_encode, Opcode_ae_l16m_xu_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_xu_Slot_ae2_slot1_encode, Opcode_ae_l16m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae_slot1_encode, Opcode_ae_l16_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l16_xc_Slot_ae2_slot1_encode, Opcode_ae_l16_xc_Slot_ae2_slot0_encode, Opcode_ae_l16_xc_Slot_ae3_slot1_encode, Opcode_ae_l16_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae_slot1_encode, Opcode_ae_l16_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l16_xc1_Slot_ae2_slot1_encode, Opcode_ae_l16_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_i_encode_fns[] = { + Opcode_ae_l16_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16_i_Slot_ae_slot1_encode, Opcode_ae_l16_i_Slot_ae_slot0_encode, 0, Opcode_ae_l16_i_Slot_ae2_slot1_encode, Opcode_ae_l16_i_Slot_ae2_slot0_encode, Opcode_ae_l16_i_Slot_ae3_slot1_encode, Opcode_ae_l16_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_ip_encode_fns[] = { + Opcode_ae_l16_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae_slot1_encode, Opcode_ae_l16_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l16_ip_Slot_ae2_slot1_encode, Opcode_ae_l16_ip_Slot_ae2_slot0_encode, Opcode_ae_l16_ip_Slot_ae3_slot1_encode, Opcode_ae_l16_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16_x_Slot_ae_slot1_encode, Opcode_ae_l16_x_Slot_ae_slot0_encode, 0, Opcode_ae_l16_x_Slot_ae2_slot1_encode, Opcode_ae_l16_x_Slot_ae2_slot0_encode, Opcode_ae_l16_x_Slot_ae3_slot1_encode, Opcode_ae_l16_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xp_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae_slot1_encode, Opcode_ae_l16_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l16_xp_Slot_ae2_slot1_encode, Opcode_ae_l16_xp_Slot_ae2_slot0_encode, Opcode_ae_l16_xp_Slot_ae3_slot1_encode, Opcode_ae_l16_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc_encode_fns[] = { + Opcode_ae_l32f24_xc_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode, Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode, Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_i_encode_fns[] = { + Opcode_ae_l32f24_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae_slot1_encode, Opcode_ae_l32f24_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_i_Slot_ae2_slot1_encode, Opcode_ae_l32f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32f24_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_ip_encode_fns[] = { + Opcode_ae_l32f24_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae_slot1_encode, Opcode_ae_l32f24_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_x_Slot_ae2_slot1_encode, Opcode_ae_l32f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32f24_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xp_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc_encode_fns[] = { + Opcode_ae_l32_xc_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae_slot1_encode, Opcode_ae_l32_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32_xc_Slot_ae2_slot1_encode, Opcode_ae_l32_xc_Slot_ae2_slot0_encode, Opcode_ae_l32_xc_Slot_ae3_slot1_encode, Opcode_ae_l32_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae_slot1_encode, Opcode_ae_l32_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l32_xc1_Slot_ae2_slot1_encode, Opcode_ae_l32_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_i_encode_fns[] = { + Opcode_ae_l32_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32_i_Slot_ae_slot1_encode, Opcode_ae_l32_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32_i_Slot_ae2_slot1_encode, Opcode_ae_l32_i_Slot_ae2_slot0_encode, Opcode_ae_l32_i_Slot_ae3_slot1_encode, Opcode_ae_l32_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_ip_encode_fns[] = { + Opcode_ae_l32_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae_slot1_encode, Opcode_ae_l32_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l32_ip_Slot_ae2_slot1_encode, Opcode_ae_l32_ip_Slot_ae2_slot0_encode, Opcode_ae_l32_ip_Slot_ae3_slot1_encode, Opcode_ae_l32_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_x_encode_fns[] = { + Opcode_ae_l32_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32_x_Slot_ae_slot1_encode, Opcode_ae_l32_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32_x_Slot_ae2_slot1_encode, Opcode_ae_l32_x_Slot_ae2_slot0_encode, Opcode_ae_l32_x_Slot_ae3_slot1_encode, Opcode_ae_l32_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xp_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae_slot1_encode, Opcode_ae_l32_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l32_xp_Slot_ae2_slot1_encode, Opcode_ae_l32_xp_Slot_ae2_slot0_encode, Opcode_ae_l32_xp_Slot_ae3_slot1_encode, Opcode_ae_l32_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae_slot1_encode, Opcode_ae_l32m_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_xc_Slot_ae2_slot1_encode, Opcode_ae_l32m_xc_Slot_ae2_slot0_encode, Opcode_ae_l32m_xc_Slot_ae3_slot1_encode, Opcode_ae_l32m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_i_encode_fns[] = { + Opcode_ae_l32m_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32m_i_Slot_ae_slot1_encode, Opcode_ae_l32m_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_i_Slot_ae2_slot1_encode, Opcode_ae_l32m_i_Slot_ae2_slot0_encode, Opcode_ae_l32m_i_Slot_ae3_slot1_encode, Opcode_ae_l32m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_iu_encode_fns[] = { + Opcode_ae_l32m_iu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae_slot1_encode, Opcode_ae_l32m_iu_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_iu_Slot_ae2_slot1_encode, Opcode_ae_l32m_iu_Slot_ae2_slot0_encode, Opcode_ae_l32m_iu_Slot_ae3_slot1_encode, Opcode_ae_l32m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_x_encode_fns[] = { + Opcode_ae_l32m_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32m_x_Slot_ae_slot1_encode, Opcode_ae_l32m_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_x_Slot_ae2_slot1_encode, Opcode_ae_l32m_x_Slot_ae2_slot0_encode, Opcode_ae_l32m_x_Slot_ae3_slot1_encode, Opcode_ae_l32m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xu_encode_fns[] = { + Opcode_ae_l32m_xu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae_slot1_encode, Opcode_ae_l32m_xu_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_xu_Slot_ae2_slot1_encode, Opcode_ae_l32m_xu_Slot_ae2_slot0_encode, Opcode_ae_l32m_xu_Slot_ae3_slot1_encode, Opcode_ae_l32m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_i_encode_fns[] = { + Opcode_ae_l16x2m_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_iu_encode_fns[] = { + Opcode_ae_l16x2m_iu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_x_encode_fns[] = { + Opcode_ae_l16x2m_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xu_encode_fns[] = { + Opcode_ae_l16x2m_xu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc_encode_fns[] = { + Opcode_ae_l32x2f24_xc_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_i_encode_fns[] = { + Opcode_ae_l32x2f24_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ip_encode_fns[] = { + Opcode_ae_l32x2f24_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_rip_encode_fns[] = { + Opcode_ae_l32x2f24_rip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ri_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_x_encode_fns[] = { + Opcode_ae_l32x2f24_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xp_encode_fns[] = { + Opcode_ae_l32x2f24_xp_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc_encode_fns[] = { + Opcode_ae_l32x2_xc_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode, Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode, Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode, Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_i_encode_fns[] = { + Opcode_ae_l32x2_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae_slot1_encode, Opcode_ae_l32x2_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_i_Slot_ae2_slot1_encode, Opcode_ae_l32x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae6_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae7_slot1_encode, Opcode_ae_l32x2_i_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ip_encode_fns[] = { + Opcode_ae_l32x2_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode, Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode, Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_x_encode_fns[] = { + Opcode_ae_l32x2_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae_slot1_encode, Opcode_ae_l32x2_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_x_Slot_ae2_slot1_encode, Opcode_ae_l32x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xp_encode_fns[] = { + Opcode_ae_l32x2_xp_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode, Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode, Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode, Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_i_encode_fns[] = { + Opcode_ae_l16x4_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae_slot1_encode, Opcode_ae_l16x4_i_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_i_Slot_ae2_slot1_encode, Opcode_ae_l16x4_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4_i_Slot_ae3_slot1_encode, Opcode_ae_l16x4_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae6_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae7_slot1_encode, Opcode_ae_l16x4_i_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_ip_encode_fns[] = { + Opcode_ae_l16x4_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae_slot1_encode, Opcode_ae_l16x4_x_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_x_Slot_ae2_slot1_encode, Opcode_ae_l16x4_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4_x_Slot_ae3_slot1_encode, Opcode_ae_l16x4_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xp_encode_fns[] = { + Opcode_ae_l16x4_xp_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l64_xc_Slot_ae_slot1_encode, Opcode_ae_l64_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l64_xc_Slot_ae2_slot1_encode, Opcode_ae_l64_xc_Slot_ae2_slot0_encode, Opcode_ae_l64_xc_Slot_ae3_slot1_encode, Opcode_ae_l64_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae_slot1_encode, Opcode_ae_l64_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l64_xc1_Slot_ae2_slot1_encode, Opcode_ae_l64_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_i_encode_fns[] = { + Opcode_ae_l64_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l64_i_Slot_ae_slot1_encode, Opcode_ae_l64_i_Slot_ae_slot0_encode, 0, Opcode_ae_l64_i_Slot_ae2_slot1_encode, Opcode_ae_l64_i_Slot_ae2_slot0_encode, Opcode_ae_l64_i_Slot_ae3_slot1_encode, Opcode_ae_l64_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_ip_encode_fns[] = { + Opcode_ae_l64_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae_slot1_encode, Opcode_ae_l64_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l64_ip_Slot_ae2_slot1_encode, Opcode_ae_l64_ip_Slot_ae2_slot0_encode, Opcode_ae_l64_ip_Slot_ae3_slot1_encode, Opcode_ae_l64_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae7_slot1_encode, Opcode_ae_l64_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l64_x_Slot_ae_slot1_encode, Opcode_ae_l64_x_Slot_ae_slot0_encode, 0, Opcode_ae_l64_x_Slot_ae2_slot1_encode, Opcode_ae_l64_x_Slot_ae2_slot0_encode, Opcode_ae_l64_x_Slot_ae3_slot1_encode, Opcode_ae_l64_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xp_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l64_xp_Slot_ae_slot1_encode, Opcode_ae_l64_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l64_xp_Slot_ae2_slot1_encode, Opcode_ae_l64_xp_Slot_ae2_slot0_encode, Opcode_ae_l64_xp_Slot_ae3_slot1_encode, Opcode_ae_l64_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_i_encode_fns[] = { + Opcode_ae_s16x2m_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_iu_encode_fns[] = { + Opcode_ae_s16x2m_iu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_x_encode_fns[] = { + Opcode_ae_s16x2m_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xu_encode_fns[] = { + Opcode_ae_s16x2m_xu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc_encode_fns[] = { + Opcode_ae_s32x2f24_xc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_i_encode_fns[] = { + Opcode_ae_s32x2f24_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ip_encode_fns[] = { + Opcode_ae_s32x2f24_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_x_encode_fns[] = { + Opcode_ae_s32x2f24_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xp_encode_fns[] = { + Opcode_ae_s32x2f24_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc_encode_fns[] = { + Opcode_ae_s32x2_xc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_i_encode_fns[] = { + Opcode_ae_s32x2_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ip_encode_fns[] = { + Opcode_ae_s32x2_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_x_encode_fns[] = { + Opcode_ae_s32x2_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xp_encode_fns[] = { + Opcode_ae_s32x2_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_i_encode_fns[] = { + Opcode_ae_s16x4_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_ip_encode_fns[] = { + Opcode_ae_s16x4_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_i_encode_fns[] = { + Opcode_ae_s16m_l_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_iu_encode_fns[] = { + Opcode_ae_s16m_l_iu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_x_encode_fns[] = { + Opcode_ae_s16m_l_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xu_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_i_encode_fns[] = { + Opcode_ae_s32f24_l_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_ip_encode_fns[] = { + Opcode_ae_s32f24_l_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_i_encode_fns[] = { + Opcode_ae_s32_l_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_ip_encode_fns[] = { + Opcode_ae_s32_l_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_x_encode_fns[] = { + Opcode_ae_s32_l_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xp_encode_fns[] = { + Opcode_ae_s32_l_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_i_encode_fns[] = { + Opcode_ae_s16_0_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_ip_encode_fns[] = { + Opcode_ae_s16_0_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xp_encode_fns[] = { + Opcode_ae_s16_0_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_i_encode_fns[] = { + Opcode_ae_s64_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s64_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_ip_encode_fns[] = { + Opcode_ae_s64_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s64_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_i_encode_fns[] = { + Opcode_ae_s32m_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_iu_encode_fns[] = { + Opcode_ae_s32m_iu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_x_encode_fns[] = { + Opcode_ae_s32m_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xu_encode_fns[] = { + Opcode_ae_s32m_xu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zalign64_encode_fns[] = { + Opcode_ae_zalign64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_zalign64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_zalign64_Slot_ae2_slot0_encode, 0, Opcode_ae_zalign64_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_zalign64_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign64_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_lalign64_i_Slot_ae2_slot0_encode, 0, Opcode_ae_lalign64_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign64_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_salign64_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_salign64_i_Slot_ae2_slot0_encode, 0, Opcode_ae_salign64_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_salign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movalign_encode_fns[] = { + Opcode_ae_movalign_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movalign_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movalign_Slot_ae2_slot0_encode, 0, Opcode_ae_movalign_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movalign_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la64_pp_encode_fns[] = { + Opcode_ae_la64_pp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la64_pp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae2_slot0_encode, 0, Opcode_ae_la64_pp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la64_pp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc_encode_fns[] = { + Opcode_ae_la32x2pos_pc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64pos_fp_encode_fns[] = { + Opcode_ae_sa64pos_fp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode, 0, Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64neg_fp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode, 0, Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic_encode_fns[] = { + Opcode_ae_la32x2_ic_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ip_encode_fns[] = { + Opcode_ae_la32x2_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode, 0, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic_encode_fns[] = { + Opcode_ae_la16x4_ic_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ip_encode_fns[] = { + Opcode_ae_la16x4_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_rip_encode_fns[] = { + Opcode_ae_la16x4_rip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode, 0, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic_encode_fns[] = { + Opcode_ae_la32x2f24_ic_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ip_encode_fns[] = { + Opcode_ae_la32x2f24_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la24_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic_encode_fns[] = { + Opcode_ae_la24x2_ic_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ip_encode_fns[] = { + Opcode_ae_la24x2_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ip_encode_fns[] = { + Opcode_ae_sa32x2_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ip_encode_fns[] = { + Opcode_ae_sa16x4_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ip_encode_fns[] = { + Opcode_ae_sa32x2f24_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addicirc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addicirc_Slot_ae_slot1_encode, Opcode_ae_addicirc_Slot_ae_slot0_encode, 0, Opcode_ae_addicirc_Slot_ae2_slot1_encode, Opcode_ae_addicirc_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode, Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode, Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae_slot1_encode, Opcode_ae_addcirc_xc_Slot_ae_slot0_encode, 0, Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode, Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xp_encode_fns[] = { + Opcode_ae_s32ra64s_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xp_encode_fns[] = { + Opcode_ae_s24ra64s_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2ra64s_ip_encode_fns[] = { + Opcode_ae_s32x2ra64s_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24x2ra64s_ip_encode_fns[] = { + Opcode_ae_s24x2ra64s_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot1_encode, Opcode_ae_addbrba32_Slot_ae_slot0_encode, 0, Opcode_ae_addbrba32_Slot_ae2_slot1_encode, Opcode_ae_addbrba32_Slot_ae2_slot0_encode, Opcode_ae_addbrba32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bitswap_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_bitswap_Slot_ae_slot1_encode, Opcode_ae_bitswap_Slot_ae_slot0_encode, 0, Opcode_ae_bitswap_Slot_ae2_slot1_encode, Opcode_ae_bitswap_Slot_ae2_slot0_encode, Opcode_ae_bitswap_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32js_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32js_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addrng32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subrng32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng3_encode_fns[] = { + 0, 0, 0, Opcode_ae_calcrng3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng2_encode_fns[] = { + 0, 0, 0, Opcode_ae_calcrng2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng1_encode_fns[] = { + 0, 0, 0, Opcode_ae_calcrng1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_rng32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_encode_fns[] = { + Opcode_ae_sel16i_Slot_inst_encode, 0, 0, Opcode_ae_sel16i_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel16i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae2_slot0_encode, Opcode_ae_sel16i_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shortswap_encode_fns[] = { + 0, 0, 0, Opcode_ae_shortswap_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab4_encode_fns[] = { + Opcode_ae_movab4_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movab4_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movab4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab2_encode_fns[] = { + Opcode_ae_movab2_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movab2_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movab2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab_encode_fns[] = { + Opcode_ae_movab_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movab_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movab_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba_encode_fns[] = { + Opcode_ae_movba_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movba_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movba_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba1x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_movba1x2_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movba1x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba4_encode_fns[] = { + Opcode_ae_movba4_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movba4_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movba4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba2_encode_fns[] = { + Opcode_ae_movba2_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movba2_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movba2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb2_encode_fns[] = { + Opcode_ae_movb2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb4_encode_fns[] = { + Opcode_ae_movb4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movt16x4_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movt16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movf16x4_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movf16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt32x2_encode_fns[] = { + Opcode_ae_movt32x2_Slot_inst_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf32x2_encode_fns[] = { + Opcode_ae_movf32x2_Slot_inst_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsara7x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movsara7x2_Slot_ae_slot1_encode, Opcode_ae_movsara7x2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsard7_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_movsard7_Slot_ae_slot0_encode, 0, Opcode_ae_movsard7_Slot_ae2_slot1_encode, Opcode_ae_movsard7_Slot_ae2_slot0_encode, 0, Opcode_ae_movsard7_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movsard7_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movasar_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_movasar_Slot_ae_slot0_encode, 0, Opcode_ae_movasar_Slot_ae2_slot1_encode, Opcode_ae_movasar_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32x2_encode_fns[] = { + Opcode_ae_movda32x2_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_movda32x2_Slot_ae_slot1_encode, Opcode_ae_movda32x2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32_encode_fns[] = { + Opcode_ae_movda32_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_movda32_Slot_ae_slot1_encode, Opcode_ae_movda32_Slot_ae_slot0_encode, 0, Opcode_ae_movda32_Slot_ae2_slot1_encode, Opcode_ae_movda32_Slot_ae2_slot0_encode, Opcode_ae_movda32_Slot_ae3_slot1_encode, Opcode_ae_movda32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movda32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16x2_encode_fns[] = { + Opcode_ae_movda16x2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16_encode_fns[] = { + Opcode_ae_movda16_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_movda16_Slot_ae_slot1_encode, Opcode_ae_movda16_Slot_ae_slot0_encode, 0, Opcode_ae_movda16_Slot_ae2_slot1_encode, Opcode_ae_movda16_Slot_ae2_slot0_encode, Opcode_ae_movda16_Slot_ae3_slot1_encode, Opcode_ae_movda16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movda16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movi_encode_fns[] = { + Opcode_ae_movi_Slot_inst_encode, 0, 0, Opcode_ae_movi_Slot_ae_slot3_encode, Opcode_ae_movi_Slot_ae_slot2_encode, Opcode_ae_movi_Slot_ae_slot1_encode, Opcode_ae_movi_Slot_ae_slot0_encode, 0, Opcode_ae_movi_Slot_ae2_slot1_encode, Opcode_ae_movi_Slot_ae2_slot0_encode, Opcode_ae_movi_Slot_ae3_slot1_encode, Opcode_ae_movi_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode, 0, Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode, Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_sat16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode, 0, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode, 0, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_32_encode_fns[] = { + Opcode_ae_sext32x2d16_32_Slot_inst_encode, 0, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode, 0, Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode, Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode, 0, Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode, Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { + Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { + Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { + Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { + Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { + Opcode_ae_truncp24q48x2_Slot_inst_encode, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32x2f64s_encode_fns[] = { + Opcode_ae_trunca32x2f64s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32x2f64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32f64s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32f64s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { + Opcode_ae_truncp16_Slot_inst_encode, 0, 0, Opcode_ae_truncp16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode, 0, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mov_encode_fns[] = { + Opcode_ae_mov_Slot_inst_encode, 0, 0, Opcode_ae_mov_Slot_ae_slot3_encode, Opcode_ae_mov_Slot_ae_slot2_encode, 0, Opcode_ae_mov_Slot_ae_slot0_encode, 0, Opcode_ae_mov_Slot_ae2_slot1_encode, Opcode_ae_mov_Slot_ae2_slot0_encode, Opcode_ae_mov_Slot_ae3_slot1_encode, Opcode_ae_mov_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_mov_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt64_encode_fns[] = { + Opcode_ae_movt64_Slot_inst_encode, 0, 0, Opcode_ae_movt64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movt64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movt64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movf64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movf64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56a32s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode, Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode, 0, Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode, Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48a32_encode_fns[] = { + Opcode_ae_cvt48a32_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_cvt48a32_Slot_ae_slot1_encode, Opcode_ae_cvt48a32_Slot_ae_slot0_encode, 0, Opcode_ae_cvt48a32_Slot_ae2_slot1_encode, Opcode_ae_cvt48a32_Slot_ae2_slot0_encode, Opcode_ae_cvt48a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64a32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_cvt64a32_Slot_ae_slot1_encode, Opcode_ae_cvt64a32_Slot_ae_slot0_encode, 0, Opcode_ae_cvt64a32_Slot_ae2_slot1_encode, Opcode_ae_cvt64a32_Slot_ae2_slot0_encode, Opcode_ae_cvt64a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_l_encode_fns[] = { + Opcode_ae_cvtq56p32s_l_Slot_inst_encode, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode, 0, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_h_encode_fns[] = { + Opcode_ae_cvtq56p32s_h_Slot_inst_encode, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode, 0, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode, 0, Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode, 0, Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode, 0, Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat48s_encode_fns[] = { + Opcode_ae_sat48s_Slot_inst_encode, 0, 0, Opcode_ae_sat48s_Slot_ae_slot3_encode, Opcode_ae_sat48s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_satq56s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sat24s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { + Opcode_ae_truncq32_Slot_inst_encode, 0, 0, Opcode_ae_truncq32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_truncq32_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { + Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode, 0, Opcode_ae_trunca32q48_Slot_ae2_slot1_encode, Opcode_ae_trunca32q48_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_l_encode_fns[] = { + Opcode_ae_movad32_l_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae_slot0_encode, 0, Opcode_ae_movad32_l_Slot_ae2_slot1_encode, Opcode_ae_movad32_l_Slot_ae2_slot0_encode, 0, Opcode_ae_movad32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_h_encode_fns[] = { + Opcode_ae_movad32_h_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad32_h_Slot_ae_slot0_encode, 0, Opcode_ae_movad32_h_Slot_ae2_slot1_encode, Opcode_ae_movad32_h_Slot_ae2_slot0_encode, 0, Opcode_ae_movad32_h_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad32_h_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_3_encode_fns[] = { + Opcode_ae_movad16_3_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad16_3_Slot_ae_slot0_encode, 0, Opcode_ae_movad16_3_Slot_ae2_slot1_encode, Opcode_ae_movad16_3_Slot_ae2_slot0_encode, 0, Opcode_ae_movad16_3_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad16_3_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_2_encode_fns[] = { + Opcode_ae_movad16_2_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad16_2_Slot_ae_slot0_encode, 0, Opcode_ae_movad16_2_Slot_ae2_slot1_encode, Opcode_ae_movad16_2_Slot_ae2_slot0_encode, 0, Opcode_ae_movad16_2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad16_2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_movad16_1_Slot_ae_slot0_encode, 0, Opcode_ae_movad16_1_Slot_ae2_slot1_encode, Opcode_ae_movad16_1_Slot_ae2_slot0_encode, 0, Opcode_ae_movad16_1_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad16_1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_0_encode_fns[] = { + Opcode_ae_movad16_0_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae_slot0_encode, 0, Opcode_ae_movad16_0_Slot_ae2_slot1_encode, Opcode_ae_movad16_0_Slot_ae2_slot0_encode, 0, Opcode_ae_movad16_0_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sra64_32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sra64_32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sra64_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr32_encode_fns[] = { + Opcode_ae_pksr32_Slot_inst_encode, 0, 0, 0, Opcode_ae_pksr32_Slot_ae_slot2_encode, 0, Opcode_ae_pksr32_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr24_encode_fns[] = { + Opcode_ae_pksr24_Slot_inst_encode, 0, 0, 0, Opcode_ae_pksr24_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksrf32_encode_fns[] = { + Opcode_ae_pksrf32_Slot_inst_encode, 0, 0, 0, Opcode_ae_pksrf32_Slot_ae_slot2_encode, 0, Opcode_ae_pksrf32_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { + Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { + Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_encode_fns[] = { + Opcode_ae_add32_Slot_inst_encode, 0, 0, Opcode_ae_add32_Slot_ae_slot3_encode, Opcode_ae_add32_Slot_ae_slot2_encode, 0, Opcode_ae_add32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_add32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32_encode_fns[] = { + Opcode_ae_sub32_Slot_inst_encode, 0, 0, Opcode_ae_sub32_Slot_ae_slot3_encode, Opcode_ae_sub32_Slot_ae_slot2_encode, 0, Opcode_ae_sub32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32_Slot_ae_slot3_encode, Opcode_ae_addsub32_Slot_ae_slot2_encode, 0, Opcode_ae_addsub32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addsub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32_Slot_ae_slot3_encode, Opcode_ae_subadd32_Slot_ae_slot2_encode, 0, Opcode_ae_subadd32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subadd32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16_Slot_ae_slot3_encode, Opcode_ae_add16_Slot_ae_slot2_encode, 0, Opcode_ae_add16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16_Slot_ae_slot3_encode, Opcode_ae_sub16_Slot_ae_slot2_encode, 0, Opcode_ae_sub16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32_Slot_ae_slot3_encode, Opcode_ae_neg32_Slot_ae_slot2_encode, 0, Opcode_ae_neg32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32_Slot_ae_slot3_encode, Opcode_ae_abs32_Slot_ae_slot2_encode, 0, Opcode_ae_abs32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add24s_encode_fns[] = { + Opcode_ae_add24s_Slot_inst_encode, 0, 0, Opcode_ae_add24s_Slot_ae_slot3_encode, Opcode_ae_add24s_Slot_ae_slot2_encode, 0, Opcode_ae_add24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub24s_Slot_ae_slot3_encode, Opcode_ae_sub24s_Slot_ae_slot2_encode, 0, Opcode_ae_sub24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_encode_fns[] = { + Opcode_ae_add32s_Slot_inst_encode, 0, 0, Opcode_ae_add32s_Slot_ae_slot3_encode, Opcode_ae_add32s_Slot_ae_slot2_encode, 0, Opcode_ae_add32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_add32s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32s_encode_fns[] = { + Opcode_ae_sub32s_Slot_inst_encode, 0, 0, Opcode_ae_sub32s_Slot_ae_slot3_encode, Opcode_ae_sub32s_Slot_ae_slot2_encode, 0, Opcode_ae_sub32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32s_Slot_ae_slot3_encode, Opcode_ae_addsub32s_Slot_ae_slot2_encode, 0, Opcode_ae_addsub32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32s_Slot_ae_slot3_encode, Opcode_ae_subadd32s_Slot_ae_slot2_encode, 0, Opcode_ae_subadd32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subadd32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16s_encode_fns[] = { + Opcode_ae_add16s_Slot_inst_encode, 0, 0, Opcode_ae_add16s_Slot_ae_slot3_encode, Opcode_ae_add16s_Slot_ae_slot2_encode, 0, Opcode_ae_add16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16s_encode_fns[] = { + Opcode_ae_sub16s_Slot_inst_encode, 0, 0, Opcode_ae_sub16s_Slot_ae_slot3_encode, Opcode_ae_sub16s_Slot_ae_slot2_encode, 0, Opcode_ae_sub16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg24s_Slot_ae_slot3_encode, Opcode_ae_neg24s_Slot_ae_slot2_encode, 0, Opcode_ae_neg24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs24s_encode_fns[] = { + Opcode_ae_abs24s_Slot_inst_encode, 0, 0, Opcode_ae_abs24s_Slot_ae_slot3_encode, Opcode_ae_abs24s_Slot_ae_slot2_encode, 0, Opcode_ae_abs24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32s_encode_fns[] = { + Opcode_ae_neg32s_Slot_inst_encode, 0, 0, Opcode_ae_neg32s_Slot_ae_slot3_encode, Opcode_ae_neg32s_Slot_ae_slot2_encode, 0, Opcode_ae_neg32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32s_encode_fns[] = { + Opcode_ae_abs32s_Slot_inst_encode, 0, 0, Opcode_ae_abs32s_Slot_ae_slot3_encode, Opcode_ae_abs32s_Slot_ae_slot2_encode, 0, Opcode_ae_abs32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg16s_encode_fns[] = { + Opcode_ae_neg16s_Slot_inst_encode, 0, 0, Opcode_ae_neg16s_Slot_ae_slot3_encode, Opcode_ae_neg16s_Slot_ae_slot2_encode, 0, Opcode_ae_neg16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16s_encode_fns[] = { + Opcode_ae_abs16s_Slot_inst_encode, 0, 0, Opcode_ae_abs16s_Slot_ae_slot3_encode, Opcode_ae_abs16s_Slot_ae_slot2_encode, 0, Opcode_ae_abs16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_lt16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_le16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_eq16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt32_encode_fns[] = { + Opcode_ae_lt32_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_lt32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_le32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq32_encode_fns[] = { + Opcode_ae_eq32_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_eq32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min32_encode_fns[] = { + Opcode_ae_min32_Slot_inst_encode, 0, 0, Opcode_ae_min32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_min32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_min32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max32_encode_fns[] = { + Opcode_ae_max32_Slot_inst_encode, 0, 0, Opcode_ae_max32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_max32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_max32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64_encode_fns[] = { + Opcode_ae_add64_Slot_inst_encode, 0, 0, Opcode_ae_add64_Slot_ae_slot3_encode, Opcode_ae_add64_Slot_ae_slot2_encode, 0, Opcode_ae_add64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64_encode_fns[] = { + Opcode_ae_sub64_Slot_inst_encode, 0, 0, Opcode_ae_sub64_Slot_ae_slot3_encode, Opcode_ae_sub64_Slot_ae_slot2_encode, 0, Opcode_ae_sub64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64_encode_fns[] = { + Opcode_ae_neg64_Slot_inst_encode, 0, 0, Opcode_ae_neg64_Slot_ae_slot3_encode, Opcode_ae_neg64_Slot_ae_slot2_encode, 0, Opcode_ae_neg64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64_encode_fns[] = { + Opcode_ae_abs64_Slot_inst_encode, 0, 0, Opcode_ae_abs64_Slot_ae_slot3_encode, Opcode_ae_abs64_Slot_ae_slot2_encode, 0, Opcode_ae_abs64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot3_encode, Opcode_ae_addsq56s_Slot_ae_slot2_encode, 0, Opcode_ae_addsq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot3_encode, Opcode_ae_subsq56s_Slot_ae_slot2_encode, 0, Opcode_ae_subsq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64s_Slot_ae_slot3_encode, Opcode_ae_add64s_Slot_ae_slot2_encode, 0, Opcode_ae_add64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64s_Slot_ae_slot3_encode, Opcode_ae_sub64s_Slot_ae_slot2_encode, 0, Opcode_ae_sub64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot3_encode, Opcode_ae_negsq56s_Slot_ae_slot2_encode, 0, Opcode_ae_negsq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_negsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot3_encode, Opcode_ae_abssq56s_Slot_ae_slot2_encode, 0, Opcode_ae_abssq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abssq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64s_Slot_ae_slot3_encode, Opcode_ae_neg64s_Slot_ae_slot2_encode, 0, Opcode_ae_neg64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64s_Slot_ae_slot3_encode, Opcode_ae_abs64s_Slot_ae_slot2_encode, 0, Opcode_ae_abs64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_and_encode_fns[] = { + Opcode_ae_and_Slot_inst_encode, 0, 0, Opcode_ae_and_Slot_ae_slot3_encode, 0, 0, Opcode_ae_and_Slot_ae_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nand_encode_fns[] = { + 0, 0, 0, Opcode_ae_nand_Slot_ae_slot3_encode, 0, 0, Opcode_ae_nand_Slot_ae_slot0_encode, 0, 0, Opcode_ae_nand_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_or_encode_fns[] = { + Opcode_ae_or_Slot_inst_encode, 0, 0, Opcode_ae_or_Slot_ae_slot3_encode, 0, 0, Opcode_ae_or_Slot_ae_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xor_encode_fns[] = { + Opcode_ae_xor_Slot_inst_encode, 0, 0, Opcode_ae_xor_Slot_ae_slot3_encode, 0, 0, Opcode_ae_xor_Slot_ae_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24_encode_fns[] = { + Opcode_ae_slai24_Slot_inst_encode, 0, 0, Opcode_ae_slai24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srli24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai24_encode_fns[] = { + Opcode_ae_srai24_Slot_inst_encode, 0, 0, Opcode_ae_srai24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24_encode_fns[] = { + Opcode_ae_slas24_Slot_inst_encode, 0, 0, Opcode_ae_slas24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srls24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras24_encode_fns[] = { + Opcode_ae_sras24_Slot_inst_encode, 0, 0, Opcode_ae_sras24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sras24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai16r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32_encode_fns[] = { + Opcode_ae_slai32_Slot_inst_encode, 0, 0, Opcode_ae_slai32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli32_encode_fns[] = { + Opcode_ae_srli32_Slot_inst_encode, 0, 0, Opcode_ae_srli32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srli32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32_encode_fns[] = { + Opcode_ae_srai32_Slot_inst_encode, 0, 0, Opcode_ae_srai32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai32r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srls32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sras32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32_encode_fns[] = { + Opcode_ae_slaa32_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaa32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_srla32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srla32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32_encode_fns[] = { + Opcode_ae_sraa32_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sraa32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16s_encode_fns[] = { + Opcode_ae_slaa16s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaa16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sraa16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa16rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24s_encode_fns[] = { + Opcode_ae_slai24s_Slot_inst_encode, 0, 0, Opcode_ae_slai24s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32s_encode_fns[] = { + Opcode_ae_slai32s_Slot_inst_encode, 0, 0, Opcode_ae_slai32s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32s_encode_fns[] = { + Opcode_ae_slaa32s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaa32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32s_encode_fns[] = { + Opcode_ae_sraa32s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sraa32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slasq56_encode_fns[] = { + Opcode_ae_slasq56_Slot_inst_encode, 0, 0, Opcode_ae_slasq56_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srlsq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { + Opcode_ae_srasq56_Slot_inst_encode, 0, 0, Opcode_ae_srasq56_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaaq56_encode_fns[] = { + Opcode_ae_slaaq56_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaaq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { + Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srlaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { + Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64_encode_fns[] = { + Opcode_ae_slai64_Slot_inst_encode, 0, 0, Opcode_ae_slai64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srli64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai64_encode_fns[] = { + Opcode_ae_srai64_Slot_inst_encode, 0, 0, Opcode_ae_srai64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srls64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sras64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64_encode_fns[] = { + Opcode_ae_slaa64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaa64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla64_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_srla64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srla64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa64_encode_fns[] = { + Opcode_ae_sraa64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sraa64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaisq56s_encode_fns[] = { + Opcode_ae_slaisq56s_Slot_inst_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slassq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slassq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { + Opcode_ae_slaasq56s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaasq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64s_encode_fns[] = { + Opcode_ae_slas64s_Slot_inst_encode, 0, 0, Opcode_ae_slas64s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_slaa64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt64_encode_fns[] = { + Opcode_ae_lt64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_lt64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le64_encode_fns[] = { + Opcode_ae_le64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_le64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq64_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_eq64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max64_encode_fns[] = { + 0, 0, 0, Opcode_ae_max64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_max64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_max64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min64_encode_fns[] = { + 0, 0, 0, Opcode_ae_min64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_min64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_min64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa64_encode_fns[] = { + Opcode_ae_nsa64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_nsa64_Slot_ae_slot0_encode, 0, Opcode_ae_nsa64_Slot_ae2_slot1_encode, Opcode_ae_nsa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz16_0_encode_fns[] = { + Opcode_ae_nsaz16_0_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32_l_encode_fns[] = { + Opcode_ae_nsaz32_l_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae_slot0_encode, 0, Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode, Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32f48p16s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32ra_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32r_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32f48p16s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32ra_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32r_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32f48p16s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32ra_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32r_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32ra_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32r_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32ra_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32r_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32ra_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32r_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32ra_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32r_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32ra_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32r_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32ra_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32r_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32u_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32u_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32u_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_33_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_33_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_33_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_32_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_32_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_21_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_21_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_21_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_31_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_31_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_31_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_30_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_30_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_30_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_10_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_10_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_10_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_20_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_20_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_20_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_11_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_11_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_11_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_33_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_33_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_33_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_32_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_32_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_21_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_21_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_21_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_31_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_31_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_31_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_30_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_30_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_30_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_10_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_10_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_10_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_20_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_20_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_20_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_11_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_11_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_11_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_33_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_33_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_33_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_32_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_32_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_21_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_21_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_21_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_31_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_31_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_31_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_30_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_30_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_30_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_10_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_10_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_10_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_20_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_20_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_20_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_11_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_11_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_11_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_33_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_13_02_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_11_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_33_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_13_02_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_11_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_33_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_13_02_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_11_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_33_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_13_02_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_11_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2r_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2ra_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24x2ra_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2r_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24x2r_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2r_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2ra_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24x2ra_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2r_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24x2r_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2r_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2ra_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24x2ra_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2r_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24x2r_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasd32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasd32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsad32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsad32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsad32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsad32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsad32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h2_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h0_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h2_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h0_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h2_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h0_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h2_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h0_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp32x16x2_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp32x16x2_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap32x16x2_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap32x16x2_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp32x16x2_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp32x16x2_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp32x2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2rs_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x2rs_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x2ras_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulap32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2rs_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap32x2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2rs_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x2rs_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x2ras_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp32x2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2rs_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x2rs_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x2ras_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4s_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulc32_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc24ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulac32_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc24ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf16x4ss_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf16x4ss_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf16x4ss_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaafq32x16_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_s2_Slot_ae7_slot3_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaafq32x16_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_s2_Slot_ae7_slot3_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq32x16_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_s2_Slot_ae7_slot3_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq32x16_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_s2_Slot_ae7_slot3_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul16_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula16_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq16_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaaaq16_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq16_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaaaaq16_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_div64d32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_div64d32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_l_encode_fns[] = { + Opcode_ae_div64d32_l_Slot_inst_encode, 0, 0, Opcode_ae_div64d32_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_div64d32_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_div64d32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { + Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { + Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { + Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { + Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ip_encode_fns[] = { + Opcode_ae_vldl16c_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic_encode_fns[] = { + Opcode_ae_vldl16c_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { + Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldsht_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { + Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_lb_Slot_ae_slot1_encode, Opcode_ae_lb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lb_Slot_ae3_slot1_encode, Opcode_ae_lb_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { + Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_lbi_Slot_ae_slot1_encode, Opcode_ae_lbi_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lbi_Slot_ae3_slot1_encode, Opcode_ae_lbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { + Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_Slot_ae3_slot1_encode, Opcode_ae_lbk_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { + Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbs_encode_fns[] = { + Opcode_ae_lbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbsi_encode_fns[] = { + Opcode_ae_lbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { + Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_db_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_db_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { + Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_dbi_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_dbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic_encode_fns[] = { + Opcode_ae_db_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic_encode_fns[] = { + Opcode_ae_dbi_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic1_encode_fns[] = { + Opcode_ae_db_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic1_encode_fns[] = { + Opcode_ae_dbi_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ip_encode_fns[] = { + Opcode_ae_db_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ip_encode_fns[] = { + Opcode_ae_dbi_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { + Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { + Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { + Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { + Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { + Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { + Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic_encode_fns[] = { + Opcode_ae_sb_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic_encode_fns[] = { + Opcode_ae_sbi_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic_encode_fns[] = { + Opcode_ae_vles16c_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic_encode_fns[] = { + Opcode_ae_sbf_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic1_encode_fns[] = { + Opcode_ae_sb_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic1_encode_fns[] = { + Opcode_ae_sbi_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic1_encode_fns[] = { + Opcode_ae_sbf_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ip_encode_fns[] = { + Opcode_ae_sb_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ip_encode_fns[] = { + Opcode_ae_sbi_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ip_encode_fns[] = { + Opcode_ae_vles16c_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ip_encode_fns[] = { + Opcode_ae_sbf_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32_encode_fns[] = { + Opcode_ae_sext32_Slot_inst_encode, 0, 0, Opcode_ae_sext32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movae_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movae_Slot_ae3_slot1_encode, Opcode_ae_movae_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movea_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movea_Slot_ae3_slot1_encode, Opcode_ae_movea_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_moveep_encode_fns[] = { + 0, 0, 0, Opcode_ae_moveep_Slot_ae_slot3_encode, Opcode_ae_moveep_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext72_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sext72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_add72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sub72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72x64_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_add72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72x64_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sub72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32ep_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32ep_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32ep_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32ep_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32ep_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32ep_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32ep_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32ep_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32ep_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32ep_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32ep_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32ep_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32ep_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32ep_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32ep_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32ep_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32ep_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32usep_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32usep_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32usep_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32usep_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai72_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai72_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sat64s_Slot_ae_slot3_encode, Opcode_ae_sat64s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16si_n_encode_fns[] = { + 0, 0, Opcode_ae_l16si_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16ui_n_encode_fns[] = { + 0, 0, Opcode_ae_l16ui_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16i_n_encode_fns[] = { + 0, 0, Opcode_ae_s16i_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfcrfsrv_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movvfcrfsr_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { + Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { + Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { + Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movt_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { + Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movf_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { + Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_moveqz_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { + Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movnez_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { + Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movgez_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { + Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movltz_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_trunc_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_utrunc_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_sx2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_sx2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ficeil_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fifloor_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firound_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fitrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firint_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { + Opcode_abs_s_Slot_inst_encode, 0, 0, 0, Opcode_abs_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { + Opcode_mul_s_Slot_inst_encode, 0, 0, Opcode_mul_s_Slot_ae_slot3_encode, Opcode_mul_s_Slot_ae_slot2_encode, 0, 0, Opcode_mul_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { + Opcode_madd_s_Slot_inst_encode, 0, 0, Opcode_madd_s_Slot_ae_slot3_encode, Opcode_madd_s_Slot_ae_slot2_encode, 0, 0, Opcode_madd_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { + Opcode_msub_s_Slot_inst_encode, 0, 0, Opcode_msub_s_Slot_ae_slot3_encode, Opcode_msub_s_Slot_ae_slot2_encode, 0, 0, Opcode_msub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_s_encode_fns[] = { + 0, 0, 0, Opcode_msubn_s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = { + Opcode_maddn_s_Slot_inst_encode, 0, 0, 0, Opcode_maddn_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { + Opcode_add_s_Slot_inst_encode, 0, 0, Opcode_add_s_Slot_ae_slot3_encode, Opcode_add_s_Slot_ae_slot2_encode, 0, 0, Opcode_add_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { + Opcode_sub_s_Slot_inst_encode, 0, 0, Opcode_sub_s_Slot_ae_slot3_encode, Opcode_sub_s_Slot_ae_slot2_encode, 0, 0, Opcode_sub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { + Opcode_neg_s_Slot_inst_encode, 0, 0, Opcode_neg_s_Slot_ae_slot3_encode, Opcode_neg_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_float_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ufloat_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_sx2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_sx2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { + Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ole_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { + Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_olt_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { + Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { + Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { + Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { + Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { + Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = { + Opcode_const_s_Slot_inst_encode, 0, 0, 0, Opcode_const_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_div0_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_recip0_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = { + Opcode_divn_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_addexp_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_min_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_max_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_s_encode_fns[] = { + 0, 0, 0, Opcode_mulmux_s_Slot_ae_slot3_encode, Opcode_mulmux_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_s_encode_fns[] = { + 0, 0, 0, Opcode_maddmux_s_Slot_ae_slot3_encode, Opcode_maddmux_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_conjc_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sigmoid_q15_encode_fns[] = { + Opcode_sigmoid_q15_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sigmoid_fp32_encode_fns[] = { + Opcode_sigmoid_fp32_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +int num_bypass_groups() { + return 0; +} + +int num_bypass_group_chunks() { + return 0; +} + +uint32 *bypass_entry(int i) { + return 0; +} + + +/* Opcode table. */ + +static xtensa_funcUnit_use Opcode_l32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16si_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32r_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l8ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s16i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32nb_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s8i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hl_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hl_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_lh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_lh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_ll_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_ll_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hl_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hl_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_lh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_lh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_ll_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_ll_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_licw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sicw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ai_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32c1i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la64_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64neg_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32u_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32u_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32u_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_33_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_33_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_32_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_21_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_21_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_31_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_31_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_30_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_30_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_10_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_10_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_20_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_20_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_11_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_11_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_33_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_33_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_32_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_21_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_21_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_31_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_31_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_30_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_30_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_10_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_10_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_20_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_20_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_11_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_11_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_33_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_33_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_32_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_21_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_21_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_31_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_31_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_30_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_30_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_10_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_10_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_20_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_20_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_11_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_11_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_33_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_33_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_13_02_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_13_02_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_11_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_11_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_33_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_33_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_13_02_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_13_02_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_11_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_11_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_33_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_33_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_13_02_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_13_02_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_11_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_11_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_33_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_33_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_13_02_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_13_02_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_11_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_11_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf48q32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf48q32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf48q32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf48q32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulq32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulq32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulq32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulq32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf48q32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf48q32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf48q32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf48q32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaq32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaq32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaq32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaq32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf48q32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf48q32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf48q32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf48q32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsq32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsq32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsq32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsq32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp24x2ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp24x2r_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp24x2ra_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp24x2r_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp24x2ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp24x2r_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp24x2ra_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp24x2r_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp24x2ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp24x2r_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp24x2ra_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp24x2r_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h2_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h0_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h2_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h0_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h2_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h0_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h2_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h0_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h2_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h0_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h2_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h0_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h2_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h0_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h2_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h0_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x16x2_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2rs_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2s_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2s_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x16x2_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2rs_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2ras_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x16x2_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2rs_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x16x2_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2rs_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2ras_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x16x2_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2rs_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2s_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2s_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x16x2_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2rs_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2ras_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x16x2_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2rs_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x16x2_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2rs_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2ras_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x16x2_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2rs_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2s_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2s_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x16x2_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2rs_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2ras_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x16x2_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2rs_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x16x2_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2rs_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2ras_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x2rs_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x2ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x2rs_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x2ras_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x2rs_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x2ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x2rs_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x2ras_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x2rs_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x2ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x2rs_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x2ras_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp16x4s_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp16x4ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulc32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfc24ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfc32ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulc32x16_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfc32x16ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulc32x16_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfc32x16ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulac32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafc24ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafc32ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulac32x16_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafc32x16ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulac32x16_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafc32x16ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16x4ss_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16x4ss_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16x4ss_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul16x4_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula16x4_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls16x4_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x2s_fir_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x2ra_fir_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x2s_fir_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x2ra_fir_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x16x2_fir_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x16x2_fir_hl_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x16x2_fir_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x16x2_fir_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x2s_fir_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x2ra_fir_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x2s_fir_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x2ra_fir_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x16x2_fir_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x16x2_fir_hl_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x16x2_fir_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x16x2_fir_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaafq32x16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaafq32x16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaafq32x16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaafq32x16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaaq32x16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaaq32x16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaaq32x16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaaq32x16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul16_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula16_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul16_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula16_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaaq16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaaq16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaaq16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaaq16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbs_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbsi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32ep_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32ep_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32ep_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32ep_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32ep_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32ep_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32ep_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32ep_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32ep_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32ep_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32ep_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32ep_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32ep_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32ep_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32usep_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32usep_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32usep_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32usep_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32usep_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32usep_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32usep_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32usep_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16si_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16ui_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16i_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 1, Opcode_l32e_funcUnit_uses }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 1, Opcode_s32e_funcUnit_uses }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 1, Opcode_l32i_n_funcUnit_uses }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 1, Opcode_s32i_n_funcUnit_uses }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 1, Opcode_l16ui_funcUnit_uses }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 1, Opcode_l16si_funcUnit_uses }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 1, Opcode_l32i_funcUnit_uses }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 1, Opcode_l32r_funcUnit_uses }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 1, Opcode_l8ui_funcUnit_uses }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 1, Opcode_s16i_funcUnit_uses }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 1, Opcode_s32i_funcUnit_uses }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 1, Opcode_s32nb_funcUnit_uses }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 1, Opcode_s8i_funcUnit_uses }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "mulsh", ICLASS_xt_mul32h, + 0, + Opcode_mulsh_encode_fns, 0, 0 }, + { "muluh", ICLASS_xt_mul32h, + 0, + Opcode_muluh_encode_fns, 0, 0 }, + { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.da.hh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.da.hl", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.ll", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 1, Opcode_mula_da_hh_lddec_funcUnit_uses }, + { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 1, Opcode_mula_da_hh_ldinc_funcUnit_uses }, + { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 1, Opcode_mula_da_hl_lddec_funcUnit_uses }, + { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 1, Opcode_mula_da_hl_ldinc_funcUnit_uses }, + { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 1, Opcode_mula_da_lh_lddec_funcUnit_uses }, + { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 1, Opcode_mula_da_lh_ldinc_funcUnit_uses }, + { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 1, Opcode_mula_da_ll_lddec_funcUnit_uses }, + { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 1, Opcode_mula_da_ll_ldinc_funcUnit_uses }, + { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 1, Opcode_mula_dd_hh_lddec_funcUnit_uses }, + { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 1, Opcode_mula_dd_hh_ldinc_funcUnit_uses }, + { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 1, Opcode_mula_dd_hl_lddec_funcUnit_uses }, + { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 1, Opcode_mula_dd_hl_ldinc_funcUnit_uses }, + { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 1, Opcode_mula_dd_lh_lddec_funcUnit_uses }, + { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 1, Opcode_mula_dd_lh_ldinc_funcUnit_uses }, + { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 1, Opcode_mula_dd_ll_lddec_funcUnit_uses }, + { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 1, Opcode_mula_dd_ll_ldinc_funcUnit_uses }, + { "lddec", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_lddec_encode_fns, 1, Opcode_lddec_funcUnit_uses }, + { "ldinc", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_ldinc_encode_fns, 1, Opcode_ldinc_funcUnit_uses }, + { "rsr.m0", ICLASS_xt_iclass_rsr_m0, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", ICLASS_xt_iclass_wsr_m0, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", ICLASS_xt_iclass_xsr_m0, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", ICLASS_xt_iclass_rsr_m1, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", ICLASS_xt_iclass_wsr_m1, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", ICLASS_xt_iclass_xsr_m1, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", ICLASS_xt_iclass_rsr_m2, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", ICLASS_xt_iclass_wsr_m2, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", ICLASS_xt_iclass_xsr_m2, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", ICLASS_xt_iclass_rsr_m3, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", ICLASS_xt_iclass_wsr_m3, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", ICLASS_xt_iclass_xsr_m3, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 1, Opcode_lddr32_p_funcUnit_uses }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 1, Opcode_sddr32_p_funcUnit_uses }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 1, Opcode_lict_funcUnit_uses }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 1, Opcode_licw_funcUnit_uses }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 1, Opcode_sict_funcUnit_uses }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 1, Opcode_sicw_funcUnit_uses }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, + 0, + Opcode_diwbui_p_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfm.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfm_b_encode_fns, 0, 0 }, + { "dpfm.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfm_bf_encode_fns, 0, 0 }, + { "dpfr.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfr_b_encode_fns, 0, 0 }, + { "dpfr.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfr_bf_encode_fns, 0, 0 }, + { "dpfw.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfw_b_encode_fns, 0, 0 }, + { "dpfw.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfw_bf_encode_fns, 0, 0 }, + { "pfnxt.f", ICLASS_xt_iclass_bpfnxt, + 0, + Opcode_pfnxt_f_encode_fns, 0, 0 }, + { "dhi.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhi_b_encode_fns, 0, 0 }, + { "dhwbi.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhwbi_b_encode_fns, 0, 0 }, + { "dhwb.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhwb_b_encode_fns, 0, 0 }, + { "pfend.a", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfend_a_encode_fns, 0, 0 }, + { "pfend.o", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfend_o_encode_fns, 0, 0 }, + { "pfwait.a", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfwait_a_encode_fns, 0, 0 }, + { "pfwait.r", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfwait_r_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 1, Opcode_sdct_funcUnit_uses }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 1, Opcode_ldct_funcUnit_uses }, + { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, + 0, + Opcode_rsr_prefctl_encode_fns, 0, 0 }, + { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, + 0, + Opcode_wsr_prefctl_encode_fns, 0, 0 }, + { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, + 0, + Opcode_xsr_prefctl_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 1, Opcode_l32ai_funcUnit_uses }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 1, Opcode_s32ri_funcUnit_uses }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 1, Opcode_s32c1i_funcUnit_uses }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "beqz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_w15_encode_fns, 0, 0 }, + { "bgez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_w15_encode_fns, 0, 0 }, + { "bltz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_w15_encode_fns, 0, 0 }, + { "bnez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_w15_encode_fns, 0, 0 }, + { "beqi.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_w15_encode_fns, 0, 0 }, + { "bgei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_w15_encode_fns, 0, 0 }, + { "blti.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_w15_encode_fns, 0, 0 }, + { "bnei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_w15_encode_fns, 0, 0 }, + { "bgeui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_w15_encode_fns, 0, 0 }, + { "bltui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_w15_encode_fns, 0, 0 }, + { "bbci.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_w15_encode_fns, 0, 0 }, + { "bbsi.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_w15_encode_fns, 0, 0 }, + { "ball.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_w15_encode_fns, 0, 0 }, + { "bany.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_w15_encode_fns, 0, 0 }, + { "bbc.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_w15_encode_fns, 0, 0 }, + { "bbs.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_w15_encode_fns, 0, 0 }, + { "beq.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_w15_encode_fns, 0, 0 }, + { "bgeu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_w15_encode_fns, 0, 0 }, + { "bge.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_w15_encode_fns, 0, 0 }, + { "bltu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_w15_encode_fns, 0, 0 }, + { "blt.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_w15_encode_fns, 0, 0 }, + { "bnall.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_w15_encode_fns, 0, 0 }, + { "bne.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_w15_encode_fns, 0, 0 }, + { "bnone.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_w15_encode_fns, 0, 0 }, + { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, + 0, + Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, + { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, + 0, + Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, + { "rur.ae_bithead", ICLASS_rur_ae_bithead, + 0, + Opcode_rur_ae_bithead_encode_fns, 0, 0 }, + { "wur.ae_bithead", ICLASS_wur_ae_bithead, + 0, + Opcode_wur_ae_bithead_encode_fns, 0, 0 }, + { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, + 0, + Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, + 0, + Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "rur.ae_cw_sd_no", ICLASS_rur_ae_cw_sd_no, + 0, + Opcode_rur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "wur.ae_cw_sd_no", ICLASS_wur_ae_cw_sd_no, + 0, + Opcode_wur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, + 0, + Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, + { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, + 0, + Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, + { "rur.ae_cend0", ICLASS_rur_ae_cend0, + 0, + Opcode_rur_ae_cend0_encode_fns, 0, 0 }, + { "wur.ae_cend0", ICLASS_wur_ae_cend0, + 0, + Opcode_wur_ae_cend0_encode_fns, 0, 0 }, + { "rur.ae_cbegin1", ICLASS_rur_ae_cbegin1, + 0, + Opcode_rur_ae_cbegin1_encode_fns, 0, 0 }, + { "wur.ae_cbegin1", ICLASS_wur_ae_cbegin1, + 0, + Opcode_wur_ae_cbegin1_encode_fns, 0, 0 }, + { "rur.ae_cend1", ICLASS_rur_ae_cend1, + 0, + Opcode_rur_ae_cend1_encode_fns, 0, 0 }, + { "wur.ae_cend1", ICLASS_wur_ae_cend1, + 0, + Opcode_wur_ae_cend1_encode_fns, 0, 0 }, + { "ae_sext16", ICLASS_ic_sext16, + 0, + Opcode_ae_sext16_encode_fns, 0, 0 }, + { "ae_zext16", ICLASS_ic_zext16, + 0, + Opcode_ae_zext16_encode_fns, 0, 0 }, + { "ae_clamps16", ICLASS_ic_clamps16, + 0, + Opcode_ae_clamps16_encode_fns, 0, 0 }, + { "rur.fcr", ICLASS_rur_fcr, + 0, + Opcode_rur_fcr_encode_fns, 0, 0 }, + { "wur.fcr", ICLASS_wur_fcr, + 0, + Opcode_wur_fcr_encode_fns, 0, 0 }, + { "rur.fsr", ICLASS_rur_fsr, + 0, + Opcode_rur_fsr_encode_fns, 0, 0 }, + { "wur.fsr", ICLASS_wur_fsr, + 0, + Opcode_wur_fsr_encode_fns, 0, 0 }, + { "f64iter", ICLASS_iclass_F64ITER, + 0, + Opcode_f64iter_encode_fns, 0, 0 }, + { "f64rnd", ICLASS_iclass_F64RND, + 0, + Opcode_f64rnd_encode_fns, 0, 0 }, + { "f64addc", ICLASS_iclass_F64ADDC_F64SUBC, + 0, + Opcode_f64addc_encode_fns, 0, 0 }, + { "f64subc", ICLASS_iclass_F64ADDC_F64SUBC, + 0, + Opcode_f64subc_encode_fns, 0, 0 }, + { "f64sig", ICLASS_iclass_F64SIG, + 0, + Opcode_f64sig_encode_fns, 0, 0 }, + { "f64cmpl", ICLASS_iclass_F64CMPL, + 0, + Opcode_f64cmpl_encode_fns, 0, 0 }, + { "f64cmph", ICLASS_iclass_F64CMPH, + 0, + Opcode_f64cmph_encode_fns, 0, 0 }, + { "f64norm", ICLASS_iclass_F64NORM, + 0, + Opcode_f64norm_encode_fns, 0, 0 }, + { "f64sexp", ICLASS_iclass_F64SEXP, + 0, + Opcode_f64sexp_encode_fns, 0, 0 }, + { "rf64r", ICLASS_iclass_RF64R, + 0, + Opcode_rf64r_encode_fns, 0, 0 }, + { "wf64r", ICLASS_iclass_WF64R, + 0, + Opcode_wf64r_encode_fns, 0, 0 }, + { "rur.f64r_lo", ICLASS_rur_f64r_lo, + 0, + Opcode_rur_f64r_lo_encode_fns, 0, 0 }, + { "wur.f64r_lo", ICLASS_wur_f64r_lo, + 0, + Opcode_wur_f64r_lo_encode_fns, 0, 0 }, + { "rur.f64r_hi", ICLASS_rur_f64r_hi, + 0, + Opcode_rur_f64r_hi_encode_fns, 0, 0 }, + { "wur.f64r_hi", ICLASS_wur_f64r_hi, + 0, + Opcode_wur_f64r_hi_encode_fns, 0, 0 }, + { "rur.f64s", ICLASS_rur_f64s, + 0, + Opcode_rur_f64s_encode_fns, 0, 0 }, + { "wur.f64s", ICLASS_wur_f64s, + 0, + Opcode_wur_f64s_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 }, + { "rur.ae_overflow", ICLASS_RUR_AE_OVERFLOW, + 0, + Opcode_rur_ae_overflow_encode_fns, 0, 0 }, + { "wur.ae_overflow", ICLASS_WUR_AE_OVERFLOW, + 0, + Opcode_wur_ae_overflow_encode_fns, 0, 0 }, + { "rur.ae_sar", ICLASS_RUR_AE_SAR, + 0, + Opcode_rur_ae_sar_encode_fns, 0, 0 }, + { "wur.ae_sar", ICLASS_WUR_AE_SAR, + 0, + Opcode_wur_ae_sar_encode_fns, 0, 0 }, + { "rur.ae_bitptr", ICLASS_RUR_AE_BITPTR, + 0, + Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, + { "wur.ae_bitptr", ICLASS_WUR_AE_BITPTR, + 0, + Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, + { "rur.ae_bitsused", ICLASS_RUR_AE_BITSUSED, + 0, + Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, + { "wur.ae_bitsused", ICLASS_WUR_AE_BITSUSED, + 0, + Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, + { "rur.ae_tablesize", ICLASS_RUR_AE_TABLESIZE, + 0, + Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, + { "wur.ae_tablesize", ICLASS_WUR_AE_TABLESIZE, + 0, + Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, + { "rur.ae_first_ts", ICLASS_RUR_AE_FIRST_TS, + 0, + Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, + { "wur.ae_first_ts", ICLASS_WUR_AE_FIRST_TS, + 0, + Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, + { "rur.ae_nextoffset", ICLASS_RUR_AE_NEXTOFFSET, + 0, + Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, + { "wur.ae_nextoffset", ICLASS_WUR_AE_NEXTOFFSET, + 0, + Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, + { "rur.ae_searchdone", ICLASS_RUR_AE_SEARCHDONE, + 0, + Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, + { "wur.ae_searchdone", ICLASS_WUR_AE_SEARCHDONE, + 0, + Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, + { "rur.ae_cwrap", ICLASS_RUR_AE_CWRAP, + 0, + Opcode_rur_ae_cwrap_encode_fns, 0, 0 }, + { "wur.ae_cwrap", ICLASS_WUR_AE_CWRAP, + 0, + Opcode_wur_ae_cwrap_encode_fns, 0, 0 }, + { "ae_l8x4f.i", ICLASS_AE_L8X4F_I, + 0, + Opcode_ae_l8x4f_i_encode_fns, 1, Opcode_ae_l8x4f_i_funcUnit_uses }, + { "ae_l8x4f.ip", ICLASS_AE_L8X4F_IP, + 0, + Opcode_ae_l8x4f_ip_encode_fns, 1, Opcode_ae_l8x4f_ip_funcUnit_uses }, + { "ae_l16m.xc", ICLASS_AE_L16M_XC, + 0, + Opcode_ae_l16m_xc_encode_fns, 1, Opcode_ae_l16m_xc_funcUnit_uses }, + { "ae_l16m.xc1", ICLASS_AE_L16M_XC1, + 0, + Opcode_ae_l16m_xc1_encode_fns, 1, Opcode_ae_l16m_xc1_funcUnit_uses }, + { "ae_l16m.i", ICLASS_AE_L16M_I, + 0, + Opcode_ae_l16m_i_encode_fns, 1, Opcode_ae_l16m_i_funcUnit_uses }, + { "ae_l16m.iu", ICLASS_AE_L16M_IU, + 0, + Opcode_ae_l16m_iu_encode_fns, 1, Opcode_ae_l16m_iu_funcUnit_uses }, + { "ae_l16m.x", ICLASS_AE_L16M_X, + 0, + Opcode_ae_l16m_x_encode_fns, 1, Opcode_ae_l16m_x_funcUnit_uses }, + { "ae_l16m.xu", ICLASS_AE_L16M_XU, + 0, + Opcode_ae_l16m_xu_encode_fns, 1, Opcode_ae_l16m_xu_funcUnit_uses }, + { "ae_l16.xc", ICLASS_AE_L16_XC, + 0, + Opcode_ae_l16_xc_encode_fns, 1, Opcode_ae_l16_xc_funcUnit_uses }, + { "ae_l16.xc1", ICLASS_AE_L16_XC1, + 0, + Opcode_ae_l16_xc1_encode_fns, 1, Opcode_ae_l16_xc1_funcUnit_uses }, + { "ae_l16.i", ICLASS_AE_L16_I, + 0, + Opcode_ae_l16_i_encode_fns, 1, Opcode_ae_l16_i_funcUnit_uses }, + { "ae_l16.ip", ICLASS_AE_L16_IP, + 0, + Opcode_ae_l16_ip_encode_fns, 1, Opcode_ae_l16_ip_funcUnit_uses }, + { "ae_l16.x", ICLASS_AE_L16_X, + 0, + Opcode_ae_l16_x_encode_fns, 1, Opcode_ae_l16_x_funcUnit_uses }, + { "ae_l16.xp", ICLASS_AE_L16_XP, + 0, + Opcode_ae_l16_xp_encode_fns, 1, Opcode_ae_l16_xp_funcUnit_uses }, + { "ae_l32f24.xc", ICLASS_AE_L32F24_XC, + 0, + Opcode_ae_l32f24_xc_encode_fns, 1, Opcode_ae_l32f24_xc_funcUnit_uses }, + { "ae_l32f24.xc1", ICLASS_AE_L32F24_XC1, + 0, + Opcode_ae_l32f24_xc1_encode_fns, 1, Opcode_ae_l32f24_xc1_funcUnit_uses }, + { "ae_l32f24.i", ICLASS_AE_L32F24_I, + 0, + Opcode_ae_l32f24_i_encode_fns, 1, Opcode_ae_l32f24_i_funcUnit_uses }, + { "ae_l32f24.ip", ICLASS_AE_L32F24_IP, + 0, + Opcode_ae_l32f24_ip_encode_fns, 1, Opcode_ae_l32f24_ip_funcUnit_uses }, + { "ae_l32f24.x", ICLASS_AE_L32F24_X, + 0, + Opcode_ae_l32f24_x_encode_fns, 1, Opcode_ae_l32f24_x_funcUnit_uses }, + { "ae_l32f24.xp", ICLASS_AE_L32F24_XP, + 0, + Opcode_ae_l32f24_xp_encode_fns, 1, Opcode_ae_l32f24_xp_funcUnit_uses }, + { "ae_l32.xc", ICLASS_AE_L32_XC, + 0, + Opcode_ae_l32_xc_encode_fns, 1, Opcode_ae_l32_xc_funcUnit_uses }, + { "ae_l32.xc1", ICLASS_AE_L32_XC1, + 0, + Opcode_ae_l32_xc1_encode_fns, 1, Opcode_ae_l32_xc1_funcUnit_uses }, + { "ae_l32.i", ICLASS_AE_L32_I, + 0, + Opcode_ae_l32_i_encode_fns, 1, Opcode_ae_l32_i_funcUnit_uses }, + { "ae_l32.ip", ICLASS_AE_L32_IP, + 0, + Opcode_ae_l32_ip_encode_fns, 1, Opcode_ae_l32_ip_funcUnit_uses }, + { "ae_l32.x", ICLASS_AE_L32_X, + 0, + Opcode_ae_l32_x_encode_fns, 1, Opcode_ae_l32_x_funcUnit_uses }, + { "ae_l32.xp", ICLASS_AE_L32_XP, + 0, + Opcode_ae_l32_xp_encode_fns, 1, Opcode_ae_l32_xp_funcUnit_uses }, + { "ae_l32m.xc", ICLASS_AE_L32M_XC, + 0, + Opcode_ae_l32m_xc_encode_fns, 1, Opcode_ae_l32m_xc_funcUnit_uses }, + { "ae_l32m.i", ICLASS_AE_L32M_I, + 0, + Opcode_ae_l32m_i_encode_fns, 1, Opcode_ae_l32m_i_funcUnit_uses }, + { "ae_l32m.iu", ICLASS_AE_L32M_IU, + 0, + Opcode_ae_l32m_iu_encode_fns, 1, Opcode_ae_l32m_iu_funcUnit_uses }, + { "ae_l32m.x", ICLASS_AE_L32M_X, + 0, + Opcode_ae_l32m_x_encode_fns, 1, Opcode_ae_l32m_x_funcUnit_uses }, + { "ae_l32m.xu", ICLASS_AE_L32M_XU, + 0, + Opcode_ae_l32m_xu_encode_fns, 1, Opcode_ae_l32m_xu_funcUnit_uses }, + { "ae_l16x2m.xc", ICLASS_AE_L16X2M_XC, + 0, + Opcode_ae_l16x2m_xc_encode_fns, 1, Opcode_ae_l16x2m_xc_funcUnit_uses }, + { "ae_l16x2m.xc1", ICLASS_AE_L16X2M_XC1, + 0, + Opcode_ae_l16x2m_xc1_encode_fns, 1, Opcode_ae_l16x2m_xc1_funcUnit_uses }, + { "ae_l16x2m.i", ICLASS_AE_L16X2M_I, + 0, + Opcode_ae_l16x2m_i_encode_fns, 1, Opcode_ae_l16x2m_i_funcUnit_uses }, + { "ae_l16x2m.iu", ICLASS_AE_L16X2M_IU, + 0, + Opcode_ae_l16x2m_iu_encode_fns, 1, Opcode_ae_l16x2m_iu_funcUnit_uses }, + { "ae_l16x2m.x", ICLASS_AE_L16X2M_X, + 0, + Opcode_ae_l16x2m_x_encode_fns, 1, Opcode_ae_l16x2m_x_funcUnit_uses }, + { "ae_l16x2m.xu", ICLASS_AE_L16X2M_XU, + 0, + Opcode_ae_l16x2m_xu_encode_fns, 1, Opcode_ae_l16x2m_xu_funcUnit_uses }, + { "ae_l32x2f24.xc", ICLASS_AE_L32X2F24_XC, + 0, + Opcode_ae_l32x2f24_xc_encode_fns, 1, Opcode_ae_l32x2f24_xc_funcUnit_uses }, + { "ae_l32x2f24.xc1", ICLASS_AE_L32X2F24_XC1, + 0, + Opcode_ae_l32x2f24_xc1_encode_fns, 1, Opcode_ae_l32x2f24_xc1_funcUnit_uses }, + { "ae_l32x2f24.i", ICLASS_AE_L32X2F24_I, + 0, + Opcode_ae_l32x2f24_i_encode_fns, 1, Opcode_ae_l32x2f24_i_funcUnit_uses }, + { "ae_l32x2f24.ip", ICLASS_AE_L32X2F24_IP, + 0, + Opcode_ae_l32x2f24_ip_encode_fns, 1, Opcode_ae_l32x2f24_ip_funcUnit_uses }, + { "ae_l32x2f24.rip", ICLASS_AE_L32X2F24_RIP, + 0, + Opcode_ae_l32x2f24_rip_encode_fns, 1, Opcode_ae_l32x2f24_rip_funcUnit_uses }, + { "ae_l32x2f24.ri", ICLASS_AE_L32X2F24_RI, + 0, + Opcode_ae_l32x2f24_ri_encode_fns, 1, Opcode_ae_l32x2f24_ri_funcUnit_uses }, + { "ae_l32x2f24.ric", ICLASS_AE_L32X2F24_RIC, + 0, + Opcode_ae_l32x2f24_ric_encode_fns, 1, Opcode_ae_l32x2f24_ric_funcUnit_uses }, + { "ae_l32x2f24.ric1", ICLASS_AE_L32X2F24_RIC1, + 0, + Opcode_ae_l32x2f24_ric1_encode_fns, 1, Opcode_ae_l32x2f24_ric1_funcUnit_uses }, + { "ae_l32x2f24.x", ICLASS_AE_L32X2F24_X, + 0, + Opcode_ae_l32x2f24_x_encode_fns, 1, Opcode_ae_l32x2f24_x_funcUnit_uses }, + { "ae_l32x2f24.xp", ICLASS_AE_L32X2F24_XP, + 0, + Opcode_ae_l32x2f24_xp_encode_fns, 1, Opcode_ae_l32x2f24_xp_funcUnit_uses }, + { "ae_l32x2.xc", ICLASS_AE_L32X2_XC, + 0, + Opcode_ae_l32x2_xc_encode_fns, 1, Opcode_ae_l32x2_xc_funcUnit_uses }, + { "ae_l32x2.xc1", ICLASS_AE_L32X2_XC1, + 0, + Opcode_ae_l32x2_xc1_encode_fns, 1, Opcode_ae_l32x2_xc1_funcUnit_uses }, + { "ae_l32x2.i", ICLASS_AE_L32X2_I, + 0, + Opcode_ae_l32x2_i_encode_fns, 1, Opcode_ae_l32x2_i_funcUnit_uses }, + { "ae_l32x2.ip", ICLASS_AE_L32X2_IP, + 0, + Opcode_ae_l32x2_ip_encode_fns, 1, Opcode_ae_l32x2_ip_funcUnit_uses }, + { "ae_l32x2.ric", ICLASS_AE_L32X2_RIC, + 0, + Opcode_ae_l32x2_ric_encode_fns, 1, Opcode_ae_l32x2_ric_funcUnit_uses }, + { "ae_l32x2.ric1", ICLASS_AE_L32X2_RIC1, + 0, + Opcode_ae_l32x2_ric1_encode_fns, 1, Opcode_ae_l32x2_ric1_funcUnit_uses }, + { "ae_l32x2.x", ICLASS_AE_L32X2_X, + 0, + Opcode_ae_l32x2_x_encode_fns, 1, Opcode_ae_l32x2_x_funcUnit_uses }, + { "ae_l32x2.xp", ICLASS_AE_L32X2_XP, + 0, + Opcode_ae_l32x2_xp_encode_fns, 1, Opcode_ae_l32x2_xp_funcUnit_uses }, + { "ae_l16x4.xc", ICLASS_AE_L16X4_XC, + 0, + Opcode_ae_l16x4_xc_encode_fns, 1, Opcode_ae_l16x4_xc_funcUnit_uses }, + { "ae_l16x4.xc1", ICLASS_AE_L16X4_XC1, + 0, + Opcode_ae_l16x4_xc1_encode_fns, 1, Opcode_ae_l16x4_xc1_funcUnit_uses }, + { "ae_l16x4.i", ICLASS_AE_L16X4_I, + 0, + Opcode_ae_l16x4_i_encode_fns, 1, Opcode_ae_l16x4_i_funcUnit_uses }, + { "ae_l16x4.ip", ICLASS_AE_L16X4_IP, + 0, + Opcode_ae_l16x4_ip_encode_fns, 1, Opcode_ae_l16x4_ip_funcUnit_uses }, + { "ae_l16x4.x", ICLASS_AE_L16X4_X, + 0, + Opcode_ae_l16x4_x_encode_fns, 1, Opcode_ae_l16x4_x_funcUnit_uses }, + { "ae_l16x4.xp", ICLASS_AE_L16X4_XP, + 0, + Opcode_ae_l16x4_xp_encode_fns, 1, Opcode_ae_l16x4_xp_funcUnit_uses }, + { "ae_l64.xc", ICLASS_AE_L64_XC, + 0, + Opcode_ae_l64_xc_encode_fns, 1, Opcode_ae_l64_xc_funcUnit_uses }, + { "ae_l64.xc1", ICLASS_AE_L64_XC1, + 0, + Opcode_ae_l64_xc1_encode_fns, 1, Opcode_ae_l64_xc1_funcUnit_uses }, + { "ae_l64.i", ICLASS_AE_L64_I, + 0, + Opcode_ae_l64_i_encode_fns, 1, Opcode_ae_l64_i_funcUnit_uses }, + { "ae_l64.ip", ICLASS_AE_L64_IP, + 0, + Opcode_ae_l64_ip_encode_fns, 1, Opcode_ae_l64_ip_funcUnit_uses }, + { "ae_l64.x", ICLASS_AE_L64_X, + 0, + Opcode_ae_l64_x_encode_fns, 1, Opcode_ae_l64_x_funcUnit_uses }, + { "ae_l64.xp", ICLASS_AE_L64_XP, + 0, + Opcode_ae_l64_xp_encode_fns, 1, Opcode_ae_l64_xp_funcUnit_uses }, + { "ae_s16x2m.xc", ICLASS_AE_S16X2M_XC, + 0, + Opcode_ae_s16x2m_xc_encode_fns, 1, Opcode_ae_s16x2m_xc_funcUnit_uses }, + { "ae_s16x2m.xc1", ICLASS_AE_S16X2M_XC1, + 0, + Opcode_ae_s16x2m_xc1_encode_fns, 1, Opcode_ae_s16x2m_xc1_funcUnit_uses }, + { "ae_s16x2m.i", ICLASS_AE_S16X2M_I, + 0, + Opcode_ae_s16x2m_i_encode_fns, 1, Opcode_ae_s16x2m_i_funcUnit_uses }, + { "ae_s16x2m.iu", ICLASS_AE_S16X2M_IU, + 0, + Opcode_ae_s16x2m_iu_encode_fns, 1, Opcode_ae_s16x2m_iu_funcUnit_uses }, + { "ae_s16x2m.x", ICLASS_AE_S16X2M_X, + 0, + Opcode_ae_s16x2m_x_encode_fns, 1, Opcode_ae_s16x2m_x_funcUnit_uses }, + { "ae_s16x2m.xu", ICLASS_AE_S16X2M_XU, + 0, + Opcode_ae_s16x2m_xu_encode_fns, 1, Opcode_ae_s16x2m_xu_funcUnit_uses }, + { "ae_s32x2f24.xc", ICLASS_AE_S32X2F24_XC, + 0, + Opcode_ae_s32x2f24_xc_encode_fns, 1, Opcode_ae_s32x2f24_xc_funcUnit_uses }, + { "ae_s32x2f24.xc1", ICLASS_AE_S32X2F24_XC1, + 0, + Opcode_ae_s32x2f24_xc1_encode_fns, 1, Opcode_ae_s32x2f24_xc1_funcUnit_uses }, + { "ae_s32x2f24.i", ICLASS_AE_S32X2F24_I, + 0, + Opcode_ae_s32x2f24_i_encode_fns, 1, Opcode_ae_s32x2f24_i_funcUnit_uses }, + { "ae_s32x2f24.ip", ICLASS_AE_S32X2F24_IP, + 0, + Opcode_ae_s32x2f24_ip_encode_fns, 1, Opcode_ae_s32x2f24_ip_funcUnit_uses }, + { "ae_s32x2f24.rip", ICLASS_AE_S32X2F24_RIP, + 0, + Opcode_ae_s32x2f24_rip_encode_fns, 1, Opcode_ae_s32x2f24_rip_funcUnit_uses }, + { "ae_s32x2f24.ric", ICLASS_AE_S32X2F24_RIC, + 0, + Opcode_ae_s32x2f24_ric_encode_fns, 1, Opcode_ae_s32x2f24_ric_funcUnit_uses }, + { "ae_s32x2f24.ric1", ICLASS_AE_S32X2F24_RIC1, + 0, + Opcode_ae_s32x2f24_ric1_encode_fns, 1, Opcode_ae_s32x2f24_ric1_funcUnit_uses }, + { "ae_s32x2f24.x", ICLASS_AE_S32X2F24_X, + 0, + Opcode_ae_s32x2f24_x_encode_fns, 1, Opcode_ae_s32x2f24_x_funcUnit_uses }, + { "ae_s32x2f24.xp", ICLASS_AE_S32X2F24_XP, + 0, + Opcode_ae_s32x2f24_xp_encode_fns, 1, Opcode_ae_s32x2f24_xp_funcUnit_uses }, + { "ae_s32x2.xc", ICLASS_AE_S32X2_XC, + 0, + Opcode_ae_s32x2_xc_encode_fns, 1, Opcode_ae_s32x2_xc_funcUnit_uses }, + { "ae_s32x2.xc1", ICLASS_AE_S32X2_XC1, + 0, + Opcode_ae_s32x2_xc1_encode_fns, 1, Opcode_ae_s32x2_xc1_funcUnit_uses }, + { "ae_s32x2.i", ICLASS_AE_S32X2_I, + 0, + Opcode_ae_s32x2_i_encode_fns, 1, Opcode_ae_s32x2_i_funcUnit_uses }, + { "ae_s32x2.ip", ICLASS_AE_S32X2_IP, + 0, + Opcode_ae_s32x2_ip_encode_fns, 1, Opcode_ae_s32x2_ip_funcUnit_uses }, + { "ae_s32x2.ric", ICLASS_AE_S32X2_RIC, + 0, + Opcode_ae_s32x2_ric_encode_fns, 1, Opcode_ae_s32x2_ric_funcUnit_uses }, + { "ae_s32x2.ric1", ICLASS_AE_S32X2_RIC1, + 0, + Opcode_ae_s32x2_ric1_encode_fns, 1, Opcode_ae_s32x2_ric1_funcUnit_uses }, + { "ae_s32x2.x", ICLASS_AE_S32X2_X, + 0, + Opcode_ae_s32x2_x_encode_fns, 1, Opcode_ae_s32x2_x_funcUnit_uses }, + { "ae_s32x2.xp", ICLASS_AE_S32X2_XP, + 0, + Opcode_ae_s32x2_xp_encode_fns, 1, Opcode_ae_s32x2_xp_funcUnit_uses }, + { "ae_s32x2rng.i", ICLASS_AE_S32X2RNG_I, + 0, + Opcode_ae_s32x2rng_i_encode_fns, 1, Opcode_ae_s32x2rng_i_funcUnit_uses }, + { "ae_s32x2rng.ip", ICLASS_AE_S32X2RNG_IP, + 0, + Opcode_ae_s32x2rng_ip_encode_fns, 1, Opcode_ae_s32x2rng_ip_funcUnit_uses }, + { "ae_s32x2rng.x", ICLASS_AE_S32X2RNG_X, + 0, + Opcode_ae_s32x2rng_x_encode_fns, 1, Opcode_ae_s32x2rng_x_funcUnit_uses }, + { "ae_s32x2rng.xp", ICLASS_AE_S32X2RNG_XP, + 0, + Opcode_ae_s32x2rng_xp_encode_fns, 1, Opcode_ae_s32x2rng_xp_funcUnit_uses }, + { "ae_s16x4.xc", ICLASS_AE_S16X4_XC, + 0, + Opcode_ae_s16x4_xc_encode_fns, 1, Opcode_ae_s16x4_xc_funcUnit_uses }, + { "ae_s16x4.xc1", ICLASS_AE_S16X4_XC1, + 0, + Opcode_ae_s16x4_xc1_encode_fns, 1, Opcode_ae_s16x4_xc1_funcUnit_uses }, + { "ae_s16x4.i", ICLASS_AE_S16X4_I, + 0, + Opcode_ae_s16x4_i_encode_fns, 1, Opcode_ae_s16x4_i_funcUnit_uses }, + { "ae_s16x4.ip", ICLASS_AE_S16X4_IP, + 0, + Opcode_ae_s16x4_ip_encode_fns, 1, Opcode_ae_s16x4_ip_funcUnit_uses }, + { "ae_s16x4.x", ICLASS_AE_S16X4_X, + 0, + Opcode_ae_s16x4_x_encode_fns, 1, Opcode_ae_s16x4_x_funcUnit_uses }, + { "ae_s16x4.xp", ICLASS_AE_S16X4_XP, + 0, + Opcode_ae_s16x4_xp_encode_fns, 1, Opcode_ae_s16x4_xp_funcUnit_uses }, + { "ae_s16m.l.xc", ICLASS_AE_S16M_L_XC, + 0, + Opcode_ae_s16m_l_xc_encode_fns, 1, Opcode_ae_s16m_l_xc_funcUnit_uses }, + { "ae_s16m.l.xc1", ICLASS_AE_S16M_L_XC1, + 0, + Opcode_ae_s16m_l_xc1_encode_fns, 1, Opcode_ae_s16m_l_xc1_funcUnit_uses }, + { "ae_s16m.l.i", ICLASS_AE_S16M_L_I, + 0, + Opcode_ae_s16m_l_i_encode_fns, 1, Opcode_ae_s16m_l_i_funcUnit_uses }, + { "ae_s16m.l.iu", ICLASS_AE_S16M_L_IU, + 0, + Opcode_ae_s16m_l_iu_encode_fns, 1, Opcode_ae_s16m_l_iu_funcUnit_uses }, + { "ae_s16m.l.x", ICLASS_AE_S16M_L_X, + 0, + Opcode_ae_s16m_l_x_encode_fns, 1, Opcode_ae_s16m_l_x_funcUnit_uses }, + { "ae_s16m.l.xu", ICLASS_AE_S16M_L_XU, + 0, + Opcode_ae_s16m_l_xu_encode_fns, 1, Opcode_ae_s16m_l_xu_funcUnit_uses }, + { "ae_s32f24.l.xc", ICLASS_AE_S32F24_L_XC, + 0, + Opcode_ae_s32f24_l_xc_encode_fns, 1, Opcode_ae_s32f24_l_xc_funcUnit_uses }, + { "ae_s32f24.l.xc1", ICLASS_AE_S32F24_L_XC1, + 0, + Opcode_ae_s32f24_l_xc1_encode_fns, 1, Opcode_ae_s32f24_l_xc1_funcUnit_uses }, + { "ae_s32f24.l.i", ICLASS_AE_S32F24_L_I, + 0, + Opcode_ae_s32f24_l_i_encode_fns, 1, Opcode_ae_s32f24_l_i_funcUnit_uses }, + { "ae_s32f24.l.ip", ICLASS_AE_S32F24_L_IP, + 0, + Opcode_ae_s32f24_l_ip_encode_fns, 1, Opcode_ae_s32f24_l_ip_funcUnit_uses }, + { "ae_s32f24.l.x", ICLASS_AE_S32F24_L_X, + 0, + Opcode_ae_s32f24_l_x_encode_fns, 1, Opcode_ae_s32f24_l_x_funcUnit_uses }, + { "ae_s32f24.l.xp", ICLASS_AE_S32F24_L_XP, + 0, + Opcode_ae_s32f24_l_xp_encode_fns, 1, Opcode_ae_s32f24_l_xp_funcUnit_uses }, + { "ae_s32.l.xc", ICLASS_AE_S32_L_XC, + 0, + Opcode_ae_s32_l_xc_encode_fns, 1, Opcode_ae_s32_l_xc_funcUnit_uses }, + { "ae_s32.l.xc1", ICLASS_AE_S32_L_XC1, + 0, + Opcode_ae_s32_l_xc1_encode_fns, 1, Opcode_ae_s32_l_xc1_funcUnit_uses }, + { "ae_s32.l.i", ICLASS_AE_S32_L_I, + 0, + Opcode_ae_s32_l_i_encode_fns, 1, Opcode_ae_s32_l_i_funcUnit_uses }, + { "ae_s32.l.ip", ICLASS_AE_S32_L_IP, + 0, + Opcode_ae_s32_l_ip_encode_fns, 1, Opcode_ae_s32_l_ip_funcUnit_uses }, + { "ae_s32.l.x", ICLASS_AE_S32_L_X, + 0, + Opcode_ae_s32_l_x_encode_fns, 1, Opcode_ae_s32_l_x_funcUnit_uses }, + { "ae_s32.l.xp", ICLASS_AE_S32_L_XP, + 0, + Opcode_ae_s32_l_xp_encode_fns, 1, Opcode_ae_s32_l_xp_funcUnit_uses }, + { "ae_s16.0.xc", ICLASS_AE_S16_0_XC, + 0, + Opcode_ae_s16_0_xc_encode_fns, 1, Opcode_ae_s16_0_xc_funcUnit_uses }, + { "ae_s16.0.xc1", ICLASS_AE_S16_0_XC1, + 0, + Opcode_ae_s16_0_xc1_encode_fns, 1, Opcode_ae_s16_0_xc1_funcUnit_uses }, + { "ae_s16.0.i", ICLASS_AE_S16_0_I, + 0, + Opcode_ae_s16_0_i_encode_fns, 1, Opcode_ae_s16_0_i_funcUnit_uses }, + { "ae_s16.0.ip", ICLASS_AE_S16_0_IP, + 0, + Opcode_ae_s16_0_ip_encode_fns, 1, Opcode_ae_s16_0_ip_funcUnit_uses }, + { "ae_s16.0.x", ICLASS_AE_S16_0_X, + 0, + Opcode_ae_s16_0_x_encode_fns, 1, Opcode_ae_s16_0_x_funcUnit_uses }, + { "ae_s16.0.xp", ICLASS_AE_S16_0_XP, + 0, + Opcode_ae_s16_0_xp_encode_fns, 1, Opcode_ae_s16_0_xp_funcUnit_uses }, + { "ae_s64.xc", ICLASS_AE_S64_XC, + 0, + Opcode_ae_s64_xc_encode_fns, 1, Opcode_ae_s64_xc_funcUnit_uses }, + { "ae_s64.xc1", ICLASS_AE_S64_XC1, + 0, + Opcode_ae_s64_xc1_encode_fns, 1, Opcode_ae_s64_xc1_funcUnit_uses }, + { "ae_s64.i", ICLASS_AE_S64_I, + 0, + Opcode_ae_s64_i_encode_fns, 1, Opcode_ae_s64_i_funcUnit_uses }, + { "ae_s64.ip", ICLASS_AE_S64_IP, + 0, + Opcode_ae_s64_ip_encode_fns, 1, Opcode_ae_s64_ip_funcUnit_uses }, + { "ae_s64.x", ICLASS_AE_S64_X, + 0, + Opcode_ae_s64_x_encode_fns, 1, Opcode_ae_s64_x_funcUnit_uses }, + { "ae_s64.xp", ICLASS_AE_S64_XP, + 0, + Opcode_ae_s64_xp_encode_fns, 1, Opcode_ae_s64_xp_funcUnit_uses }, + { "ae_s32m.xc", ICLASS_AE_S32M_XC, + 0, + Opcode_ae_s32m_xc_encode_fns, 1, Opcode_ae_s32m_xc_funcUnit_uses }, + { "ae_s32m.i", ICLASS_AE_S32M_I, + 0, + Opcode_ae_s32m_i_encode_fns, 1, Opcode_ae_s32m_i_funcUnit_uses }, + { "ae_s32m.iu", ICLASS_AE_S32M_IU, + 0, + Opcode_ae_s32m_iu_encode_fns, 1, Opcode_ae_s32m_iu_funcUnit_uses }, + { "ae_s32m.x", ICLASS_AE_S32M_X, + 0, + Opcode_ae_s32m_x_encode_fns, 1, Opcode_ae_s32m_x_funcUnit_uses }, + { "ae_s32m.xu", ICLASS_AE_S32M_XU, + 0, + Opcode_ae_s32m_xu_encode_fns, 1, Opcode_ae_s32m_xu_funcUnit_uses }, + { "ae_zalign64", ICLASS_AE_ZALIGN64, + 0, + Opcode_ae_zalign64_encode_fns, 0, 0 }, + { "ae_lalign64.i", ICLASS_AE_LALIGN64_I, + 0, + Opcode_ae_lalign64_i_encode_fns, 1, Opcode_ae_lalign64_i_funcUnit_uses }, + { "ae_salign64.i", ICLASS_AE_SALIGN64_I, + 0, + Opcode_ae_salign64_i_encode_fns, 1, Opcode_ae_salign64_i_funcUnit_uses }, + { "ae_movalign", ICLASS_AE_MOVALIGN, + 0, + Opcode_ae_movalign_encode_fns, 0, 0 }, + { "ae_la64.pp", ICLASS_AE_LA64_PP, + 0, + Opcode_ae_la64_pp_encode_fns, 1, Opcode_ae_la64_pp_funcUnit_uses }, + { "ae_la24pos.pc", ICLASS_AE_LA24POS_PC, + 0, + Opcode_ae_la24pos_pc_encode_fns, 1, Opcode_ae_la24pos_pc_funcUnit_uses }, + { "ae_la24x2pos.pc", ICLASS_AE_LA24X2POS_PC, + 0, + Opcode_ae_la24x2pos_pc_encode_fns, 1, Opcode_ae_la24x2pos_pc_funcUnit_uses }, + { "ae_la32x2pos.pc", ICLASS_AE_LA32X2POS_PC, + 0, + Opcode_ae_la32x2pos_pc_encode_fns, 1, Opcode_ae_la32x2pos_pc_funcUnit_uses }, + { "ae_la16x4pos.pc", ICLASS_AE_LA16X4POS_PC, + 0, + Opcode_ae_la16x4pos_pc_encode_fns, 1, Opcode_ae_la16x4pos_pc_funcUnit_uses }, + { "ae_la24neg.pc", ICLASS_AE_LA24NEG_PC, + 0, + Opcode_ae_la24neg_pc_encode_fns, 1, Opcode_ae_la24neg_pc_funcUnit_uses }, + { "ae_la24x2neg.pc", ICLASS_AE_LA24X2NEG_PC, + 0, + Opcode_ae_la24x2neg_pc_encode_fns, 1, Opcode_ae_la24x2neg_pc_funcUnit_uses }, + { "ae_la32x2neg.pc", ICLASS_AE_LA32X2NEG_PC, + 0, + Opcode_ae_la32x2neg_pc_encode_fns, 1, Opcode_ae_la32x2neg_pc_funcUnit_uses }, + { "ae_la16x4neg.pc", ICLASS_AE_LA16X4NEG_PC, + 0, + Opcode_ae_la16x4neg_pc_encode_fns, 1, Opcode_ae_la16x4neg_pc_funcUnit_uses }, + { "ae_la24pos.pc1", ICLASS_AE_LA24POS_PC1, + 0, + Opcode_ae_la24pos_pc1_encode_fns, 1, Opcode_ae_la24pos_pc1_funcUnit_uses }, + { "ae_la24x2pos.pc1", ICLASS_AE_LA24X2POS_PC1, + 0, + Opcode_ae_la24x2pos_pc1_encode_fns, 1, Opcode_ae_la24x2pos_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc1", ICLASS_AE_LA32X2POS_PC1, + 0, + Opcode_ae_la32x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2pos_pc1_funcUnit_uses }, + { "ae_la16x4pos.pc1", ICLASS_AE_LA16X4POS_PC1, + 0, + Opcode_ae_la16x4pos_pc1_encode_fns, 1, Opcode_ae_la16x4pos_pc1_funcUnit_uses }, + { "ae_la24neg.pc1", ICLASS_AE_LA24NEG_PC1, + 0, + Opcode_ae_la24neg_pc1_encode_fns, 1, Opcode_ae_la24neg_pc1_funcUnit_uses }, + { "ae_la24x2neg.pc1", ICLASS_AE_LA24X2NEG_PC1, + 0, + Opcode_ae_la24x2neg_pc1_encode_fns, 1, Opcode_ae_la24x2neg_pc1_funcUnit_uses }, + { "ae_la32x2neg.pc1", ICLASS_AE_LA32X2NEG_PC1, + 0, + Opcode_ae_la32x2neg_pc1_encode_fns, 1, Opcode_ae_la32x2neg_pc1_funcUnit_uses }, + { "ae_la16x4neg.pc1", ICLASS_AE_LA16X4NEG_PC1, + 0, + Opcode_ae_la16x4neg_pc1_encode_fns, 1, Opcode_ae_la16x4neg_pc1_funcUnit_uses }, + { "ae_sa64pos.fp", ICLASS_AE_SA64POS_FP, + 0, + Opcode_ae_sa64pos_fp_encode_fns, 1, Opcode_ae_sa64pos_fp_funcUnit_uses }, + { "ae_sa64neg.fp", ICLASS_AE_SA64NEG_FP, + 0, + Opcode_ae_sa64neg_fp_encode_fns, 1, Opcode_ae_sa64neg_fp_funcUnit_uses }, + { "ae_la32x2.ic", ICLASS_AE_LA32X2_IC, + 0, + Opcode_ae_la32x2_ic_encode_fns, 1, Opcode_ae_la32x2_ic_funcUnit_uses }, + { "ae_la32x2.ic1", ICLASS_AE_LA32X2_IC1, + 0, + Opcode_ae_la32x2_ic1_encode_fns, 1, Opcode_ae_la32x2_ic1_funcUnit_uses }, + { "ae_la32x2.ip", ICLASS_AE_LA32X2_IP, + 0, + Opcode_ae_la32x2_ip_encode_fns, 1, Opcode_ae_la32x2_ip_funcUnit_uses }, + { "ae_la32x2.rip", ICLASS_AE_LA32X2_RIP, + 0, + Opcode_ae_la32x2_rip_encode_fns, 1, Opcode_ae_la32x2_rip_funcUnit_uses }, + { "ae_la32x2.ric", ICLASS_AE_LA32X2_RIC, + 0, + Opcode_ae_la32x2_ric_encode_fns, 1, Opcode_ae_la32x2_ric_funcUnit_uses }, + { "ae_la32x2.ric1", ICLASS_AE_LA32X2_RIC1, + 0, + Opcode_ae_la32x2_ric1_encode_fns, 1, Opcode_ae_la32x2_ric1_funcUnit_uses }, + { "ae_la16x4.ic", ICLASS_AE_LA16X4_IC, + 0, + Opcode_ae_la16x4_ic_encode_fns, 1, Opcode_ae_la16x4_ic_funcUnit_uses }, + { "ae_la16x4.ic1", ICLASS_AE_LA16X4_IC1, + 0, + Opcode_ae_la16x4_ic1_encode_fns, 1, Opcode_ae_la16x4_ic1_funcUnit_uses }, + { "ae_la16x4.ip", ICLASS_AE_LA16X4_IP, + 0, + Opcode_ae_la16x4_ip_encode_fns, 1, Opcode_ae_la16x4_ip_funcUnit_uses }, + { "ae_la16x4.rip", ICLASS_AE_LA16X4_RIP, + 0, + Opcode_ae_la16x4_rip_encode_fns, 1, Opcode_ae_la16x4_rip_funcUnit_uses }, + { "ae_la16x4.ric", ICLASS_AE_LA16X4_RIC, + 0, + Opcode_ae_la16x4_ric_encode_fns, 1, Opcode_ae_la16x4_ric_funcUnit_uses }, + { "ae_la16x4.ric1", ICLASS_AE_LA16X4_RIC1, + 0, + Opcode_ae_la16x4_ric1_encode_fns, 1, Opcode_ae_la16x4_ric1_funcUnit_uses }, + { "ae_la32x2f24.ic", ICLASS_AE_LA32X2F24_IC, + 0, + Opcode_ae_la32x2f24_ic_encode_fns, 1, Opcode_ae_la32x2f24_ic_funcUnit_uses }, + { "ae_la32x2f24.ic1", ICLASS_AE_LA32X2F24_IC1, + 0, + Opcode_ae_la32x2f24_ic1_encode_fns, 1, Opcode_ae_la32x2f24_ic1_funcUnit_uses }, + { "ae_la32x2f24.ip", ICLASS_AE_LA32X2F24_IP, + 0, + Opcode_ae_la32x2f24_ip_encode_fns, 1, Opcode_ae_la32x2f24_ip_funcUnit_uses }, + { "ae_la32x2f24.rip", ICLASS_AE_LA32X2F24_RIP, + 0, + Opcode_ae_la32x2f24_rip_encode_fns, 1, Opcode_ae_la32x2f24_rip_funcUnit_uses }, + { "ae_la32x2f24.ric", ICLASS_AE_LA32X2F24_RIC, + 0, + Opcode_ae_la32x2f24_ric_encode_fns, 1, Opcode_ae_la32x2f24_ric_funcUnit_uses }, + { "ae_la32x2f24.ric1", ICLASS_AE_LA32X2F24_RIC1, + 0, + Opcode_ae_la32x2f24_ric1_encode_fns, 1, Opcode_ae_la32x2f24_ric1_funcUnit_uses }, + { "ae_la24.ic", ICLASS_AE_LA24_IC, + 0, + Opcode_ae_la24_ic_encode_fns, 1, Opcode_ae_la24_ic_funcUnit_uses }, + { "ae_la24.ic1", ICLASS_AE_LA24_IC1, + 0, + Opcode_ae_la24_ic1_encode_fns, 1, Opcode_ae_la24_ic1_funcUnit_uses }, + { "ae_la24.ip", ICLASS_AE_LA24_IP, + 0, + Opcode_ae_la24_ip_encode_fns, 1, Opcode_ae_la24_ip_funcUnit_uses }, + { "ae_la24.rip", ICLASS_AE_LA24_RIP, + 0, + Opcode_ae_la24_rip_encode_fns, 1, Opcode_ae_la24_rip_funcUnit_uses }, + { "ae_la24.ric", ICLASS_AE_LA24_RIC, + 0, + Opcode_ae_la24_ric_encode_fns, 1, Opcode_ae_la24_ric_funcUnit_uses }, + { "ae_la24.ric1", ICLASS_AE_LA24_RIC1, + 0, + Opcode_ae_la24_ric1_encode_fns, 1, Opcode_ae_la24_ric1_funcUnit_uses }, + { "ae_la24x2.ic", ICLASS_AE_LA24X2_IC, + 0, + Opcode_ae_la24x2_ic_encode_fns, 1, Opcode_ae_la24x2_ic_funcUnit_uses }, + { "ae_la24x2.ic1", ICLASS_AE_LA24X2_IC1, + 0, + Opcode_ae_la24x2_ic1_encode_fns, 1, Opcode_ae_la24x2_ic1_funcUnit_uses }, + { "ae_la24x2.ip", ICLASS_AE_LA24X2_IP, + 0, + Opcode_ae_la24x2_ip_encode_fns, 1, Opcode_ae_la24x2_ip_funcUnit_uses }, + { "ae_la24x2.rip", ICLASS_AE_LA24X2_RIP, + 0, + Opcode_ae_la24x2_rip_encode_fns, 1, Opcode_ae_la24x2_rip_funcUnit_uses }, + { "ae_la24x2.ric", ICLASS_AE_LA24X2_RIC, + 0, + Opcode_ae_la24x2_ric_encode_fns, 1, Opcode_ae_la24x2_ric_funcUnit_uses }, + { "ae_la24x2.ric1", ICLASS_AE_LA24X2_RIC1, + 0, + Opcode_ae_la24x2_ric1_encode_fns, 1, Opcode_ae_la24x2_ric1_funcUnit_uses }, + { "ae_sa32x2.ic", ICLASS_AE_SA32X2_IC, + 0, + Opcode_ae_sa32x2_ic_encode_fns, 1, Opcode_ae_sa32x2_ic_funcUnit_uses }, + { "ae_sa32x2.ic1", ICLASS_AE_SA32X2_IC1, + 0, + Opcode_ae_sa32x2_ic1_encode_fns, 1, Opcode_ae_sa32x2_ic1_funcUnit_uses }, + { "ae_sa32x2.ip", ICLASS_AE_SA32X2_IP, + 0, + Opcode_ae_sa32x2_ip_encode_fns, 1, Opcode_ae_sa32x2_ip_funcUnit_uses }, + { "ae_sa32x2.rip", ICLASS_AE_SA32X2_RIP, + 0, + Opcode_ae_sa32x2_rip_encode_fns, 1, Opcode_ae_sa32x2_rip_funcUnit_uses }, + { "ae_sa32x2.ric", ICLASS_AE_SA32X2_RIC, + 0, + Opcode_ae_sa32x2_ric_encode_fns, 1, Opcode_ae_sa32x2_ric_funcUnit_uses }, + { "ae_sa32x2.ric1", ICLASS_AE_SA32X2_RIC1, + 0, + Opcode_ae_sa32x2_ric1_encode_fns, 1, Opcode_ae_sa32x2_ric1_funcUnit_uses }, + { "ae_sa16x4.ic", ICLASS_AE_SA16X4_IC, + 0, + Opcode_ae_sa16x4_ic_encode_fns, 1, Opcode_ae_sa16x4_ic_funcUnit_uses }, + { "ae_sa16x4.ic1", ICLASS_AE_SA16X4_IC1, + 0, + Opcode_ae_sa16x4_ic1_encode_fns, 1, Opcode_ae_sa16x4_ic1_funcUnit_uses }, + { "ae_sa16x4.ip", ICLASS_AE_SA16X4_IP, + 0, + Opcode_ae_sa16x4_ip_encode_fns, 1, Opcode_ae_sa16x4_ip_funcUnit_uses }, + { "ae_sa16x4.rip", ICLASS_AE_SA16X4_RIP, + 0, + Opcode_ae_sa16x4_rip_encode_fns, 1, Opcode_ae_sa16x4_rip_funcUnit_uses }, + { "ae_sa16x4.ric", ICLASS_AE_SA16X4_RIC, + 0, + Opcode_ae_sa16x4_ric_encode_fns, 1, Opcode_ae_sa16x4_ric_funcUnit_uses }, + { "ae_sa16x4.ric1", ICLASS_AE_SA16X4_RIC1, + 0, + Opcode_ae_sa16x4_ric1_encode_fns, 1, Opcode_ae_sa16x4_ric1_funcUnit_uses }, + { "ae_sa32x2f24.ic", ICLASS_AE_SA32X2F24_IC, + 0, + Opcode_ae_sa32x2f24_ic_encode_fns, 1, Opcode_ae_sa32x2f24_ic_funcUnit_uses }, + { "ae_sa32x2f24.ic1", ICLASS_AE_SA32X2F24_IC1, + 0, + Opcode_ae_sa32x2f24_ic1_encode_fns, 1, Opcode_ae_sa32x2f24_ic1_funcUnit_uses }, + { "ae_sa32x2f24.ip", ICLASS_AE_SA32X2F24_IP, + 0, + Opcode_ae_sa32x2f24_ip_encode_fns, 1, Opcode_ae_sa32x2f24_ip_funcUnit_uses }, + { "ae_sa32x2f24.rip", ICLASS_AE_SA32X2F24_RIP, + 0, + Opcode_ae_sa32x2f24_rip_encode_fns, 1, Opcode_ae_sa32x2f24_rip_funcUnit_uses }, + { "ae_sa32x2f24.ric", ICLASS_AE_SA32X2F24_RIC, + 0, + Opcode_ae_sa32x2f24_ric_encode_fns, 1, Opcode_ae_sa32x2f24_ric_funcUnit_uses }, + { "ae_sa32x2f24.ric1", ICLASS_AE_SA32X2F24_RIC1, + 0, + Opcode_ae_sa32x2f24_ric1_encode_fns, 1, Opcode_ae_sa32x2f24_ric1_funcUnit_uses }, + { "ae_sa24.l.ic", ICLASS_AE_SA24_L_IC, + 0, + Opcode_ae_sa24_l_ic_encode_fns, 1, Opcode_ae_sa24_l_ic_funcUnit_uses }, + { "ae_sa24.l.ic1", ICLASS_AE_SA24_L_IC1, + 0, + Opcode_ae_sa24_l_ic1_encode_fns, 1, Opcode_ae_sa24_l_ic1_funcUnit_uses }, + { "ae_sa24.l.ip", ICLASS_AE_SA24_L_IP, + 0, + Opcode_ae_sa24_l_ip_encode_fns, 1, Opcode_ae_sa24_l_ip_funcUnit_uses }, + { "ae_sa24.l.rip", ICLASS_AE_SA24_L_RIP, + 0, + Opcode_ae_sa24_l_rip_encode_fns, 1, Opcode_ae_sa24_l_rip_funcUnit_uses }, + { "ae_sa24.l.ric", ICLASS_AE_SA24_L_RIC, + 0, + Opcode_ae_sa24_l_ric_encode_fns, 1, Opcode_ae_sa24_l_ric_funcUnit_uses }, + { "ae_sa24.l.ric1", ICLASS_AE_SA24_L_RIC1, + 0, + Opcode_ae_sa24_l_ric1_encode_fns, 1, Opcode_ae_sa24_l_ric1_funcUnit_uses }, + { "ae_sa24x2.ic", ICLASS_AE_SA24X2_IC, + 0, + Opcode_ae_sa24x2_ic_encode_fns, 1, Opcode_ae_sa24x2_ic_funcUnit_uses }, + { "ae_sa24x2.ic1", ICLASS_AE_SA24X2_IC1, + 0, + Opcode_ae_sa24x2_ic1_encode_fns, 1, Opcode_ae_sa24x2_ic1_funcUnit_uses }, + { "ae_sa24x2.ip", ICLASS_AE_SA24X2_IP, + 0, + Opcode_ae_sa24x2_ip_encode_fns, 1, Opcode_ae_sa24x2_ip_funcUnit_uses }, + { "ae_sa24x2.rip", ICLASS_AE_SA24X2_RIP, + 0, + Opcode_ae_sa24x2_rip_encode_fns, 1, Opcode_ae_sa24x2_rip_funcUnit_uses }, + { "ae_sa24x2.ric", ICLASS_AE_SA24X2_RIC, + 0, + Opcode_ae_sa24x2_ric_encode_fns, 1, Opcode_ae_sa24x2_ric_funcUnit_uses }, + { "ae_sa24x2.ric1", ICLASS_AE_SA24X2_RIC1, + 0, + Opcode_ae_sa24x2_ric1_encode_fns, 1, Opcode_ae_sa24x2_ric1_funcUnit_uses }, + { "ae_addicirc", ICLASS_AE_ADDICIRC, + 0, + Opcode_ae_addicirc_encode_fns, 0, 0 }, + { "ae_addcirc.xc1", ICLASS_AE_ADDCIRC_XC1, + 0, + Opcode_ae_addcirc_xc1_encode_fns, 0, 0 }, + { "ae_addcirc.xc", ICLASS_AE_ADDCIRC_XC, + 0, + Opcode_ae_addcirc_xc_encode_fns, 0, 0 }, + { "ae_s32ra64s.i", ICLASS_AE_S32RA64S_I, + 0, + Opcode_ae_s32ra64s_i_encode_fns, 1, Opcode_ae_s32ra64s_i_funcUnit_uses }, + { "ae_s32ra64s.ip", ICLASS_AE_S32RA64S_IP, + 0, + Opcode_ae_s32ra64s_ip_encode_fns, 1, Opcode_ae_s32ra64s_ip_funcUnit_uses }, + { "ae_s32ra64s.x", ICLASS_AE_S32RA64S_X, + 0, + Opcode_ae_s32ra64s_x_encode_fns, 1, Opcode_ae_s32ra64s_x_funcUnit_uses }, + { "ae_s32ra64s.xp", ICLASS_AE_S32RA64S_XP, + 0, + Opcode_ae_s32ra64s_xp_encode_fns, 1, Opcode_ae_s32ra64s_xp_funcUnit_uses }, + { "ae_s32ra64s.xc", ICLASS_AE_S32RA64S_XC, + 0, + Opcode_ae_s32ra64s_xc_encode_fns, 1, Opcode_ae_s32ra64s_xc_funcUnit_uses }, + { "ae_s32ra64s.xc1", ICLASS_AE_S32RA64S_XC1, + 0, + Opcode_ae_s32ra64s_xc1_encode_fns, 1, Opcode_ae_s32ra64s_xc1_funcUnit_uses }, + { "ae_s24ra64s.i", ICLASS_AE_S24RA64S_I, + 0, + Opcode_ae_s24ra64s_i_encode_fns, 1, Opcode_ae_s24ra64s_i_funcUnit_uses }, + { "ae_s24ra64s.ip", ICLASS_AE_S24RA64S_IP, + 0, + Opcode_ae_s24ra64s_ip_encode_fns, 1, Opcode_ae_s24ra64s_ip_funcUnit_uses }, + { "ae_s24ra64s.x", ICLASS_AE_S24RA64S_X, + 0, + Opcode_ae_s24ra64s_x_encode_fns, 1, Opcode_ae_s24ra64s_x_funcUnit_uses }, + { "ae_s24ra64s.xp", ICLASS_AE_S24RA64S_XP, + 0, + Opcode_ae_s24ra64s_xp_encode_fns, 1, Opcode_ae_s24ra64s_xp_funcUnit_uses }, + { "ae_s24ra64s.xc", ICLASS_AE_S24RA64S_XC, + 0, + Opcode_ae_s24ra64s_xc_encode_fns, 1, Opcode_ae_s24ra64s_xc_funcUnit_uses }, + { "ae_s24ra64s.xc1", ICLASS_AE_S24RA64S_XC1, + 0, + Opcode_ae_s24ra64s_xc1_encode_fns, 1, Opcode_ae_s24ra64s_xc1_funcUnit_uses }, + { "ae_s32x2ra64s.ip", ICLASS_AE_S32X2RA64S_IP, + 0, + Opcode_ae_s32x2ra64s_ip_encode_fns, 1, Opcode_ae_s32x2ra64s_ip_funcUnit_uses }, + { "ae_s24x2ra64s.ip", ICLASS_AE_S24X2RA64S_IP, + 0, + Opcode_ae_s24x2ra64s_ip_encode_fns, 1, Opcode_ae_s24x2ra64s_ip_funcUnit_uses }, + { "ae_addbrba32", ICLASS_AE_ADDBRBA32, + 0, + Opcode_ae_addbrba32_encode_fns, 0, 0 }, + { "ae_bitswap", ICLASS_AE_BITSWAP, + 0, + Opcode_ae_bitswap_encode_fns, 0, 0 }, + { "ae_mul32js", ICLASS_AE_MUL32JS, + 0, + Opcode_ae_mul32js_encode_fns, 0, 0 }, + { "ae_addandsub32s", ICLASS_AE_ADDANDSUB32S, + 0, + Opcode_ae_addandsub32s_encode_fns, 0, 0 }, + { "ae_addandsubrng32", ICLASS_AE_ADDANDSUBRNG32, + 0, + Opcode_ae_addandsubrng32_encode_fns, 0, 0 }, + { "ae_addrng32", ICLASS_AE_ADDRNG32, + 0, + Opcode_ae_addrng32_encode_fns, 0, 0 }, + { "ae_subrng32", ICLASS_AE_SUBRNG32, + 0, + Opcode_ae_subrng32_encode_fns, 0, 0 }, + { "ae_calcrng3", ICLASS_AE_CALCRNG3, + 0, + Opcode_ae_calcrng3_encode_fns, 0, 0 }, + { "ae_calcrng2", ICLASS_AE_CALCRNG2, + 0, + Opcode_ae_calcrng2_encode_fns, 0, 0 }, + { "ae_calcrng1", ICLASS_AE_CALCRNG1, + 0, + Opcode_ae_calcrng1_encode_fns, 0, 0 }, + { "ae_rng32x2", ICLASS_AE_RNG32X2, + 0, + Opcode_ae_rng32x2_encode_fns, 0, 0 }, + { "ae_sel16i", ICLASS_AE_SEL16I, + 0, + Opcode_ae_sel16i_encode_fns, 0, 0 }, + { "ae_sel16i.n", ICLASS_AE_SEL16I_N, + 0, + Opcode_ae_sel16i_n_encode_fns, 0, 0 }, + { "ae_shortswap", ICLASS_AE_SHORTSWAP, + 0, + Opcode_ae_shortswap_encode_fns, 0, 0 }, + { "ae_movab4", ICLASS_AE_MOVAB4, + 0, + Opcode_ae_movab4_encode_fns, 0, 0 }, + { "ae_movab2", ICLASS_AE_MOVAB2, + 0, + Opcode_ae_movab2_encode_fns, 0, 0 }, + { "ae_movab", ICLASS_AE_MOVAB, + 0, + Opcode_ae_movab_encode_fns, 0, 0 }, + { "ae_movba", ICLASS_AE_MOVBA, + 0, + Opcode_ae_movba_encode_fns, 0, 0 }, + { "ae_movba1x2", ICLASS_AE_MOVBA1X2, + 0, + Opcode_ae_movba1x2_encode_fns, 0, 0 }, + { "ae_movba4", ICLASS_AE_MOVBA4, + 0, + Opcode_ae_movba4_encode_fns, 0, 0 }, + { "ae_movba2", ICLASS_AE_MOVBA2, + 0, + Opcode_ae_movba2_encode_fns, 0, 0 }, + { "ae_movb2", ICLASS_AE_MOVB2, + 0, + Opcode_ae_movb2_encode_fns, 0, 0 }, + { "ae_movb4", ICLASS_AE_MOVB4, + 0, + Opcode_ae_movb4_encode_fns, 0, 0 }, + { "ae_movt16x4", ICLASS_AE_MOVT16X4, + 0, + Opcode_ae_movt16x4_encode_fns, 0, 0 }, + { "ae_movf16x4", ICLASS_AE_MOVF16X4, + 0, + Opcode_ae_movf16x4_encode_fns, 0, 0 }, + { "ae_movt32x2", ICLASS_AE_MOVT32X2, + 0, + Opcode_ae_movt32x2_encode_fns, 0, 0 }, + { "ae_movf32x2", ICLASS_AE_MOVF32X2, + 0, + Opcode_ae_movf32x2_encode_fns, 0, 0 }, + { "ae_movsara7x2", ICLASS_AE_MOVSARA7X2, + 0, + Opcode_ae_movsara7x2_encode_fns, 0, 0 }, + { "ae_movsard7", ICLASS_AE_MOVSARD7, + 0, + Opcode_ae_movsard7_encode_fns, 0, 0 }, + { "ae_movasar", ICLASS_AE_MOVASAR, + 0, + Opcode_ae_movasar_encode_fns, 0, 0 }, + { "ae_movda32x2", ICLASS_AE_MOVDA32X2, + 0, + Opcode_ae_movda32x2_encode_fns, 0, 0 }, + { "ae_movda32", ICLASS_AE_MOVDA32, + 0, + Opcode_ae_movda32_encode_fns, 0, 0 }, + { "ae_movda16x2", ICLASS_AE_MOVDA16X2, + 0, + Opcode_ae_movda16x2_encode_fns, 0, 0 }, + { "ae_movda16", ICLASS_AE_MOVDA16, + 0, + Opcode_ae_movda16_encode_fns, 0, 0 }, + { "ae_movi", ICLASS_AE_MOVI, + 0, + Opcode_ae_movi_encode_fns, 0, 0 }, + { "ae_truncp24a32x2", ICLASS_AE_TRUNCP24A32X2, + 0, + Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, + { "ae_sat16x4", ICLASS_AE_SAT16X4, + 0, + Opcode_ae_sat16x4_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.32", ICLASS_AE_CVT32X2F16_32, + 0, + Opcode_ae_cvt32x2f16_32_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.10", ICLASS_AE_CVT32X2F16_10, + 0, + Opcode_ae_cvt32x2f16_10_encode_fns, 0, 0 }, + { "ae_sext32x2d16.32", ICLASS_AE_SEXT32X2D16_32, + 0, + Opcode_ae_sext32x2d16_32_encode_fns, 0, 0 }, + { "ae_sext32x2d16.10", ICLASS_AE_SEXT32X2D16_10, + 0, + Opcode_ae_sext32x2d16_10_encode_fns, 0, 0 }, + { "ae_cvta32f24s.l", ICLASS_AE_CVTA32F24S_L, + 0, + Opcode_ae_cvta32f24s_l_encode_fns, 0, 0 }, + { "ae_cvta32f24s.h", ICLASS_AE_CVTA32F24S_H, + 0, + Opcode_ae_cvta32f24s_h_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.ll", ICLASS_AE_CVTP24A16X2_LL, + 0, + Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.lh", ICLASS_AE_CVTP24A16X2_LH, + 0, + Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hl", ICLASS_AE_CVTP24A16X2_HL, + 0, + Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hh", ICLASS_AE_CVTP24A16X2_HH, + 0, + Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, + { "ae_truncp24q48x2", ICLASS_AE_TRUNCP24Q48X2, + 0, + Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, + { "ae_trunca32x2f64s", ICLASS_AE_TRUNCA32X2F64S, + 0, + Opcode_ae_trunca32x2f64s_encode_fns, 0, 0 }, + { "ae_trunci32x2f64s", ICLASS_AE_TRUNCI32X2F64S, + 0, + Opcode_ae_trunci32x2f64s_encode_fns, 0, 0 }, + { "ae_trunca32f64s.l", ICLASS_AE_TRUNCA32F64S_L, + 0, + Opcode_ae_trunca32f64s_l_encode_fns, 0, 0 }, + { "ae_trunci32f64s.l", ICLASS_AE_TRUNCI32F64S_L, + 0, + Opcode_ae_trunci32f64s_l_encode_fns, 0, 0 }, + { "ae_truncp16", ICLASS_AE_TRUNCP16, + 0, + Opcode_ae_truncp16_encode_fns, 0, 0 }, + { "ae_round32x2f64ssym", ICLASS_AE_ROUND32X2F64SSYM, + 0, + Opcode_ae_round32x2f64ssym_encode_fns, 0, 0 }, + { "ae_round32x2f64sasym", ICLASS_AE_ROUND32X2F64SASYM, + 0, + Opcode_ae_round32x2f64sasym_encode_fns, 0, 0 }, + { "ae_round32x2f48ssym", ICLASS_AE_ROUND32X2F48SSYM, + 0, + Opcode_ae_round32x2f48ssym_encode_fns, 0, 0 }, + { "ae_round32x2f48sasym", ICLASS_AE_ROUND32X2F48SASYM, + 0, + Opcode_ae_round32x2f48sasym_encode_fns, 0, 0 }, + { "ae_round16x4f32ssym", ICLASS_AE_ROUND16X4F32SSYM, + 0, + Opcode_ae_round16x4f32ssym_encode_fns, 0, 0 }, + { "ae_round16x4f32sasym", ICLASS_AE_ROUND16X4F32SASYM, + 0, + Opcode_ae_round16x4f32sasym_encode_fns, 0, 0 }, + { "ae_round24x2f48ssym", ICLASS_AE_ROUND24X2F48SSYM, + 0, + Opcode_ae_round24x2f48ssym_encode_fns, 0, 0 }, + { "ae_round24x2f48sasym", ICLASS_AE_ROUND24X2F48SASYM, + 0, + Opcode_ae_round24x2f48sasym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2sym", ICLASS_AE_ROUNDSP16Q48X2SYM, + 0, + Opcode_ae_roundsp16q48x2sym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2asym", ICLASS_AE_ROUNDSP16Q48X2ASYM, + 0, + Opcode_ae_roundsp16q48x2asym_encode_fns, 0, 0 }, + { "ae_minabs32s", ICLASS_AE_MINABS32S, + 0, + Opcode_ae_minabs32s_encode_fns, 0, 0 }, + { "ae_maxabs32s", ICLASS_AE_MAXABS32S, + 0, + Opcode_ae_maxabs32s_encode_fns, 0, 0 }, + { "ae_roundsp16f24sym", ICLASS_AE_ROUNDSP16F24SYM, + 0, + Opcode_ae_roundsp16f24sym_encode_fns, 0, 0 }, + { "ae_roundsp16f24asym", ICLASS_AE_ROUNDSP16F24ASYM, + 0, + Opcode_ae_roundsp16f24asym_encode_fns, 0, 0 }, + { "ae_mov", ICLASS_AE_MOV, + 0, + Opcode_ae_mov_encode_fns, 0, 0 }, + { "ae_movt64", ICLASS_AE_MOVT64, + 0, + Opcode_ae_movt64_encode_fns, 0, 0 }, + { "ae_movf64", ICLASS_AE_MOVF64, + 0, + Opcode_ae_movf64_encode_fns, 0, 0 }, + { "ae_cvtq56a32s", ICLASS_AE_CVTQ56A32S, + 0, + Opcode_ae_cvtq56a32s_encode_fns, 0, 0 }, + { "ae_cvt48a32", ICLASS_AE_CVT48A32, + 0, + Opcode_ae_cvt48a32_encode_fns, 0, 0 }, + { "ae_cvt64a32", ICLASS_AE_CVT64A32, + 0, + Opcode_ae_cvt64a32_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.l", ICLASS_AE_CVTQ56P32S_L, + 0, + Opcode_ae_cvtq56p32s_l_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.h", ICLASS_AE_CVTQ56P32S_H, + 0, + Opcode_ae_cvtq56p32s_h_encode_fns, 0, 0 }, + { "ae_cvt64f32.h", ICLASS_AE_CVT64F32_H, + 0, + Opcode_ae_cvt64f32_h_encode_fns, 0, 0 }, + { "ae_cvt48f32.l", ICLASS_AE_CVT48F32_L, + 0, + Opcode_ae_cvt48f32_l_encode_fns, 0, 0 }, + { "ae_cvt48f32.h", ICLASS_AE_CVT48F32_H, + 0, + Opcode_ae_cvt48f32_h_encode_fns, 0, 0 }, + { "ae_sat48s", ICLASS_AE_SAT48S, + 0, + Opcode_ae_sat48s_encode_fns, 0, 0 }, + { "ae_satq56s", ICLASS_AE_SATQ56S, + 0, + Opcode_ae_satq56s_encode_fns, 0, 0 }, + { "ae_sat24s", ICLASS_AE_SAT24S, + 0, + Opcode_ae_sat24s_encode_fns, 0, 0 }, + { "ae_truncq32", ICLASS_AE_TRUNCQ32, + 0, + Opcode_ae_truncq32_encode_fns, 0, 0 }, + { "ae_minabs64s", ICLASS_AE_MINABS64S, + 0, + Opcode_ae_minabs64s_encode_fns, 0, 0 }, + { "ae_maxabs64s", ICLASS_AE_MAXABS64S, + 0, + Opcode_ae_maxabs64s_encode_fns, 0, 0 }, + { "ae_roundsq32f48sym", ICLASS_AE_ROUNDSQ32F48SYM, + 0, + Opcode_ae_roundsq32f48sym_encode_fns, 0, 0 }, + { "ae_roundsq32f48asym", ICLASS_AE_ROUNDSQ32F48ASYM, + 0, + Opcode_ae_roundsq32f48asym_encode_fns, 0, 0 }, + { "ae_trunca32q48", ICLASS_AE_TRUNCA32Q48, + 0, + Opcode_ae_trunca32q48_encode_fns, 0, 0 }, + { "ae_movad32.l", ICLASS_AE_MOVAD32_L, + 0, + Opcode_ae_movad32_l_encode_fns, 0, 0 }, + { "ae_movad32.h", ICLASS_AE_MOVAD32_H, + 0, + Opcode_ae_movad32_h_encode_fns, 0, 0 }, + { "ae_movad16.3", ICLASS_AE_MOVAD16_3, + 0, + Opcode_ae_movad16_3_encode_fns, 0, 0 }, + { "ae_movad16.2", ICLASS_AE_MOVAD16_2, + 0, + Opcode_ae_movad16_2_encode_fns, 0, 0 }, + { "ae_movad16.1", ICLASS_AE_MOVAD16_1, + 0, + Opcode_ae_movad16_1_encode_fns, 0, 0 }, + { "ae_movad16.0", ICLASS_AE_MOVAD16_0, + 0, + Opcode_ae_movad16_0_encode_fns, 0, 0 }, + { "ae_sra64_32", ICLASS_AE_SRA64_32, + 0, + Opcode_ae_sra64_32_encode_fns, 0, 0 }, + { "ae_pksr32", ICLASS_AE_PKSR32, + 0, + Opcode_ae_pksr32_encode_fns, 0, 0 }, + { "ae_pksr24", ICLASS_AE_PKSR24, + 0, + Opcode_ae_pksr24_encode_fns, 0, 0 }, + { "ae_pksrf32", ICLASS_AE_PKSRF32, + 0, + Opcode_ae_pksrf32_encode_fns, 0, 0 }, + { "ae_trunca16p24s.l", ICLASS_AE_TRUNCA16P24S_L, + 0, + Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, + { "ae_trunca16p24s.h", ICLASS_AE_TRUNCA16P24S_H, + 0, + Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, + { "ae_add32", ICLASS_AE_ADD32, + 0, + Opcode_ae_add32_encode_fns, 0, 0 }, + { "ae_sub32", ICLASS_AE_SUB32, + 0, + Opcode_ae_sub32_encode_fns, 0, 0 }, + { "ae_addsub32", ICLASS_AE_ADDSUB32, + 0, + Opcode_ae_addsub32_encode_fns, 0, 0 }, + { "ae_subadd32", ICLASS_AE_SUBADD32, + 0, + Opcode_ae_subadd32_encode_fns, 0, 0 }, + { "ae_add16", ICLASS_AE_ADD16, + 0, + Opcode_ae_add16_encode_fns, 0, 0 }, + { "ae_sub16", ICLASS_AE_SUB16, + 0, + Opcode_ae_sub16_encode_fns, 0, 0 }, + { "ae_add32_hl_lh", ICLASS_AE_ADD32_HL_LH, + 0, + Opcode_ae_add32_hl_lh_encode_fns, 0, 0 }, + { "ae_neg32", ICLASS_AE_NEG32, + 0, + Opcode_ae_neg32_encode_fns, 0, 0 }, + { "ae_abs32", ICLASS_AE_ABS32, + 0, + Opcode_ae_abs32_encode_fns, 0, 0 }, + { "ae_add24s", ICLASS_AE_ADD24S, + 0, + Opcode_ae_add24s_encode_fns, 0, 0 }, + { "ae_sub24s", ICLASS_AE_SUB24S, + 0, + Opcode_ae_sub24s_encode_fns, 0, 0 }, + { "ae_add32s", ICLASS_AE_ADD32S, + 0, + Opcode_ae_add32s_encode_fns, 0, 0 }, + { "ae_sub32s", ICLASS_AE_SUB32S, + 0, + Opcode_ae_sub32s_encode_fns, 0, 0 }, + { "ae_addsub32s", ICLASS_AE_ADDSUB32S, + 0, + Opcode_ae_addsub32s_encode_fns, 0, 0 }, + { "ae_subadd32s", ICLASS_AE_SUBADD32S, + 0, + Opcode_ae_subadd32s_encode_fns, 0, 0 }, + { "ae_add16s", ICLASS_AE_ADD16S, + 0, + Opcode_ae_add16s_encode_fns, 0, 0 }, + { "ae_sub16s", ICLASS_AE_SUB16S, + 0, + Opcode_ae_sub16s_encode_fns, 0, 0 }, + { "ae_add32s_hl_lh", ICLASS_AE_ADD32S_HL_LH, + 0, + Opcode_ae_add32s_hl_lh_encode_fns, 0, 0 }, + { "ae_neg24s", ICLASS_AE_NEG24S, + 0, + Opcode_ae_neg24s_encode_fns, 0, 0 }, + { "ae_abs24s", ICLASS_AE_ABS24S, + 0, + Opcode_ae_abs24s_encode_fns, 0, 0 }, + { "ae_neg32s", ICLASS_AE_NEG32S, + 0, + Opcode_ae_neg32s_encode_fns, 0, 0 }, + { "ae_abs32s", ICLASS_AE_ABS32S, + 0, + Opcode_ae_abs32s_encode_fns, 0, 0 }, + { "ae_neg16s", ICLASS_AE_NEG16S, + 0, + Opcode_ae_neg16s_encode_fns, 0, 0 }, + { "ae_abs16s", ICLASS_AE_ABS16S, + 0, + Opcode_ae_abs16s_encode_fns, 0, 0 }, + { "ae_lt16", ICLASS_AE_LT16, + 0, + Opcode_ae_lt16_encode_fns, 0, 0 }, + { "ae_le16", ICLASS_AE_LE16, + 0, + Opcode_ae_le16_encode_fns, 0, 0 }, + { "ae_eq16", ICLASS_AE_EQ16, + 0, + Opcode_ae_eq16_encode_fns, 0, 0 }, + { "ae_lt32", ICLASS_AE_LT32, + 0, + Opcode_ae_lt32_encode_fns, 0, 0 }, + { "ae_le32", ICLASS_AE_LE32, + 0, + Opcode_ae_le32_encode_fns, 0, 0 }, + { "ae_eq32", ICLASS_AE_EQ32, + 0, + Opcode_ae_eq32_encode_fns, 0, 0 }, + { "ae_min32", ICLASS_AE_MIN32, + 0, + Opcode_ae_min32_encode_fns, 0, 0 }, + { "ae_max32", ICLASS_AE_MAX32, + 0, + Opcode_ae_max32_encode_fns, 0, 0 }, + { "ae_add64", ICLASS_AE_ADD64, + 0, + Opcode_ae_add64_encode_fns, 0, 0 }, + { "ae_sub64", ICLASS_AE_SUB64, + 0, + Opcode_ae_sub64_encode_fns, 0, 0 }, + { "ae_neg64", ICLASS_AE_NEG64, + 0, + Opcode_ae_neg64_encode_fns, 0, 0 }, + { "ae_abs64", ICLASS_AE_ABS64, + 0, + Opcode_ae_abs64_encode_fns, 0, 0 }, + { "ae_addsq56s", ICLASS_AE_ADDSQ56S, + 0, + Opcode_ae_addsq56s_encode_fns, 0, 0 }, + { "ae_subsq56s", ICLASS_AE_SUBSQ56S, + 0, + Opcode_ae_subsq56s_encode_fns, 0, 0 }, + { "ae_add64s", ICLASS_AE_ADD64S, + 0, + Opcode_ae_add64s_encode_fns, 0, 0 }, + { "ae_sub64s", ICLASS_AE_SUB64S, + 0, + Opcode_ae_sub64s_encode_fns, 0, 0 }, + { "ae_negsq56s", ICLASS_AE_NEGSQ56S, + 0, + Opcode_ae_negsq56s_encode_fns, 0, 0 }, + { "ae_abssq56s", ICLASS_AE_ABSSQ56S, + 0, + Opcode_ae_abssq56s_encode_fns, 0, 0 }, + { "ae_neg64s", ICLASS_AE_NEG64S, + 0, + Opcode_ae_neg64s_encode_fns, 0, 0 }, + { "ae_abs64s", ICLASS_AE_ABS64S, + 0, + Opcode_ae_abs64s_encode_fns, 0, 0 }, + { "ae_and", ICLASS_AE_AND, + 0, + Opcode_ae_and_encode_fns, 0, 0 }, + { "ae_nand", ICLASS_AE_NAND, + 0, + Opcode_ae_nand_encode_fns, 0, 0 }, + { "ae_or", ICLASS_AE_OR, + 0, + Opcode_ae_or_encode_fns, 0, 0 }, + { "ae_xor", ICLASS_AE_XOR, + 0, + Opcode_ae_xor_encode_fns, 0, 0 }, + { "ae_slai24", ICLASS_AE_SLAI24, + 0, + Opcode_ae_slai24_encode_fns, 0, 0 }, + { "ae_srli24", ICLASS_AE_SRLI24, + 0, + Opcode_ae_srli24_encode_fns, 0, 0 }, + { "ae_srai24", ICLASS_AE_SRAI24, + 0, + Opcode_ae_srai24_encode_fns, 0, 0 }, + { "ae_slas24", ICLASS_AE_SLAS24, + 0, + Opcode_ae_slas24_encode_fns, 0, 0 }, + { "ae_srls24", ICLASS_AE_SRLS24, + 0, + Opcode_ae_srls24_encode_fns, 0, 0 }, + { "ae_sras24", ICLASS_AE_SRAS24, + 0, + Opcode_ae_sras24_encode_fns, 0, 0 }, + { "ae_srai16", ICLASS_AE_SRAI16, + 0, + Opcode_ae_srai16_encode_fns, 0, 0 }, + { "ae_srai16r", ICLASS_AE_SRAI16R, + 0, + Opcode_ae_srai16r_encode_fns, 0, 0 }, + { "ae_slai32", ICLASS_AE_SLAI32, + 0, + Opcode_ae_slai32_encode_fns, 0, 0 }, + { "ae_srli32", ICLASS_AE_SRLI32, + 0, + Opcode_ae_srli32_encode_fns, 0, 0 }, + { "ae_srai32", ICLASS_AE_SRAI32, + 0, + Opcode_ae_srai32_encode_fns, 0, 0 }, + { "ae_srai32r", ICLASS_AE_SRAI32R, + 0, + Opcode_ae_srai32r_encode_fns, 0, 0 }, + { "ae_slas32", ICLASS_AE_SLAS32, + 0, + Opcode_ae_slas32_encode_fns, 0, 0 }, + { "ae_srls32", ICLASS_AE_SRLS32, + 0, + Opcode_ae_srls32_encode_fns, 0, 0 }, + { "ae_sras32", ICLASS_AE_SRAS32, + 0, + Opcode_ae_sras32_encode_fns, 0, 0 }, + { "ae_slaa32", ICLASS_AE_SLAA32, + 0, + Opcode_ae_slaa32_encode_fns, 0, 0 }, + { "ae_srla32", ICLASS_AE_SRLA32, + 0, + Opcode_ae_srla32_encode_fns, 0, 0 }, + { "ae_sraa32", ICLASS_AE_SRAA32, + 0, + Opcode_ae_sraa32_encode_fns, 0, 0 }, + { "ae_slai16s", ICLASS_AE_SLAI16S, + 0, + Opcode_ae_slai16s_encode_fns, 0, 0 }, + { "ae_slaa16s", ICLASS_AE_SLAA16S, + 0, + Opcode_ae_slaa16s_encode_fns, 0, 0 }, + { "ae_sraa16s", ICLASS_AE_SRAA16S, + 0, + Opcode_ae_sraa16s_encode_fns, 0, 0 }, + { "ae_sraa16rs", ICLASS_AE_SRAA16RS, + 0, + Opcode_ae_sraa16rs_encode_fns, 0, 0 }, + { "ae_slai24s", ICLASS_AE_SLAI24S, + 0, + Opcode_ae_slai24s_encode_fns, 0, 0 }, + { "ae_slas24s", ICLASS_AE_SLAS24S, + 0, + Opcode_ae_slas24s_encode_fns, 0, 0 }, + { "ae_slai32s", ICLASS_AE_SLAI32S, + 0, + Opcode_ae_slai32s_encode_fns, 0, 0 }, + { "ae_slas32s", ICLASS_AE_SLAS32S, + 0, + Opcode_ae_slas32s_encode_fns, 0, 0 }, + { "ae_slaa32s", ICLASS_AE_SLAA32S, + 0, + Opcode_ae_slaa32s_encode_fns, 0, 0 }, + { "ae_sraa32s", ICLASS_AE_SRAA32S, + 0, + Opcode_ae_sraa32s_encode_fns, 0, 0 }, + { "ae_sraa32rs", ICLASS_AE_SRAA32RS, + 0, + Opcode_ae_sraa32rs_encode_fns, 0, 0 }, + { "ae_slasq56", ICLASS_AE_SLASQ56, + 0, + Opcode_ae_slasq56_encode_fns, 0, 0 }, + { "ae_srlsq56", ICLASS_AE_SRLSQ56, + 0, + Opcode_ae_srlsq56_encode_fns, 0, 0 }, + { "ae_srasq56", ICLASS_AE_SRASQ56, + 0, + Opcode_ae_srasq56_encode_fns, 0, 0 }, + { "ae_slaaq56", ICLASS_AE_SLAAQ56, + 0, + Opcode_ae_slaaq56_encode_fns, 0, 0 }, + { "ae_srlaq56", ICLASS_AE_SRLAQ56, + 0, + Opcode_ae_srlaq56_encode_fns, 0, 0 }, + { "ae_sraaq56", ICLASS_AE_SRAAQ56, + 0, + Opcode_ae_sraaq56_encode_fns, 0, 0 }, + { "ae_slai64", ICLASS_AE_SLAI64, + 0, + Opcode_ae_slai64_encode_fns, 0, 0 }, + { "ae_srli64", ICLASS_AE_SRLI64, + 0, + Opcode_ae_srli64_encode_fns, 0, 0 }, + { "ae_srai64", ICLASS_AE_SRAI64, + 0, + Opcode_ae_srai64_encode_fns, 0, 0 }, + { "ae_slas64", ICLASS_AE_SLAS64, + 0, + Opcode_ae_slas64_encode_fns, 0, 0 }, + { "ae_srls64", ICLASS_AE_SRLS64, + 0, + Opcode_ae_srls64_encode_fns, 0, 0 }, + { "ae_sras64", ICLASS_AE_SRAS64, + 0, + Opcode_ae_sras64_encode_fns, 0, 0 }, + { "ae_slaa64", ICLASS_AE_SLAA64, + 0, + Opcode_ae_slaa64_encode_fns, 0, 0 }, + { "ae_srla64", ICLASS_AE_SRLA64, + 0, + Opcode_ae_srla64_encode_fns, 0, 0 }, + { "ae_sraa64", ICLASS_AE_SRAA64, + 0, + Opcode_ae_sraa64_encode_fns, 0, 0 }, + { "ae_slaisq56s", ICLASS_AE_SLAISQ56S, + 0, + Opcode_ae_slaisq56s_encode_fns, 0, 0 }, + { "ae_slassq56s", ICLASS_AE_SLASSQ56S, + 0, + Opcode_ae_slassq56s_encode_fns, 0, 0 }, + { "ae_slaasq56s", ICLASS_AE_SLAASQ56S, + 0, + Opcode_ae_slaasq56s_encode_fns, 0, 0 }, + { "ae_slai64s", ICLASS_AE_SLAI64S, + 0, + Opcode_ae_slai64s_encode_fns, 0, 0 }, + { "ae_slas64s", ICLASS_AE_SLAS64S, + 0, + Opcode_ae_slas64s_encode_fns, 0, 0 }, + { "ae_slaa64s", ICLASS_AE_SLAA64S, + 0, + Opcode_ae_slaa64s_encode_fns, 0, 0 }, + { "ae_lt64", ICLASS_AE_LT64, + 0, + Opcode_ae_lt64_encode_fns, 0, 0 }, + { "ae_le64", ICLASS_AE_LE64, + 0, + Opcode_ae_le64_encode_fns, 0, 0 }, + { "ae_eq64", ICLASS_AE_EQ64, + 0, + Opcode_ae_eq64_encode_fns, 0, 0 }, + { "ae_max64", ICLASS_AE_MAX64, + 0, + Opcode_ae_max64_encode_fns, 0, 0 }, + { "ae_min64", ICLASS_AE_MIN64, + 0, + Opcode_ae_min64_encode_fns, 0, 0 }, + { "ae_nsa64", ICLASS_AE_NSA64, + 0, + Opcode_ae_nsa64_encode_fns, 0, 0 }, + { "ae_nsaz16.0", ICLASS_AE_NSAZ16_0, + 0, + Opcode_ae_nsaz16_0_encode_fns, 0, 0 }, + { "ae_nsaz32.l", ICLASS_AE_NSAZ32_L, + 0, + Opcode_ae_nsaz32_l_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.ll", ICLASS_AE_MULS32F48P16S_LL, + 0, + Opcode_ae_muls32f48p16s_ll_encode_fns, 1, Opcode_ae_muls32f48p16s_ll_funcUnit_uses }, + { "ae_mulf32s.ll", ICLASS_AE_MULF32S_LL, + 0, + Opcode_ae_mulf32s_ll_encode_fns, 1, Opcode_ae_mulf32s_ll_funcUnit_uses }, + { "ae_mul32.ll", ICLASS_AE_MUL32_LL, + 0, + Opcode_ae_mul32_ll_encode_fns, 1, Opcode_ae_mul32_ll_funcUnit_uses }, + { "ae_mulf32s.ll_s2", ICLASS_AE_MULF32S_LL_S2, + 0, + Opcode_ae_mulf32s_ll_s2_encode_fns, 1, Opcode_ae_mulf32s_ll_s2_funcUnit_uses }, + { "ae_mul32.ll_s2", ICLASS_AE_MUL32_LL_S2, + 0, + Opcode_ae_mul32_ll_s2_encode_fns, 1, Opcode_ae_mul32_ll_s2_funcUnit_uses }, + { "ae_muls32f48p16s.ll_s2", ICLASS_AE_MULS32F48P16S_LL_S2, + 0, + Opcode_ae_muls32f48p16s_ll_s2_encode_fns, 1, Opcode_ae_muls32f48p16s_ll_s2_funcUnit_uses }, + { "ae_mulf32r.ll", ICLASS_AE_MULF32R_LL, + 0, + Opcode_ae_mulf32r_ll_encode_fns, 1, Opcode_ae_mulf32r_ll_funcUnit_uses }, + { "ae_mulf32ra.ll", ICLASS_AE_MULF32RA_LL, + 0, + Opcode_ae_mulf32ra_ll_encode_fns, 1, Opcode_ae_mulf32ra_ll_funcUnit_uses }, + { "ae_mulf32ra.ll_s2", ICLASS_AE_MULF32RA_LL_S2, + 0, + Opcode_ae_mulf32ra_ll_s2_encode_fns, 1, Opcode_ae_mulf32ra_ll_s2_funcUnit_uses }, + { "ae_mulf32r.ll_s2", ICLASS_AE_MULF32R_LL_S2, + 0, + Opcode_ae_mulf32r_ll_s2_encode_fns, 1, Opcode_ae_mulf32r_ll_s2_funcUnit_uses }, + { "ae_muls32f48p16s.lh", ICLASS_AE_MULS32F48P16S_LH, + 0, + Opcode_ae_muls32f48p16s_lh_encode_fns, 1, Opcode_ae_muls32f48p16s_lh_funcUnit_uses }, + { "ae_mulf32s.lh", ICLASS_AE_MULF32S_LH, + 0, + Opcode_ae_mulf32s_lh_encode_fns, 1, Opcode_ae_mulf32s_lh_funcUnit_uses }, + { "ae_mul32.lh", ICLASS_AE_MUL32_LH, + 0, + Opcode_ae_mul32_lh_encode_fns, 1, Opcode_ae_mul32_lh_funcUnit_uses }, + { "ae_mulf32s.lh_s2", ICLASS_AE_MULF32S_LH_S2, + 0, + Opcode_ae_mulf32s_lh_s2_encode_fns, 1, Opcode_ae_mulf32s_lh_s2_funcUnit_uses }, + { "ae_mul32.lh_s2", ICLASS_AE_MUL32_LH_S2, + 0, + Opcode_ae_mul32_lh_s2_encode_fns, 1, Opcode_ae_mul32_lh_s2_funcUnit_uses }, + { "ae_muls32f48p16s.lh_s2", ICLASS_AE_MULS32F48P16S_LH_S2, + 0, + Opcode_ae_muls32f48p16s_lh_s2_encode_fns, 1, Opcode_ae_muls32f48p16s_lh_s2_funcUnit_uses }, + { "ae_mulf32r.lh", ICLASS_AE_MULF32R_LH, + 0, + Opcode_ae_mulf32r_lh_encode_fns, 1, Opcode_ae_mulf32r_lh_funcUnit_uses }, + { "ae_mulf32ra.lh", ICLASS_AE_MULF32RA_LH, + 0, + Opcode_ae_mulf32ra_lh_encode_fns, 1, Opcode_ae_mulf32ra_lh_funcUnit_uses }, + { "ae_mulf32ra.lh_s2", ICLASS_AE_MULF32RA_LH_S2, + 0, + Opcode_ae_mulf32ra_lh_s2_encode_fns, 1, Opcode_ae_mulf32ra_lh_s2_funcUnit_uses }, + { "ae_mulf32r.lh_s2", ICLASS_AE_MULF32R_LH_S2, + 0, + Opcode_ae_mulf32r_lh_s2_encode_fns, 1, Opcode_ae_mulf32r_lh_s2_funcUnit_uses }, + { "ae_muls32f48p16s.hh", ICLASS_AE_MULS32F48P16S_HH, + 0, + Opcode_ae_muls32f48p16s_hh_encode_fns, 1, Opcode_ae_muls32f48p16s_hh_funcUnit_uses }, + { "ae_mulf32s.hh", ICLASS_AE_MULF32S_HH, + 0, + Opcode_ae_mulf32s_hh_encode_fns, 1, Opcode_ae_mulf32s_hh_funcUnit_uses }, + { "ae_mul32.hh", ICLASS_AE_MUL32_HH, + 0, + Opcode_ae_mul32_hh_encode_fns, 1, Opcode_ae_mul32_hh_funcUnit_uses }, + { "ae_mulf32s.hh_s2", ICLASS_AE_MULF32S_HH_S2, + 0, + Opcode_ae_mulf32s_hh_s2_encode_fns, 1, Opcode_ae_mulf32s_hh_s2_funcUnit_uses }, + { "ae_mul32.hh_s2", ICLASS_AE_MUL32_HH_S2, + 0, + Opcode_ae_mul32_hh_s2_encode_fns, 1, Opcode_ae_mul32_hh_s2_funcUnit_uses }, + { "ae_muls32f48p16s.hh_s2", ICLASS_AE_MULS32F48P16S_HH_S2, + 0, + Opcode_ae_muls32f48p16s_hh_s2_encode_fns, 1, Opcode_ae_muls32f48p16s_hh_s2_funcUnit_uses }, + { "ae_mulf32r.hh", ICLASS_AE_MULF32R_HH, + 0, + Opcode_ae_mulf32r_hh_encode_fns, 1, Opcode_ae_mulf32r_hh_funcUnit_uses }, + { "ae_mulf32ra.hh", ICLASS_AE_MULF32RA_HH, + 0, + Opcode_ae_mulf32ra_hh_encode_fns, 1, Opcode_ae_mulf32ra_hh_funcUnit_uses }, + { "ae_mulf32ra.hh_s2", ICLASS_AE_MULF32RA_HH_S2, + 0, + Opcode_ae_mulf32ra_hh_s2_encode_fns, 1, Opcode_ae_mulf32ra_hh_s2_funcUnit_uses }, + { "ae_mulf32r.hh_s2", ICLASS_AE_MULF32R_HH_S2, + 0, + Opcode_ae_mulf32r_hh_s2_encode_fns, 1, Opcode_ae_mulf32r_hh_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.ll", ICLASS_AE_MULAS32F48P16S_LL, + 0, + Opcode_ae_mulas32f48p16s_ll_encode_fns, 1, Opcode_ae_mulas32f48p16s_ll_funcUnit_uses }, + { "ae_mulaf32s.ll", ICLASS_AE_MULAF32S_LL, + 0, + Opcode_ae_mulaf32s_ll_encode_fns, 1, Opcode_ae_mulaf32s_ll_funcUnit_uses }, + { "ae_mula32.ll", ICLASS_AE_MULA32_LL, + 0, + Opcode_ae_mula32_ll_encode_fns, 1, Opcode_ae_mula32_ll_funcUnit_uses }, + { "ae_mulaf32s.ll_s2", ICLASS_AE_MULAF32S_LL_S2, + 0, + Opcode_ae_mulaf32s_ll_s2_encode_fns, 1, Opcode_ae_mulaf32s_ll_s2_funcUnit_uses }, + { "ae_mula32.ll_s2", ICLASS_AE_MULA32_LL_S2, + 0, + Opcode_ae_mula32_ll_s2_encode_fns, 1, Opcode_ae_mula32_ll_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.ll_s2", ICLASS_AE_MULAS32F48P16S_LL_S2, + 0, + Opcode_ae_mulas32f48p16s_ll_s2_encode_fns, 1, Opcode_ae_mulas32f48p16s_ll_s2_funcUnit_uses }, + { "ae_mulaf32r.ll", ICLASS_AE_MULAF32R_LL, + 0, + Opcode_ae_mulaf32r_ll_encode_fns, 1, Opcode_ae_mulaf32r_ll_funcUnit_uses }, + { "ae_mulaf32ra.ll", ICLASS_AE_MULAF32RA_LL, + 0, + Opcode_ae_mulaf32ra_ll_encode_fns, 1, Opcode_ae_mulaf32ra_ll_funcUnit_uses }, + { "ae_mulaf32ra.ll_s2", ICLASS_AE_MULAF32RA_LL_S2, + 0, + Opcode_ae_mulaf32ra_ll_s2_encode_fns, 1, Opcode_ae_mulaf32ra_ll_s2_funcUnit_uses }, + { "ae_mulaf32r.ll_s2", ICLASS_AE_MULAF32R_LL_S2, + 0, + Opcode_ae_mulaf32r_ll_s2_encode_fns, 1, Opcode_ae_mulaf32r_ll_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.lh", ICLASS_AE_MULAS32F48P16S_LH, + 0, + Opcode_ae_mulas32f48p16s_lh_encode_fns, 1, Opcode_ae_mulas32f48p16s_lh_funcUnit_uses }, + { "ae_mulaf32s.lh", ICLASS_AE_MULAF32S_LH, + 0, + Opcode_ae_mulaf32s_lh_encode_fns, 1, Opcode_ae_mulaf32s_lh_funcUnit_uses }, + { "ae_mula32.lh", ICLASS_AE_MULA32_LH, + 0, + Opcode_ae_mula32_lh_encode_fns, 1, Opcode_ae_mula32_lh_funcUnit_uses }, + { "ae_mulaf32s.lh_s2", ICLASS_AE_MULAF32S_LH_S2, + 0, + Opcode_ae_mulaf32s_lh_s2_encode_fns, 1, Opcode_ae_mulaf32s_lh_s2_funcUnit_uses }, + { "ae_mula32.lh_s2", ICLASS_AE_MULA32_LH_S2, + 0, + Opcode_ae_mula32_lh_s2_encode_fns, 1, Opcode_ae_mula32_lh_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.lh_s2", ICLASS_AE_MULAS32F48P16S_LH_S2, + 0, + Opcode_ae_mulas32f48p16s_lh_s2_encode_fns, 1, Opcode_ae_mulas32f48p16s_lh_s2_funcUnit_uses }, + { "ae_mulaf32r.lh", ICLASS_AE_MULAF32R_LH, + 0, + Opcode_ae_mulaf32r_lh_encode_fns, 1, Opcode_ae_mulaf32r_lh_funcUnit_uses }, + { "ae_mulaf32ra.lh", ICLASS_AE_MULAF32RA_LH, + 0, + Opcode_ae_mulaf32ra_lh_encode_fns, 1, Opcode_ae_mulaf32ra_lh_funcUnit_uses }, + { "ae_mulaf32ra.lh_s2", ICLASS_AE_MULAF32RA_LH_S2, + 0, + Opcode_ae_mulaf32ra_lh_s2_encode_fns, 1, Opcode_ae_mulaf32ra_lh_s2_funcUnit_uses }, + { "ae_mulaf32r.lh_s2", ICLASS_AE_MULAF32R_LH_S2, + 0, + Opcode_ae_mulaf32r_lh_s2_encode_fns, 1, Opcode_ae_mulaf32r_lh_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.hh", ICLASS_AE_MULAS32F48P16S_HH, + 0, + Opcode_ae_mulas32f48p16s_hh_encode_fns, 1, Opcode_ae_mulas32f48p16s_hh_funcUnit_uses }, + { "ae_mulaf32s.hh", ICLASS_AE_MULAF32S_HH, + 0, + Opcode_ae_mulaf32s_hh_encode_fns, 1, Opcode_ae_mulaf32s_hh_funcUnit_uses }, + { "ae_mula32.hh", ICLASS_AE_MULA32_HH, + 0, + Opcode_ae_mula32_hh_encode_fns, 1, Opcode_ae_mula32_hh_funcUnit_uses }, + { "ae_mulaf32s.hh_s2", ICLASS_AE_MULAF32S_HH_S2, + 0, + Opcode_ae_mulaf32s_hh_s2_encode_fns, 1, Opcode_ae_mulaf32s_hh_s2_funcUnit_uses }, + { "ae_mula32.hh_s2", ICLASS_AE_MULA32_HH_S2, + 0, + Opcode_ae_mula32_hh_s2_encode_fns, 1, Opcode_ae_mula32_hh_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.hh_s2", ICLASS_AE_MULAS32F48P16S_HH_S2, + 0, + Opcode_ae_mulas32f48p16s_hh_s2_encode_fns, 1, Opcode_ae_mulas32f48p16s_hh_s2_funcUnit_uses }, + { "ae_mulaf32r.hh", ICLASS_AE_MULAF32R_HH, + 0, + Opcode_ae_mulaf32r_hh_encode_fns, 1, Opcode_ae_mulaf32r_hh_funcUnit_uses }, + { "ae_mulaf32ra.hh", ICLASS_AE_MULAF32RA_HH, + 0, + Opcode_ae_mulaf32ra_hh_encode_fns, 1, Opcode_ae_mulaf32ra_hh_funcUnit_uses }, + { "ae_mulaf32ra.hh_s2", ICLASS_AE_MULAF32RA_HH_S2, + 0, + Opcode_ae_mulaf32ra_hh_s2_encode_fns, 1, Opcode_ae_mulaf32ra_hh_s2_funcUnit_uses }, + { "ae_mulaf32r.hh_s2", ICLASS_AE_MULAF32R_HH_S2, + 0, + Opcode_ae_mulaf32r_hh_s2_encode_fns, 1, Opcode_ae_mulaf32r_hh_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.ll", ICLASS_AE_MULSS32F48P16S_LL, + 0, + Opcode_ae_mulss32f48p16s_ll_encode_fns, 1, Opcode_ae_mulss32f48p16s_ll_funcUnit_uses }, + { "ae_mulsf32s.ll", ICLASS_AE_MULSF32S_LL, + 0, + Opcode_ae_mulsf32s_ll_encode_fns, 1, Opcode_ae_mulsf32s_ll_funcUnit_uses }, + { "ae_muls32.ll", ICLASS_AE_MULS32_LL, + 0, + Opcode_ae_muls32_ll_encode_fns, 1, Opcode_ae_muls32_ll_funcUnit_uses }, + { "ae_mulsf32s.ll_s2", ICLASS_AE_MULSF32S_LL_S2, + 0, + Opcode_ae_mulsf32s_ll_s2_encode_fns, 1, Opcode_ae_mulsf32s_ll_s2_funcUnit_uses }, + { "ae_muls32.ll_s2", ICLASS_AE_MULS32_LL_S2, + 0, + Opcode_ae_muls32_ll_s2_encode_fns, 1, Opcode_ae_muls32_ll_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.ll_s2", ICLASS_AE_MULSS32F48P16S_LL_S2, + 0, + Opcode_ae_mulss32f48p16s_ll_s2_encode_fns, 1, Opcode_ae_mulss32f48p16s_ll_s2_funcUnit_uses }, + { "ae_mulsf32r.ll", ICLASS_AE_MULSF32R_LL, + 0, + Opcode_ae_mulsf32r_ll_encode_fns, 1, Opcode_ae_mulsf32r_ll_funcUnit_uses }, + { "ae_mulsf32ra.ll", ICLASS_AE_MULSF32RA_LL, + 0, + Opcode_ae_mulsf32ra_ll_encode_fns, 1, Opcode_ae_mulsf32ra_ll_funcUnit_uses }, + { "ae_mulsf32ra.ll_s2", ICLASS_AE_MULSF32RA_LL_S2, + 0, + Opcode_ae_mulsf32ra_ll_s2_encode_fns, 1, Opcode_ae_mulsf32ra_ll_s2_funcUnit_uses }, + { "ae_mulsf32r.ll_s2", ICLASS_AE_MULSF32R_LL_S2, + 0, + Opcode_ae_mulsf32r_ll_s2_encode_fns, 1, Opcode_ae_mulsf32r_ll_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.lh", ICLASS_AE_MULSS32F48P16S_LH, + 0, + Opcode_ae_mulss32f48p16s_lh_encode_fns, 1, Opcode_ae_mulss32f48p16s_lh_funcUnit_uses }, + { "ae_mulsf32s.lh", ICLASS_AE_MULSF32S_LH, + 0, + Opcode_ae_mulsf32s_lh_encode_fns, 1, Opcode_ae_mulsf32s_lh_funcUnit_uses }, + { "ae_muls32.lh", ICLASS_AE_MULS32_LH, + 0, + Opcode_ae_muls32_lh_encode_fns, 1, Opcode_ae_muls32_lh_funcUnit_uses }, + { "ae_mulsf32s.lh_s2", ICLASS_AE_MULSF32S_LH_S2, + 0, + Opcode_ae_mulsf32s_lh_s2_encode_fns, 1, Opcode_ae_mulsf32s_lh_s2_funcUnit_uses }, + { "ae_muls32.lh_s2", ICLASS_AE_MULS32_LH_S2, + 0, + Opcode_ae_muls32_lh_s2_encode_fns, 1, Opcode_ae_muls32_lh_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.lh_s2", ICLASS_AE_MULSS32F48P16S_LH_S2, + 0, + Opcode_ae_mulss32f48p16s_lh_s2_encode_fns, 1, Opcode_ae_mulss32f48p16s_lh_s2_funcUnit_uses }, + { "ae_mulsf32r.lh", ICLASS_AE_MULSF32R_LH, + 0, + Opcode_ae_mulsf32r_lh_encode_fns, 1, Opcode_ae_mulsf32r_lh_funcUnit_uses }, + { "ae_mulsf32ra.lh", ICLASS_AE_MULSF32RA_LH, + 0, + Opcode_ae_mulsf32ra_lh_encode_fns, 1, Opcode_ae_mulsf32ra_lh_funcUnit_uses }, + { "ae_mulsf32ra.lh_s2", ICLASS_AE_MULSF32RA_LH_S2, + 0, + Opcode_ae_mulsf32ra_lh_s2_encode_fns, 1, Opcode_ae_mulsf32ra_lh_s2_funcUnit_uses }, + { "ae_mulsf32r.lh_s2", ICLASS_AE_MULSF32R_LH_S2, + 0, + Opcode_ae_mulsf32r_lh_s2_encode_fns, 1, Opcode_ae_mulsf32r_lh_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.hh", ICLASS_AE_MULSS32F48P16S_HH, + 0, + Opcode_ae_mulss32f48p16s_hh_encode_fns, 1, Opcode_ae_mulss32f48p16s_hh_funcUnit_uses }, + { "ae_mulsf32s.hh", ICLASS_AE_MULSF32S_HH, + 0, + Opcode_ae_mulsf32s_hh_encode_fns, 1, Opcode_ae_mulsf32s_hh_funcUnit_uses }, + { "ae_muls32.hh", ICLASS_AE_MULS32_HH, + 0, + Opcode_ae_muls32_hh_encode_fns, 1, Opcode_ae_muls32_hh_funcUnit_uses }, + { "ae_mulsf32s.hh_s2", ICLASS_AE_MULSF32S_HH_S2, + 0, + Opcode_ae_mulsf32s_hh_s2_encode_fns, 1, Opcode_ae_mulsf32s_hh_s2_funcUnit_uses }, + { "ae_muls32.hh_s2", ICLASS_AE_MULS32_HH_S2, + 0, + Opcode_ae_muls32_hh_s2_encode_fns, 1, Opcode_ae_muls32_hh_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.hh_s2", ICLASS_AE_MULSS32F48P16S_HH_S2, + 0, + Opcode_ae_mulss32f48p16s_hh_s2_encode_fns, 1, Opcode_ae_mulss32f48p16s_hh_s2_funcUnit_uses }, + { "ae_mulsf32r.hh", ICLASS_AE_MULSF32R_HH, + 0, + Opcode_ae_mulsf32r_hh_encode_fns, 1, Opcode_ae_mulsf32r_hh_funcUnit_uses }, + { "ae_mulsf32ra.hh", ICLASS_AE_MULSF32RA_HH, + 0, + Opcode_ae_mulsf32ra_hh_encode_fns, 1, Opcode_ae_mulsf32ra_hh_funcUnit_uses }, + { "ae_mulsf32ra.hh_s2", ICLASS_AE_MULSF32RA_HH_S2, + 0, + Opcode_ae_mulsf32ra_hh_s2_encode_fns, 1, Opcode_ae_mulsf32ra_hh_s2_funcUnit_uses }, + { "ae_mulsf32r.hh_s2", ICLASS_AE_MULSF32R_HH_S2, + 0, + Opcode_ae_mulsf32r_hh_s2_encode_fns, 1, Opcode_ae_mulsf32r_hh_s2_funcUnit_uses }, + { "ae_mul32u.ll", ICLASS_AE_MUL32U_LL, + 0, + Opcode_ae_mul32u_ll_encode_fns, 1, Opcode_ae_mul32u_ll_funcUnit_uses }, + { "ae_mula32u.ll", ICLASS_AE_MULA32U_LL, + 0, + Opcode_ae_mula32u_ll_encode_fns, 1, Opcode_ae_mula32u_ll_funcUnit_uses }, + { "ae_muls32u.ll", ICLASS_AE_MULS32U_LL, + 0, + Opcode_ae_muls32u_ll_encode_fns, 1, Opcode_ae_muls32u_ll_funcUnit_uses }, + { "ae_mulf16ss.33", ICLASS_AE_MULF16SS_33, + 0, + Opcode_ae_mulf16ss_33_encode_fns, 1, Opcode_ae_mulf16ss_33_funcUnit_uses }, + { "ae_mulf16ss.33_s2", ICLASS_AE_MULF16SS_33_S2, + 0, + Opcode_ae_mulf16ss_33_s2_encode_fns, 1, Opcode_ae_mulf16ss_33_s2_funcUnit_uses }, + { "ae_mulf16ss.22", ICLASS_AE_MULF16SS_22, + 0, + Opcode_ae_mulf16ss_22_encode_fns, 1, Opcode_ae_mulf16ss_22_funcUnit_uses }, + { "ae_mulf16ss.22_s2", ICLASS_AE_MULF16SS_22_S2, + 0, + Opcode_ae_mulf16ss_22_s2_encode_fns, 1, Opcode_ae_mulf16ss_22_s2_funcUnit_uses }, + { "ae_mulf16ss.32", ICLASS_AE_MULF16SS_32, + 0, + Opcode_ae_mulf16ss_32_encode_fns, 1, Opcode_ae_mulf16ss_32_funcUnit_uses }, + { "ae_mulf16ss.32_s2", ICLASS_AE_MULF16SS_32_S2, + 0, + Opcode_ae_mulf16ss_32_s2_encode_fns, 1, Opcode_ae_mulf16ss_32_s2_funcUnit_uses }, + { "ae_mulf16ss.21", ICLASS_AE_MULF16SS_21, + 0, + Opcode_ae_mulf16ss_21_encode_fns, 1, Opcode_ae_mulf16ss_21_funcUnit_uses }, + { "ae_mulf16ss.21_s2", ICLASS_AE_MULF16SS_21_S2, + 0, + Opcode_ae_mulf16ss_21_s2_encode_fns, 1, Opcode_ae_mulf16ss_21_s2_funcUnit_uses }, + { "ae_mulf16ss.31", ICLASS_AE_MULF16SS_31, + 0, + Opcode_ae_mulf16ss_31_encode_fns, 1, Opcode_ae_mulf16ss_31_funcUnit_uses }, + { "ae_mulf16ss.31_s2", ICLASS_AE_MULF16SS_31_S2, + 0, + Opcode_ae_mulf16ss_31_s2_encode_fns, 1, Opcode_ae_mulf16ss_31_s2_funcUnit_uses }, + { "ae_mulf16ss.30", ICLASS_AE_MULF16SS_30, + 0, + Opcode_ae_mulf16ss_30_encode_fns, 1, Opcode_ae_mulf16ss_30_funcUnit_uses }, + { "ae_mulf16ss.30_s2", ICLASS_AE_MULF16SS_30_S2, + 0, + Opcode_ae_mulf16ss_30_s2_encode_fns, 1, Opcode_ae_mulf16ss_30_s2_funcUnit_uses }, + { "ae_mulf16ss.10", ICLASS_AE_MULF16SS_10, + 0, + Opcode_ae_mulf16ss_10_encode_fns, 1, Opcode_ae_mulf16ss_10_funcUnit_uses }, + { "ae_mulf16ss.10_s2", ICLASS_AE_MULF16SS_10_S2, + 0, + Opcode_ae_mulf16ss_10_s2_encode_fns, 1, Opcode_ae_mulf16ss_10_s2_funcUnit_uses }, + { "ae_mulf16ss.20", ICLASS_AE_MULF16SS_20, + 0, + Opcode_ae_mulf16ss_20_encode_fns, 1, Opcode_ae_mulf16ss_20_funcUnit_uses }, + { "ae_mulf16ss.20_s2", ICLASS_AE_MULF16SS_20_S2, + 0, + Opcode_ae_mulf16ss_20_s2_encode_fns, 1, Opcode_ae_mulf16ss_20_s2_funcUnit_uses }, + { "ae_mulf16ss.11", ICLASS_AE_MULF16SS_11, + 0, + Opcode_ae_mulf16ss_11_encode_fns, 1, Opcode_ae_mulf16ss_11_funcUnit_uses }, + { "ae_mulf16ss.11_s2", ICLASS_AE_MULF16SS_11_S2, + 0, + Opcode_ae_mulf16ss_11_s2_encode_fns, 1, Opcode_ae_mulf16ss_11_s2_funcUnit_uses }, + { "ae_mulf16ss.00", ICLASS_AE_MULF16SS_00, + 0, + Opcode_ae_mulf16ss_00_encode_fns, 1, Opcode_ae_mulf16ss_00_funcUnit_uses }, + { "ae_mulf16ss.00_s2", ICLASS_AE_MULF16SS_00_S2, + 0, + Opcode_ae_mulf16ss_00_s2_encode_fns, 1, Opcode_ae_mulf16ss_00_s2_funcUnit_uses }, + { "ae_mulsf16ss.33", ICLASS_AE_MULSF16SS_33, + 0, + Opcode_ae_mulsf16ss_33_encode_fns, 1, Opcode_ae_mulsf16ss_33_funcUnit_uses }, + { "ae_mulsf16ss.33_s2", ICLASS_AE_MULSF16SS_33_S2, + 0, + Opcode_ae_mulsf16ss_33_s2_encode_fns, 1, Opcode_ae_mulsf16ss_33_s2_funcUnit_uses }, + { "ae_mulsf16ss.22", ICLASS_AE_MULSF16SS_22, + 0, + Opcode_ae_mulsf16ss_22_encode_fns, 1, Opcode_ae_mulsf16ss_22_funcUnit_uses }, + { "ae_mulsf16ss.22_s2", ICLASS_AE_MULSF16SS_22_S2, + 0, + Opcode_ae_mulsf16ss_22_s2_encode_fns, 1, Opcode_ae_mulsf16ss_22_s2_funcUnit_uses }, + { "ae_mulsf16ss.32", ICLASS_AE_MULSF16SS_32, + 0, + Opcode_ae_mulsf16ss_32_encode_fns, 1, Opcode_ae_mulsf16ss_32_funcUnit_uses }, + { "ae_mulsf16ss.32_s2", ICLASS_AE_MULSF16SS_32_S2, + 0, + Opcode_ae_mulsf16ss_32_s2_encode_fns, 1, Opcode_ae_mulsf16ss_32_s2_funcUnit_uses }, + { "ae_mulsf16ss.21", ICLASS_AE_MULSF16SS_21, + 0, + Opcode_ae_mulsf16ss_21_encode_fns, 1, Opcode_ae_mulsf16ss_21_funcUnit_uses }, + { "ae_mulsf16ss.21_s2", ICLASS_AE_MULSF16SS_21_S2, + 0, + Opcode_ae_mulsf16ss_21_s2_encode_fns, 1, Opcode_ae_mulsf16ss_21_s2_funcUnit_uses }, + { "ae_mulsf16ss.31", ICLASS_AE_MULSF16SS_31, + 0, + Opcode_ae_mulsf16ss_31_encode_fns, 1, Opcode_ae_mulsf16ss_31_funcUnit_uses }, + { "ae_mulsf16ss.31_s2", ICLASS_AE_MULSF16SS_31_S2, + 0, + Opcode_ae_mulsf16ss_31_s2_encode_fns, 1, Opcode_ae_mulsf16ss_31_s2_funcUnit_uses }, + { "ae_mulsf16ss.30", ICLASS_AE_MULSF16SS_30, + 0, + Opcode_ae_mulsf16ss_30_encode_fns, 1, Opcode_ae_mulsf16ss_30_funcUnit_uses }, + { "ae_mulsf16ss.30_s2", ICLASS_AE_MULSF16SS_30_S2, + 0, + Opcode_ae_mulsf16ss_30_s2_encode_fns, 1, Opcode_ae_mulsf16ss_30_s2_funcUnit_uses }, + { "ae_mulsf16ss.10", ICLASS_AE_MULSF16SS_10, + 0, + Opcode_ae_mulsf16ss_10_encode_fns, 1, Opcode_ae_mulsf16ss_10_funcUnit_uses }, + { "ae_mulsf16ss.10_s2", ICLASS_AE_MULSF16SS_10_S2, + 0, + Opcode_ae_mulsf16ss_10_s2_encode_fns, 1, Opcode_ae_mulsf16ss_10_s2_funcUnit_uses }, + { "ae_mulsf16ss.20", ICLASS_AE_MULSF16SS_20, + 0, + Opcode_ae_mulsf16ss_20_encode_fns, 1, Opcode_ae_mulsf16ss_20_funcUnit_uses }, + { "ae_mulsf16ss.20_s2", ICLASS_AE_MULSF16SS_20_S2, + 0, + Opcode_ae_mulsf16ss_20_s2_encode_fns, 1, Opcode_ae_mulsf16ss_20_s2_funcUnit_uses }, + { "ae_mulsf16ss.11", ICLASS_AE_MULSF16SS_11, + 0, + Opcode_ae_mulsf16ss_11_encode_fns, 1, Opcode_ae_mulsf16ss_11_funcUnit_uses }, + { "ae_mulsf16ss.11_s2", ICLASS_AE_MULSF16SS_11_S2, + 0, + Opcode_ae_mulsf16ss_11_s2_encode_fns, 1, Opcode_ae_mulsf16ss_11_s2_funcUnit_uses }, + { "ae_mulsf16ss.00", ICLASS_AE_MULSF16SS_00, + 0, + Opcode_ae_mulsf16ss_00_encode_fns, 1, Opcode_ae_mulsf16ss_00_funcUnit_uses }, + { "ae_mulsf16ss.00_s2", ICLASS_AE_MULSF16SS_00_S2, + 0, + Opcode_ae_mulsf16ss_00_s2_encode_fns, 1, Opcode_ae_mulsf16ss_00_s2_funcUnit_uses }, + { "ae_mulaf16ss.33", ICLASS_AE_MULAF16SS_33, + 0, + Opcode_ae_mulaf16ss_33_encode_fns, 1, Opcode_ae_mulaf16ss_33_funcUnit_uses }, + { "ae_mulaf16ss.33_s2", ICLASS_AE_MULAF16SS_33_S2, + 0, + Opcode_ae_mulaf16ss_33_s2_encode_fns, 1, Opcode_ae_mulaf16ss_33_s2_funcUnit_uses }, + { "ae_mulaf16ss.22", ICLASS_AE_MULAF16SS_22, + 0, + Opcode_ae_mulaf16ss_22_encode_fns, 1, Opcode_ae_mulaf16ss_22_funcUnit_uses }, + { "ae_mulaf16ss.22_s2", ICLASS_AE_MULAF16SS_22_S2, + 0, + Opcode_ae_mulaf16ss_22_s2_encode_fns, 1, Opcode_ae_mulaf16ss_22_s2_funcUnit_uses }, + { "ae_mulaf16ss.32", ICLASS_AE_MULAF16SS_32, + 0, + Opcode_ae_mulaf16ss_32_encode_fns, 1, Opcode_ae_mulaf16ss_32_funcUnit_uses }, + { "ae_mulaf16ss.32_s2", ICLASS_AE_MULAF16SS_32_S2, + 0, + Opcode_ae_mulaf16ss_32_s2_encode_fns, 1, Opcode_ae_mulaf16ss_32_s2_funcUnit_uses }, + { "ae_mulaf16ss.21", ICLASS_AE_MULAF16SS_21, + 0, + Opcode_ae_mulaf16ss_21_encode_fns, 1, Opcode_ae_mulaf16ss_21_funcUnit_uses }, + { "ae_mulaf16ss.21_s2", ICLASS_AE_MULAF16SS_21_S2, + 0, + Opcode_ae_mulaf16ss_21_s2_encode_fns, 1, Opcode_ae_mulaf16ss_21_s2_funcUnit_uses }, + { "ae_mulaf16ss.31", ICLASS_AE_MULAF16SS_31, + 0, + Opcode_ae_mulaf16ss_31_encode_fns, 1, Opcode_ae_mulaf16ss_31_funcUnit_uses }, + { "ae_mulaf16ss.31_s2", ICLASS_AE_MULAF16SS_31_S2, + 0, + Opcode_ae_mulaf16ss_31_s2_encode_fns, 1, Opcode_ae_mulaf16ss_31_s2_funcUnit_uses }, + { "ae_mulaf16ss.30", ICLASS_AE_MULAF16SS_30, + 0, + Opcode_ae_mulaf16ss_30_encode_fns, 1, Opcode_ae_mulaf16ss_30_funcUnit_uses }, + { "ae_mulaf16ss.30_s2", ICLASS_AE_MULAF16SS_30_S2, + 0, + Opcode_ae_mulaf16ss_30_s2_encode_fns, 1, Opcode_ae_mulaf16ss_30_s2_funcUnit_uses }, + { "ae_mulaf16ss.10", ICLASS_AE_MULAF16SS_10, + 0, + Opcode_ae_mulaf16ss_10_encode_fns, 1, Opcode_ae_mulaf16ss_10_funcUnit_uses }, + { "ae_mulaf16ss.10_s2", ICLASS_AE_MULAF16SS_10_S2, + 0, + Opcode_ae_mulaf16ss_10_s2_encode_fns, 1, Opcode_ae_mulaf16ss_10_s2_funcUnit_uses }, + { "ae_mulaf16ss.20", ICLASS_AE_MULAF16SS_20, + 0, + Opcode_ae_mulaf16ss_20_encode_fns, 1, Opcode_ae_mulaf16ss_20_funcUnit_uses }, + { "ae_mulaf16ss.20_s2", ICLASS_AE_MULAF16SS_20_S2, + 0, + Opcode_ae_mulaf16ss_20_s2_encode_fns, 1, Opcode_ae_mulaf16ss_20_s2_funcUnit_uses }, + { "ae_mulaf16ss.11", ICLASS_AE_MULAF16SS_11, + 0, + Opcode_ae_mulaf16ss_11_encode_fns, 1, Opcode_ae_mulaf16ss_11_funcUnit_uses }, + { "ae_mulaf16ss.11_s2", ICLASS_AE_MULAF16SS_11_S2, + 0, + Opcode_ae_mulaf16ss_11_s2_encode_fns, 1, Opcode_ae_mulaf16ss_11_s2_funcUnit_uses }, + { "ae_mulaf16ss.00", ICLASS_AE_MULAF16SS_00, + 0, + Opcode_ae_mulaf16ss_00_encode_fns, 1, Opcode_ae_mulaf16ss_00_funcUnit_uses }, + { "ae_mulaf16ss.00_s2", ICLASS_AE_MULAF16SS_00_S2, + 0, + Opcode_ae_mulaf16ss_00_s2_encode_fns, 1, Opcode_ae_mulaf16ss_00_s2_funcUnit_uses }, + { "ae_mulaafd16ss.33_22", ICLASS_AE_MULAAFD16SS_33_22, + 0, + Opcode_ae_mulaafd16ss_33_22_encode_fns, 1, Opcode_ae_mulaafd16ss_33_22_funcUnit_uses }, + { "ae_mulaafd16ss.33_22_s2", ICLASS_AE_MULAAFD16SS_33_22_S2, + 0, + Opcode_ae_mulaafd16ss_33_22_s2_encode_fns, 1, Opcode_ae_mulaafd16ss_33_22_s2_funcUnit_uses }, + { "ae_mulaafd16ss.13_02", ICLASS_AE_MULAAFD16SS_13_02, + 0, + Opcode_ae_mulaafd16ss_13_02_encode_fns, 1, Opcode_ae_mulaafd16ss_13_02_funcUnit_uses }, + { "ae_mulaafd16ss.13_02_s2", ICLASS_AE_MULAAFD16SS_13_02_S2, + 0, + Opcode_ae_mulaafd16ss_13_02_s2_encode_fns, 1, Opcode_ae_mulaafd16ss_13_02_s2_funcUnit_uses }, + { "ae_mulaafd16ss.11_00", ICLASS_AE_MULAAFD16SS_11_00, + 0, + Opcode_ae_mulaafd16ss_11_00_encode_fns, 1, Opcode_ae_mulaafd16ss_11_00_funcUnit_uses }, + { "ae_mulaafd16ss.11_00_s2", ICLASS_AE_MULAAFD16SS_11_00_S2, + 0, + Opcode_ae_mulaafd16ss_11_00_s2_encode_fns, 1, Opcode_ae_mulaafd16ss_11_00_s2_funcUnit_uses }, + { "ae_mulssfd16ss.33_22", ICLASS_AE_MULSSFD16SS_33_22, + 0, + Opcode_ae_mulssfd16ss_33_22_encode_fns, 1, Opcode_ae_mulssfd16ss_33_22_funcUnit_uses }, + { "ae_mulssfd16ss.33_22_s2", ICLASS_AE_MULSSFD16SS_33_22_S2, + 0, + Opcode_ae_mulssfd16ss_33_22_s2_encode_fns, 1, Opcode_ae_mulssfd16ss_33_22_s2_funcUnit_uses }, + { "ae_mulssfd16ss.13_02", ICLASS_AE_MULSSFD16SS_13_02, + 0, + Opcode_ae_mulssfd16ss_13_02_encode_fns, 1, Opcode_ae_mulssfd16ss_13_02_funcUnit_uses }, + { "ae_mulssfd16ss.13_02_s2", ICLASS_AE_MULSSFD16SS_13_02_S2, + 0, + Opcode_ae_mulssfd16ss_13_02_s2_encode_fns, 1, Opcode_ae_mulssfd16ss_13_02_s2_funcUnit_uses }, + { "ae_mulssfd16ss.11_00", ICLASS_AE_MULSSFD16SS_11_00, + 0, + Opcode_ae_mulssfd16ss_11_00_encode_fns, 1, Opcode_ae_mulssfd16ss_11_00_funcUnit_uses }, + { "ae_mulssfd16ss.11_00_s2", ICLASS_AE_MULSSFD16SS_11_00_S2, + 0, + Opcode_ae_mulssfd16ss_11_00_s2_encode_fns, 1, Opcode_ae_mulssfd16ss_11_00_s2_funcUnit_uses }, + { "ae_mulzaafd16ss.33_22", ICLASS_AE_MULZAAFD16SS_33_22, + 0, + Opcode_ae_mulzaafd16ss_33_22_encode_fns, 1, Opcode_ae_mulzaafd16ss_33_22_funcUnit_uses }, + { "ae_mulzaafd16ss.33_22_s2", ICLASS_AE_MULZAAFD16SS_33_22_S2, + 0, + Opcode_ae_mulzaafd16ss_33_22_s2_encode_fns, 1, Opcode_ae_mulzaafd16ss_33_22_s2_funcUnit_uses }, + { "ae_mulzaafd16ss.13_02", ICLASS_AE_MULZAAFD16SS_13_02, + 0, + Opcode_ae_mulzaafd16ss_13_02_encode_fns, 1, Opcode_ae_mulzaafd16ss_13_02_funcUnit_uses }, + { "ae_mulzaafd16ss.13_02_s2", ICLASS_AE_MULZAAFD16SS_13_02_S2, + 0, + Opcode_ae_mulzaafd16ss_13_02_s2_encode_fns, 1, Opcode_ae_mulzaafd16ss_13_02_s2_funcUnit_uses }, + { "ae_mulzaafd16ss.11_00", ICLASS_AE_MULZAAFD16SS_11_00, + 0, + Opcode_ae_mulzaafd16ss_11_00_encode_fns, 1, Opcode_ae_mulzaafd16ss_11_00_funcUnit_uses }, + { "ae_mulzaafd16ss.11_00_s2", ICLASS_AE_MULZAAFD16SS_11_00_S2, + 0, + Opcode_ae_mulzaafd16ss_11_00_s2_encode_fns, 1, Opcode_ae_mulzaafd16ss_11_00_s2_funcUnit_uses }, + { "ae_mulzssfd16ss.33_22", ICLASS_AE_MULZSSFD16SS_33_22, + 0, + Opcode_ae_mulzssfd16ss_33_22_encode_fns, 1, Opcode_ae_mulzssfd16ss_33_22_funcUnit_uses }, + { "ae_mulzssfd16ss.33_22_s2", ICLASS_AE_MULZSSFD16SS_33_22_S2, + 0, + Opcode_ae_mulzssfd16ss_33_22_s2_encode_fns, 1, Opcode_ae_mulzssfd16ss_33_22_s2_funcUnit_uses }, + { "ae_mulzssfd16ss.13_02", ICLASS_AE_MULZSSFD16SS_13_02, + 0, + Opcode_ae_mulzssfd16ss_13_02_encode_fns, 1, Opcode_ae_mulzssfd16ss_13_02_funcUnit_uses }, + { "ae_mulzssfd16ss.13_02_s2", ICLASS_AE_MULZSSFD16SS_13_02_S2, + 0, + Opcode_ae_mulzssfd16ss_13_02_s2_encode_fns, 1, Opcode_ae_mulzssfd16ss_13_02_s2_funcUnit_uses }, + { "ae_mulzssfd16ss.11_00", ICLASS_AE_MULZSSFD16SS_11_00, + 0, + Opcode_ae_mulzssfd16ss_11_00_encode_fns, 1, Opcode_ae_mulzssfd16ss_11_00_funcUnit_uses }, + { "ae_mulzssfd16ss.11_00_s2", ICLASS_AE_MULZSSFD16SS_11_00_S2, + 0, + Opcode_ae_mulzssfd16ss_11_00_s2_encode_fns, 1, Opcode_ae_mulzssfd16ss_11_00_s2_funcUnit_uses }, + { "ae_mulf48q32sp16s.l", ICLASS_AE_MULF48Q32SP16S_L, + 0, + Opcode_ae_mulf48q32sp16s_l_encode_fns, 1, Opcode_ae_mulf48q32sp16s_l_funcUnit_uses }, + { "ae_mulf48q32sp16s.l_s2", ICLASS_AE_MULF48Q32SP16S_L_S2, + 0, + Opcode_ae_mulf48q32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulf48q32sp16s_l_s2_funcUnit_uses }, + { "ae_mulf48q32sp16u.l", ICLASS_AE_MULF48Q32SP16U_L, + 0, + Opcode_ae_mulf48q32sp16u_l_encode_fns, 1, Opcode_ae_mulf48q32sp16u_l_funcUnit_uses }, + { "ae_mulf48q32sp16u.l_s2", ICLASS_AE_MULF48Q32SP16U_L_S2, + 0, + Opcode_ae_mulf48q32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulf48q32sp16u_l_s2_funcUnit_uses }, + { "ae_mulq32sp16s.l", ICLASS_AE_MULQ32SP16S_L, + 0, + Opcode_ae_mulq32sp16s_l_encode_fns, 1, Opcode_ae_mulq32sp16s_l_funcUnit_uses }, + { "ae_mulq32sp16s.l_s2", ICLASS_AE_MULQ32SP16S_L_S2, + 0, + Opcode_ae_mulq32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulq32sp16s_l_s2_funcUnit_uses }, + { "ae_mulq32sp16u.l", ICLASS_AE_MULQ32SP16U_L, + 0, + Opcode_ae_mulq32sp16u_l_encode_fns, 1, Opcode_ae_mulq32sp16u_l_funcUnit_uses }, + { "ae_mulq32sp16u.l_s2", ICLASS_AE_MULQ32SP16U_L_S2, + 0, + Opcode_ae_mulq32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulq32sp16u_l_s2_funcUnit_uses }, + { "ae_mulaf48q32sp16s.l", ICLASS_AE_MULAF48Q32SP16S_L, + 0, + Opcode_ae_mulaf48q32sp16s_l_encode_fns, 1, Opcode_ae_mulaf48q32sp16s_l_funcUnit_uses }, + { "ae_mulaf48q32sp16s.l_s2", ICLASS_AE_MULAF48Q32SP16S_L_S2, + 0, + Opcode_ae_mulaf48q32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulaf48q32sp16s_l_s2_funcUnit_uses }, + { "ae_mulaf48q32sp16u.l", ICLASS_AE_MULAF48Q32SP16U_L, + 0, + Opcode_ae_mulaf48q32sp16u_l_encode_fns, 1, Opcode_ae_mulaf48q32sp16u_l_funcUnit_uses }, + { "ae_mulaf48q32sp16u.l_s2", ICLASS_AE_MULAF48Q32SP16U_L_S2, + 0, + Opcode_ae_mulaf48q32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulaf48q32sp16u_l_s2_funcUnit_uses }, + { "ae_mulaq32sp16s.l", ICLASS_AE_MULAQ32SP16S_L, + 0, + Opcode_ae_mulaq32sp16s_l_encode_fns, 1, Opcode_ae_mulaq32sp16s_l_funcUnit_uses }, + { "ae_mulaq32sp16s.l_s2", ICLASS_AE_MULAQ32SP16S_L_S2, + 0, + Opcode_ae_mulaq32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulaq32sp16s_l_s2_funcUnit_uses }, + { "ae_mulaq32sp16u.l", ICLASS_AE_MULAQ32SP16U_L, + 0, + Opcode_ae_mulaq32sp16u_l_encode_fns, 1, Opcode_ae_mulaq32sp16u_l_funcUnit_uses }, + { "ae_mulaq32sp16u.l_s2", ICLASS_AE_MULAQ32SP16U_L_S2, + 0, + Opcode_ae_mulaq32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulaq32sp16u_l_s2_funcUnit_uses }, + { "ae_mulsf48q32sp16s.l", ICLASS_AE_MULSF48Q32SP16S_L, + 0, + Opcode_ae_mulsf48q32sp16s_l_encode_fns, 1, Opcode_ae_mulsf48q32sp16s_l_funcUnit_uses }, + { "ae_mulsf48q32sp16s.l_s2", ICLASS_AE_MULSF48Q32SP16S_L_S2, + 0, + Opcode_ae_mulsf48q32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulsf48q32sp16s_l_s2_funcUnit_uses }, + { "ae_mulsf48q32sp16u.l", ICLASS_AE_MULSF48Q32SP16U_L, + 0, + Opcode_ae_mulsf48q32sp16u_l_encode_fns, 1, Opcode_ae_mulsf48q32sp16u_l_funcUnit_uses }, + { "ae_mulsf48q32sp16u.l_s2", ICLASS_AE_MULSF48Q32SP16U_L_S2, + 0, + Opcode_ae_mulsf48q32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulsf48q32sp16u_l_s2_funcUnit_uses }, + { "ae_mulsq32sp16s.l", ICLASS_AE_MULSQ32SP16S_L, + 0, + Opcode_ae_mulsq32sp16s_l_encode_fns, 1, Opcode_ae_mulsq32sp16s_l_funcUnit_uses }, + { "ae_mulsq32sp16s.l_s2", ICLASS_AE_MULSQ32SP16S_L_S2, + 0, + Opcode_ae_mulsq32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulsq32sp16s_l_s2_funcUnit_uses }, + { "ae_mulsq32sp16u.l", ICLASS_AE_MULSQ32SP16U_L, + 0, + Opcode_ae_mulsq32sp16u_l_encode_fns, 1, Opcode_ae_mulsq32sp16u_l_funcUnit_uses }, + { "ae_mulsq32sp16u.l_s2", ICLASS_AE_MULSQ32SP16U_L_S2, + 0, + Opcode_ae_mulsq32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulsq32sp16u_l_s2_funcUnit_uses }, + { "ae_mulfp24x2ra", ICLASS_AE_MULFP24X2RA, + 0, + Opcode_ae_mulfp24x2ra_encode_fns, 1, Opcode_ae_mulfp24x2ra_funcUnit_uses }, + { "ae_mulfp24x2r", ICLASS_AE_MULFP24X2R, + 0, + Opcode_ae_mulfp24x2r_encode_fns, 1, Opcode_ae_mulfp24x2r_funcUnit_uses }, + { "ae_mulfp24x2ra_s2", ICLASS_AE_MULFP24X2RA_S2, + 0, + Opcode_ae_mulfp24x2ra_s2_encode_fns, 1, Opcode_ae_mulfp24x2ra_s2_funcUnit_uses }, + { "ae_mulfp24x2r_s2", ICLASS_AE_MULFP24X2R_S2, + 0, + Opcode_ae_mulfp24x2r_s2_encode_fns, 1, Opcode_ae_mulfp24x2r_s2_funcUnit_uses }, + { "ae_mulafp24x2ra", ICLASS_AE_MULAFP24X2RA, + 0, + Opcode_ae_mulafp24x2ra_encode_fns, 1, Opcode_ae_mulafp24x2ra_funcUnit_uses }, + { "ae_mulafp24x2r", ICLASS_AE_MULAFP24X2R, + 0, + Opcode_ae_mulafp24x2r_encode_fns, 1, Opcode_ae_mulafp24x2r_funcUnit_uses }, + { "ae_mulafp24x2ra_s2", ICLASS_AE_MULAFP24X2RA_S2, + 0, + Opcode_ae_mulafp24x2ra_s2_encode_fns, 1, Opcode_ae_mulafp24x2ra_s2_funcUnit_uses }, + { "ae_mulafp24x2r_s2", ICLASS_AE_MULAFP24X2R_S2, + 0, + Opcode_ae_mulafp24x2r_s2_encode_fns, 1, Opcode_ae_mulafp24x2r_s2_funcUnit_uses }, + { "ae_mulsfp24x2ra", ICLASS_AE_MULSFP24X2RA, + 0, + Opcode_ae_mulsfp24x2ra_encode_fns, 1, Opcode_ae_mulsfp24x2ra_funcUnit_uses }, + { "ae_mulsfp24x2r", ICLASS_AE_MULSFP24X2R, + 0, + Opcode_ae_mulsfp24x2r_encode_fns, 1, Opcode_ae_mulsfp24x2r_funcUnit_uses }, + { "ae_mulsfp24x2ra_s2", ICLASS_AE_MULSFP24X2RA_S2, + 0, + Opcode_ae_mulsfp24x2ra_s2_encode_fns, 1, Opcode_ae_mulsfp24x2ra_s2_funcUnit_uses }, + { "ae_mulsfp24x2r_s2", ICLASS_AE_MULSFP24X2R_S2, + 0, + Opcode_ae_mulsfp24x2r_s2_encode_fns, 1, Opcode_ae_mulsfp24x2r_s2_funcUnit_uses }, + { "ae_mulzaafd32s.hh.ll", ICLASS_AE_MULZAAFD32S_HH_LL, + 0, + Opcode_ae_mulzaafd32s_hh_ll_encode_fns, 1, Opcode_ae_mulzaafd32s_hh_ll_funcUnit_uses }, + { "ae_mulzaafd32ra.hh.ll", ICLASS_AE_MULZAAFD32RA_HH_LL, + 0, + Opcode_ae_mulzaafd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulzaafd32ra_hh_ll_funcUnit_uses }, + { "ae_mulzaad32.hh.ll", ICLASS_AE_MULZAAD32_HH_LL, + 0, + Opcode_ae_mulzaad32_hh_ll_encode_fns, 1, Opcode_ae_mulzaad32_hh_ll_funcUnit_uses }, + { "ae_mulzaafd32s.hh.ll_s2", ICLASS_AE_MULZAAFD32S_HH_LL_S2, + 0, + Opcode_ae_mulzaafd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzaafd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulzaafd32ra.hh.ll_s2", ICLASS_AE_MULZAAFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulzaafd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzaafd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulzaad32.hh.ll_s2", ICLASS_AE_MULZAAD32_HH_LL_S2, + 0, + Opcode_ae_mulzaad32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzaad32_hh_ll_s2_funcUnit_uses }, + { "ae_mulzaafd32s.hl.lh", ICLASS_AE_MULZAAFD32S_HL_LH, + 0, + Opcode_ae_mulzaafd32s_hl_lh_encode_fns, 1, Opcode_ae_mulzaafd32s_hl_lh_funcUnit_uses }, + { "ae_mulzaafd32ra.hl.lh", ICLASS_AE_MULZAAFD32RA_HL_LH, + 0, + Opcode_ae_mulzaafd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulzaafd32ra_hl_lh_funcUnit_uses }, + { "ae_mulzaad32.hl.lh", ICLASS_AE_MULZAAD32_HL_LH, + 0, + Opcode_ae_mulzaad32_hl_lh_encode_fns, 1, Opcode_ae_mulzaad32_hl_lh_funcUnit_uses }, + { "ae_mulzaafd32s.hl.lh_s2", ICLASS_AE_MULZAAFD32S_HL_LH_S2, + 0, + Opcode_ae_mulzaafd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzaafd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulzaafd32ra.hl.lh_s2", ICLASS_AE_MULZAAFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulzaafd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzaafd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulzaad32.hl.lh_s2", ICLASS_AE_MULZAAD32_HL_LH_S2, + 0, + Opcode_ae_mulzaad32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzaad32_hl_lh_s2_funcUnit_uses }, + { "ae_mulzasfd32s.hh.ll", ICLASS_AE_MULZASFD32S_HH_LL, + 0, + Opcode_ae_mulzasfd32s_hh_ll_encode_fns, 1, Opcode_ae_mulzasfd32s_hh_ll_funcUnit_uses }, + { "ae_mulzasfd32ra.hh.ll", ICLASS_AE_MULZASFD32RA_HH_LL, + 0, + Opcode_ae_mulzasfd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulzasfd32ra_hh_ll_funcUnit_uses }, + { "ae_mulzasd32.hh.ll", ICLASS_AE_MULZASD32_HH_LL, + 0, + Opcode_ae_mulzasd32_hh_ll_encode_fns, 1, Opcode_ae_mulzasd32_hh_ll_funcUnit_uses }, + { "ae_mulzasfd32s.hh.ll_s2", ICLASS_AE_MULZASFD32S_HH_LL_S2, + 0, + Opcode_ae_mulzasfd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzasfd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulzasfd32ra.hh.ll_s2", ICLASS_AE_MULZASFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulzasfd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzasfd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulzasd32.hh.ll_s2", ICLASS_AE_MULZASD32_HH_LL_S2, + 0, + Opcode_ae_mulzasd32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzasd32_hh_ll_s2_funcUnit_uses }, + { "ae_mulzasfd32s.hl.lh", ICLASS_AE_MULZASFD32S_HL_LH, + 0, + Opcode_ae_mulzasfd32s_hl_lh_encode_fns, 1, Opcode_ae_mulzasfd32s_hl_lh_funcUnit_uses }, + { "ae_mulzasfd32ra.hl.lh", ICLASS_AE_MULZASFD32RA_HL_LH, + 0, + Opcode_ae_mulzasfd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulzasfd32ra_hl_lh_funcUnit_uses }, + { "ae_mulzasd32.hl.lh", ICLASS_AE_MULZASD32_HL_LH, + 0, + Opcode_ae_mulzasd32_hl_lh_encode_fns, 1, Opcode_ae_mulzasd32_hl_lh_funcUnit_uses }, + { "ae_mulzasfd32s.hl.lh_s2", ICLASS_AE_MULZASFD32S_HL_LH_S2, + 0, + Opcode_ae_mulzasfd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzasfd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulzasfd32ra.hl.lh_s2", ICLASS_AE_MULZASFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulzasfd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzasfd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulzasd32.hl.lh_s2", ICLASS_AE_MULZASD32_HL_LH_S2, + 0, + Opcode_ae_mulzasd32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzasd32_hl_lh_s2_funcUnit_uses }, + { "ae_mulzsafd32s.hh.ll", ICLASS_AE_MULZSAFD32S_HH_LL, + 0, + Opcode_ae_mulzsafd32s_hh_ll_encode_fns, 1, Opcode_ae_mulzsafd32s_hh_ll_funcUnit_uses }, + { "ae_mulzsafd32ra.hh.ll", ICLASS_AE_MULZSAFD32RA_HH_LL, + 0, + Opcode_ae_mulzsafd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulzsafd32ra_hh_ll_funcUnit_uses }, + { "ae_mulzsad32.hh.ll", ICLASS_AE_MULZSAD32_HH_LL, + 0, + Opcode_ae_mulzsad32_hh_ll_encode_fns, 1, Opcode_ae_mulzsad32_hh_ll_funcUnit_uses }, + { "ae_mulzsafd32s.hh.ll_s2", ICLASS_AE_MULZSAFD32S_HH_LL_S2, + 0, + Opcode_ae_mulzsafd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzsafd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulzsafd32ra.hh.ll_s2", ICLASS_AE_MULZSAFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulzsafd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzsafd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulzsad32.hh.ll_s2", ICLASS_AE_MULZSAD32_HH_LL_S2, + 0, + Opcode_ae_mulzsad32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzsad32_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssfd32s.hh.ll", ICLASS_AE_MULZSSFD32S_HH_LL, + 0, + Opcode_ae_mulzssfd32s_hh_ll_encode_fns, 1, Opcode_ae_mulzssfd32s_hh_ll_funcUnit_uses }, + { "ae_mulzssfd32ra.hh.ll", ICLASS_AE_MULZSSFD32RA_HH_LL, + 0, + Opcode_ae_mulzssfd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulzssfd32ra_hh_ll_funcUnit_uses }, + { "ae_mulzssd32.hh.ll", ICLASS_AE_MULZSSD32_HH_LL, + 0, + Opcode_ae_mulzssd32_hh_ll_encode_fns, 1, Opcode_ae_mulzssd32_hh_ll_funcUnit_uses }, + { "ae_mulzssfd32s.hh.ll_s2", ICLASS_AE_MULZSSFD32S_HH_LL_S2, + 0, + Opcode_ae_mulzssfd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzssfd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssfd32ra.hh.ll_s2", ICLASS_AE_MULZSSFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulzssfd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzssfd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssd32.hh.ll_s2", ICLASS_AE_MULZSSD32_HH_LL_S2, + 0, + Opcode_ae_mulzssd32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzssd32_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssfd32s.hl.lh", ICLASS_AE_MULZSSFD32S_HL_LH, + 0, + Opcode_ae_mulzssfd32s_hl_lh_encode_fns, 1, Opcode_ae_mulzssfd32s_hl_lh_funcUnit_uses }, + { "ae_mulzssfd32ra.hl.lh", ICLASS_AE_MULZSSFD32RA_HL_LH, + 0, + Opcode_ae_mulzssfd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulzssfd32ra_hl_lh_funcUnit_uses }, + { "ae_mulzssd32.hl.lh", ICLASS_AE_MULZSSD32_HL_LH, + 0, + Opcode_ae_mulzssd32_hl_lh_encode_fns, 1, Opcode_ae_mulzssd32_hl_lh_funcUnit_uses }, + { "ae_mulzssfd32s.hl.lh_s2", ICLASS_AE_MULZSSFD32S_HL_LH_S2, + 0, + Opcode_ae_mulzssfd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzssfd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulzssfd32ra.hl.lh_s2", ICLASS_AE_MULZSSFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulzssfd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzssfd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulzssd32.hl.lh_s2", ICLASS_AE_MULZSSD32_HL_LH_S2, + 0, + Opcode_ae_mulzssd32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzssd32_hl_lh_s2_funcUnit_uses }, + { "ae_mulaafd32s.hh.ll", ICLASS_AE_MULAAFD32S_HH_LL, + 0, + Opcode_ae_mulaafd32s_hh_ll_encode_fns, 1, Opcode_ae_mulaafd32s_hh_ll_funcUnit_uses }, + { "ae_mulaafd32ra.hh.ll", ICLASS_AE_MULAAFD32RA_HH_LL, + 0, + Opcode_ae_mulaafd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulaafd32ra_hh_ll_funcUnit_uses }, + { "ae_mulaad32.hh.ll", ICLASS_AE_MULAAD32_HH_LL, + 0, + Opcode_ae_mulaad32_hh_ll_encode_fns, 1, Opcode_ae_mulaad32_hh_ll_funcUnit_uses }, + { "ae_mulaafd32s.hh.ll_s2", ICLASS_AE_MULAAFD32S_HH_LL_S2, + 0, + Opcode_ae_mulaafd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulaafd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulaafd32ra.hh.ll_s2", ICLASS_AE_MULAAFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulaafd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulaafd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulaad32.hh.ll_s2", ICLASS_AE_MULAAD32_HH_LL_S2, + 0, + Opcode_ae_mulaad32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulaad32_hh_ll_s2_funcUnit_uses }, + { "ae_mulaafd32s.hl.lh", ICLASS_AE_MULAAFD32S_HL_LH, + 0, + Opcode_ae_mulaafd32s_hl_lh_encode_fns, 1, Opcode_ae_mulaafd32s_hl_lh_funcUnit_uses }, + { "ae_mulaafd32ra.hl.lh", ICLASS_AE_MULAAFD32RA_HL_LH, + 0, + Opcode_ae_mulaafd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulaafd32ra_hl_lh_funcUnit_uses }, + { "ae_mulaad32.hl.lh", ICLASS_AE_MULAAD32_HL_LH, + 0, + Opcode_ae_mulaad32_hl_lh_encode_fns, 1, Opcode_ae_mulaad32_hl_lh_funcUnit_uses }, + { "ae_mulaafd32s.hl.lh_s2", ICLASS_AE_MULAAFD32S_HL_LH_S2, + 0, + Opcode_ae_mulaafd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulaafd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulaafd32ra.hl.lh_s2", ICLASS_AE_MULAAFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulaafd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulaafd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulaad32.hl.lh_s2", ICLASS_AE_MULAAD32_HL_LH_S2, + 0, + Opcode_ae_mulaad32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulaad32_hl_lh_s2_funcUnit_uses }, + { "ae_mulasfd32s.hh.ll", ICLASS_AE_MULASFD32S_HH_LL, + 0, + Opcode_ae_mulasfd32s_hh_ll_encode_fns, 1, Opcode_ae_mulasfd32s_hh_ll_funcUnit_uses }, + { "ae_mulasfd32ra.hh.ll", ICLASS_AE_MULASFD32RA_HH_LL, + 0, + Opcode_ae_mulasfd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulasfd32ra_hh_ll_funcUnit_uses }, + { "ae_mulasd32.hh.ll", ICLASS_AE_MULASD32_HH_LL, + 0, + Opcode_ae_mulasd32_hh_ll_encode_fns, 1, Opcode_ae_mulasd32_hh_ll_funcUnit_uses }, + { "ae_mulasfd32s.hh.ll_s2", ICLASS_AE_MULASFD32S_HH_LL_S2, + 0, + Opcode_ae_mulasfd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulasfd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulasfd32ra.hh.ll_s2", ICLASS_AE_MULASFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulasfd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulasfd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulasd32.hh.ll_s2", ICLASS_AE_MULASD32_HH_LL_S2, + 0, + Opcode_ae_mulasd32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulasd32_hh_ll_s2_funcUnit_uses }, + { "ae_mulasfd32s.hl.lh", ICLASS_AE_MULASFD32S_HL_LH, + 0, + Opcode_ae_mulasfd32s_hl_lh_encode_fns, 1, Opcode_ae_mulasfd32s_hl_lh_funcUnit_uses }, + { "ae_mulasfd32ra.hl.lh", ICLASS_AE_MULASFD32RA_HL_LH, + 0, + Opcode_ae_mulasfd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulasfd32ra_hl_lh_funcUnit_uses }, + { "ae_mulasd32.hl.lh", ICLASS_AE_MULASD32_HL_LH, + 0, + Opcode_ae_mulasd32_hl_lh_encode_fns, 1, Opcode_ae_mulasd32_hl_lh_funcUnit_uses }, + { "ae_mulasfd32s.hl.lh_s2", ICLASS_AE_MULASFD32S_HL_LH_S2, + 0, + Opcode_ae_mulasfd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulasfd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulasfd32ra.hl.lh_s2", ICLASS_AE_MULASFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulasfd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulasfd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulasd32.hl.lh_s2", ICLASS_AE_MULASD32_HL_LH_S2, + 0, + Opcode_ae_mulasd32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulasd32_hl_lh_s2_funcUnit_uses }, + { "ae_mulsafd32s.hh.ll", ICLASS_AE_MULSAFD32S_HH_LL, + 0, + Opcode_ae_mulsafd32s_hh_ll_encode_fns, 1, Opcode_ae_mulsafd32s_hh_ll_funcUnit_uses }, + { "ae_mulsafd32ra.hh.ll", ICLASS_AE_MULSAFD32RA_HH_LL, + 0, + Opcode_ae_mulsafd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulsafd32ra_hh_ll_funcUnit_uses }, + { "ae_mulsad32.hh.ll", ICLASS_AE_MULSAD32_HH_LL, + 0, + Opcode_ae_mulsad32_hh_ll_encode_fns, 1, Opcode_ae_mulsad32_hh_ll_funcUnit_uses }, + { "ae_mulsafd32s.hh.ll_s2", ICLASS_AE_MULSAFD32S_HH_LL_S2, + 0, + Opcode_ae_mulsafd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulsafd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulsafd32ra.hh.ll_s2", ICLASS_AE_MULSAFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulsafd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulsafd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulsad32.hh.ll_s2", ICLASS_AE_MULSAD32_HH_LL_S2, + 0, + Opcode_ae_mulsad32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulsad32_hh_ll_s2_funcUnit_uses }, + { "ae_mulssfd32s.hh.ll", ICLASS_AE_MULSSFD32S_HH_LL, + 0, + Opcode_ae_mulssfd32s_hh_ll_encode_fns, 1, Opcode_ae_mulssfd32s_hh_ll_funcUnit_uses }, + { "ae_mulssfd32ra.hh.ll", ICLASS_AE_MULSSFD32RA_HH_LL, + 0, + Opcode_ae_mulssfd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulssfd32ra_hh_ll_funcUnit_uses }, + { "ae_mulssd32.hh.ll", ICLASS_AE_MULSSD32_HH_LL, + 0, + Opcode_ae_mulssd32_hh_ll_encode_fns, 1, Opcode_ae_mulssd32_hh_ll_funcUnit_uses }, + { "ae_mulssfd32s.hh.ll_s2", ICLASS_AE_MULSSFD32S_HH_LL_S2, + 0, + Opcode_ae_mulssfd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulssfd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulssfd32ra.hh.ll_s2", ICLASS_AE_MULSSFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulssfd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulssfd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulssd32.hh.ll_s2", ICLASS_AE_MULSSD32_HH_LL_S2, + 0, + Opcode_ae_mulssd32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulssd32_hh_ll_s2_funcUnit_uses }, + { "ae_mulssfd32s.hl.lh", ICLASS_AE_MULSSFD32S_HL_LH, + 0, + Opcode_ae_mulssfd32s_hl_lh_encode_fns, 1, Opcode_ae_mulssfd32s_hl_lh_funcUnit_uses }, + { "ae_mulssfd32ra.hl.lh", ICLASS_AE_MULSSFD32RA_HL_LH, + 0, + Opcode_ae_mulssfd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulssfd32ra_hl_lh_funcUnit_uses }, + { "ae_mulssd32.hl.lh", ICLASS_AE_MULSSD32_HL_LH, + 0, + Opcode_ae_mulssd32_hl_lh_encode_fns, 1, Opcode_ae_mulssd32_hl_lh_funcUnit_uses }, + { "ae_mulssfd32s.hl.lh_s2", ICLASS_AE_MULSSFD32S_HL_LH_S2, + 0, + Opcode_ae_mulssfd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulssfd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulssfd32ra.hl.lh_s2", ICLASS_AE_MULSSFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulssfd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulssfd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulssd32.hl.lh_s2", ICLASS_AE_MULSSD32_HL_LH_S2, + 0, + Opcode_ae_mulssd32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulssd32_hl_lh_s2_funcUnit_uses }, + { "ae_mulf32x16.l0", ICLASS_AE_MULF32X16_L0, + 0, + Opcode_ae_mulf32x16_l0_encode_fns, 1, Opcode_ae_mulf32x16_l0_funcUnit_uses }, + { "ae_mul32x16.l0", ICLASS_AE_MUL32X16_L0, + 0, + Opcode_ae_mul32x16_l0_encode_fns, 1, Opcode_ae_mul32x16_l0_funcUnit_uses }, + { "ae_mulf32x16.l0_s2", ICLASS_AE_MULF32X16_L0_S2, + 0, + Opcode_ae_mulf32x16_l0_s2_encode_fns, 1, Opcode_ae_mulf32x16_l0_s2_funcUnit_uses }, + { "ae_mul32x16.l0_s2", ICLASS_AE_MUL32X16_L0_S2, + 0, + Opcode_ae_mul32x16_l0_s2_encode_fns, 1, Opcode_ae_mul32x16_l0_s2_funcUnit_uses }, + { "ae_mulf32x16.l1", ICLASS_AE_MULF32X16_L1, + 0, + Opcode_ae_mulf32x16_l1_encode_fns, 1, Opcode_ae_mulf32x16_l1_funcUnit_uses }, + { "ae_mul32x16.l1", ICLASS_AE_MUL32X16_L1, + 0, + Opcode_ae_mul32x16_l1_encode_fns, 1, Opcode_ae_mul32x16_l1_funcUnit_uses }, + { "ae_mulf32x16.l1_s2", ICLASS_AE_MULF32X16_L1_S2, + 0, + Opcode_ae_mulf32x16_l1_s2_encode_fns, 1, Opcode_ae_mulf32x16_l1_s2_funcUnit_uses }, + { "ae_mul32x16.l1_s2", ICLASS_AE_MUL32X16_L1_S2, + 0, + Opcode_ae_mul32x16_l1_s2_encode_fns, 1, Opcode_ae_mul32x16_l1_s2_funcUnit_uses }, + { "ae_mulf32x16.l2", ICLASS_AE_MULF32X16_L2, + 0, + Opcode_ae_mulf32x16_l2_encode_fns, 1, Opcode_ae_mulf32x16_l2_funcUnit_uses }, + { "ae_mul32x16.l2", ICLASS_AE_MUL32X16_L2, + 0, + Opcode_ae_mul32x16_l2_encode_fns, 1, Opcode_ae_mul32x16_l2_funcUnit_uses }, + { "ae_mulf32x16.l2_s2", ICLASS_AE_MULF32X16_L2_S2, + 0, + Opcode_ae_mulf32x16_l2_s2_encode_fns, 1, Opcode_ae_mulf32x16_l2_s2_funcUnit_uses }, + { "ae_mul32x16.l2_s2", ICLASS_AE_MUL32X16_L2_S2, + 0, + Opcode_ae_mul32x16_l2_s2_encode_fns, 1, Opcode_ae_mul32x16_l2_s2_funcUnit_uses }, + { "ae_mulf32x16.l3", ICLASS_AE_MULF32X16_L3, + 0, + Opcode_ae_mulf32x16_l3_encode_fns, 1, Opcode_ae_mulf32x16_l3_funcUnit_uses }, + { "ae_mul32x16.l3", ICLASS_AE_MUL32X16_L3, + 0, + Opcode_ae_mul32x16_l3_encode_fns, 1, Opcode_ae_mul32x16_l3_funcUnit_uses }, + { "ae_mulf32x16.l3_s2", ICLASS_AE_MULF32X16_L3_S2, + 0, + Opcode_ae_mulf32x16_l3_s2_encode_fns, 1, Opcode_ae_mulf32x16_l3_s2_funcUnit_uses }, + { "ae_mul32x16.l3_s2", ICLASS_AE_MUL32X16_L3_S2, + 0, + Opcode_ae_mul32x16_l3_s2_encode_fns, 1, Opcode_ae_mul32x16_l3_s2_funcUnit_uses }, + { "ae_mulf32x16.h0", ICLASS_AE_MULF32X16_H0, + 0, + Opcode_ae_mulf32x16_h0_encode_fns, 1, Opcode_ae_mulf32x16_h0_funcUnit_uses }, + { "ae_mul32x16.h0", ICLASS_AE_MUL32X16_H0, + 0, + Opcode_ae_mul32x16_h0_encode_fns, 1, Opcode_ae_mul32x16_h0_funcUnit_uses }, + { "ae_mulf32x16.h0_s2", ICLASS_AE_MULF32X16_H0_S2, + 0, + Opcode_ae_mulf32x16_h0_s2_encode_fns, 1, Opcode_ae_mulf32x16_h0_s2_funcUnit_uses }, + { "ae_mul32x16.h0_s2", ICLASS_AE_MUL32X16_H0_S2, + 0, + Opcode_ae_mul32x16_h0_s2_encode_fns, 1, Opcode_ae_mul32x16_h0_s2_funcUnit_uses }, + { "ae_mulf32x16.h1", ICLASS_AE_MULF32X16_H1, + 0, + Opcode_ae_mulf32x16_h1_encode_fns, 1, Opcode_ae_mulf32x16_h1_funcUnit_uses }, + { "ae_mul32x16.h1", ICLASS_AE_MUL32X16_H1, + 0, + Opcode_ae_mul32x16_h1_encode_fns, 1, Opcode_ae_mul32x16_h1_funcUnit_uses }, + { "ae_mulf32x16.h1_s2", ICLASS_AE_MULF32X16_H1_S2, + 0, + Opcode_ae_mulf32x16_h1_s2_encode_fns, 1, Opcode_ae_mulf32x16_h1_s2_funcUnit_uses }, + { "ae_mul32x16.h1_s2", ICLASS_AE_MUL32X16_H1_S2, + 0, + Opcode_ae_mul32x16_h1_s2_encode_fns, 1, Opcode_ae_mul32x16_h1_s2_funcUnit_uses }, + { "ae_mulf32x16.h2", ICLASS_AE_MULF32X16_H2, + 0, + Opcode_ae_mulf32x16_h2_encode_fns, 1, Opcode_ae_mulf32x16_h2_funcUnit_uses }, + { "ae_mul32x16.h2", ICLASS_AE_MUL32X16_H2, + 0, + Opcode_ae_mul32x16_h2_encode_fns, 1, Opcode_ae_mul32x16_h2_funcUnit_uses }, + { "ae_mulf32x16.h2_s2", ICLASS_AE_MULF32X16_H2_S2, + 0, + Opcode_ae_mulf32x16_h2_s2_encode_fns, 1, Opcode_ae_mulf32x16_h2_s2_funcUnit_uses }, + { "ae_mul32x16.h2_s2", ICLASS_AE_MUL32X16_H2_S2, + 0, + Opcode_ae_mul32x16_h2_s2_encode_fns, 1, Opcode_ae_mul32x16_h2_s2_funcUnit_uses }, + { "ae_mulf32x16.h3", ICLASS_AE_MULF32X16_H3, + 0, + Opcode_ae_mulf32x16_h3_encode_fns, 1, Opcode_ae_mulf32x16_h3_funcUnit_uses }, + { "ae_mul32x16.h3", ICLASS_AE_MUL32X16_H3, + 0, + Opcode_ae_mul32x16_h3_encode_fns, 1, Opcode_ae_mul32x16_h3_funcUnit_uses }, + { "ae_mulf32x16.h3_s2", ICLASS_AE_MULF32X16_H3_S2, + 0, + Opcode_ae_mulf32x16_h3_s2_encode_fns, 1, Opcode_ae_mulf32x16_h3_s2_funcUnit_uses }, + { "ae_mul32x16.h3_s2", ICLASS_AE_MUL32X16_H3_S2, + 0, + Opcode_ae_mul32x16_h3_s2_encode_fns, 1, Opcode_ae_mul32x16_h3_s2_funcUnit_uses }, + { "ae_mulaf32x16.l0", ICLASS_AE_MULAF32X16_L0, + 0, + Opcode_ae_mulaf32x16_l0_encode_fns, 1, Opcode_ae_mulaf32x16_l0_funcUnit_uses }, + { "ae_mula32x16.l0", ICLASS_AE_MULA32X16_L0, + 0, + Opcode_ae_mula32x16_l0_encode_fns, 1, Opcode_ae_mula32x16_l0_funcUnit_uses }, + { "ae_mulaf32x16.l0_s2", ICLASS_AE_MULAF32X16_L0_S2, + 0, + Opcode_ae_mulaf32x16_l0_s2_encode_fns, 1, Opcode_ae_mulaf32x16_l0_s2_funcUnit_uses }, + { "ae_mula32x16.l0_s2", ICLASS_AE_MULA32X16_L0_S2, + 0, + Opcode_ae_mula32x16_l0_s2_encode_fns, 1, Opcode_ae_mula32x16_l0_s2_funcUnit_uses }, + { "ae_mulaf32x16.l1", ICLASS_AE_MULAF32X16_L1, + 0, + Opcode_ae_mulaf32x16_l1_encode_fns, 1, Opcode_ae_mulaf32x16_l1_funcUnit_uses }, + { "ae_mula32x16.l1", ICLASS_AE_MULA32X16_L1, + 0, + Opcode_ae_mula32x16_l1_encode_fns, 1, Opcode_ae_mula32x16_l1_funcUnit_uses }, + { "ae_mulaf32x16.l1_s2", ICLASS_AE_MULAF32X16_L1_S2, + 0, + Opcode_ae_mulaf32x16_l1_s2_encode_fns, 1, Opcode_ae_mulaf32x16_l1_s2_funcUnit_uses }, + { "ae_mula32x16.l1_s2", ICLASS_AE_MULA32X16_L1_S2, + 0, + Opcode_ae_mula32x16_l1_s2_encode_fns, 1, Opcode_ae_mula32x16_l1_s2_funcUnit_uses }, + { "ae_mulaf32x16.l2", ICLASS_AE_MULAF32X16_L2, + 0, + Opcode_ae_mulaf32x16_l2_encode_fns, 1, Opcode_ae_mulaf32x16_l2_funcUnit_uses }, + { "ae_mula32x16.l2", ICLASS_AE_MULA32X16_L2, + 0, + Opcode_ae_mula32x16_l2_encode_fns, 1, Opcode_ae_mula32x16_l2_funcUnit_uses }, + { "ae_mulaf32x16.l2_s2", ICLASS_AE_MULAF32X16_L2_S2, + 0, + Opcode_ae_mulaf32x16_l2_s2_encode_fns, 1, Opcode_ae_mulaf32x16_l2_s2_funcUnit_uses }, + { "ae_mula32x16.l2_s2", ICLASS_AE_MULA32X16_L2_S2, + 0, + Opcode_ae_mula32x16_l2_s2_encode_fns, 1, Opcode_ae_mula32x16_l2_s2_funcUnit_uses }, + { "ae_mulaf32x16.l3", ICLASS_AE_MULAF32X16_L3, + 0, + Opcode_ae_mulaf32x16_l3_encode_fns, 1, Opcode_ae_mulaf32x16_l3_funcUnit_uses }, + { "ae_mula32x16.l3", ICLASS_AE_MULA32X16_L3, + 0, + Opcode_ae_mula32x16_l3_encode_fns, 1, Opcode_ae_mula32x16_l3_funcUnit_uses }, + { "ae_mulaf32x16.l3_s2", ICLASS_AE_MULAF32X16_L3_S2, + 0, + Opcode_ae_mulaf32x16_l3_s2_encode_fns, 1, Opcode_ae_mulaf32x16_l3_s2_funcUnit_uses }, + { "ae_mula32x16.l3_s2", ICLASS_AE_MULA32X16_L3_S2, + 0, + Opcode_ae_mula32x16_l3_s2_encode_fns, 1, Opcode_ae_mula32x16_l3_s2_funcUnit_uses }, + { "ae_mulaf32x16.h0", ICLASS_AE_MULAF32X16_H0, + 0, + Opcode_ae_mulaf32x16_h0_encode_fns, 1, Opcode_ae_mulaf32x16_h0_funcUnit_uses }, + { "ae_mula32x16.h0", ICLASS_AE_MULA32X16_H0, + 0, + Opcode_ae_mula32x16_h0_encode_fns, 1, Opcode_ae_mula32x16_h0_funcUnit_uses }, + { "ae_mulaf32x16.h0_s2", ICLASS_AE_MULAF32X16_H0_S2, + 0, + Opcode_ae_mulaf32x16_h0_s2_encode_fns, 1, Opcode_ae_mulaf32x16_h0_s2_funcUnit_uses }, + { "ae_mula32x16.h0_s2", ICLASS_AE_MULA32X16_H0_S2, + 0, + Opcode_ae_mula32x16_h0_s2_encode_fns, 1, Opcode_ae_mula32x16_h0_s2_funcUnit_uses }, + { "ae_mulaf32x16.h1", ICLASS_AE_MULAF32X16_H1, + 0, + Opcode_ae_mulaf32x16_h1_encode_fns, 1, Opcode_ae_mulaf32x16_h1_funcUnit_uses }, + { "ae_mula32x16.h1", ICLASS_AE_MULA32X16_H1, + 0, + Opcode_ae_mula32x16_h1_encode_fns, 1, Opcode_ae_mula32x16_h1_funcUnit_uses }, + { "ae_mulaf32x16.h1_s2", ICLASS_AE_MULAF32X16_H1_S2, + 0, + Opcode_ae_mulaf32x16_h1_s2_encode_fns, 1, Opcode_ae_mulaf32x16_h1_s2_funcUnit_uses }, + { "ae_mula32x16.h1_s2", ICLASS_AE_MULA32X16_H1_S2, + 0, + Opcode_ae_mula32x16_h1_s2_encode_fns, 1, Opcode_ae_mula32x16_h1_s2_funcUnit_uses }, + { "ae_mulaf32x16.h2", ICLASS_AE_MULAF32X16_H2, + 0, + Opcode_ae_mulaf32x16_h2_encode_fns, 1, Opcode_ae_mulaf32x16_h2_funcUnit_uses }, + { "ae_mula32x16.h2", ICLASS_AE_MULA32X16_H2, + 0, + Opcode_ae_mula32x16_h2_encode_fns, 1, Opcode_ae_mula32x16_h2_funcUnit_uses }, + { "ae_mulaf32x16.h2_s2", ICLASS_AE_MULAF32X16_H2_S2, + 0, + Opcode_ae_mulaf32x16_h2_s2_encode_fns, 1, Opcode_ae_mulaf32x16_h2_s2_funcUnit_uses }, + { "ae_mula32x16.h2_s2", ICLASS_AE_MULA32X16_H2_S2, + 0, + Opcode_ae_mula32x16_h2_s2_encode_fns, 1, Opcode_ae_mula32x16_h2_s2_funcUnit_uses }, + { "ae_mulaf32x16.h3", ICLASS_AE_MULAF32X16_H3, + 0, + Opcode_ae_mulaf32x16_h3_encode_fns, 1, Opcode_ae_mulaf32x16_h3_funcUnit_uses }, + { "ae_mula32x16.h3", ICLASS_AE_MULA32X16_H3, + 0, + Opcode_ae_mula32x16_h3_encode_fns, 1, Opcode_ae_mula32x16_h3_funcUnit_uses }, + { "ae_mulaf32x16.h3_s2", ICLASS_AE_MULAF32X16_H3_S2, + 0, + Opcode_ae_mulaf32x16_h3_s2_encode_fns, 1, Opcode_ae_mulaf32x16_h3_s2_funcUnit_uses }, + { "ae_mula32x16.h3_s2", ICLASS_AE_MULA32X16_H3_S2, + 0, + Opcode_ae_mula32x16_h3_s2_encode_fns, 1, Opcode_ae_mula32x16_h3_s2_funcUnit_uses }, + { "ae_mulsf32x16.l0", ICLASS_AE_MULSF32X16_L0, + 0, + Opcode_ae_mulsf32x16_l0_encode_fns, 1, Opcode_ae_mulsf32x16_l0_funcUnit_uses }, + { "ae_muls32x16.l0", ICLASS_AE_MULS32X16_L0, + 0, + Opcode_ae_muls32x16_l0_encode_fns, 1, Opcode_ae_muls32x16_l0_funcUnit_uses }, + { "ae_mulsf32x16.l0_s2", ICLASS_AE_MULSF32X16_L0_S2, + 0, + Opcode_ae_mulsf32x16_l0_s2_encode_fns, 1, Opcode_ae_mulsf32x16_l0_s2_funcUnit_uses }, + { "ae_muls32x16.l0_s2", ICLASS_AE_MULS32X16_L0_S2, + 0, + Opcode_ae_muls32x16_l0_s2_encode_fns, 1, Opcode_ae_muls32x16_l0_s2_funcUnit_uses }, + { "ae_mulsf32x16.l1", ICLASS_AE_MULSF32X16_L1, + 0, + Opcode_ae_mulsf32x16_l1_encode_fns, 1, Opcode_ae_mulsf32x16_l1_funcUnit_uses }, + { "ae_muls32x16.l1", ICLASS_AE_MULS32X16_L1, + 0, + Opcode_ae_muls32x16_l1_encode_fns, 1, Opcode_ae_muls32x16_l1_funcUnit_uses }, + { "ae_mulsf32x16.l1_s2", ICLASS_AE_MULSF32X16_L1_S2, + 0, + Opcode_ae_mulsf32x16_l1_s2_encode_fns, 1, Opcode_ae_mulsf32x16_l1_s2_funcUnit_uses }, + { "ae_muls32x16.l1_s2", ICLASS_AE_MULS32X16_L1_S2, + 0, + Opcode_ae_muls32x16_l1_s2_encode_fns, 1, Opcode_ae_muls32x16_l1_s2_funcUnit_uses }, + { "ae_mulsf32x16.l2", ICLASS_AE_MULSF32X16_L2, + 0, + Opcode_ae_mulsf32x16_l2_encode_fns, 1, Opcode_ae_mulsf32x16_l2_funcUnit_uses }, + { "ae_muls32x16.l2", ICLASS_AE_MULS32X16_L2, + 0, + Opcode_ae_muls32x16_l2_encode_fns, 1, Opcode_ae_muls32x16_l2_funcUnit_uses }, + { "ae_mulsf32x16.l2_s2", ICLASS_AE_MULSF32X16_L2_S2, + 0, + Opcode_ae_mulsf32x16_l2_s2_encode_fns, 1, Opcode_ae_mulsf32x16_l2_s2_funcUnit_uses }, + { "ae_muls32x16.l2_s2", ICLASS_AE_MULS32X16_L2_S2, + 0, + Opcode_ae_muls32x16_l2_s2_encode_fns, 1, Opcode_ae_muls32x16_l2_s2_funcUnit_uses }, + { "ae_mulsf32x16.l3", ICLASS_AE_MULSF32X16_L3, + 0, + Opcode_ae_mulsf32x16_l3_encode_fns, 1, Opcode_ae_mulsf32x16_l3_funcUnit_uses }, + { "ae_muls32x16.l3", ICLASS_AE_MULS32X16_L3, + 0, + Opcode_ae_muls32x16_l3_encode_fns, 1, Opcode_ae_muls32x16_l3_funcUnit_uses }, + { "ae_mulsf32x16.l3_s2", ICLASS_AE_MULSF32X16_L3_S2, + 0, + Opcode_ae_mulsf32x16_l3_s2_encode_fns, 1, Opcode_ae_mulsf32x16_l3_s2_funcUnit_uses }, + { "ae_muls32x16.l3_s2", ICLASS_AE_MULS32X16_L3_S2, + 0, + Opcode_ae_muls32x16_l3_s2_encode_fns, 1, Opcode_ae_muls32x16_l3_s2_funcUnit_uses }, + { "ae_mulsf32x16.h0", ICLASS_AE_MULSF32X16_H0, + 0, + Opcode_ae_mulsf32x16_h0_encode_fns, 1, Opcode_ae_mulsf32x16_h0_funcUnit_uses }, + { "ae_muls32x16.h0", ICLASS_AE_MULS32X16_H0, + 0, + Opcode_ae_muls32x16_h0_encode_fns, 1, Opcode_ae_muls32x16_h0_funcUnit_uses }, + { "ae_mulsf32x16.h0_s2", ICLASS_AE_MULSF32X16_H0_S2, + 0, + Opcode_ae_mulsf32x16_h0_s2_encode_fns, 1, Opcode_ae_mulsf32x16_h0_s2_funcUnit_uses }, + { "ae_muls32x16.h0_s2", ICLASS_AE_MULS32X16_H0_S2, + 0, + Opcode_ae_muls32x16_h0_s2_encode_fns, 1, Opcode_ae_muls32x16_h0_s2_funcUnit_uses }, + { "ae_mulsf32x16.h1", ICLASS_AE_MULSF32X16_H1, + 0, + Opcode_ae_mulsf32x16_h1_encode_fns, 1, Opcode_ae_mulsf32x16_h1_funcUnit_uses }, + { "ae_muls32x16.h1", ICLASS_AE_MULS32X16_H1, + 0, + Opcode_ae_muls32x16_h1_encode_fns, 1, Opcode_ae_muls32x16_h1_funcUnit_uses }, + { "ae_mulsf32x16.h1_s2", ICLASS_AE_MULSF32X16_H1_S2, + 0, + Opcode_ae_mulsf32x16_h1_s2_encode_fns, 1, Opcode_ae_mulsf32x16_h1_s2_funcUnit_uses }, + { "ae_muls32x16.h1_s2", ICLASS_AE_MULS32X16_H1_S2, + 0, + Opcode_ae_muls32x16_h1_s2_encode_fns, 1, Opcode_ae_muls32x16_h1_s2_funcUnit_uses }, + { "ae_mulsf32x16.h2", ICLASS_AE_MULSF32X16_H2, + 0, + Opcode_ae_mulsf32x16_h2_encode_fns, 1, Opcode_ae_mulsf32x16_h2_funcUnit_uses }, + { "ae_muls32x16.h2", ICLASS_AE_MULS32X16_H2, + 0, + Opcode_ae_muls32x16_h2_encode_fns, 1, Opcode_ae_muls32x16_h2_funcUnit_uses }, + { "ae_mulsf32x16.h2_s2", ICLASS_AE_MULSF32X16_H2_S2, + 0, + Opcode_ae_mulsf32x16_h2_s2_encode_fns, 1, Opcode_ae_mulsf32x16_h2_s2_funcUnit_uses }, + { "ae_muls32x16.h2_s2", ICLASS_AE_MULS32X16_H2_S2, + 0, + Opcode_ae_muls32x16_h2_s2_encode_fns, 1, Opcode_ae_muls32x16_h2_s2_funcUnit_uses }, + { "ae_mulsf32x16.h3", ICLASS_AE_MULSF32X16_H3, + 0, + Opcode_ae_mulsf32x16_h3_encode_fns, 1, Opcode_ae_mulsf32x16_h3_funcUnit_uses }, + { "ae_muls32x16.h3", ICLASS_AE_MULS32X16_H3, + 0, + Opcode_ae_muls32x16_h3_encode_fns, 1, Opcode_ae_muls32x16_h3_funcUnit_uses }, + { "ae_mulsf32x16.h3_s2", ICLASS_AE_MULSF32X16_H3_S2, + 0, + Opcode_ae_mulsf32x16_h3_s2_encode_fns, 1, Opcode_ae_mulsf32x16_h3_s2_funcUnit_uses }, + { "ae_muls32x16.h3_s2", ICLASS_AE_MULS32X16_H3_S2, + 0, + Opcode_ae_muls32x16_h3_s2_encode_fns, 1, Opcode_ae_muls32x16_h3_s2_funcUnit_uses }, + { "ae_mulaafd32x16.h3.l2", ICLASS_AE_MULAAFD32X16_H3_L2, + 0, + Opcode_ae_mulaafd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulaafd32x16_h3_l2_funcUnit_uses }, + { "ae_mulaad32x16.h3.l2", ICLASS_AE_MULAAD32X16_H3_L2, + 0, + Opcode_ae_mulaad32x16_h3_l2_encode_fns, 1, Opcode_ae_mulaad32x16_h3_l2_funcUnit_uses }, + { "ae_mulaafd32x16.h3.l2_s2", ICLASS_AE_MULAAFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulaafd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulaafd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulaad32x16.h3.l2_s2", ICLASS_AE_MULAAD32X16_H3_L2_S2, + 0, + Opcode_ae_mulaad32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulaad32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulaafd32x16.h1.l0", ICLASS_AE_MULAAFD32X16_H1_L0, + 0, + Opcode_ae_mulaafd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulaafd32x16_h1_l0_funcUnit_uses }, + { "ae_mulaad32x16.h1.l0", ICLASS_AE_MULAAD32X16_H1_L0, + 0, + Opcode_ae_mulaad32x16_h1_l0_encode_fns, 1, Opcode_ae_mulaad32x16_h1_l0_funcUnit_uses }, + { "ae_mulaafd32x16.h1.l0_s2", ICLASS_AE_MULAAFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulaafd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulaafd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulaad32x16.h1.l0_s2", ICLASS_AE_MULAAD32X16_H1_L0_S2, + 0, + Opcode_ae_mulaad32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulaad32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulasfd32x16.h3.l2", ICLASS_AE_MULASFD32X16_H3_L2, + 0, + Opcode_ae_mulasfd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulasfd32x16_h3_l2_funcUnit_uses }, + { "ae_mulasd32x16.h3.l2", ICLASS_AE_MULASD32X16_H3_L2, + 0, + Opcode_ae_mulasd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulasd32x16_h3_l2_funcUnit_uses }, + { "ae_mulasfd32x16.h3.l2_s2", ICLASS_AE_MULASFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulasfd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulasfd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulasd32x16.h3.l2_s2", ICLASS_AE_MULASD32X16_H3_L2_S2, + 0, + Opcode_ae_mulasd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulasd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulasfd32x16.h1.l0", ICLASS_AE_MULASFD32X16_H1_L0, + 0, + Opcode_ae_mulasfd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulasfd32x16_h1_l0_funcUnit_uses }, + { "ae_mulasd32x16.h1.l0", ICLASS_AE_MULASD32X16_H1_L0, + 0, + Opcode_ae_mulasd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulasd32x16_h1_l0_funcUnit_uses }, + { "ae_mulasfd32x16.h1.l0_s2", ICLASS_AE_MULASFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulasfd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulasfd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulasd32x16.h1.l0_s2", ICLASS_AE_MULASD32X16_H1_L0_S2, + 0, + Opcode_ae_mulasd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulasd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulsafd32x16.h3.l2", ICLASS_AE_MULSAFD32X16_H3_L2, + 0, + Opcode_ae_mulsafd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulsafd32x16_h3_l2_funcUnit_uses }, + { "ae_mulsad32x16.h3.l2", ICLASS_AE_MULSAD32X16_H3_L2, + 0, + Opcode_ae_mulsad32x16_h3_l2_encode_fns, 1, Opcode_ae_mulsad32x16_h3_l2_funcUnit_uses }, + { "ae_mulsafd32x16.h3.l2_s2", ICLASS_AE_MULSAFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulsafd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulsafd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulsad32x16.h3.l2_s2", ICLASS_AE_MULSAD32X16_H3_L2_S2, + 0, + Opcode_ae_mulsad32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulsad32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulsafd32x16.h1.l0", ICLASS_AE_MULSAFD32X16_H1_L0, + 0, + Opcode_ae_mulsafd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulsafd32x16_h1_l0_funcUnit_uses }, + { "ae_mulsad32x16.h1.l0", ICLASS_AE_MULSAD32X16_H1_L0, + 0, + Opcode_ae_mulsad32x16_h1_l0_encode_fns, 1, Opcode_ae_mulsad32x16_h1_l0_funcUnit_uses }, + { "ae_mulsafd32x16.h1.l0_s2", ICLASS_AE_MULSAFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulsafd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulsafd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulsad32x16.h1.l0_s2", ICLASS_AE_MULSAD32X16_H1_L0_S2, + 0, + Opcode_ae_mulsad32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulsad32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulssfd32x16.h3.l2", ICLASS_AE_MULSSFD32X16_H3_L2, + 0, + Opcode_ae_mulssfd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulssfd32x16_h3_l2_funcUnit_uses }, + { "ae_mulssd32x16.h3.l2", ICLASS_AE_MULSSD32X16_H3_L2, + 0, + Opcode_ae_mulssd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulssd32x16_h3_l2_funcUnit_uses }, + { "ae_mulssfd32x16.h3.l2_s2", ICLASS_AE_MULSSFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulssfd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulssfd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulssd32x16.h3.l2_s2", ICLASS_AE_MULSSD32X16_H3_L2_S2, + 0, + Opcode_ae_mulssd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulssd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulssfd32x16.h1.l0", ICLASS_AE_MULSSFD32X16_H1_L0, + 0, + Opcode_ae_mulssfd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulssfd32x16_h1_l0_funcUnit_uses }, + { "ae_mulssd32x16.h1.l0", ICLASS_AE_MULSSD32X16_H1_L0, + 0, + Opcode_ae_mulssd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulssd32x16_h1_l0_funcUnit_uses }, + { "ae_mulssfd32x16.h1.l0_s2", ICLASS_AE_MULSSFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulssfd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulssfd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulssd32x16.h1.l0_s2", ICLASS_AE_MULSSD32X16_H1_L0_S2, + 0, + Opcode_ae_mulssd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulssd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzaafd32x16.h3.l2", ICLASS_AE_MULZAAFD32X16_H3_L2, + 0, + Opcode_ae_mulzaafd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzaad32x16.h3.l2", ICLASS_AE_MULZAAD32X16_H3_L2, + 0, + Opcode_ae_mulzaad32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzaad32x16_h3_l2_funcUnit_uses }, + { "ae_mulzaafd32x16.h3.l2_s2", ICLASS_AE_MULZAAFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzaafd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzaad32x16.h3.l2_s2", ICLASS_AE_MULZAAD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzaad32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzaad32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzaafd32x16.h1.l0", ICLASS_AE_MULZAAFD32X16_H1_L0, + 0, + Opcode_ae_mulzaafd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzaafd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzaad32x16.h1.l0", ICLASS_AE_MULZAAD32X16_H1_L0, + 0, + Opcode_ae_mulzaad32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzaad32x16_h1_l0_funcUnit_uses }, + { "ae_mulzaafd32x16.h1.l0_s2", ICLASS_AE_MULZAAFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzaafd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzaad32x16.h1.l0_s2", ICLASS_AE_MULZAAD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzaad32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzaad32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzasfd32x16.h3.l2", ICLASS_AE_MULZASFD32X16_H3_L2, + 0, + Opcode_ae_mulzasfd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzasfd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzasd32x16.h3.l2", ICLASS_AE_MULZASD32X16_H3_L2, + 0, + Opcode_ae_mulzasd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzasd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzasfd32x16.h3.l2_s2", ICLASS_AE_MULZASFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzasfd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzasfd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzasd32x16.h3.l2_s2", ICLASS_AE_MULZASD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzasd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzasd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzasfd32x16.h1.l0", ICLASS_AE_MULZASFD32X16_H1_L0, + 0, + Opcode_ae_mulzasfd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzasfd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzasd32x16.h1.l0", ICLASS_AE_MULZASD32X16_H1_L0, + 0, + Opcode_ae_mulzasd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzasd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzasfd32x16.h1.l0_s2", ICLASS_AE_MULZASFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzasfd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzasfd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzasd32x16.h1.l0_s2", ICLASS_AE_MULZASD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzasd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzasd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzsafd32x16.h3.l2", ICLASS_AE_MULZSAFD32X16_H3_L2, + 0, + Opcode_ae_mulzsafd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzsafd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzsad32x16.h3.l2", ICLASS_AE_MULZSAD32X16_H3_L2, + 0, + Opcode_ae_mulzsad32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzsad32x16_h3_l2_funcUnit_uses }, + { "ae_mulzsafd32x16.h3.l2_s2", ICLASS_AE_MULZSAFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzsafd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzsafd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzsad32x16.h3.l2_s2", ICLASS_AE_MULZSAD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzsad32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzsad32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzsafd32x16.h1.l0", ICLASS_AE_MULZSAFD32X16_H1_L0, + 0, + Opcode_ae_mulzsafd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzsafd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzsad32x16.h1.l0", ICLASS_AE_MULZSAD32X16_H1_L0, + 0, + Opcode_ae_mulzsad32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzsad32x16_h1_l0_funcUnit_uses }, + { "ae_mulzsafd32x16.h1.l0_s2", ICLASS_AE_MULZSAFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzsafd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzsafd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzsad32x16.h1.l0_s2", ICLASS_AE_MULZSAD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzsad32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzsad32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzssfd32x16.h3.l2", ICLASS_AE_MULZSSFD32X16_H3_L2, + 0, + Opcode_ae_mulzssfd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzssfd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzssd32x16.h3.l2", ICLASS_AE_MULZSSD32X16_H3_L2, + 0, + Opcode_ae_mulzssd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzssd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzssfd32x16.h3.l2_s2", ICLASS_AE_MULZSSFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzssfd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzssfd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzssd32x16.h3.l2_s2", ICLASS_AE_MULZSSD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzssd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzssd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzssfd32x16.h1.l0", ICLASS_AE_MULZSSFD32X16_H1_L0, + 0, + Opcode_ae_mulzssfd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzssfd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzssd32x16.h1.l0", ICLASS_AE_MULZSSD32X16_H1_L0, + 0, + Opcode_ae_mulzssd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzssd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzssfd32x16.h1.l0_s2", ICLASS_AE_MULZSSFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzssfd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzssfd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzssd32x16.h1.l0_s2", ICLASS_AE_MULZSSD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzssd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzssd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzaafd32x16.h2.l3", ICLASS_AE_MULZAAFD32X16_H2_L3, + 0, + Opcode_ae_mulzaafd32x16_h2_l3_encode_fns, 1, Opcode_ae_mulzaafd32x16_h2_l3_funcUnit_uses }, + { "ae_mulzaafd32x16.h0.l1", ICLASS_AE_MULZAAFD32X16_H0_L1, + 0, + Opcode_ae_mulzaafd32x16_h0_l1_encode_fns, 1, Opcode_ae_mulzaafd32x16_h0_l1_funcUnit_uses }, + { "ae_mulaafd32x16.h2.l3", ICLASS_AE_MULAAFD32X16_H2_L3, + 0, + Opcode_ae_mulaafd32x16_h2_l3_encode_fns, 1, Opcode_ae_mulaafd32x16_h2_l3_funcUnit_uses }, + { "ae_mulaafd32x16.h0.l1", ICLASS_AE_MULAAFD32X16_H0_L1, + 0, + Opcode_ae_mulaafd32x16_h0_l1_encode_fns, 1, Opcode_ae_mulaafd32x16_h0_l1_funcUnit_uses }, + { "ae_mulzaad32x16.h2.l3", ICLASS_AE_MULZAAD32X16_H2_L3, + 0, + Opcode_ae_mulzaad32x16_h2_l3_encode_fns, 1, Opcode_ae_mulzaad32x16_h2_l3_funcUnit_uses }, + { "ae_mulzaad32x16.h0.l1", ICLASS_AE_MULZAAD32X16_H0_L1, + 0, + Opcode_ae_mulzaad32x16_h0_l1_encode_fns, 1, Opcode_ae_mulzaad32x16_h0_l1_funcUnit_uses }, + { "ae_mulaad32x16.h2.l3", ICLASS_AE_MULAAD32X16_H2_L3, + 0, + Opcode_ae_mulaad32x16_h2_l3_encode_fns, 1, Opcode_ae_mulaad32x16_h2_l3_funcUnit_uses }, + { "ae_mulaad32x16.h0.l1", ICLASS_AE_MULAAD32X16_H0_L1, + 0, + Opcode_ae_mulaad32x16_h0_l1_encode_fns, 1, Opcode_ae_mulaad32x16_h0_l1_funcUnit_uses }, + { "ae_mulzaafd32x16.h2.l3_s2", ICLASS_AE_MULZAAFD32X16_H2_L3_S2, + 0, + Opcode_ae_mulzaafd32x16_h2_l3_s2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h2_l3_s2_funcUnit_uses }, + { "ae_mulzaafd32x16.h0.l1_s2", ICLASS_AE_MULZAAFD32X16_H0_L1_S2, + 0, + Opcode_ae_mulzaafd32x16_h0_l1_s2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h0_l1_s2_funcUnit_uses }, + { "ae_mulaafd32x16.h2.l3_s2", ICLASS_AE_MULAAFD32X16_H2_L3_S2, + 0, + Opcode_ae_mulaafd32x16_h2_l3_s2_encode_fns, 1, Opcode_ae_mulaafd32x16_h2_l3_s2_funcUnit_uses }, + { "ae_mulaafd32x16.h0.l1_s2", ICLASS_AE_MULAAFD32X16_H0_L1_S2, + 0, + Opcode_ae_mulaafd32x16_h0_l1_s2_encode_fns, 1, Opcode_ae_mulaafd32x16_h0_l1_s2_funcUnit_uses }, + { "ae_mulzaad32x16.h2.l3_s2", ICLASS_AE_MULZAAD32X16_H2_L3_S2, + 0, + Opcode_ae_mulzaad32x16_h2_l3_s2_encode_fns, 1, Opcode_ae_mulzaad32x16_h2_l3_s2_funcUnit_uses }, + { "ae_mulzaad32x16.h0.l1_s2", ICLASS_AE_MULZAAD32X16_H0_L1_S2, + 0, + Opcode_ae_mulzaad32x16_h0_l1_s2_encode_fns, 1, Opcode_ae_mulzaad32x16_h0_l1_s2_funcUnit_uses }, + { "ae_mulaad32x16.h2.l3_s2", ICLASS_AE_MULAAD32X16_H2_L3_S2, + 0, + Opcode_ae_mulaad32x16_h2_l3_s2_encode_fns, 1, Opcode_ae_mulaad32x16_h2_l3_s2_funcUnit_uses }, + { "ae_mulaad32x16.h0.l1_s2", ICLASS_AE_MULAAD32X16_H0_L1_S2, + 0, + Opcode_ae_mulaad32x16_h0_l1_s2_encode_fns, 1, Opcode_ae_mulaad32x16_h0_l1_s2_funcUnit_uses }, + { "ae_mulp32x16x2.h", ICLASS_AE_MULP32X16X2_H, + 0, + Opcode_ae_mulp32x16x2_h_encode_fns, 1, Opcode_ae_mulp32x16x2_h_funcUnit_uses }, + { "ae_mulfp32x16x2rs.h", ICLASS_AE_MULFP32X16X2RS_H, + 0, + Opcode_ae_mulfp32x16x2rs_h_encode_fns, 1, Opcode_ae_mulfp32x16x2rs_h_funcUnit_uses }, + { "ae_mulfp32x16x2ras.h", ICLASS_AE_MULFP32X16X2RAS_H, + 0, + Opcode_ae_mulfp32x16x2ras_h_encode_fns, 1, Opcode_ae_mulfp32x16x2ras_h_funcUnit_uses }, + { "ae_mulfp32x16x2s.h", ICLASS_AE_MULFP32X16X2S_H, + 0, + Opcode_ae_mulfp32x16x2s_h_encode_fns, 1, Opcode_ae_mulfp32x16x2s_h_funcUnit_uses }, + { "ae_mulfp32x16x2s.h_s2", ICLASS_AE_MULFP32X16X2S_H_S2, + 0, + Opcode_ae_mulfp32x16x2s_h_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2s_h_s2_funcUnit_uses }, + { "ae_mulp32x16x2.h_s2", ICLASS_AE_MULP32X16X2_H_S2, + 0, + Opcode_ae_mulp32x16x2_h_s2_encode_fns, 1, Opcode_ae_mulp32x16x2_h_s2_funcUnit_uses }, + { "ae_mulfp32x16x2rs.h_s2", ICLASS_AE_MULFP32X16X2RS_H_S2, + 0, + Opcode_ae_mulfp32x16x2rs_h_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2rs_h_s2_funcUnit_uses }, + { "ae_mulfp32x16x2ras.h_s2", ICLASS_AE_MULFP32X16X2RAS_H_S2, + 0, + Opcode_ae_mulfp32x16x2ras_h_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2ras_h_s2_funcUnit_uses }, + { "ae_mulp32x16x2.l", ICLASS_AE_MULP32X16X2_L, + 0, + Opcode_ae_mulp32x16x2_l_encode_fns, 1, Opcode_ae_mulp32x16x2_l_funcUnit_uses }, + { "ae_mulfp32x16x2rs.l", ICLASS_AE_MULFP32X16X2RS_L, + 0, + Opcode_ae_mulfp32x16x2rs_l_encode_fns, 1, Opcode_ae_mulfp32x16x2rs_l_funcUnit_uses }, + { "ae_mulfp32x16x2ras.l", ICLASS_AE_MULFP32X16X2RAS_L, + 0, + Opcode_ae_mulfp32x16x2ras_l_encode_fns, 1, Opcode_ae_mulfp32x16x2ras_l_funcUnit_uses }, + { "ae_mulfp32x16x2s.l", ICLASS_AE_MULFP32X16X2S_L, + 0, + Opcode_ae_mulfp32x16x2s_l_encode_fns, 1, Opcode_ae_mulfp32x16x2s_l_funcUnit_uses }, + { "ae_mulfp32x16x2s.l_s2", ICLASS_AE_MULFP32X16X2S_L_S2, + 0, + Opcode_ae_mulfp32x16x2s_l_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2s_l_s2_funcUnit_uses }, + { "ae_mulp32x16x2.l_s2", ICLASS_AE_MULP32X16X2_L_S2, + 0, + Opcode_ae_mulp32x16x2_l_s2_encode_fns, 1, Opcode_ae_mulp32x16x2_l_s2_funcUnit_uses }, + { "ae_mulfp32x16x2rs.l_s2", ICLASS_AE_MULFP32X16X2RS_L_S2, + 0, + Opcode_ae_mulfp32x16x2rs_l_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2rs_l_s2_funcUnit_uses }, + { "ae_mulfp32x16x2ras.l_s2", ICLASS_AE_MULFP32X16X2RAS_L_S2, + 0, + Opcode_ae_mulfp32x16x2ras_l_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2ras_l_s2_funcUnit_uses }, + { "ae_mulap32x16x2.h", ICLASS_AE_MULAP32X16X2_H, + 0, + Opcode_ae_mulap32x16x2_h_encode_fns, 1, Opcode_ae_mulap32x16x2_h_funcUnit_uses }, + { "ae_mulafp32x16x2rs.h", ICLASS_AE_MULAFP32X16X2RS_H, + 0, + Opcode_ae_mulafp32x16x2rs_h_encode_fns, 1, Opcode_ae_mulafp32x16x2rs_h_funcUnit_uses }, + { "ae_mulafp32x16x2ras.h", ICLASS_AE_MULAFP32X16X2RAS_H, + 0, + Opcode_ae_mulafp32x16x2ras_h_encode_fns, 1, Opcode_ae_mulafp32x16x2ras_h_funcUnit_uses }, + { "ae_mulafp32x16x2s.h", ICLASS_AE_MULAFP32X16X2S_H, + 0, + Opcode_ae_mulafp32x16x2s_h_encode_fns, 1, Opcode_ae_mulafp32x16x2s_h_funcUnit_uses }, + { "ae_mulafp32x16x2s.h_s2", ICLASS_AE_MULAFP32X16X2S_H_S2, + 0, + Opcode_ae_mulafp32x16x2s_h_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2s_h_s2_funcUnit_uses }, + { "ae_mulap32x16x2.h_s2", ICLASS_AE_MULAP32X16X2_H_S2, + 0, + Opcode_ae_mulap32x16x2_h_s2_encode_fns, 1, Opcode_ae_mulap32x16x2_h_s2_funcUnit_uses }, + { "ae_mulafp32x16x2rs.h_s2", ICLASS_AE_MULAFP32X16X2RS_H_S2, + 0, + Opcode_ae_mulafp32x16x2rs_h_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2rs_h_s2_funcUnit_uses }, + { "ae_mulafp32x16x2ras.h_s2", ICLASS_AE_MULAFP32X16X2RAS_H_S2, + 0, + Opcode_ae_mulafp32x16x2ras_h_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2ras_h_s2_funcUnit_uses }, + { "ae_mulap32x16x2.l", ICLASS_AE_MULAP32X16X2_L, + 0, + Opcode_ae_mulap32x16x2_l_encode_fns, 1, Opcode_ae_mulap32x16x2_l_funcUnit_uses }, + { "ae_mulafp32x16x2rs.l", ICLASS_AE_MULAFP32X16X2RS_L, + 0, + Opcode_ae_mulafp32x16x2rs_l_encode_fns, 1, Opcode_ae_mulafp32x16x2rs_l_funcUnit_uses }, + { "ae_mulafp32x16x2ras.l", ICLASS_AE_MULAFP32X16X2RAS_L, + 0, + Opcode_ae_mulafp32x16x2ras_l_encode_fns, 1, Opcode_ae_mulafp32x16x2ras_l_funcUnit_uses }, + { "ae_mulafp32x16x2s.l", ICLASS_AE_MULAFP32X16X2S_L, + 0, + Opcode_ae_mulafp32x16x2s_l_encode_fns, 1, Opcode_ae_mulafp32x16x2s_l_funcUnit_uses }, + { "ae_mulafp32x16x2s.l_s2", ICLASS_AE_MULAFP32X16X2S_L_S2, + 0, + Opcode_ae_mulafp32x16x2s_l_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2s_l_s2_funcUnit_uses }, + { "ae_mulap32x16x2.l_s2", ICLASS_AE_MULAP32X16X2_L_S2, + 0, + Opcode_ae_mulap32x16x2_l_s2_encode_fns, 1, Opcode_ae_mulap32x16x2_l_s2_funcUnit_uses }, + { "ae_mulafp32x16x2rs.l_s2", ICLASS_AE_MULAFP32X16X2RS_L_S2, + 0, + Opcode_ae_mulafp32x16x2rs_l_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2rs_l_s2_funcUnit_uses }, + { "ae_mulafp32x16x2ras.l_s2", ICLASS_AE_MULAFP32X16X2RAS_L_S2, + 0, + Opcode_ae_mulafp32x16x2ras_l_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2ras_l_s2_funcUnit_uses }, + { "ae_mulsp32x16x2.h", ICLASS_AE_MULSP32X16X2_H, + 0, + Opcode_ae_mulsp32x16x2_h_encode_fns, 1, Opcode_ae_mulsp32x16x2_h_funcUnit_uses }, + { "ae_mulsfp32x16x2rs.h", ICLASS_AE_MULSFP32X16X2RS_H, + 0, + Opcode_ae_mulsfp32x16x2rs_h_encode_fns, 1, Opcode_ae_mulsfp32x16x2rs_h_funcUnit_uses }, + { "ae_mulsfp32x16x2ras.h", ICLASS_AE_MULSFP32X16X2RAS_H, + 0, + Opcode_ae_mulsfp32x16x2ras_h_encode_fns, 1, Opcode_ae_mulsfp32x16x2ras_h_funcUnit_uses }, + { "ae_mulsfp32x16x2s.h", ICLASS_AE_MULSFP32X16X2S_H, + 0, + Opcode_ae_mulsfp32x16x2s_h_encode_fns, 1, Opcode_ae_mulsfp32x16x2s_h_funcUnit_uses }, + { "ae_mulsfp32x16x2s.h_s2", ICLASS_AE_MULSFP32X16X2S_H_S2, + 0, + Opcode_ae_mulsfp32x16x2s_h_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2s_h_s2_funcUnit_uses }, + { "ae_mulsp32x16x2.h_s2", ICLASS_AE_MULSP32X16X2_H_S2, + 0, + Opcode_ae_mulsp32x16x2_h_s2_encode_fns, 1, Opcode_ae_mulsp32x16x2_h_s2_funcUnit_uses }, + { "ae_mulsfp32x16x2rs.h_s2", ICLASS_AE_MULSFP32X16X2RS_H_S2, + 0, + Opcode_ae_mulsfp32x16x2rs_h_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2rs_h_s2_funcUnit_uses }, + { "ae_mulsfp32x16x2ras.h_s2", ICLASS_AE_MULSFP32X16X2RAS_H_S2, + 0, + Opcode_ae_mulsfp32x16x2ras_h_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2ras_h_s2_funcUnit_uses }, + { "ae_mulsp32x16x2.l", ICLASS_AE_MULSP32X16X2_L, + 0, + Opcode_ae_mulsp32x16x2_l_encode_fns, 1, Opcode_ae_mulsp32x16x2_l_funcUnit_uses }, + { "ae_mulsfp32x16x2rs.l", ICLASS_AE_MULSFP32X16X2RS_L, + 0, + Opcode_ae_mulsfp32x16x2rs_l_encode_fns, 1, Opcode_ae_mulsfp32x16x2rs_l_funcUnit_uses }, + { "ae_mulsfp32x16x2ras.l", ICLASS_AE_MULSFP32X16X2RAS_L, + 0, + Opcode_ae_mulsfp32x16x2ras_l_encode_fns, 1, Opcode_ae_mulsfp32x16x2ras_l_funcUnit_uses }, + { "ae_mulsfp32x16x2s.l", ICLASS_AE_MULSFP32X16X2S_L, + 0, + Opcode_ae_mulsfp32x16x2s_l_encode_fns, 1, Opcode_ae_mulsfp32x16x2s_l_funcUnit_uses }, + { "ae_mulsfp32x16x2s.l_s2", ICLASS_AE_MULSFP32X16X2S_L_S2, + 0, + Opcode_ae_mulsfp32x16x2s_l_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2s_l_s2_funcUnit_uses }, + { "ae_mulsp32x16x2.l_s2", ICLASS_AE_MULSP32X16X2_L_S2, + 0, + Opcode_ae_mulsp32x16x2_l_s2_encode_fns, 1, Opcode_ae_mulsp32x16x2_l_s2_funcUnit_uses }, + { "ae_mulsfp32x16x2rs.l_s2", ICLASS_AE_MULSFP32X16X2RS_L_S2, + 0, + Opcode_ae_mulsfp32x16x2rs_l_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2rs_l_s2_funcUnit_uses }, + { "ae_mulsfp32x16x2ras.l_s2", ICLASS_AE_MULSFP32X16X2RAS_L_S2, + 0, + Opcode_ae_mulsfp32x16x2ras_l_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2ras_l_s2_funcUnit_uses }, + { "ae_mulp32x2", ICLASS_AE_MULP32X2, + 0, + Opcode_ae_mulp32x2_encode_fns, 1, Opcode_ae_mulp32x2_funcUnit_uses }, + { "ae_mulfp32x2rs", ICLASS_AE_MULFP32X2RS, + 0, + Opcode_ae_mulfp32x2rs_encode_fns, 1, Opcode_ae_mulfp32x2rs_funcUnit_uses }, + { "ae_mulfp32x2ras", ICLASS_AE_MULFP32X2RAS, + 0, + Opcode_ae_mulfp32x2ras_encode_fns, 1, Opcode_ae_mulfp32x2ras_funcUnit_uses }, + { "ae_mulp32x2_s2", ICLASS_AE_MULP32X2_S2, + 0, + Opcode_ae_mulp32x2_s2_encode_fns, 1, Opcode_ae_mulp32x2_s2_funcUnit_uses }, + { "ae_mulfp32x2rs_s2", ICLASS_AE_MULFP32X2RS_S2, + 0, + Opcode_ae_mulfp32x2rs_s2_encode_fns, 1, Opcode_ae_mulfp32x2rs_s2_funcUnit_uses }, + { "ae_mulfp32x2ras_s2", ICLASS_AE_MULFP32X2RAS_S2, + 0, + Opcode_ae_mulfp32x2ras_s2_encode_fns, 1, Opcode_ae_mulfp32x2ras_s2_funcUnit_uses }, + { "ae_mulap32x2", ICLASS_AE_MULAP32X2, + 0, + Opcode_ae_mulap32x2_encode_fns, 1, Opcode_ae_mulap32x2_funcUnit_uses }, + { "ae_mulafp32x2rs", ICLASS_AE_MULAFP32X2RS, + 0, + Opcode_ae_mulafp32x2rs_encode_fns, 1, Opcode_ae_mulafp32x2rs_funcUnit_uses }, + { "ae_mulafp32x2ras", ICLASS_AE_MULAFP32X2RAS, + 0, + Opcode_ae_mulafp32x2ras_encode_fns, 1, Opcode_ae_mulafp32x2ras_funcUnit_uses }, + { "ae_mulap32x2_s2", ICLASS_AE_MULAP32X2_S2, + 0, + Opcode_ae_mulap32x2_s2_encode_fns, 1, Opcode_ae_mulap32x2_s2_funcUnit_uses }, + { "ae_mulafp32x2rs_s2", ICLASS_AE_MULAFP32X2RS_S2, + 0, + Opcode_ae_mulafp32x2rs_s2_encode_fns, 1, Opcode_ae_mulafp32x2rs_s2_funcUnit_uses }, + { "ae_mulafp32x2ras_s2", ICLASS_AE_MULAFP32X2RAS_S2, + 0, + Opcode_ae_mulafp32x2ras_s2_encode_fns, 1, Opcode_ae_mulafp32x2ras_s2_funcUnit_uses }, + { "ae_mulsp32x2", ICLASS_AE_MULSP32X2, + 0, + Opcode_ae_mulsp32x2_encode_fns, 1, Opcode_ae_mulsp32x2_funcUnit_uses }, + { "ae_mulsfp32x2rs", ICLASS_AE_MULSFP32X2RS, + 0, + Opcode_ae_mulsfp32x2rs_encode_fns, 1, Opcode_ae_mulsfp32x2rs_funcUnit_uses }, + { "ae_mulsfp32x2ras", ICLASS_AE_MULSFP32X2RAS, + 0, + Opcode_ae_mulsfp32x2ras_encode_fns, 1, Opcode_ae_mulsfp32x2ras_funcUnit_uses }, + { "ae_mulsp32x2_s2", ICLASS_AE_MULSP32X2_S2, + 0, + Opcode_ae_mulsp32x2_s2_encode_fns, 1, Opcode_ae_mulsp32x2_s2_funcUnit_uses }, + { "ae_mulsfp32x2rs_s2", ICLASS_AE_MULSFP32X2RS_S2, + 0, + Opcode_ae_mulsfp32x2rs_s2_encode_fns, 1, Opcode_ae_mulsfp32x2rs_s2_funcUnit_uses }, + { "ae_mulsfp32x2ras_s2", ICLASS_AE_MULSFP32X2RAS_S2, + 0, + Opcode_ae_mulsfp32x2ras_s2_encode_fns, 1, Opcode_ae_mulsfp32x2ras_s2_funcUnit_uses }, + { "ae_mulfp16x4s", ICLASS_AE_MULFP16X4S, + 0, + Opcode_ae_mulfp16x4s_encode_fns, 2, Opcode_ae_mulfp16x4s_funcUnit_uses }, + { "ae_mulfp16x4ras", ICLASS_AE_MULFP16X4RAS, + 0, + Opcode_ae_mulfp16x4ras_encode_fns, 2, Opcode_ae_mulfp16x4ras_funcUnit_uses }, + { "ae_mulc32", ICLASS_AE_MULC32, + 0, + Opcode_ae_mulc32_encode_fns, 2, Opcode_ae_mulc32_funcUnit_uses }, + { "ae_mulfc24ra", ICLASS_AE_MULFC24RA, + 0, + Opcode_ae_mulfc24ra_encode_fns, 2, Opcode_ae_mulfc24ra_funcUnit_uses }, + { "ae_mulfc32ras", ICLASS_AE_MULFC32RAS, + 0, + Opcode_ae_mulfc32ras_encode_fns, 2, Opcode_ae_mulfc32ras_funcUnit_uses }, + { "ae_mulc32x16.l", ICLASS_AE_MULC32X16_L, + 0, + Opcode_ae_mulc32x16_l_encode_fns, 2, Opcode_ae_mulc32x16_l_funcUnit_uses }, + { "ae_mulfc32x16ras.l", ICLASS_AE_MULFC32X16RAS_L, + 0, + Opcode_ae_mulfc32x16ras_l_encode_fns, 2, Opcode_ae_mulfc32x16ras_l_funcUnit_uses }, + { "ae_mulc32x16.h", ICLASS_AE_MULC32X16_H, + 0, + Opcode_ae_mulc32x16_h_encode_fns, 2, Opcode_ae_mulc32x16_h_funcUnit_uses }, + { "ae_mulfc32x16ras.h", ICLASS_AE_MULFC32X16RAS_H, + 0, + Opcode_ae_mulfc32x16ras_h_encode_fns, 2, Opcode_ae_mulfc32x16ras_h_funcUnit_uses }, + { "ae_mulac32", ICLASS_AE_MULAC32, + 0, + Opcode_ae_mulac32_encode_fns, 2, Opcode_ae_mulac32_funcUnit_uses }, + { "ae_mulafc24ra", ICLASS_AE_MULAFC24RA, + 0, + Opcode_ae_mulafc24ra_encode_fns, 2, Opcode_ae_mulafc24ra_funcUnit_uses }, + { "ae_mulafc32ras", ICLASS_AE_MULAFC32RAS, + 0, + Opcode_ae_mulafc32ras_encode_fns, 2, Opcode_ae_mulafc32ras_funcUnit_uses }, + { "ae_mulac32x16.l", ICLASS_AE_MULAC32X16_L, + 0, + Opcode_ae_mulac32x16_l_encode_fns, 2, Opcode_ae_mulac32x16_l_funcUnit_uses }, + { "ae_mulafc32x16ras.l", ICLASS_AE_MULAFC32X16RAS_L, + 0, + Opcode_ae_mulafc32x16ras_l_encode_fns, 2, Opcode_ae_mulafc32x16ras_l_funcUnit_uses }, + { "ae_mulac32x16.h", ICLASS_AE_MULAC32X16_H, + 0, + Opcode_ae_mulac32x16_h_encode_fns, 2, Opcode_ae_mulac32x16_h_funcUnit_uses }, + { "ae_mulafc32x16ras.h", ICLASS_AE_MULAFC32X16RAS_H, + 0, + Opcode_ae_mulafc32x16ras_h_encode_fns, 2, Opcode_ae_mulafc32x16ras_h_funcUnit_uses }, + { "ae_mulf16x4ss", ICLASS_AE_MULF16X4SS, + 0, + Opcode_ae_mulf16x4ss_encode_fns, 2, Opcode_ae_mulf16x4ss_funcUnit_uses }, + { "ae_mulaf16x4ss", ICLASS_AE_MULAF16X4SS, + 0, + Opcode_ae_mulaf16x4ss_encode_fns, 2, Opcode_ae_mulaf16x4ss_funcUnit_uses }, + { "ae_mulsf16x4ss", ICLASS_AE_MULSF16X4SS, + 0, + Opcode_ae_mulsf16x4ss_encode_fns, 2, Opcode_ae_mulsf16x4ss_funcUnit_uses }, + { "ae_mul16x4", ICLASS_AE_MUL16X4, + 0, + Opcode_ae_mul16x4_encode_fns, 2, Opcode_ae_mul16x4_funcUnit_uses }, + { "ae_mula16x4", ICLASS_AE_MULA16X4, + 0, + Opcode_ae_mula16x4_encode_fns, 2, Opcode_ae_mula16x4_funcUnit_uses }, + { "ae_muls16x4", ICLASS_AE_MULS16X4, + 0, + Opcode_ae_muls16x4_encode_fns, 2, Opcode_ae_muls16x4_funcUnit_uses }, + { "ae_mulfd32x2s.fir.h", ICLASS_AE_MULFD32X2S_FIR_H, + 0, + Opcode_ae_mulfd32x2s_fir_h_encode_fns, 2, Opcode_ae_mulfd32x2s_fir_h_funcUnit_uses }, + { "ae_mulfd32x2ra.fir.h", ICLASS_AE_MULFD32X2RA_FIR_H, + 0, + Opcode_ae_mulfd32x2ra_fir_h_encode_fns, 2, Opcode_ae_mulfd32x2ra_fir_h_funcUnit_uses }, + { "ae_mulfd32x2s.fir.l", ICLASS_AE_MULFD32X2S_FIR_L, + 0, + Opcode_ae_mulfd32x2s_fir_l_encode_fns, 2, Opcode_ae_mulfd32x2s_fir_l_funcUnit_uses }, + { "ae_mulfd32x2ra.fir.l", ICLASS_AE_MULFD32X2RA_FIR_L, + 0, + Opcode_ae_mulfd32x2ra_fir_l_encode_fns, 2, Opcode_ae_mulfd32x2ra_fir_l_funcUnit_uses }, + { "ae_mulfd32x16x2.fir.hh", ICLASS_AE_MULFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulfd32x16x2_fir_hh_encode_fns, 2, Opcode_ae_mulfd32x16x2_fir_hh_funcUnit_uses }, + { "ae_mulfd32x16x2.fir.hl", ICLASS_AE_MULFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulfd32x16x2_fir_hl_encode_fns, 2, Opcode_ae_mulfd32x16x2_fir_hl_funcUnit_uses }, + { "ae_mulfd32x16x2.fir.lh", ICLASS_AE_MULFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulfd32x16x2_fir_lh_encode_fns, 2, Opcode_ae_mulfd32x16x2_fir_lh_funcUnit_uses }, + { "ae_mulfd32x16x2.fir.ll", ICLASS_AE_MULFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulfd32x16x2_fir_ll_encode_fns, 2, Opcode_ae_mulfd32x16x2_fir_ll_funcUnit_uses }, + { "ae_mulafd32x2s.fir.h", ICLASS_AE_MULAFD32X2S_FIR_H, + 0, + Opcode_ae_mulafd32x2s_fir_h_encode_fns, 2, Opcode_ae_mulafd32x2s_fir_h_funcUnit_uses }, + { "ae_mulafd32x2ra.fir.h", ICLASS_AE_MULAFD32X2RA_FIR_H, + 0, + Opcode_ae_mulafd32x2ra_fir_h_encode_fns, 2, Opcode_ae_mulafd32x2ra_fir_h_funcUnit_uses }, + { "ae_mulafd32x2s.fir.l", ICLASS_AE_MULAFD32X2S_FIR_L, + 0, + Opcode_ae_mulafd32x2s_fir_l_encode_fns, 2, Opcode_ae_mulafd32x2s_fir_l_funcUnit_uses }, + { "ae_mulafd32x2ra.fir.l", ICLASS_AE_MULAFD32X2RA_FIR_L, + 0, + Opcode_ae_mulafd32x2ra_fir_l_encode_fns, 2, Opcode_ae_mulafd32x2ra_fir_l_funcUnit_uses }, + { "ae_mulafd32x16x2.fir.hh", ICLASS_AE_MULAFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulafd32x16x2_fir_hh_encode_fns, 2, Opcode_ae_mulafd32x16x2_fir_hh_funcUnit_uses }, + { "ae_mulafd32x16x2.fir.hl", ICLASS_AE_MULAFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulafd32x16x2_fir_hl_encode_fns, 2, Opcode_ae_mulafd32x16x2_fir_hl_funcUnit_uses }, + { "ae_mulafd32x16x2.fir.lh", ICLASS_AE_MULAFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulafd32x16x2_fir_lh_encode_fns, 2, Opcode_ae_mulafd32x16x2_fir_lh_funcUnit_uses }, + { "ae_mulafd32x16x2.fir.ll", ICLASS_AE_MULAFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulafd32x16x2_fir_ll_encode_fns, 2, Opcode_ae_mulafd32x16x2_fir_ll_funcUnit_uses }, + { "ae_mulzaaaafq32x16", ICLASS_AE_MULZAAAAFQ32X16, + 0, + Opcode_ae_mulzaaaafq32x16_encode_fns, 1, Opcode_ae_mulzaaaafq32x16_funcUnit_uses }, + { "ae_mulaaaafq32x16", ICLASS_AE_MULAAAAFQ32X16, + 0, + Opcode_ae_mulaaaafq32x16_encode_fns, 1, Opcode_ae_mulaaaafq32x16_funcUnit_uses }, + { "ae_mulzaaaafq32x16_s2", ICLASS_AE_MULZAAAAFQ32X16_S2, + 0, + Opcode_ae_mulzaaaafq32x16_s2_encode_fns, 1, Opcode_ae_mulzaaaafq32x16_s2_funcUnit_uses }, + { "ae_mulaaaafq32x16_s2", ICLASS_AE_MULAAAAFQ32X16_S2, + 0, + Opcode_ae_mulaaaafq32x16_s2_encode_fns, 1, Opcode_ae_mulaaaafq32x16_s2_funcUnit_uses }, + { "ae_mulzaaaaq32x16", ICLASS_AE_MULZAAAAQ32X16, + 0, + Opcode_ae_mulzaaaaq32x16_encode_fns, 1, Opcode_ae_mulzaaaaq32x16_funcUnit_uses }, + { "ae_mulaaaaq32x16", ICLASS_AE_MULAAAAQ32X16, + 0, + Opcode_ae_mulaaaaq32x16_encode_fns, 1, Opcode_ae_mulaaaaq32x16_funcUnit_uses }, + { "ae_mulzaaaaq32x16_s2", ICLASS_AE_MULZAAAAQ32X16_S2, + 0, + Opcode_ae_mulzaaaaq32x16_s2_encode_fns, 1, Opcode_ae_mulzaaaaq32x16_s2_funcUnit_uses }, + { "ae_mulaaaaq32x16_s2", ICLASS_AE_MULAAAAQ32X16_S2, + 0, + Opcode_ae_mulaaaaq32x16_s2_encode_fns, 1, Opcode_ae_mulaaaaq32x16_s2_funcUnit_uses }, + { "ae_mul16.00", ICLASS_AE_MUL16_00, + 0, + Opcode_ae_mul16_00_encode_fns, 1, Opcode_ae_mul16_00_funcUnit_uses }, + { "ae_mula16.00", ICLASS_AE_MULA16_00, + 0, + Opcode_ae_mula16_00_encode_fns, 1, Opcode_ae_mula16_00_funcUnit_uses }, + { "ae_mul16.00_s2", ICLASS_AE_MUL16_00_S2, + 0, + Opcode_ae_mul16_00_s2_encode_fns, 1, Opcode_ae_mul16_00_s2_funcUnit_uses }, + { "ae_mula16.00_s2", ICLASS_AE_MULA16_00_S2, + 0, + Opcode_ae_mula16_00_s2_encode_fns, 1, Opcode_ae_mula16_00_s2_funcUnit_uses }, + { "ae_mulzaaaaq16", ICLASS_AE_MULZAAAAQ16, + 0, + Opcode_ae_mulzaaaaq16_encode_fns, 1, Opcode_ae_mulzaaaaq16_funcUnit_uses }, + { "ae_mulaaaaq16", ICLASS_AE_MULAAAAQ16, + 0, + Opcode_ae_mulaaaaq16_encode_fns, 1, Opcode_ae_mulaaaaq16_funcUnit_uses }, + { "ae_mulzaaaaq16_s2", ICLASS_AE_MULZAAAAQ16_S2, + 0, + Opcode_ae_mulzaaaaq16_s2_encode_fns, 1, Opcode_ae_mulzaaaaq16_s2_funcUnit_uses }, + { "ae_mulaaaaq16_s2", ICLASS_AE_MULAAAAQ16_S2, + 0, + Opcode_ae_mulaaaaq16_s2_encode_fns, 1, Opcode_ae_mulaaaaq16_s2_funcUnit_uses }, + { "ae_div64d32.h", ICLASS_AE_DIV64D32_H, + 0, + Opcode_ae_div64d32_h_encode_fns, 0, 0 }, + { "ae_div64d32.l", ICLASS_AE_DIV64D32_L, + 0, + Opcode_ae_div64d32_l_encode_fns, 0, 0 }, + { "ae_sha32", ICLASS_AE_SHA32, + 0, + Opcode_ae_sha32_encode_fns, 0, 0 }, + { "ae_vldl32t", ICLASS_AE_VLDL32T, + 0, + Opcode_ae_vldl32t_encode_fns, 2, Opcode_ae_vldl32t_funcUnit_uses }, + { "ae_vldl16t", ICLASS_AE_VLDL16T, + 0, + Opcode_ae_vldl16t_encode_fns, 2, Opcode_ae_vldl16t_funcUnit_uses }, + { "ae_vldl16c", ICLASS_AE_VLDL16C, + 0, + Opcode_ae_vldl16c_encode_fns, 4, Opcode_ae_vldl16c_funcUnit_uses }, + { "ae_vldl16c.ip", ICLASS_AE_VLDL16C_IP, + 0, + Opcode_ae_vldl16c_ip_encode_fns, 4, Opcode_ae_vldl16c_ip_funcUnit_uses }, + { "ae_vldl16c.ic", ICLASS_AE_VLDL16C_IC, + 0, + Opcode_ae_vldl16c_ic_encode_fns, 4, Opcode_ae_vldl16c_ic_funcUnit_uses }, + { "ae_vldl16c.ic1", ICLASS_AE_VLDL16C_IC1, + 0, + Opcode_ae_vldl16c_ic1_encode_fns, 4, Opcode_ae_vldl16c_ic1_funcUnit_uses }, + { "ae_vldsht", ICLASS_AE_VLDSHT, + 0, + Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, + { "ae_lb", ICLASS_AE_LB, + 0, + Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, + { "ae_lbi", ICLASS_AE_LBI, + 0, + Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, + { "ae_lbk", ICLASS_AE_LBK, + 0, + Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, + { "ae_lbki", ICLASS_AE_LBKI, + 0, + Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, + { "ae_lbs", ICLASS_AE_LBS, + 0, + Opcode_ae_lbs_encode_fns, 1, Opcode_ae_lbs_funcUnit_uses }, + { "ae_lbsi", ICLASS_AE_LBSI, + 0, + Opcode_ae_lbsi_encode_fns, 1, Opcode_ae_lbsi_funcUnit_uses }, + { "ae_db", ICLASS_AE_DB, + 0, + Opcode_ae_db_encode_fns, 3, Opcode_ae_db_funcUnit_uses }, + { "ae_dbi", ICLASS_AE_DBI, + 0, + Opcode_ae_dbi_encode_fns, 3, Opcode_ae_dbi_funcUnit_uses }, + { "ae_db.ic", ICLASS_AE_DB_IC, + 0, + Opcode_ae_db_ic_encode_fns, 3, Opcode_ae_db_ic_funcUnit_uses }, + { "ae_dbi.ic", ICLASS_AE_DBI_IC, + 0, + Opcode_ae_dbi_ic_encode_fns, 3, Opcode_ae_dbi_ic_funcUnit_uses }, + { "ae_db.ic1", ICLASS_AE_DB_IC1, + 0, + Opcode_ae_db_ic1_encode_fns, 3, Opcode_ae_db_ic1_funcUnit_uses }, + { "ae_dbi.ic1", ICLASS_AE_DBI_IC1, + 0, + Opcode_ae_dbi_ic1_encode_fns, 3, Opcode_ae_dbi_ic1_funcUnit_uses }, + { "ae_db.ip", ICLASS_AE_DB_IP, + 0, + Opcode_ae_db_ip_encode_fns, 3, Opcode_ae_db_ip_funcUnit_uses }, + { "ae_dbi.ip", ICLASS_AE_DBI_IP, + 0, + Opcode_ae_dbi_ip_encode_fns, 3, Opcode_ae_dbi_ip_funcUnit_uses }, + { "ae_vlel32t", ICLASS_AE_VLEL32T, + 0, + Opcode_ae_vlel32t_encode_fns, 2, Opcode_ae_vlel32t_funcUnit_uses }, + { "ae_vlel16t", ICLASS_AE_VLEL16T, + 0, + Opcode_ae_vlel16t_encode_fns, 2, Opcode_ae_vlel16t_funcUnit_uses }, + { "ae_sb", ICLASS_AE_SB, + 0, + Opcode_ae_sb_encode_fns, 3, Opcode_ae_sb_funcUnit_uses }, + { "ae_sbi", ICLASS_AE_SBI, + 0, + Opcode_ae_sbi_encode_fns, 3, Opcode_ae_sbi_funcUnit_uses }, + { "ae_vles16c", ICLASS_AE_VLES16C, + 0, + Opcode_ae_vles16c_encode_fns, 3, Opcode_ae_vles16c_funcUnit_uses }, + { "ae_sbf", ICLASS_AE_SBF, + 0, + Opcode_ae_sbf_encode_fns, 3, Opcode_ae_sbf_funcUnit_uses }, + { "ae_sb.ic", ICLASS_AE_SB_IC, + 0, + Opcode_ae_sb_ic_encode_fns, 3, Opcode_ae_sb_ic_funcUnit_uses }, + { "ae_sbi.ic", ICLASS_AE_SBI_IC, + 0, + Opcode_ae_sbi_ic_encode_fns, 3, Opcode_ae_sbi_ic_funcUnit_uses }, + { "ae_vles16c.ic", ICLASS_AE_VLES16C_IC, + 0, + Opcode_ae_vles16c_ic_encode_fns, 3, Opcode_ae_vles16c_ic_funcUnit_uses }, + { "ae_sbf.ic", ICLASS_AE_SBF_IC, + 0, + Opcode_ae_sbf_ic_encode_fns, 3, Opcode_ae_sbf_ic_funcUnit_uses }, + { "ae_sb.ic1", ICLASS_AE_SB_IC1, + 0, + Opcode_ae_sb_ic1_encode_fns, 3, Opcode_ae_sb_ic1_funcUnit_uses }, + { "ae_sbi.ic1", ICLASS_AE_SBI_IC1, + 0, + Opcode_ae_sbi_ic1_encode_fns, 3, Opcode_ae_sbi_ic1_funcUnit_uses }, + { "ae_vles16c.ic1", ICLASS_AE_VLES16C_IC1, + 0, + Opcode_ae_vles16c_ic1_encode_fns, 3, Opcode_ae_vles16c_ic1_funcUnit_uses }, + { "ae_sbf.ic1", ICLASS_AE_SBF_IC1, + 0, + Opcode_ae_sbf_ic1_encode_fns, 3, Opcode_ae_sbf_ic1_funcUnit_uses }, + { "ae_sb.ip", ICLASS_AE_SB_IP, + 0, + Opcode_ae_sb_ip_encode_fns, 3, Opcode_ae_sb_ip_funcUnit_uses }, + { "ae_sbi.ip", ICLASS_AE_SBI_IP, + 0, + Opcode_ae_sbi_ip_encode_fns, 3, Opcode_ae_sbi_ip_funcUnit_uses }, + { "ae_vles16c.ip", ICLASS_AE_VLES16C_IP, + 0, + Opcode_ae_vles16c_ip_encode_fns, 3, Opcode_ae_vles16c_ip_funcUnit_uses }, + { "ae_sbf.ip", ICLASS_AE_SBF_IP, + 0, + Opcode_ae_sbf_ip_encode_fns, 3, Opcode_ae_sbf_ip_funcUnit_uses }, + { "ae_sext32", ICLASS_AE_SEXT32, + 0, + Opcode_ae_sext32_encode_fns, 0, 0 }, + { "ae_movae", ICLASS_AE_MOVAE, + 0, + Opcode_ae_movae_encode_fns, 0, 0 }, + { "ae_movea", ICLASS_AE_MOVEA, + 0, + Opcode_ae_movea_encode_fns, 0, 0 }, + { "ae_moveep", ICLASS_AE_MOVEEP, + 0, + Opcode_ae_moveep_encode_fns, 0, 0 }, + { "ae_sext72", ICLASS_AE_SEXT72, + 0, + Opcode_ae_sext72_encode_fns, 0, 0 }, + { "ae_add72", ICLASS_AE_ADD72, + 0, + Opcode_ae_add72_encode_fns, 0, 0 }, + { "ae_sub72", ICLASS_AE_SUB72, + 0, + Opcode_ae_sub72_encode_fns, 0, 0 }, + { "ae_add72x64", ICLASS_AE_ADD72X64, + 0, + Opcode_ae_add72x64_encode_fns, 0, 0 }, + { "ae_sub72x64", ICLASS_AE_SUB72X64, + 0, + Opcode_ae_sub72x64_encode_fns, 0, 0 }, + { "ae_mul32ep.hh", ICLASS_AE_MUL32EP_HH, + 0, + Opcode_ae_mul32ep_hh_encode_fns, 1, Opcode_ae_mul32ep_hh_funcUnit_uses }, + { "ae_mul32ep.hh_s2", ICLASS_AE_MUL32EP_HH_S2, + 0, + Opcode_ae_mul32ep_hh_s2_encode_fns, 1, Opcode_ae_mul32ep_hh_s2_funcUnit_uses }, + { "ae_mula32ep.hh", ICLASS_AE_MULA32EP_HH, + 0, + Opcode_ae_mula32ep_hh_encode_fns, 1, Opcode_ae_mula32ep_hh_funcUnit_uses }, + { "ae_muls32ep.hh", ICLASS_AE_MULS32EP_HH, + 0, + Opcode_ae_muls32ep_hh_encode_fns, 1, Opcode_ae_muls32ep_hh_funcUnit_uses }, + { "ae_mula32ep.hh_s2", ICLASS_AE_MULA32EP_HH_S2, + 0, + Opcode_ae_mula32ep_hh_s2_encode_fns, 1, Opcode_ae_mula32ep_hh_s2_funcUnit_uses }, + { "ae_muls32ep.hh_s2", ICLASS_AE_MULS32EP_HH_S2, + 0, + Opcode_ae_muls32ep_hh_s2_encode_fns, 1, Opcode_ae_muls32ep_hh_s2_funcUnit_uses }, + { "ae_mulzaad32ep.hh.ll", ICLASS_AE_MULZAAD32EP_HH_LL, + 0, + Opcode_ae_mulzaad32ep_hh_ll_encode_fns, 1, Opcode_ae_mulzaad32ep_hh_ll_funcUnit_uses }, + { "ae_mulzssd32ep.hh.ll", ICLASS_AE_MULZSSD32EP_HH_LL, + 0, + Opcode_ae_mulzssd32ep_hh_ll_encode_fns, 1, Opcode_ae_mulzssd32ep_hh_ll_funcUnit_uses }, + { "ae_mulaad32ep.hh.ll", ICLASS_AE_MULAAD32EP_HH_LL, + 0, + Opcode_ae_mulaad32ep_hh_ll_encode_fns, 1, Opcode_ae_mulaad32ep_hh_ll_funcUnit_uses }, + { "ae_mulssd32ep.hh.ll", ICLASS_AE_MULSSD32EP_HH_LL, + 0, + Opcode_ae_mulssd32ep_hh_ll_encode_fns, 1, Opcode_ae_mulssd32ep_hh_ll_funcUnit_uses }, + { "ae_mulzaad32ep.hh.ll_s2", ICLASS_AE_MULZAAD32EP_HH_LL_S2, + 0, + Opcode_ae_mulzaad32ep_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzaad32ep_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssd32ep.hh.ll_s2", ICLASS_AE_MULZSSD32EP_HH_LL_S2, + 0, + Opcode_ae_mulzssd32ep_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzssd32ep_hh_ll_s2_funcUnit_uses }, + { "ae_mulaad32ep.hh.ll_s2", ICLASS_AE_MULAAD32EP_HH_LL_S2, + 0, + Opcode_ae_mulaad32ep_hh_ll_s2_encode_fns, 1, Opcode_ae_mulaad32ep_hh_ll_s2_funcUnit_uses }, + { "ae_mulssd32ep.hh.ll_s2", ICLASS_AE_MULSSD32EP_HH_LL_S2, + 0, + Opcode_ae_mulssd32ep_hh_ll_s2_encode_fns, 1, Opcode_ae_mulssd32ep_hh_ll_s2_funcUnit_uses }, + { "ae_mulaad32usep.hl.lh", ICLASS_AE_MULAAD32USEP_HL_LH, + 0, + Opcode_ae_mulaad32usep_hl_lh_encode_fns, 1, Opcode_ae_mulaad32usep_hl_lh_funcUnit_uses }, + { "ae_mulaad32usep.hl.lh_s2", ICLASS_AE_MULAAD32USEP_HL_LH_S2, + 0, + Opcode_ae_mulaad32usep_hl_lh_s2_encode_fns, 1, Opcode_ae_mulaad32usep_hl_lh_s2_funcUnit_uses }, + { "ae_mulzaad32usep.hl.lh", ICLASS_AE_MULZAAD32USEP_HL_LH, + 0, + Opcode_ae_mulzaad32usep_hl_lh_encode_fns, 1, Opcode_ae_mulzaad32usep_hl_lh_funcUnit_uses }, + { "ae_mulzaad32usep.hl.lh_s2", ICLASS_AE_MULZAAD32USEP_HL_LH_S2, + 0, + Opcode_ae_mulzaad32usep_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzaad32usep_hl_lh_s2_funcUnit_uses }, + { "ae_mul32usep.lh", ICLASS_AE_MUL32USEP_LH, + 0, + Opcode_ae_mul32usep_lh_encode_fns, 1, Opcode_ae_mul32usep_lh_funcUnit_uses }, + { "ae_mula32usep.lh", ICLASS_AE_MULA32USEP_LH, + 0, + Opcode_ae_mula32usep_lh_encode_fns, 1, Opcode_ae_mula32usep_lh_funcUnit_uses }, + { "ae_mul32usep.ll", ICLASS_AE_MUL32USEP_LL, + 0, + Opcode_ae_mul32usep_ll_encode_fns, 1, Opcode_ae_mul32usep_ll_funcUnit_uses }, + { "ae_mula32usep.ll", ICLASS_AE_MULA32USEP_LL, + 0, + Opcode_ae_mula32usep_ll_encode_fns, 1, Opcode_ae_mula32usep_ll_funcUnit_uses }, + { "ae_srai72", ICLASS_AE_SRAI72, + 0, + Opcode_ae_srai72_encode_fns, 0, 0 }, + { "ae_slai72", ICLASS_AE_SLAI72, + 0, + Opcode_ae_slai72_encode_fns, 0, 0 }, + { "ae_sat64s", ICLASS_AE_SAT64S, + 0, + Opcode_ae_sat64s_encode_fns, 0, 0 }, + { "ae_l16si.n", ICLASS_AE_L16SI_N, + 0, + Opcode_ae_l16si_n_encode_fns, 2, Opcode_ae_l16si_n_funcUnit_uses }, + { "ae_l16ui.n", ICLASS_AE_L16UI_N, + 0, + Opcode_ae_l16ui_n_encode_fns, 2, Opcode_ae_l16ui_n_funcUnit_uses }, + { "ae_s16i.n", ICLASS_AE_S16I_N, + 0, + Opcode_ae_s16i_n_encode_fns, 2, Opcode_ae_s16i_n_funcUnit_uses }, + { "ae_movfcrfsrv", ICLASS_AE_MOVFCRFSRV, + 0, + Opcode_ae_movfcrfsrv_encode_fns, 0, 0 }, + { "ae_movvfcrfsr", ICLASS_AE_MOVVFCRFSR, + 0, + Opcode_ae_movvfcrfsr_encode_fns, 0, 0 }, + { "rfr", ICLASS_RFR, + 0, + Opcode_rfr_encode_fns, 0, 0 }, + { "wfr", ICLASS_WFR, + 0, + Opcode_wfr_encode_fns, 0, 0 }, + { "movt.s", ICLASS_MOVT_S, + 0, + Opcode_movt_s_encode_fns, 0, 0 }, + { "movf.s", ICLASS_MOVF_S, + 0, + Opcode_movf_s_encode_fns, 0, 0 }, + { "moveqz.s", ICLASS_MOVEQZ_S, + 0, + Opcode_moveqz_s_encode_fns, 0, 0 }, + { "movnez.s", ICLASS_MOVNEZ_S, + 0, + Opcode_movnez_s_encode_fns, 0, 0 }, + { "movgez.s", ICLASS_MOVGEZ_S, + 0, + Opcode_movgez_s_encode_fns, 0, 0 }, + { "movltz.s", ICLASS_MOVLTZ_S, + 0, + Opcode_movltz_s_encode_fns, 0, 0 }, + { "trunc.s", ICLASS_TRUNC_S, + 0, + Opcode_trunc_s_encode_fns, 0, 0 }, + { "utrunc.s", ICLASS_UTRUNC_S, + 0, + Opcode_utrunc_s_encode_fns, 0, 0 }, + { "trunc.sx2", ICLASS_TRUNC_SX2, + 0, + Opcode_trunc_sx2_encode_fns, 0, 0 }, + { "utrunc.sx2", ICLASS_UTRUNC_SX2, + 0, + Opcode_utrunc_sx2_encode_fns, 0, 0 }, + { "ficeil.s", ICLASS_FICEIL_S, + 0, + Opcode_ficeil_s_encode_fns, 0, 0 }, + { "fifloor.s", ICLASS_FIFLOOR_S, + 0, + Opcode_fifloor_s_encode_fns, 0, 0 }, + { "firound.s", ICLASS_FIROUND_S, + 0, + Opcode_firound_s_encode_fns, 0, 0 }, + { "fitrunc.s", ICLASS_FITRUNC_S, + 0, + Opcode_fitrunc_s_encode_fns, 0, 0 }, + { "firint.s", ICLASS_FIRINT_S, + 0, + Opcode_firint_s_encode_fns, 0, 0 }, + { "cvtsf16.l", ICLASS_CVTSF16_L, + 0, + Opcode_cvtsf16_l_encode_fns, 0, 0 }, + { "cvtsf16.h", ICLASS_CVTSF16_H, + 0, + Opcode_cvtsf16_h_encode_fns, 0, 0 }, + { "cvtf16s.l", ICLASS_CVTF16S_L, + 0, + Opcode_cvtf16s_l_encode_fns, 0, 0 }, + { "cvtf16s.h", ICLASS_CVTF16S_H, + 0, + Opcode_cvtf16s_h_encode_fns, 0, 0 }, + { "abs.s", ICLASS_ABS_S, + 0, + Opcode_abs_s_encode_fns, 0, 0 }, + { "mul.s", ICLASS_MUL_S, + 0, + Opcode_mul_s_encode_fns, 0, 0 }, + { "madd.s", ICLASS_MADD_S, + 0, + Opcode_madd_s_encode_fns, 0, 0 }, + { "msub.s", ICLASS_MSUB_S, + 0, + Opcode_msub_s_encode_fns, 0, 0 }, + { "msubn.s", ICLASS_MSUBN_S, + 0, + Opcode_msubn_s_encode_fns, 0, 0 }, + { "maddn.s", ICLASS_MADDN_S, + 0, + Opcode_maddn_s_encode_fns, 0, 0 }, + { "add.s", ICLASS_ADD_S, + 0, + Opcode_add_s_encode_fns, 0, 0 }, + { "sub.s", ICLASS_SUB_S, + 0, + Opcode_sub_s_encode_fns, 0, 0 }, + { "neg.s", ICLASS_NEG_S, + 0, + Opcode_neg_s_encode_fns, 0, 0 }, + { "float.s", ICLASS_FLOAT_S, + 0, + Opcode_float_s_encode_fns, 0, 0 }, + { "ufloat.s", ICLASS_UFLOAT_S, + 0, + Opcode_ufloat_s_encode_fns, 0, 0 }, + { "float.sx2", ICLASS_FLOAT_SX2, + 0, + Opcode_float_sx2_encode_fns, 0, 0 }, + { "ufloat.sx2", ICLASS_UFLOAT_SX2, + 0, + Opcode_ufloat_sx2_encode_fns, 0, 0 }, + { "ole.s", ICLASS_OLE_S, + 0, + Opcode_ole_s_encode_fns, 0, 0 }, + { "olt.s", ICLASS_OLT_S, + 0, + Opcode_olt_s_encode_fns, 0, 0 }, + { "oeq.s", ICLASS_OEQ_S, + 0, + Opcode_oeq_s_encode_fns, 0, 0 }, + { "un.s", ICLASS_UN_S, + 0, + Opcode_un_s_encode_fns, 0, 0 }, + { "ule.s", ICLASS_ULE_S, + 0, + Opcode_ule_s_encode_fns, 0, 0 }, + { "ult.s", ICLASS_ULT_S, + 0, + Opcode_ult_s_encode_fns, 0, 0 }, + { "ueq.s", ICLASS_UEQ_S, + 0, + Opcode_ueq_s_encode_fns, 0, 0 }, + { "const.s", ICLASS_CONST_S, + 0, + Opcode_const_s_encode_fns, 0, 0 }, + { "nexp01.s", ICLASS_NEXP01_S, + 0, + Opcode_nexp01_s_encode_fns, 0, 0 }, + { "mksadj.s", ICLASS_MKSADJ_S, + 0, + Opcode_mksadj_s_encode_fns, 0, 0 }, + { "mkdadj.s", ICLASS_MKDADJ_S, + 0, + Opcode_mkdadj_s_encode_fns, 0, 0 }, + { "div0.s", ICLASS_DIV0_S, + 0, + Opcode_div0_s_encode_fns, 0, 0 }, + { "sqrt0.s", ICLASS_SQRT0_S, + 0, + Opcode_sqrt0_s_encode_fns, 0, 0 }, + { "recip0.s", ICLASS_RECIP0_S, + 0, + Opcode_recip0_s_encode_fns, 0, 0 }, + { "rsqrt0.s", ICLASS_RSQRT0_S, + 0, + Opcode_rsqrt0_s_encode_fns, 0, 0 }, + { "divn.s", ICLASS_DIVN_S, + 0, + Opcode_divn_s_encode_fns, 0, 0 }, + { "addexp.s", ICLASS_ADDEXP_S, + 0, + Opcode_addexp_s_encode_fns, 0, 0 }, + { "addexpm.s", ICLASS_ADDEXPM_S, + 0, + Opcode_addexpm_s_encode_fns, 0, 0 }, + { "min.s", ICLASS_MIN_S, + 0, + Opcode_min_s_encode_fns, 0, 0 }, + { "max.s", ICLASS_MAX_S, + 0, + Opcode_max_s_encode_fns, 0, 0 }, + { "mulmux.s", ICLASS_MULMUX_S, + 0, + Opcode_mulmux_s_encode_fns, 0, 0 }, + { "maddmux.s", ICLASS_MADDMUX_S, + 0, + Opcode_maddmux_s_encode_fns, 0, 0 }, + { "conjc.s", ICLASS_CONJC_S, + 0, + Opcode_conjc_s_encode_fns, 0, 0 }, + { "sigmoid_q15", ICLASS_SIGMOID_Q15, + 0, + Opcode_sigmoid_q15_encode_fns, 0, 0 }, + { "sigmoid_fp32", ICLASS_SIGMOID_FP32, + 0, + Opcode_sigmoid_fp32_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUB, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BNEI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BALL, + OPCODE_BANY, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQ, + OPCODE_BGE, + OPCODE_BGEU, + OPCODE_BLT, + OPCODE_BLTU, + OPCODE_BNALL, + OPCODE_BNE, + OPCODE_BNONE, + OPCODE_BEQZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_BNEZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPGTZ, + OPCODE_LOOPNEZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVGEZ, + OPCODE_MOVLTZ, + OPCODE_MOVNEZ, + OPCODE_ABS, + OPCODE_NEG, + OPCODE_NOP, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSA8B, + OPCODE_SSA8L, + OPCODE_SSL, + OPCODE_SSR, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRA, + OPCODE_SRL, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_DSYNC, + OPCODE_ESYNC, + OPCODE_RSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_MUL16S, + OPCODE_MUL16U, + OPCODE_MULL, + OPCODE_MULSH, + OPCODE_MULUH, + OPCODE_MUL_AA_HH, + OPCODE_MUL_AA_HL, + OPCODE_MUL_AA_LH, + OPCODE_MUL_AA_LL, + OPCODE_UMUL_AA_HH, + OPCODE_UMUL_AA_HL, + OPCODE_UMUL_AA_LH, + OPCODE_UMUL_AA_LL, + OPCODE_MUL_AD_HH, + OPCODE_MUL_AD_HL, + OPCODE_MUL_AD_LH, + OPCODE_MUL_AD_LL, + OPCODE_MUL_DA_HH, + OPCODE_MUL_DA_HL, + OPCODE_MUL_DA_LH, + OPCODE_MUL_DA_LL, + OPCODE_MUL_DD_HH, + OPCODE_MUL_DD_HL, + OPCODE_MUL_DD_LH, + OPCODE_MUL_DD_LL, + OPCODE_MULA_AA_HH, + OPCODE_MULA_AA_HL, + OPCODE_MULA_AA_LH, + OPCODE_MULA_AA_LL, + OPCODE_MULS_AA_HH, + OPCODE_MULS_AA_HL, + OPCODE_MULS_AA_LH, + OPCODE_MULS_AA_LL, + OPCODE_MULA_AD_HH, + OPCODE_MULA_AD_HL, + OPCODE_MULA_AD_LH, + OPCODE_MULA_AD_LL, + OPCODE_MULS_AD_HH, + OPCODE_MULS_AD_HL, + OPCODE_MULS_AD_LH, + OPCODE_MULS_AD_LL, + OPCODE_MULA_DA_HH, + OPCODE_MULA_DA_HL, + OPCODE_MULA_DA_LH, + OPCODE_MULA_DA_LL, + OPCODE_MULS_DA_HH, + OPCODE_MULS_DA_HL, + OPCODE_MULS_DA_LH, + OPCODE_MULS_DA_LL, + OPCODE_MULA_DD_HH, + OPCODE_MULA_DD_HL, + OPCODE_MULA_DD_LH, + OPCODE_MULA_DD_LL, + OPCODE_MULS_DD_HH, + OPCODE_MULS_DD_HL, + OPCODE_MULS_DD_LH, + OPCODE_MULS_DD_LL, + OPCODE_MULA_DA_HH_LDDEC, + OPCODE_MULA_DA_HH_LDINC, + OPCODE_MULA_DA_HL_LDDEC, + OPCODE_MULA_DA_HL_LDINC, + OPCODE_MULA_DA_LH_LDDEC, + OPCODE_MULA_DA_LH_LDINC, + OPCODE_MULA_DA_LL_LDDEC, + OPCODE_MULA_DA_LL_LDINC, + OPCODE_MULA_DD_HH_LDDEC, + OPCODE_MULA_DD_HH_LDINC, + OPCODE_MULA_DD_HL_LDDEC, + OPCODE_MULA_DD_HL_LDINC, + OPCODE_MULA_DD_LH_LDDEC, + OPCODE_MULA_DD_LH_LDINC, + OPCODE_MULA_DD_LL_LDDEC, + OPCODE_MULA_DD_LL_LDINC, + OPCODE_LDDEC, + OPCODE_LDINC, + OPCODE_RSR_M0, + OPCODE_WSR_M0, + OPCODE_XSR_M0, + OPCODE_RSR_M1, + OPCODE_WSR_M1, + OPCODE_XSR_M1, + OPCODE_RSR_M2, + OPCODE_WSR_M2, + OPCODE_XSR_M2, + OPCODE_RSR_M3, + OPCODE_WSR_M3, + OPCODE_XSR_M3, + OPCODE_RSR_ACCLO, + OPCODE_WSR_ACCLO, + OPCODE_XSR_ACCLO, + OPCODE_RSR_ACCHI, + OPCODE_WSR_ACCHI, + OPCODE_XSR_ACCHI, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ALL4, + OPCODE_ANY4, + OPCODE_ALL8, + OPCODE_ANY8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_IHI, + OPCODE_IPF, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_IPFL, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWBUI_P, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFRO, + OPCODE_DPFW, + OPCODE_DPFWO, + OPCODE_DPFM_B, + OPCODE_DPFM_BF, + OPCODE_DPFR_B, + OPCODE_DPFR_BF, + OPCODE_DPFW_B, + OPCODE_DPFW_BF, + OPCODE_PFNXT_F, + OPCODE_DHI_B, + OPCODE_DHWBI_B, + OPCODE_DHWB_B, + OPCODE_PFEND_A, + OPCODE_PFEND_O, + OPCODE_PFWAIT_A, + OPCODE_PFWAIT_R, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_DPFL, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_RSR_PREFCTL, + OPCODE_WSR_PREFCTL, + OPCODE_XSR_PREFCTL, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MAX, + OPCODE_MAXU, + OPCODE_MIN, + OPCODE_MINU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOS, + OPCODE_QUOU, + OPCODE_REMS, + OPCODE_REMU, + OPCODE_RER, + OPCODE_WER, + OPCODE_BEQZ_W15, + OPCODE_BGEZ_W15, + OPCODE_BLTZ_W15, + OPCODE_BNEZ_W15, + OPCODE_BEQI_W15, + OPCODE_BGEI_W15, + OPCODE_BLTI_W15, + OPCODE_BNEI_W15, + OPCODE_BGEUI_W15, + OPCODE_BLTUI_W15, + OPCODE_BBCI_W15, + OPCODE_BBSI_W15, + OPCODE_BALL_W15, + OPCODE_BANY_W15, + OPCODE_BBC_W15, + OPCODE_BBS_W15, + OPCODE_BEQ_W15, + OPCODE_BGEU_W15, + OPCODE_BGE_W15, + OPCODE_BLTU_W15, + OPCODE_BLT_W15, + OPCODE_BNALL_W15, + OPCODE_BNE_W15, + OPCODE_BNONE_W15, + OPCODE_RUR_AE_OVF_SAR, + OPCODE_WUR_AE_OVF_SAR, + OPCODE_RUR_AE_BITHEAD, + OPCODE_WUR_AE_BITHEAD, + OPCODE_RUR_AE_TS_FTS_BU_BP, + OPCODE_WUR_AE_TS_FTS_BU_BP, + OPCODE_RUR_AE_CW_SD_NO, + OPCODE_WUR_AE_CW_SD_NO, + OPCODE_RUR_AE_CBEGIN0, + OPCODE_WUR_AE_CBEGIN0, + OPCODE_RUR_AE_CEND0, + OPCODE_WUR_AE_CEND0, + OPCODE_RUR_AE_CBEGIN1, + OPCODE_WUR_AE_CBEGIN1, + OPCODE_RUR_AE_CEND1, + OPCODE_WUR_AE_CEND1, + OPCODE_AE_SEXT16, + OPCODE_AE_ZEXT16, + OPCODE_AE_CLAMPS16, + OPCODE_RUR_FCR, + OPCODE_WUR_FCR, + OPCODE_RUR_FSR, + OPCODE_WUR_FSR, + OPCODE_F64ITER, + OPCODE_F64RND, + OPCODE_F64ADDC, + OPCODE_F64SUBC, + OPCODE_F64SIG, + OPCODE_F64CMPL, + OPCODE_F64CMPH, + OPCODE_F64NORM, + OPCODE_F64SEXP, + OPCODE_RF64R, + OPCODE_WF64R, + OPCODE_RUR_F64R_LO, + OPCODE_WUR_F64R_LO, + OPCODE_RUR_F64R_HI, + OPCODE_WUR_F64R_HI, + OPCODE_RUR_F64S, + OPCODE_WUR_F64S, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE, + OPCODE_RUR_AE_OVERFLOW, + OPCODE_WUR_AE_OVERFLOW, + OPCODE_RUR_AE_SAR, + OPCODE_WUR_AE_SAR, + OPCODE_RUR_AE_BITPTR, + OPCODE_WUR_AE_BITPTR, + OPCODE_RUR_AE_BITSUSED, + OPCODE_WUR_AE_BITSUSED, + OPCODE_RUR_AE_TABLESIZE, + OPCODE_WUR_AE_TABLESIZE, + OPCODE_RUR_AE_FIRST_TS, + OPCODE_WUR_AE_FIRST_TS, + OPCODE_RUR_AE_NEXTOFFSET, + OPCODE_WUR_AE_NEXTOFFSET, + OPCODE_RUR_AE_SEARCHDONE, + OPCODE_WUR_AE_SEARCHDONE, + OPCODE_RUR_AE_CWRAP, + OPCODE_WUR_AE_CWRAP, + OPCODE_AE_L8X4F_I, + OPCODE_AE_L8X4F_IP, + OPCODE_AE_L16M_XC, + OPCODE_AE_L16M_XC1, + OPCODE_AE_L16M_I, + OPCODE_AE_L16M_IU, + OPCODE_AE_L16M_X, + OPCODE_AE_L16M_XU, + OPCODE_AE_L16_XC, + OPCODE_AE_L16_XC1, + OPCODE_AE_L16_I, + OPCODE_AE_L16_IP, + OPCODE_AE_L16_X, + OPCODE_AE_L16_XP, + OPCODE_AE_L32F24_XC, + OPCODE_AE_L32F24_XC1, + OPCODE_AE_L32F24_I, + OPCODE_AE_L32F24_IP, + OPCODE_AE_L32F24_X, + OPCODE_AE_L32F24_XP, + OPCODE_AE_L32_XC, + OPCODE_AE_L32_XC1, + OPCODE_AE_L32_I, + OPCODE_AE_L32_IP, + OPCODE_AE_L32_X, + OPCODE_AE_L32_XP, + OPCODE_AE_L32M_XC, + OPCODE_AE_L32M_I, + OPCODE_AE_L32M_IU, + OPCODE_AE_L32M_X, + OPCODE_AE_L32M_XU, + OPCODE_AE_L16X2M_XC, + OPCODE_AE_L16X2M_XC1, + OPCODE_AE_L16X2M_I, + OPCODE_AE_L16X2M_IU, + OPCODE_AE_L16X2M_X, + OPCODE_AE_L16X2M_XU, + OPCODE_AE_L32X2F24_XC, + OPCODE_AE_L32X2F24_XC1, + OPCODE_AE_L32X2F24_I, + OPCODE_AE_L32X2F24_IP, + OPCODE_AE_L32X2F24_RIP, + OPCODE_AE_L32X2F24_RI, + OPCODE_AE_L32X2F24_RIC, + OPCODE_AE_L32X2F24_RIC1, + OPCODE_AE_L32X2F24_X, + OPCODE_AE_L32X2F24_XP, + OPCODE_AE_L32X2_XC, + OPCODE_AE_L32X2_XC1, + OPCODE_AE_L32X2_I, + OPCODE_AE_L32X2_IP, + OPCODE_AE_L32X2_RIC, + OPCODE_AE_L32X2_RIC1, + OPCODE_AE_L32X2_X, + OPCODE_AE_L32X2_XP, + OPCODE_AE_L16X4_XC, + OPCODE_AE_L16X4_XC1, + OPCODE_AE_L16X4_I, + OPCODE_AE_L16X4_IP, + OPCODE_AE_L16X4_X, + OPCODE_AE_L16X4_XP, + OPCODE_AE_L64_XC, + OPCODE_AE_L64_XC1, + OPCODE_AE_L64_I, + OPCODE_AE_L64_IP, + OPCODE_AE_L64_X, + OPCODE_AE_L64_XP, + OPCODE_AE_S16X2M_XC, + OPCODE_AE_S16X2M_XC1, + OPCODE_AE_S16X2M_I, + OPCODE_AE_S16X2M_IU, + OPCODE_AE_S16X2M_X, + OPCODE_AE_S16X2M_XU, + OPCODE_AE_S32X2F24_XC, + OPCODE_AE_S32X2F24_XC1, + OPCODE_AE_S32X2F24_I, + OPCODE_AE_S32X2F24_IP, + OPCODE_AE_S32X2F24_RIP, + OPCODE_AE_S32X2F24_RIC, + OPCODE_AE_S32X2F24_RIC1, + OPCODE_AE_S32X2F24_X, + OPCODE_AE_S32X2F24_XP, + OPCODE_AE_S32X2_XC, + OPCODE_AE_S32X2_XC1, + OPCODE_AE_S32X2_I, + OPCODE_AE_S32X2_IP, + OPCODE_AE_S32X2_RIC, + OPCODE_AE_S32X2_RIC1, + OPCODE_AE_S32X2_X, + OPCODE_AE_S32X2_XP, + OPCODE_AE_S32X2RNG_I, + OPCODE_AE_S32X2RNG_IP, + OPCODE_AE_S32X2RNG_X, + OPCODE_AE_S32X2RNG_XP, + OPCODE_AE_S16X4_XC, + OPCODE_AE_S16X4_XC1, + OPCODE_AE_S16X4_I, + OPCODE_AE_S16X4_IP, + OPCODE_AE_S16X4_X, + OPCODE_AE_S16X4_XP, + OPCODE_AE_S16M_L_XC, + OPCODE_AE_S16M_L_XC1, + OPCODE_AE_S16M_L_I, + OPCODE_AE_S16M_L_IU, + OPCODE_AE_S16M_L_X, + OPCODE_AE_S16M_L_XU, + OPCODE_AE_S32F24_L_XC, + OPCODE_AE_S32F24_L_XC1, + OPCODE_AE_S32F24_L_I, + OPCODE_AE_S32F24_L_IP, + OPCODE_AE_S32F24_L_X, + OPCODE_AE_S32F24_L_XP, + OPCODE_AE_S32_L_XC, + OPCODE_AE_S32_L_XC1, + OPCODE_AE_S32_L_I, + OPCODE_AE_S32_L_IP, + OPCODE_AE_S32_L_X, + OPCODE_AE_S32_L_XP, + OPCODE_AE_S16_0_XC, + OPCODE_AE_S16_0_XC1, + OPCODE_AE_S16_0_I, + OPCODE_AE_S16_0_IP, + OPCODE_AE_S16_0_X, + OPCODE_AE_S16_0_XP, + OPCODE_AE_S64_XC, + OPCODE_AE_S64_XC1, + OPCODE_AE_S64_I, + OPCODE_AE_S64_IP, + OPCODE_AE_S64_X, + OPCODE_AE_S64_XP, + OPCODE_AE_S32M_XC, + OPCODE_AE_S32M_I, + OPCODE_AE_S32M_IU, + OPCODE_AE_S32M_X, + OPCODE_AE_S32M_XU, + OPCODE_AE_ZALIGN64, + OPCODE_AE_LALIGN64_I, + OPCODE_AE_SALIGN64_I, + OPCODE_AE_MOVALIGN, + OPCODE_AE_LA64_PP, + OPCODE_AE_LA24POS_PC, + OPCODE_AE_LA24X2POS_PC, + OPCODE_AE_LA32X2POS_PC, + OPCODE_AE_LA16X4POS_PC, + OPCODE_AE_LA24NEG_PC, + OPCODE_AE_LA24X2NEG_PC, + OPCODE_AE_LA32X2NEG_PC, + OPCODE_AE_LA16X4NEG_PC, + OPCODE_AE_LA24POS_PC1, + OPCODE_AE_LA24X2POS_PC1, + OPCODE_AE_LA32X2POS_PC1, + OPCODE_AE_LA16X4POS_PC1, + OPCODE_AE_LA24NEG_PC1, + OPCODE_AE_LA24X2NEG_PC1, + OPCODE_AE_LA32X2NEG_PC1, + OPCODE_AE_LA16X4NEG_PC1, + OPCODE_AE_SA64POS_FP, + OPCODE_AE_SA64NEG_FP, + OPCODE_AE_LA32X2_IC, + OPCODE_AE_LA32X2_IC1, + OPCODE_AE_LA32X2_IP, + OPCODE_AE_LA32X2_RIP, + OPCODE_AE_LA32X2_RIC, + OPCODE_AE_LA32X2_RIC1, + OPCODE_AE_LA16X4_IC, + OPCODE_AE_LA16X4_IC1, + OPCODE_AE_LA16X4_IP, + OPCODE_AE_LA16X4_RIP, + OPCODE_AE_LA16X4_RIC, + OPCODE_AE_LA16X4_RIC1, + OPCODE_AE_LA32X2F24_IC, + OPCODE_AE_LA32X2F24_IC1, + OPCODE_AE_LA32X2F24_IP, + OPCODE_AE_LA32X2F24_RIP, + OPCODE_AE_LA32X2F24_RIC, + OPCODE_AE_LA32X2F24_RIC1, + OPCODE_AE_LA24_IC, + OPCODE_AE_LA24_IC1, + OPCODE_AE_LA24_IP, + OPCODE_AE_LA24_RIP, + OPCODE_AE_LA24_RIC, + OPCODE_AE_LA24_RIC1, + OPCODE_AE_LA24X2_IC, + OPCODE_AE_LA24X2_IC1, + OPCODE_AE_LA24X2_IP, + OPCODE_AE_LA24X2_RIP, + OPCODE_AE_LA24X2_RIC, + OPCODE_AE_LA24X2_RIC1, + OPCODE_AE_SA32X2_IC, + OPCODE_AE_SA32X2_IC1, + OPCODE_AE_SA32X2_IP, + OPCODE_AE_SA32X2_RIP, + OPCODE_AE_SA32X2_RIC, + OPCODE_AE_SA32X2_RIC1, + OPCODE_AE_SA16X4_IC, + OPCODE_AE_SA16X4_IC1, + OPCODE_AE_SA16X4_IP, + OPCODE_AE_SA16X4_RIP, + OPCODE_AE_SA16X4_RIC, + OPCODE_AE_SA16X4_RIC1, + OPCODE_AE_SA32X2F24_IC, + OPCODE_AE_SA32X2F24_IC1, + OPCODE_AE_SA32X2F24_IP, + OPCODE_AE_SA32X2F24_RIP, + OPCODE_AE_SA32X2F24_RIC, + OPCODE_AE_SA32X2F24_RIC1, + OPCODE_AE_SA24_L_IC, + OPCODE_AE_SA24_L_IC1, + OPCODE_AE_SA24_L_IP, + OPCODE_AE_SA24_L_RIP, + OPCODE_AE_SA24_L_RIC, + OPCODE_AE_SA24_L_RIC1, + OPCODE_AE_SA24X2_IC, + OPCODE_AE_SA24X2_IC1, + OPCODE_AE_SA24X2_IP, + OPCODE_AE_SA24X2_RIP, + OPCODE_AE_SA24X2_RIC, + OPCODE_AE_SA24X2_RIC1, + OPCODE_AE_ADDICIRC, + OPCODE_AE_ADDCIRC_XC1, + OPCODE_AE_ADDCIRC_XC, + OPCODE_AE_S32RA64S_I, + OPCODE_AE_S32RA64S_IP, + OPCODE_AE_S32RA64S_X, + OPCODE_AE_S32RA64S_XP, + OPCODE_AE_S32RA64S_XC, + OPCODE_AE_S32RA64S_XC1, + OPCODE_AE_S24RA64S_I, + OPCODE_AE_S24RA64S_IP, + OPCODE_AE_S24RA64S_X, + OPCODE_AE_S24RA64S_XP, + OPCODE_AE_S24RA64S_XC, + OPCODE_AE_S24RA64S_XC1, + OPCODE_AE_S32X2RA64S_IP, + OPCODE_AE_S24X2RA64S_IP, + OPCODE_AE_ADDBRBA32, + OPCODE_AE_BITSWAP, + OPCODE_AE_MUL32JS, + OPCODE_AE_ADDANDSUB32S, + OPCODE_AE_ADDANDSUBRNG32, + OPCODE_AE_ADDRNG32, + OPCODE_AE_SUBRNG32, + OPCODE_AE_CALCRNG3, + OPCODE_AE_CALCRNG2, + OPCODE_AE_CALCRNG1, + OPCODE_AE_RNG32X2, + OPCODE_AE_SEL16I, + OPCODE_AE_SEL16I_N, + OPCODE_AE_SHORTSWAP, + OPCODE_AE_MOVAB4, + OPCODE_AE_MOVAB2, + OPCODE_AE_MOVAB, + OPCODE_AE_MOVBA, + OPCODE_AE_MOVBA1X2, + OPCODE_AE_MOVBA4, + OPCODE_AE_MOVBA2, + OPCODE_AE_MOVB2, + OPCODE_AE_MOVB4, + OPCODE_AE_MOVT16X4, + OPCODE_AE_MOVF16X4, + OPCODE_AE_MOVT32X2, + OPCODE_AE_MOVF32X2, + OPCODE_AE_MOVSARA7X2, + OPCODE_AE_MOVSARD7, + OPCODE_AE_MOVASAR, + OPCODE_AE_MOVDA32X2, + OPCODE_AE_MOVDA32, + OPCODE_AE_MOVDA16X2, + OPCODE_AE_MOVDA16, + OPCODE_AE_MOVI, + OPCODE_AE_TRUNCP24A32X2, + OPCODE_AE_SAT16X4, + OPCODE_AE_CVT32X2F16_32, + OPCODE_AE_CVT32X2F16_10, + OPCODE_AE_SEXT32X2D16_32, + OPCODE_AE_SEXT32X2D16_10, + OPCODE_AE_CVTA32F24S_L, + OPCODE_AE_CVTA32F24S_H, + OPCODE_AE_CVTP24A16X2_LL, + OPCODE_AE_CVTP24A16X2_LH, + OPCODE_AE_CVTP24A16X2_HL, + OPCODE_AE_CVTP24A16X2_HH, + OPCODE_AE_TRUNCP24Q48X2, + OPCODE_AE_TRUNCA32X2F64S, + OPCODE_AE_TRUNCI32X2F64S, + OPCODE_AE_TRUNCA32F64S_L, + OPCODE_AE_TRUNCI32F64S_L, + OPCODE_AE_TRUNCP16, + OPCODE_AE_ROUND32X2F64SSYM, + OPCODE_AE_ROUND32X2F64SASYM, + OPCODE_AE_ROUND32X2F48SSYM, + OPCODE_AE_ROUND32X2F48SASYM, + OPCODE_AE_ROUND16X4F32SSYM, + OPCODE_AE_ROUND16X4F32SASYM, + OPCODE_AE_ROUND24X2F48SSYM, + OPCODE_AE_ROUND24X2F48SASYM, + OPCODE_AE_ROUNDSP16Q48X2SYM, + OPCODE_AE_ROUNDSP16Q48X2ASYM, + OPCODE_AE_MINABS32S, + OPCODE_AE_MAXABS32S, + OPCODE_AE_ROUNDSP16F24SYM, + OPCODE_AE_ROUNDSP16F24ASYM, + OPCODE_AE_MOV, + OPCODE_AE_MOVT64, + OPCODE_AE_MOVF64, + OPCODE_AE_CVTQ56A32S, + OPCODE_AE_CVT48A32, + OPCODE_AE_CVT64A32, + OPCODE_AE_CVTQ56P32S_L, + OPCODE_AE_CVTQ56P32S_H, + OPCODE_AE_CVT64F32_H, + OPCODE_AE_CVT48F32_L, + OPCODE_AE_CVT48F32_H, + OPCODE_AE_SAT48S, + OPCODE_AE_SATQ56S, + OPCODE_AE_SAT24S, + OPCODE_AE_TRUNCQ32, + OPCODE_AE_MINABS64S, + OPCODE_AE_MAXABS64S, + OPCODE_AE_ROUNDSQ32F48SYM, + OPCODE_AE_ROUNDSQ32F48ASYM, + OPCODE_AE_TRUNCA32Q48, + OPCODE_AE_MOVAD32_L, + OPCODE_AE_MOVAD32_H, + OPCODE_AE_MOVAD16_3, + OPCODE_AE_MOVAD16_2, + OPCODE_AE_MOVAD16_1, + OPCODE_AE_MOVAD16_0, + OPCODE_AE_SRA64_32, + OPCODE_AE_PKSR32, + OPCODE_AE_PKSR24, + OPCODE_AE_PKSRF32, + OPCODE_AE_TRUNCA16P24S_L, + OPCODE_AE_TRUNCA16P24S_H, + OPCODE_AE_ADD32, + OPCODE_AE_SUB32, + OPCODE_AE_ADDSUB32, + OPCODE_AE_SUBADD32, + OPCODE_AE_ADD16, + OPCODE_AE_SUB16, + OPCODE_AE_ADD32_HL_LH, + OPCODE_AE_NEG32, + OPCODE_AE_ABS32, + OPCODE_AE_ADD24S, + OPCODE_AE_SUB24S, + OPCODE_AE_ADD32S, + OPCODE_AE_SUB32S, + OPCODE_AE_ADDSUB32S, + OPCODE_AE_SUBADD32S, + OPCODE_AE_ADD16S, + OPCODE_AE_SUB16S, + OPCODE_AE_ADD32S_HL_LH, + OPCODE_AE_NEG24S, + OPCODE_AE_ABS24S, + OPCODE_AE_NEG32S, + OPCODE_AE_ABS32S, + OPCODE_AE_NEG16S, + OPCODE_AE_ABS16S, + OPCODE_AE_LT16, + OPCODE_AE_LE16, + OPCODE_AE_EQ16, + OPCODE_AE_LT32, + OPCODE_AE_LE32, + OPCODE_AE_EQ32, + OPCODE_AE_MIN32, + OPCODE_AE_MAX32, + OPCODE_AE_ADD64, + OPCODE_AE_SUB64, + OPCODE_AE_NEG64, + OPCODE_AE_ABS64, + OPCODE_AE_ADDSQ56S, + OPCODE_AE_SUBSQ56S, + OPCODE_AE_ADD64S, + OPCODE_AE_SUB64S, + OPCODE_AE_NEGSQ56S, + OPCODE_AE_ABSSQ56S, + OPCODE_AE_NEG64S, + OPCODE_AE_ABS64S, + OPCODE_AE_AND, + OPCODE_AE_NAND, + OPCODE_AE_OR, + OPCODE_AE_XOR, + OPCODE_AE_SLAI24, + OPCODE_AE_SRLI24, + OPCODE_AE_SRAI24, + OPCODE_AE_SLAS24, + OPCODE_AE_SRLS24, + OPCODE_AE_SRAS24, + OPCODE_AE_SRAI16, + OPCODE_AE_SRAI16R, + OPCODE_AE_SLAI32, + OPCODE_AE_SRLI32, + OPCODE_AE_SRAI32, + OPCODE_AE_SRAI32R, + OPCODE_AE_SLAS32, + OPCODE_AE_SRLS32, + OPCODE_AE_SRAS32, + OPCODE_AE_SLAA32, + OPCODE_AE_SRLA32, + OPCODE_AE_SRAA32, + OPCODE_AE_SLAI16S, + OPCODE_AE_SLAA16S, + OPCODE_AE_SRAA16S, + OPCODE_AE_SRAA16RS, + OPCODE_AE_SLAI24S, + OPCODE_AE_SLAS24S, + OPCODE_AE_SLAI32S, + OPCODE_AE_SLAS32S, + OPCODE_AE_SLAA32S, + OPCODE_AE_SRAA32S, + OPCODE_AE_SRAA32RS, + OPCODE_AE_SLASQ56, + OPCODE_AE_SRLSQ56, + OPCODE_AE_SRASQ56, + OPCODE_AE_SLAAQ56, + OPCODE_AE_SRLAQ56, + OPCODE_AE_SRAAQ56, + OPCODE_AE_SLAI64, + OPCODE_AE_SRLI64, + OPCODE_AE_SRAI64, + OPCODE_AE_SLAS64, + OPCODE_AE_SRLS64, + OPCODE_AE_SRAS64, + OPCODE_AE_SLAA64, + OPCODE_AE_SRLA64, + OPCODE_AE_SRAA64, + OPCODE_AE_SLAISQ56S, + OPCODE_AE_SLASSQ56S, + OPCODE_AE_SLAASQ56S, + OPCODE_AE_SLAI64S, + OPCODE_AE_SLAS64S, + OPCODE_AE_SLAA64S, + OPCODE_AE_LT64, + OPCODE_AE_LE64, + OPCODE_AE_EQ64, + OPCODE_AE_MAX64, + OPCODE_AE_MIN64, + OPCODE_AE_NSA64, + OPCODE_AE_NSAZ16_0, + OPCODE_AE_NSAZ32_L, + OPCODE_AE_MULS32F48P16S_LL, + OPCODE_AE_MULF32S_LL, + OPCODE_AE_MUL32_LL, + OPCODE_AE_MULF32S_LL_S2, + OPCODE_AE_MUL32_LL_S2, + OPCODE_AE_MULS32F48P16S_LL_S2, + OPCODE_AE_MULF32R_LL, + OPCODE_AE_MULF32RA_LL, + OPCODE_AE_MULF32RA_LL_S2, + OPCODE_AE_MULF32R_LL_S2, + OPCODE_AE_MULS32F48P16S_LH, + OPCODE_AE_MULF32S_LH, + OPCODE_AE_MUL32_LH, + OPCODE_AE_MULF32S_LH_S2, + OPCODE_AE_MUL32_LH_S2, + OPCODE_AE_MULS32F48P16S_LH_S2, + OPCODE_AE_MULF32R_LH, + OPCODE_AE_MULF32RA_LH, + OPCODE_AE_MULF32RA_LH_S2, + OPCODE_AE_MULF32R_LH_S2, + OPCODE_AE_MULS32F48P16S_HH, + OPCODE_AE_MULF32S_HH, + OPCODE_AE_MUL32_HH, + OPCODE_AE_MULF32S_HH_S2, + OPCODE_AE_MUL32_HH_S2, + OPCODE_AE_MULS32F48P16S_HH_S2, + OPCODE_AE_MULF32R_HH, + OPCODE_AE_MULF32RA_HH, + OPCODE_AE_MULF32RA_HH_S2, + OPCODE_AE_MULF32R_HH_S2, + OPCODE_AE_MULAS32F48P16S_LL, + OPCODE_AE_MULAF32S_LL, + OPCODE_AE_MULA32_LL, + OPCODE_AE_MULAF32S_LL_S2, + OPCODE_AE_MULA32_LL_S2, + OPCODE_AE_MULAS32F48P16S_LL_S2, + OPCODE_AE_MULAF32R_LL, + OPCODE_AE_MULAF32RA_LL, + OPCODE_AE_MULAF32RA_LL_S2, + OPCODE_AE_MULAF32R_LL_S2, + OPCODE_AE_MULAS32F48P16S_LH, + OPCODE_AE_MULAF32S_LH, + OPCODE_AE_MULA32_LH, + OPCODE_AE_MULAF32S_LH_S2, + OPCODE_AE_MULA32_LH_S2, + OPCODE_AE_MULAS32F48P16S_LH_S2, + OPCODE_AE_MULAF32R_LH, + OPCODE_AE_MULAF32RA_LH, + OPCODE_AE_MULAF32RA_LH_S2, + OPCODE_AE_MULAF32R_LH_S2, + OPCODE_AE_MULAS32F48P16S_HH, + OPCODE_AE_MULAF32S_HH, + OPCODE_AE_MULA32_HH, + OPCODE_AE_MULAF32S_HH_S2, + OPCODE_AE_MULA32_HH_S2, + OPCODE_AE_MULAS32F48P16S_HH_S2, + OPCODE_AE_MULAF32R_HH, + OPCODE_AE_MULAF32RA_HH, + OPCODE_AE_MULAF32RA_HH_S2, + OPCODE_AE_MULAF32R_HH_S2, + OPCODE_AE_MULSS32F48P16S_LL, + OPCODE_AE_MULSF32S_LL, + OPCODE_AE_MULS32_LL, + OPCODE_AE_MULSF32S_LL_S2, + OPCODE_AE_MULS32_LL_S2, + OPCODE_AE_MULSS32F48P16S_LL_S2, + OPCODE_AE_MULSF32R_LL, + OPCODE_AE_MULSF32RA_LL, + OPCODE_AE_MULSF32RA_LL_S2, + OPCODE_AE_MULSF32R_LL_S2, + OPCODE_AE_MULSS32F48P16S_LH, + OPCODE_AE_MULSF32S_LH, + OPCODE_AE_MULS32_LH, + OPCODE_AE_MULSF32S_LH_S2, + OPCODE_AE_MULS32_LH_S2, + OPCODE_AE_MULSS32F48P16S_LH_S2, + OPCODE_AE_MULSF32R_LH, + OPCODE_AE_MULSF32RA_LH, + OPCODE_AE_MULSF32RA_LH_S2, + OPCODE_AE_MULSF32R_LH_S2, + OPCODE_AE_MULSS32F48P16S_HH, + OPCODE_AE_MULSF32S_HH, + OPCODE_AE_MULS32_HH, + OPCODE_AE_MULSF32S_HH_S2, + OPCODE_AE_MULS32_HH_S2, + OPCODE_AE_MULSS32F48P16S_HH_S2, + OPCODE_AE_MULSF32R_HH, + OPCODE_AE_MULSF32RA_HH, + OPCODE_AE_MULSF32RA_HH_S2, + OPCODE_AE_MULSF32R_HH_S2, + OPCODE_AE_MUL32U_LL, + OPCODE_AE_MULA32U_LL, + OPCODE_AE_MULS32U_LL, + OPCODE_AE_MULF16SS_33, + OPCODE_AE_MULF16SS_33_S2, + OPCODE_AE_MULF16SS_22, + OPCODE_AE_MULF16SS_22_S2, + OPCODE_AE_MULF16SS_32, + OPCODE_AE_MULF16SS_32_S2, + OPCODE_AE_MULF16SS_21, + OPCODE_AE_MULF16SS_21_S2, + OPCODE_AE_MULF16SS_31, + OPCODE_AE_MULF16SS_31_S2, + OPCODE_AE_MULF16SS_30, + OPCODE_AE_MULF16SS_30_S2, + OPCODE_AE_MULF16SS_10, + OPCODE_AE_MULF16SS_10_S2, + OPCODE_AE_MULF16SS_20, + OPCODE_AE_MULF16SS_20_S2, + OPCODE_AE_MULF16SS_11, + OPCODE_AE_MULF16SS_11_S2, + OPCODE_AE_MULF16SS_00, + OPCODE_AE_MULF16SS_00_S2, + OPCODE_AE_MULSF16SS_33, + OPCODE_AE_MULSF16SS_33_S2, + OPCODE_AE_MULSF16SS_22, + OPCODE_AE_MULSF16SS_22_S2, + OPCODE_AE_MULSF16SS_32, + OPCODE_AE_MULSF16SS_32_S2, + OPCODE_AE_MULSF16SS_21, + OPCODE_AE_MULSF16SS_21_S2, + OPCODE_AE_MULSF16SS_31, + OPCODE_AE_MULSF16SS_31_S2, + OPCODE_AE_MULSF16SS_30, + OPCODE_AE_MULSF16SS_30_S2, + OPCODE_AE_MULSF16SS_10, + OPCODE_AE_MULSF16SS_10_S2, + OPCODE_AE_MULSF16SS_20, + OPCODE_AE_MULSF16SS_20_S2, + OPCODE_AE_MULSF16SS_11, + OPCODE_AE_MULSF16SS_11_S2, + OPCODE_AE_MULSF16SS_00, + OPCODE_AE_MULSF16SS_00_S2, + OPCODE_AE_MULAF16SS_33, + OPCODE_AE_MULAF16SS_33_S2, + OPCODE_AE_MULAF16SS_22, + OPCODE_AE_MULAF16SS_22_S2, + OPCODE_AE_MULAF16SS_32, + OPCODE_AE_MULAF16SS_32_S2, + OPCODE_AE_MULAF16SS_21, + OPCODE_AE_MULAF16SS_21_S2, + OPCODE_AE_MULAF16SS_31, + OPCODE_AE_MULAF16SS_31_S2, + OPCODE_AE_MULAF16SS_30, + OPCODE_AE_MULAF16SS_30_S2, + OPCODE_AE_MULAF16SS_10, + OPCODE_AE_MULAF16SS_10_S2, + OPCODE_AE_MULAF16SS_20, + OPCODE_AE_MULAF16SS_20_S2, + OPCODE_AE_MULAF16SS_11, + OPCODE_AE_MULAF16SS_11_S2, + OPCODE_AE_MULAF16SS_00, + OPCODE_AE_MULAF16SS_00_S2, + OPCODE_AE_MULAAFD16SS_33_22, + OPCODE_AE_MULAAFD16SS_33_22_S2, + OPCODE_AE_MULAAFD16SS_13_02, + OPCODE_AE_MULAAFD16SS_13_02_S2, + OPCODE_AE_MULAAFD16SS_11_00, + OPCODE_AE_MULAAFD16SS_11_00_S2, + OPCODE_AE_MULSSFD16SS_33_22, + OPCODE_AE_MULSSFD16SS_33_22_S2, + OPCODE_AE_MULSSFD16SS_13_02, + OPCODE_AE_MULSSFD16SS_13_02_S2, + OPCODE_AE_MULSSFD16SS_11_00, + OPCODE_AE_MULSSFD16SS_11_00_S2, + OPCODE_AE_MULZAAFD16SS_33_22, + OPCODE_AE_MULZAAFD16SS_33_22_S2, + OPCODE_AE_MULZAAFD16SS_13_02, + OPCODE_AE_MULZAAFD16SS_13_02_S2, + OPCODE_AE_MULZAAFD16SS_11_00, + OPCODE_AE_MULZAAFD16SS_11_00_S2, + OPCODE_AE_MULZSSFD16SS_33_22, + OPCODE_AE_MULZSSFD16SS_33_22_S2, + OPCODE_AE_MULZSSFD16SS_13_02, + OPCODE_AE_MULZSSFD16SS_13_02_S2, + OPCODE_AE_MULZSSFD16SS_11_00, + OPCODE_AE_MULZSSFD16SS_11_00_S2, + OPCODE_AE_MULF48Q32SP16S_L, + OPCODE_AE_MULF48Q32SP16S_L_S2, + OPCODE_AE_MULF48Q32SP16U_L, + OPCODE_AE_MULF48Q32SP16U_L_S2, + OPCODE_AE_MULQ32SP16S_L, + OPCODE_AE_MULQ32SP16S_L_S2, + OPCODE_AE_MULQ32SP16U_L, + OPCODE_AE_MULQ32SP16U_L_S2, + OPCODE_AE_MULAF48Q32SP16S_L, + OPCODE_AE_MULAF48Q32SP16S_L_S2, + OPCODE_AE_MULAF48Q32SP16U_L, + OPCODE_AE_MULAF48Q32SP16U_L_S2, + OPCODE_AE_MULAQ32SP16S_L, + OPCODE_AE_MULAQ32SP16S_L_S2, + OPCODE_AE_MULAQ32SP16U_L, + OPCODE_AE_MULAQ32SP16U_L_S2, + OPCODE_AE_MULSF48Q32SP16S_L, + OPCODE_AE_MULSF48Q32SP16S_L_S2, + OPCODE_AE_MULSF48Q32SP16U_L, + OPCODE_AE_MULSF48Q32SP16U_L_S2, + OPCODE_AE_MULSQ32SP16S_L, + OPCODE_AE_MULSQ32SP16S_L_S2, + OPCODE_AE_MULSQ32SP16U_L, + OPCODE_AE_MULSQ32SP16U_L_S2, + OPCODE_AE_MULFP24X2RA, + OPCODE_AE_MULFP24X2R, + OPCODE_AE_MULFP24X2RA_S2, + OPCODE_AE_MULFP24X2R_S2, + OPCODE_AE_MULAFP24X2RA, + OPCODE_AE_MULAFP24X2R, + OPCODE_AE_MULAFP24X2RA_S2, + OPCODE_AE_MULAFP24X2R_S2, + OPCODE_AE_MULSFP24X2RA, + OPCODE_AE_MULSFP24X2R, + OPCODE_AE_MULSFP24X2RA_S2, + OPCODE_AE_MULSFP24X2R_S2, + OPCODE_AE_MULZAAFD32S_HH_LL, + OPCODE_AE_MULZAAFD32RA_HH_LL, + OPCODE_AE_MULZAAD32_HH_LL, + OPCODE_AE_MULZAAFD32S_HH_LL_S2, + OPCODE_AE_MULZAAFD32RA_HH_LL_S2, + OPCODE_AE_MULZAAD32_HH_LL_S2, + OPCODE_AE_MULZAAFD32S_HL_LH, + OPCODE_AE_MULZAAFD32RA_HL_LH, + OPCODE_AE_MULZAAD32_HL_LH, + OPCODE_AE_MULZAAFD32S_HL_LH_S2, + OPCODE_AE_MULZAAFD32RA_HL_LH_S2, + OPCODE_AE_MULZAAD32_HL_LH_S2, + OPCODE_AE_MULZASFD32S_HH_LL, + OPCODE_AE_MULZASFD32RA_HH_LL, + OPCODE_AE_MULZASD32_HH_LL, + OPCODE_AE_MULZASFD32S_HH_LL_S2, + OPCODE_AE_MULZASFD32RA_HH_LL_S2, + OPCODE_AE_MULZASD32_HH_LL_S2, + OPCODE_AE_MULZASFD32S_HL_LH, + OPCODE_AE_MULZASFD32RA_HL_LH, + OPCODE_AE_MULZASD32_HL_LH, + OPCODE_AE_MULZASFD32S_HL_LH_S2, + OPCODE_AE_MULZASFD32RA_HL_LH_S2, + OPCODE_AE_MULZASD32_HL_LH_S2, + OPCODE_AE_MULZSAFD32S_HH_LL, + OPCODE_AE_MULZSAFD32RA_HH_LL, + OPCODE_AE_MULZSAD32_HH_LL, + OPCODE_AE_MULZSAFD32S_HH_LL_S2, + OPCODE_AE_MULZSAFD32RA_HH_LL_S2, + OPCODE_AE_MULZSAD32_HH_LL_S2, + OPCODE_AE_MULZSSFD32S_HH_LL, + OPCODE_AE_MULZSSFD32RA_HH_LL, + OPCODE_AE_MULZSSD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HH_LL_S2, + OPCODE_AE_MULZSSFD32RA_HH_LL_S2, + OPCODE_AE_MULZSSD32_HH_LL_S2, + OPCODE_AE_MULZSSFD32S_HL_LH, + OPCODE_AE_MULZSSFD32RA_HL_LH, + OPCODE_AE_MULZSSD32_HL_LH, + OPCODE_AE_MULZSSFD32S_HL_LH_S2, + OPCODE_AE_MULZSSFD32RA_HL_LH_S2, + OPCODE_AE_MULZSSD32_HL_LH_S2, + OPCODE_AE_MULAAFD32S_HH_LL, + OPCODE_AE_MULAAFD32RA_HH_LL, + OPCODE_AE_MULAAD32_HH_LL, + OPCODE_AE_MULAAFD32S_HH_LL_S2, + OPCODE_AE_MULAAFD32RA_HH_LL_S2, + OPCODE_AE_MULAAD32_HH_LL_S2, + OPCODE_AE_MULAAFD32S_HL_LH, + OPCODE_AE_MULAAFD32RA_HL_LH, + OPCODE_AE_MULAAD32_HL_LH, + OPCODE_AE_MULAAFD32S_HL_LH_S2, + OPCODE_AE_MULAAFD32RA_HL_LH_S2, + OPCODE_AE_MULAAD32_HL_LH_S2, + OPCODE_AE_MULASFD32S_HH_LL, + OPCODE_AE_MULASFD32RA_HH_LL, + OPCODE_AE_MULASD32_HH_LL, + OPCODE_AE_MULASFD32S_HH_LL_S2, + OPCODE_AE_MULASFD32RA_HH_LL_S2, + OPCODE_AE_MULASD32_HH_LL_S2, + OPCODE_AE_MULASFD32S_HL_LH, + OPCODE_AE_MULASFD32RA_HL_LH, + OPCODE_AE_MULASD32_HL_LH, + OPCODE_AE_MULASFD32S_HL_LH_S2, + OPCODE_AE_MULASFD32RA_HL_LH_S2, + OPCODE_AE_MULASD32_HL_LH_S2, + OPCODE_AE_MULSAFD32S_HH_LL, + OPCODE_AE_MULSAFD32RA_HH_LL, + OPCODE_AE_MULSAD32_HH_LL, + OPCODE_AE_MULSAFD32S_HH_LL_S2, + OPCODE_AE_MULSAFD32RA_HH_LL_S2, + OPCODE_AE_MULSAD32_HH_LL_S2, + OPCODE_AE_MULSSFD32S_HH_LL, + OPCODE_AE_MULSSFD32RA_HH_LL, + OPCODE_AE_MULSSD32_HH_LL, + OPCODE_AE_MULSSFD32S_HH_LL_S2, + OPCODE_AE_MULSSFD32RA_HH_LL_S2, + OPCODE_AE_MULSSD32_HH_LL_S2, + OPCODE_AE_MULSSFD32S_HL_LH, + OPCODE_AE_MULSSFD32RA_HL_LH, + OPCODE_AE_MULSSD32_HL_LH, + OPCODE_AE_MULSSFD32S_HL_LH_S2, + OPCODE_AE_MULSSFD32RA_HL_LH_S2, + OPCODE_AE_MULSSD32_HL_LH_S2, + OPCODE_AE_MULF32X16_L0, + OPCODE_AE_MUL32X16_L0, + OPCODE_AE_MULF32X16_L0_S2, + OPCODE_AE_MUL32X16_L0_S2, + OPCODE_AE_MULF32X16_L1, + OPCODE_AE_MUL32X16_L1, + OPCODE_AE_MULF32X16_L1_S2, + OPCODE_AE_MUL32X16_L1_S2, + OPCODE_AE_MULF32X16_L2, + OPCODE_AE_MUL32X16_L2, + OPCODE_AE_MULF32X16_L2_S2, + OPCODE_AE_MUL32X16_L2_S2, + OPCODE_AE_MULF32X16_L3, + OPCODE_AE_MUL32X16_L3, + OPCODE_AE_MULF32X16_L3_S2, + OPCODE_AE_MUL32X16_L3_S2, + OPCODE_AE_MULF32X16_H0, + OPCODE_AE_MUL32X16_H0, + OPCODE_AE_MULF32X16_H0_S2, + OPCODE_AE_MUL32X16_H0_S2, + OPCODE_AE_MULF32X16_H1, + OPCODE_AE_MUL32X16_H1, + OPCODE_AE_MULF32X16_H1_S2, + OPCODE_AE_MUL32X16_H1_S2, + OPCODE_AE_MULF32X16_H2, + OPCODE_AE_MUL32X16_H2, + OPCODE_AE_MULF32X16_H2_S2, + OPCODE_AE_MUL32X16_H2_S2, + OPCODE_AE_MULF32X16_H3, + OPCODE_AE_MUL32X16_H3, + OPCODE_AE_MULF32X16_H3_S2, + OPCODE_AE_MUL32X16_H3_S2, + OPCODE_AE_MULAF32X16_L0, + OPCODE_AE_MULA32X16_L0, + OPCODE_AE_MULAF32X16_L0_S2, + OPCODE_AE_MULA32X16_L0_S2, + OPCODE_AE_MULAF32X16_L1, + OPCODE_AE_MULA32X16_L1, + OPCODE_AE_MULAF32X16_L1_S2, + OPCODE_AE_MULA32X16_L1_S2, + OPCODE_AE_MULAF32X16_L2, + OPCODE_AE_MULA32X16_L2, + OPCODE_AE_MULAF32X16_L2_S2, + OPCODE_AE_MULA32X16_L2_S2, + OPCODE_AE_MULAF32X16_L3, + OPCODE_AE_MULA32X16_L3, + OPCODE_AE_MULAF32X16_L3_S2, + OPCODE_AE_MULA32X16_L3_S2, + OPCODE_AE_MULAF32X16_H0, + OPCODE_AE_MULA32X16_H0, + OPCODE_AE_MULAF32X16_H0_S2, + OPCODE_AE_MULA32X16_H0_S2, + OPCODE_AE_MULAF32X16_H1, + OPCODE_AE_MULA32X16_H1, + OPCODE_AE_MULAF32X16_H1_S2, + OPCODE_AE_MULA32X16_H1_S2, + OPCODE_AE_MULAF32X16_H2, + OPCODE_AE_MULA32X16_H2, + OPCODE_AE_MULAF32X16_H2_S2, + OPCODE_AE_MULA32X16_H2_S2, + OPCODE_AE_MULAF32X16_H3, + OPCODE_AE_MULA32X16_H3, + OPCODE_AE_MULAF32X16_H3_S2, + OPCODE_AE_MULA32X16_H3_S2, + OPCODE_AE_MULSF32X16_L0, + OPCODE_AE_MULS32X16_L0, + OPCODE_AE_MULSF32X16_L0_S2, + OPCODE_AE_MULS32X16_L0_S2, + OPCODE_AE_MULSF32X16_L1, + OPCODE_AE_MULS32X16_L1, + OPCODE_AE_MULSF32X16_L1_S2, + OPCODE_AE_MULS32X16_L1_S2, + OPCODE_AE_MULSF32X16_L2, + OPCODE_AE_MULS32X16_L2, + OPCODE_AE_MULSF32X16_L2_S2, + OPCODE_AE_MULS32X16_L2_S2, + OPCODE_AE_MULSF32X16_L3, + OPCODE_AE_MULS32X16_L3, + OPCODE_AE_MULSF32X16_L3_S2, + OPCODE_AE_MULS32X16_L3_S2, + OPCODE_AE_MULSF32X16_H0, + OPCODE_AE_MULS32X16_H0, + OPCODE_AE_MULSF32X16_H0_S2, + OPCODE_AE_MULS32X16_H0_S2, + OPCODE_AE_MULSF32X16_H1, + OPCODE_AE_MULS32X16_H1, + OPCODE_AE_MULSF32X16_H1_S2, + OPCODE_AE_MULS32X16_H1_S2, + OPCODE_AE_MULSF32X16_H2, + OPCODE_AE_MULS32X16_H2, + OPCODE_AE_MULSF32X16_H2_S2, + OPCODE_AE_MULS32X16_H2_S2, + OPCODE_AE_MULSF32X16_H3, + OPCODE_AE_MULS32X16_H3, + OPCODE_AE_MULSF32X16_H3_S2, + OPCODE_AE_MULS32X16_H3_S2, + OPCODE_AE_MULAAFD32X16_H3_L2, + OPCODE_AE_MULAAD32X16_H3_L2, + OPCODE_AE_MULAAFD32X16_H3_L2_S2, + OPCODE_AE_MULAAD32X16_H3_L2_S2, + OPCODE_AE_MULAAFD32X16_H1_L0, + OPCODE_AE_MULAAD32X16_H1_L0, + OPCODE_AE_MULAAFD32X16_H1_L0_S2, + OPCODE_AE_MULAAD32X16_H1_L0_S2, + OPCODE_AE_MULASFD32X16_H3_L2, + OPCODE_AE_MULASD32X16_H3_L2, + OPCODE_AE_MULASFD32X16_H3_L2_S2, + OPCODE_AE_MULASD32X16_H3_L2_S2, + OPCODE_AE_MULASFD32X16_H1_L0, + OPCODE_AE_MULASD32X16_H1_L0, + OPCODE_AE_MULASFD32X16_H1_L0_S2, + OPCODE_AE_MULASD32X16_H1_L0_S2, + OPCODE_AE_MULSAFD32X16_H3_L2, + OPCODE_AE_MULSAD32X16_H3_L2, + OPCODE_AE_MULSAFD32X16_H3_L2_S2, + OPCODE_AE_MULSAD32X16_H3_L2_S2, + OPCODE_AE_MULSAFD32X16_H1_L0, + OPCODE_AE_MULSAD32X16_H1_L0, + OPCODE_AE_MULSAFD32X16_H1_L0_S2, + OPCODE_AE_MULSAD32X16_H1_L0_S2, + OPCODE_AE_MULSSFD32X16_H3_L2, + OPCODE_AE_MULSSD32X16_H3_L2, + OPCODE_AE_MULSSFD32X16_H3_L2_S2, + OPCODE_AE_MULSSD32X16_H3_L2_S2, + OPCODE_AE_MULSSFD32X16_H1_L0, + OPCODE_AE_MULSSD32X16_H1_L0, + OPCODE_AE_MULSSFD32X16_H1_L0_S2, + OPCODE_AE_MULSSD32X16_H1_L0_S2, + OPCODE_AE_MULZAAFD32X16_H3_L2, + OPCODE_AE_MULZAAD32X16_H3_L2, + OPCODE_AE_MULZAAFD32X16_H3_L2_S2, + OPCODE_AE_MULZAAD32X16_H3_L2_S2, + OPCODE_AE_MULZAAFD32X16_H1_L0, + OPCODE_AE_MULZAAD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H1_L0_S2, + OPCODE_AE_MULZAAD32X16_H1_L0_S2, + OPCODE_AE_MULZASFD32X16_H3_L2, + OPCODE_AE_MULZASD32X16_H3_L2, + OPCODE_AE_MULZASFD32X16_H3_L2_S2, + OPCODE_AE_MULZASD32X16_H3_L2_S2, + OPCODE_AE_MULZASFD32X16_H1_L0, + OPCODE_AE_MULZASD32X16_H1_L0, + OPCODE_AE_MULZASFD32X16_H1_L0_S2, + OPCODE_AE_MULZASD32X16_H1_L0_S2, + OPCODE_AE_MULZSAFD32X16_H3_L2, + OPCODE_AE_MULZSAD32X16_H3_L2, + OPCODE_AE_MULZSAFD32X16_H3_L2_S2, + OPCODE_AE_MULZSAD32X16_H3_L2_S2, + OPCODE_AE_MULZSAFD32X16_H1_L0, + OPCODE_AE_MULZSAD32X16_H1_L0, + OPCODE_AE_MULZSAFD32X16_H1_L0_S2, + OPCODE_AE_MULZSAD32X16_H1_L0_S2, + OPCODE_AE_MULZSSFD32X16_H3_L2, + OPCODE_AE_MULZSSD32X16_H3_L2, + OPCODE_AE_MULZSSFD32X16_H3_L2_S2, + OPCODE_AE_MULZSSD32X16_H3_L2_S2, + OPCODE_AE_MULZSSFD32X16_H1_L0, + OPCODE_AE_MULZSSD32X16_H1_L0, + OPCODE_AE_MULZSSFD32X16_H1_L0_S2, + OPCODE_AE_MULZSSD32X16_H1_L0_S2, + OPCODE_AE_MULZAAFD32X16_H2_L3, + OPCODE_AE_MULZAAFD32X16_H0_L1, + OPCODE_AE_MULAAFD32X16_H2_L3, + OPCODE_AE_MULAAFD32X16_H0_L1, + OPCODE_AE_MULZAAD32X16_H2_L3, + OPCODE_AE_MULZAAD32X16_H0_L1, + OPCODE_AE_MULAAD32X16_H2_L3, + OPCODE_AE_MULAAD32X16_H0_L1, + OPCODE_AE_MULZAAFD32X16_H2_L3_S2, + OPCODE_AE_MULZAAFD32X16_H0_L1_S2, + OPCODE_AE_MULAAFD32X16_H2_L3_S2, + OPCODE_AE_MULAAFD32X16_H0_L1_S2, + OPCODE_AE_MULZAAD32X16_H2_L3_S2, + OPCODE_AE_MULZAAD32X16_H0_L1_S2, + OPCODE_AE_MULAAD32X16_H2_L3_S2, + OPCODE_AE_MULAAD32X16_H0_L1_S2, + OPCODE_AE_MULP32X16X2_H, + OPCODE_AE_MULFP32X16X2RS_H, + OPCODE_AE_MULFP32X16X2RAS_H, + OPCODE_AE_MULFP32X16X2S_H, + OPCODE_AE_MULFP32X16X2S_H_S2, + OPCODE_AE_MULP32X16X2_H_S2, + OPCODE_AE_MULFP32X16X2RS_H_S2, + OPCODE_AE_MULFP32X16X2RAS_H_S2, + OPCODE_AE_MULP32X16X2_L, + OPCODE_AE_MULFP32X16X2RS_L, + OPCODE_AE_MULFP32X16X2RAS_L, + OPCODE_AE_MULFP32X16X2S_L, + OPCODE_AE_MULFP32X16X2S_L_S2, + OPCODE_AE_MULP32X16X2_L_S2, + OPCODE_AE_MULFP32X16X2RS_L_S2, + OPCODE_AE_MULFP32X16X2RAS_L_S2, + OPCODE_AE_MULAP32X16X2_H, + OPCODE_AE_MULAFP32X16X2RS_H, + OPCODE_AE_MULAFP32X16X2RAS_H, + OPCODE_AE_MULAFP32X16X2S_H, + OPCODE_AE_MULAFP32X16X2S_H_S2, + OPCODE_AE_MULAP32X16X2_H_S2, + OPCODE_AE_MULAFP32X16X2RS_H_S2, + OPCODE_AE_MULAFP32X16X2RAS_H_S2, + OPCODE_AE_MULAP32X16X2_L, + OPCODE_AE_MULAFP32X16X2RS_L, + OPCODE_AE_MULAFP32X16X2RAS_L, + OPCODE_AE_MULAFP32X16X2S_L, + OPCODE_AE_MULAFP32X16X2S_L_S2, + OPCODE_AE_MULAP32X16X2_L_S2, + OPCODE_AE_MULAFP32X16X2RS_L_S2, + OPCODE_AE_MULAFP32X16X2RAS_L_S2, + OPCODE_AE_MULSP32X16X2_H, + OPCODE_AE_MULSFP32X16X2RS_H, + OPCODE_AE_MULSFP32X16X2RAS_H, + OPCODE_AE_MULSFP32X16X2S_H, + OPCODE_AE_MULSFP32X16X2S_H_S2, + OPCODE_AE_MULSP32X16X2_H_S2, + OPCODE_AE_MULSFP32X16X2RS_H_S2, + OPCODE_AE_MULSFP32X16X2RAS_H_S2, + OPCODE_AE_MULSP32X16X2_L, + OPCODE_AE_MULSFP32X16X2RS_L, + OPCODE_AE_MULSFP32X16X2RAS_L, + OPCODE_AE_MULSFP32X16X2S_L, + OPCODE_AE_MULSFP32X16X2S_L_S2, + OPCODE_AE_MULSP32X16X2_L_S2, + OPCODE_AE_MULSFP32X16X2RS_L_S2, + OPCODE_AE_MULSFP32X16X2RAS_L_S2, + OPCODE_AE_MULP32X2, + OPCODE_AE_MULFP32X2RS, + OPCODE_AE_MULFP32X2RAS, + OPCODE_AE_MULP32X2_S2, + OPCODE_AE_MULFP32X2RS_S2, + OPCODE_AE_MULFP32X2RAS_S2, + OPCODE_AE_MULAP32X2, + OPCODE_AE_MULAFP32X2RS, + OPCODE_AE_MULAFP32X2RAS, + OPCODE_AE_MULAP32X2_S2, + OPCODE_AE_MULAFP32X2RS_S2, + OPCODE_AE_MULAFP32X2RAS_S2, + OPCODE_AE_MULSP32X2, + OPCODE_AE_MULSFP32X2RS, + OPCODE_AE_MULSFP32X2RAS, + OPCODE_AE_MULSP32X2_S2, + OPCODE_AE_MULSFP32X2RS_S2, + OPCODE_AE_MULSFP32X2RAS_S2, + OPCODE_AE_MULFP16X4S, + OPCODE_AE_MULFP16X4RAS, + OPCODE_AE_MULC32, + OPCODE_AE_MULFC24RA, + OPCODE_AE_MULFC32RAS, + OPCODE_AE_MULC32X16_L, + OPCODE_AE_MULFC32X16RAS_L, + OPCODE_AE_MULC32X16_H, + OPCODE_AE_MULFC32X16RAS_H, + OPCODE_AE_MULAC32, + OPCODE_AE_MULAFC24RA, + OPCODE_AE_MULAFC32RAS, + OPCODE_AE_MULAC32X16_L, + OPCODE_AE_MULAFC32X16RAS_L, + OPCODE_AE_MULAC32X16_H, + OPCODE_AE_MULAFC32X16RAS_H, + OPCODE_AE_MULF16X4SS, + OPCODE_AE_MULAF16X4SS, + OPCODE_AE_MULSF16X4SS, + OPCODE_AE_MUL16X4, + OPCODE_AE_MULA16X4, + OPCODE_AE_MULS16X4, + OPCODE_AE_MULFD32X2S_FIR_H, + OPCODE_AE_MULFD32X2RA_FIR_H, + OPCODE_AE_MULFD32X2S_FIR_L, + OPCODE_AE_MULFD32X2RA_FIR_L, + OPCODE_AE_MULFD32X16X2_FIR_HH, + OPCODE_AE_MULFD32X16X2_FIR_HL, + OPCODE_AE_MULFD32X16X2_FIR_LH, + OPCODE_AE_MULFD32X16X2_FIR_LL, + OPCODE_AE_MULAFD32X2S_FIR_H, + OPCODE_AE_MULAFD32X2RA_FIR_H, + OPCODE_AE_MULAFD32X2S_FIR_L, + OPCODE_AE_MULAFD32X2RA_FIR_L, + OPCODE_AE_MULAFD32X16X2_FIR_HH, + OPCODE_AE_MULAFD32X16X2_FIR_HL, + OPCODE_AE_MULAFD32X16X2_FIR_LH, + OPCODE_AE_MULAFD32X16X2_FIR_LL, + OPCODE_AE_MULZAAAAFQ32X16, + OPCODE_AE_MULAAAAFQ32X16, + OPCODE_AE_MULZAAAAFQ32X16_S2, + OPCODE_AE_MULAAAAFQ32X16_S2, + OPCODE_AE_MULZAAAAQ32X16, + OPCODE_AE_MULAAAAQ32X16, + OPCODE_AE_MULZAAAAQ32X16_S2, + OPCODE_AE_MULAAAAQ32X16_S2, + OPCODE_AE_MUL16_00, + OPCODE_AE_MULA16_00, + OPCODE_AE_MUL16_00_S2, + OPCODE_AE_MULA16_00_S2, + OPCODE_AE_MULZAAAAQ16, + OPCODE_AE_MULAAAAQ16, + OPCODE_AE_MULZAAAAQ16_S2, + OPCODE_AE_MULAAAAQ16_S2, + OPCODE_AE_DIV64D32_H, + OPCODE_AE_DIV64D32_L, + OPCODE_AE_SHA32, + OPCODE_AE_VLDL32T, + OPCODE_AE_VLDL16T, + OPCODE_AE_VLDL16C, + OPCODE_AE_VLDL16C_IP, + OPCODE_AE_VLDL16C_IC, + OPCODE_AE_VLDL16C_IC1, + OPCODE_AE_VLDSHT, + OPCODE_AE_LB, + OPCODE_AE_LBI, + OPCODE_AE_LBK, + OPCODE_AE_LBKI, + OPCODE_AE_LBS, + OPCODE_AE_LBSI, + OPCODE_AE_DB, + OPCODE_AE_DBI, + OPCODE_AE_DB_IC, + OPCODE_AE_DBI_IC, + OPCODE_AE_DB_IC1, + OPCODE_AE_DBI_IC1, + OPCODE_AE_DB_IP, + OPCODE_AE_DBI_IP, + OPCODE_AE_VLEL32T, + OPCODE_AE_VLEL16T, + OPCODE_AE_SB, + OPCODE_AE_SBI, + OPCODE_AE_VLES16C, + OPCODE_AE_SBF, + OPCODE_AE_SB_IC, + OPCODE_AE_SBI_IC, + OPCODE_AE_VLES16C_IC, + OPCODE_AE_SBF_IC, + OPCODE_AE_SB_IC1, + OPCODE_AE_SBI_IC1, + OPCODE_AE_VLES16C_IC1, + OPCODE_AE_SBF_IC1, + OPCODE_AE_SB_IP, + OPCODE_AE_SBI_IP, + OPCODE_AE_VLES16C_IP, + OPCODE_AE_SBF_IP, + OPCODE_AE_SEXT32, + OPCODE_AE_MOVAE, + OPCODE_AE_MOVEA, + OPCODE_AE_MOVEEP, + OPCODE_AE_SEXT72, + OPCODE_AE_ADD72, + OPCODE_AE_SUB72, + OPCODE_AE_ADD72X64, + OPCODE_AE_SUB72X64, + OPCODE_AE_MUL32EP_HH, + OPCODE_AE_MUL32EP_HH_S2, + OPCODE_AE_MULA32EP_HH, + OPCODE_AE_MULS32EP_HH, + OPCODE_AE_MULA32EP_HH_S2, + OPCODE_AE_MULS32EP_HH_S2, + OPCODE_AE_MULZAAD32EP_HH_LL, + OPCODE_AE_MULZSSD32EP_HH_LL, + OPCODE_AE_MULAAD32EP_HH_LL, + OPCODE_AE_MULSSD32EP_HH_LL, + OPCODE_AE_MULZAAD32EP_HH_LL_S2, + OPCODE_AE_MULZSSD32EP_HH_LL_S2, + OPCODE_AE_MULAAD32EP_HH_LL_S2, + OPCODE_AE_MULSSD32EP_HH_LL_S2, + OPCODE_AE_MULAAD32USEP_HL_LH, + OPCODE_AE_MULAAD32USEP_HL_LH_S2, + OPCODE_AE_MULZAAD32USEP_HL_LH, + OPCODE_AE_MULZAAD32USEP_HL_LH_S2, + OPCODE_AE_MUL32USEP_LH, + OPCODE_AE_MULA32USEP_LH, + OPCODE_AE_MUL32USEP_LL, + OPCODE_AE_MULA32USEP_LL, + OPCODE_AE_SRAI72, + OPCODE_AE_SLAI72, + OPCODE_AE_SAT64S, + OPCODE_AE_L16SI_N, + OPCODE_AE_L16UI_N, + OPCODE_AE_S16I_N, + OPCODE_AE_MOVFCRFSRV, + OPCODE_AE_MOVVFCRFSR, + OPCODE_RFR, + OPCODE_WFR, + OPCODE_MOVT_S, + OPCODE_MOVF_S, + OPCODE_MOVEQZ_S, + OPCODE_MOVNEZ_S, + OPCODE_MOVGEZ_S, + OPCODE_MOVLTZ_S, + OPCODE_TRUNC_S, + OPCODE_UTRUNC_S, + OPCODE_TRUNC_SX2, + OPCODE_UTRUNC_SX2, + OPCODE_FICEIL_S, + OPCODE_FIFLOOR_S, + OPCODE_FIROUND_S, + OPCODE_FITRUNC_S, + OPCODE_FIRINT_S, + OPCODE_CVTSF16_L, + OPCODE_CVTSF16_H, + OPCODE_CVTF16S_L, + OPCODE_CVTF16S_H, + OPCODE_ABS_S, + OPCODE_MUL_S, + OPCODE_MADD_S, + OPCODE_MSUB_S, + OPCODE_MSUBN_S, + OPCODE_MADDN_S, + OPCODE_ADD_S, + OPCODE_SUB_S, + OPCODE_NEG_S, + OPCODE_FLOAT_S, + OPCODE_UFLOAT_S, + OPCODE_FLOAT_SX2, + OPCODE_UFLOAT_SX2, + OPCODE_OLE_S, + OPCODE_OLT_S, + OPCODE_OEQ_S, + OPCODE_UN_S, + OPCODE_ULE_S, + OPCODE_ULT_S, + OPCODE_UEQ_S, + OPCODE_CONST_S, + OPCODE_NEXP01_S, + OPCODE_MKSADJ_S, + OPCODE_MKDADJ_S, + OPCODE_DIV0_S, + OPCODE_SQRT0_S, + OPCODE_RECIP0_S, + OPCODE_RSQRT0_S, + OPCODE_DIVN_S, + OPCODE_ADDEXP_S, + OPCODE_ADDEXPM_S, + OPCODE_MIN_S, + OPCODE_MAX_S, + OPCODE_MULMUX_S, + OPCODE_MADDMUX_S, + OPCODE_CONJC_S, + OPCODE_SIGMOID_Q15, + OPCODE_SIGMOID_FP32 +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 6 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 1 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_SIGMOID_Q15; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 6 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 0 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_SIGMOID_FP32; + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + } + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFNXT_F; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFEND_A; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFEND_O; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFWAIT_A; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFWAIT_R; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_RITLB0; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_PITLB; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_WITLB; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_RITLB1; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RDTLB0; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PDTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WDTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RDTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_XSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_XSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_XSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_XSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_XSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_XSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_XSR_M3; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_XSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MULUH; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MULSH; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_RSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_RSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_RSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_RSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_RSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_RSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_RSR_M3; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_RSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_WSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_WSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_WSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_WSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_WSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_WSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_WSR_M3; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_WSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 232) + return OPCODE_RUR_FCR; + if (Field_st_Slot_inst_get (insn) == 233) + return OPCODE_RUR_FSR; + if (Field_st_Slot_inst_get (insn) == 234) + return OPCODE_RUR_F64R_LO; + if (Field_st_Slot_inst_get (insn) == 235) + return OPCODE_RUR_F64R_HI; + if (Field_st_Slot_inst_get (insn) == 236) + return OPCODE_RUR_F64S; + if (Field_st_Slot_inst_get (insn) == 240) + return OPCODE_RUR_AE_OVF_SAR; + if (Field_st_Slot_inst_get (insn) == 241) + return OPCODE_RUR_AE_BITHEAD; + if (Field_st_Slot_inst_get (insn) == 242) + return OPCODE_RUR_AE_TS_FTS_BU_BP; + if (Field_st_Slot_inst_get (insn) == 243) + return OPCODE_RUR_AE_CW_SD_NO; + if (Field_st_Slot_inst_get (insn) == 246) + return OPCODE_RUR_AE_CBEGIN0; + if (Field_st_Slot_inst_get (insn) == 247) + return OPCODE_RUR_AE_CEND0; + if (Field_st_Slot_inst_get (insn) == 248) + return OPCODE_RUR_AE_CBEGIN1; + if (Field_st_Slot_inst_get (insn) == 249) + return OPCODE_RUR_AE_CEND1; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WUR_FCR; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WUR_FSR; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WUR_F64R_LO; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_WUR_F64R_HI; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WUR_F64S; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WUR_AE_OVF_SAR; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WUR_AE_BITHEAD; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WUR_AE_TS_FTS_BU_BP; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_WUR_AE_CW_SD_NO; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WUR_AE_CBEGIN0; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WUR_AE_CEND0; + if (Field_sr_Slot_inst_get (insn) == 248) + return OPCODE_WUR_AE_CBEGIN1; + if (Field_sr_Slot_inst_get (insn) == 249) + return OPCODE_WUR_AE_CEND1; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 3) + return OPCODE_DPFM_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 7) + return OPCODE_DPFM_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 1) + return OPCODE_DPFR_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 5) + return OPCODE_DPFR_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 2) + return OPCODE_DPFW_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 6) + return OPCODE_DPFW_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 9) + return OPCODE_DHI_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 11) + return OPCODE_DHWBI_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 10) + return OPCODE_DHWB_B; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_op1_Slot_inst_get (insn) == 10) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ADD_S; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_SUB_S; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_MUL_S; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MADD_S; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MSUB_S; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MADDN_S; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_DIVN_S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_CONST_S; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_RFR; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_WFR; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_NEG_S; + } + } + if (Field_op1_Slot_inst_get (insn) == 11) + { + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_UN_S; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OEQ_S; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_UEQ_S; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_OLT_S; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_ULT_S; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_OLE_S; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_ULE_S; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ_S; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ_S; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ_S; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ_S; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF_S; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT_S; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_dfp_fld_op1_Slot_inst_get (insn) == 11) + { + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 0) + { + if (Field_dfp_fld_r_3_1_Slot_inst_get (insn) == 7) + return OPCODE_WF64R; + if (Field_dfp_fld_s_3_1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 12) + return OPCODE_RF64R; + } + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 14) + { + return OPCODE_F64CMPL; + } + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 15) + { + if (Field_dfp_fld_r_3_Slot_inst_get (insn) == 0) + return OPCODE_F64ADDC; + if (Field_dfp_fld_r_3_Slot_inst_get (insn) == 1) + return OPCODE_F64SUBC; + } + } + if (Field_dfp_fld_op1_Slot_inst_get (insn) == 14) + { + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_F64SIG; + } + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 1) + { + return OPCODE_F64SEXP; + } + if (Field_dfp_fld_op2_3_Slot_inst_get (insn) == 1) + return OPCODE_F64ITER; + if (Field_dfp_fld_op2_3_1_Slot_inst_get (insn) == 1) + return OPCODE_F64NORM; + if (Field_dfp_fld_op2_3_2_Slot_inst_get (insn) == 1) + return OPCODE_F64RND; + } + if (Field_dfp_fld_op1_Slot_inst_get (insn) == 15) + { + return OPCODE_F64CMPH; + } + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_DPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_DHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_DIU; + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_DIWBUI_P; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_S32C1I; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1860) + return OPCODE_AE_DBI_IC1; + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1918 && + Field_fld_inst_7_4_Slot_inst_get (insn) == 12) + return OPCODE_AE_SBF_IC1; + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1956) + return OPCODE_AE_SB_IC1; + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1972) + return OPCODE_AE_DB_IC1; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 27 && + Field_fld_inst_7_7_Slot_inst_get (insn) == 0 && + Field_fld_inst_4_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 31) + return OPCODE_AE_SBI_IC1; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 36 && + Field_fld_inst_13_8_Slot_inst_get (insn) == 23) + return OPCODE_AE_MOVBA4; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 36 && + Field_fld_inst_12_8_Slot_inst_get (insn) == 7) + return OPCODE_AE_MOVBA2; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 38 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_AE_MOVAB; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 46 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_AE_MOVBA; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 47 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8 && + Field_fld_inst_5_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_MOVAB4; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 47 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8 && + Field_fld_inst_4_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_MOVAB2; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 47 && + Field_fld_inst_13_8_Slot_inst_get (insn) == 8 && + Field_fld_inst_5_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_MOVB4; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 70) + return OPCODE_AE_L64_IP; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 104 && + Field_fld_inst_12_8_Slot_inst_get (insn) == 8 && + Field_fld_inst_4_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_MOVB2; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 104 && + Field_fld_inst_9_8_Slot_inst_get (insn) == 1) + return OPCODE_AE_PKSRF32; + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_S64_I; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_S64_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_LA32X2_IC; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_6_Slot_inst_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_6_Slot_inst_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 0) + return OPCODE_AE_LA24X2_IC; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 1) + return OPCODE_AE_LA24X2_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_6_Slot_inst_get (insn) == 3) + return OPCODE_AE_SA32X2_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_S32RA64S_XP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_SRAA32; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_SLAA32S; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_SLAASQ56S; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_VLDL32T; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_VLDL16T; + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_MOVDA32X2; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_MOVDA16X2; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_TRUNCP16; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_TRUNCQ32; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_OR; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_XOR; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_SEXT32; + if (Field_op2_Slot_inst_get (insn) == 2) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_inst_11_8_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 1 && + Field_inst_5_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_ZALIGN64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_inst_11_8_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 0) + return OPCODE_AE_MOVALIGN; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_AE_SAT48S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_TRUNCA32Q48; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVAD32_L; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 11) + return OPCODE_AE_MOVAD32_H; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 10) + return OPCODE_AE_MOVAD16_3; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 9) + return OPCODE_AE_MOVAD16_2; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 8) + return OPCODE_AE_MOVAD16_0; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_9_8_Slot_inst_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_inst_9_8_Slot_inst_get (insn) == 2) + return OPCODE_AE_PKSR24; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 1) + return OPCODE_AE_ABS24S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_AE_NEG32S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_AE_ABS32S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_AE_NEG16S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_AE_ABS16S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 5) + return OPCODE_AE_NEG64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_AE_ABS64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_AE_SLAS24; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 14) + return OPCODE_AE_SRAS24; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_SLAA32; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_SLAA16S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLASQ56; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 15) + return OPCODE_AE_SRASQ56; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_SLAAQ56; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_SLAA64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 13) + return OPCODE_AE_SLAS64S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 13) + return OPCODE_AE_NSA64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 14) + return OPCODE_AE_NSAZ16_0; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 15) + return OPCODE_AE_NSAZ32_L; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 4) + return OPCODE_AE_DIV64D32_L; + if (Field_op2_Slot_inst_get (insn) == 3) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_LA16X4_IC; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 3) + return OPCODE_AE_LA16X4_IP; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_LA16X4_RIP; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_inst_7_6_Slot_inst_get (insn) == 3) + return OPCODE_AE_SA32X2F24_IP; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_inst_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_MOVDA32; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_MOVDA16; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_MOVI; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_CVT48A32; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_ADD32; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_ADD24S; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_ADD16S; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_ADD64; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_inst_7_4_Slot_inst_get (insn) == 8) + return OPCODE_AE_SHA32; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_15_12_Slot_inst_get (insn) == 1 && + Field_inst_11_8_Slot_inst_get (insn) == 0) + return OPCODE_AE_VLDSHT; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_SUB32; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_ADD32S; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_SUB32S; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_SUB16S; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_SUB64; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_AND; + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_12_Slot_inst_get (insn) == 1) + return OPCODE_AE_LT32; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_12_Slot_inst_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_MIN32; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_MAX32; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_LT64; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_LE64; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_SBI_IC; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_SBI_IP; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 13) + return OPCODE_WUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 14) + return OPCODE_RUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 15) + return OPCODE_WUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 0) + return OPCODE_RUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 1) + return OPCODE_WUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_RUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_WUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 4) + return OPCODE_RUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 5) + return OPCODE_WUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_RUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_WUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_RUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 9) + return OPCODE_WUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_CWRAP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_CWRAP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_inst_7_Slot_inst_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_MOVT64; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_SRLAQ56; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_AE_LB; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_AE_LBI; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_AE_LBS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_AE_LBSI; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_SBI; + if (Field_op2_Slot_inst_get (insn) == 7) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 2) + return OPCODE_AE_LA64_PP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 1) + return OPCODE_AE_LA32X2POS_PC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 3) + return OPCODE_AE_SA64POS_FP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 6) + return OPCODE_AE_VLDL16C; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 8) + return OPCODE_AE_VLDL16C_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 7) + return OPCODE_AE_VLDL16C_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 4) + return OPCODE_AE_DB; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 5) + return OPCODE_AE_DBI; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 6) + return OPCODE_AE_DB_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 7) + return OPCODE_AE_DBI_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 8) + return OPCODE_AE_DB_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 9) + return OPCODE_AE_DBI_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 10) + return OPCODE_AE_SB; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_VLES16C; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_SBF; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 11) + return OPCODE_AE_SB_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_VLES16C_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_SBF_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 12) + return OPCODE_AE_SB_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 4) + return OPCODE_AE_VLES16C_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 5) + return OPCODE_AE_SBF_IP; + if (Field_op2_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_SRAA32S; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_inst_19_18_Slot_inst_get (insn) == 2) + return OPCODE_AE_SLAI64; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_inst_19_18_Slot_inst_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_SRAA64; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_inst_19_18_Slot_inst_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_LBK; + if (Field_op2_Slot_inst_get (insn) == 9) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 2) + return OPCODE_AE_SLAI24; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 6) + return OPCODE_AE_SRAI24; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 1) + return OPCODE_AE_SRLI32; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 7) + return OPCODE_AE_SRAI32; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 4) + return OPCODE_AE_SLAI24S; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 5) + return OPCODE_AE_SLAI32S; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_SEL16I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_L16M_IU; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_L16M_XU; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_L16_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_L32F24_XC; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_L32F24_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_L32F24_IP; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_L32_XC; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_L32_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_L32_IP; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_L32_X; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 8) + return OPCODE_AE_L16X2M_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 9) + return OPCODE_AE_L16X2M_IU; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 10) + return OPCODE_AE_L16X2M_X; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 11) + return OPCODE_AE_L16X2M_XU; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 8) + return OPCODE_AE_L32M_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 9) + return OPCODE_AE_L32M_IU; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 10) + return OPCODE_AE_L32M_X; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 11) + return OPCODE_AE_L32M_XU; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_L32X2F24_XC; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_L32X2F24_X; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_L32X2F24_XP; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_L32X2_XC; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_L32X2_X; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_L16X4_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_L16X4_XP; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_L64_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_LBKI; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 8) + return OPCODE_AE_S16X2M_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 9) + return OPCODE_AE_S16X2M_IU; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 10) + return OPCODE_AE_S16X2M_X; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 11) + return OPCODE_AE_S16X2M_XU; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_S16X4_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_S16M_L_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_S16M_L_IU; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_S16M_L_X; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_S32F24_L_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_S32F24_L_IP; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_S16_0_XP; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_S24RA64S_XP; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_VLEL32T; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_VLEL16T; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_S32X2F24_XC; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_S32X2F24_I; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_S32X2F24_X; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_S32X2F24_XP; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 8) + return OPCODE_AE_S32X2_XC; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 9) + return OPCODE_AE_S32X2_I; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 10) + return OPCODE_AE_S32X2_X; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 11) + return OPCODE_AE_S32X2_XP; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_S32_L_I; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_S32_L_IP; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_S32_L_X; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_S32_L_XP; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_S32M_I; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_S32M_IU; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_S32M_X; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_S32M_XU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_TRUNCA32X2F64S; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_L16SI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 2) + return OPCODE_AE_L16UI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 3) + return OPCODE_AE_S16I_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_SEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_CLAMPS16; + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_get (insn) == 14592) + return OPCODE_NOP; + if (Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_get (insn) == 6) + return OPCODE_MOVI_N; + if (Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_ADD; + if (Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_ADDI_N; + if (Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_L32I_N; + if (Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_get (insn) == 56) + return OPCODE_MOV_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66116) + return OPCODE_ADD; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66117) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66118) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66119) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66120) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66121) + return OPCODE_AND; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66122) + return OPCODE_MAX; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66123) + return OPCODE_MAXU; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66124) + return OPCODE_MIN; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66125) + return OPCODE_MINU; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66126) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66127) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66320) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66321) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66322) + return OPCODE_OR; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66323) + return OPCODE_SRC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66324) + return OPCODE_SUB; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66325) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66326) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66327) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66328) + return OPCODE_XOR; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66329) + return OPCODE_MOVF; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66330) + return OPCODE_MOVT; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66331) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66332) + return OPCODE_SEXT; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66333) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66334) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66335) + return OPCODE_SRLI; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66336) + return OPCODE_ANDB; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66337) + return OPCODE_ANDBC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66338) + return OPCODE_ORB; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66339) + return OPCODE_ORBC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66340) + return OPCODE_XORB; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66341 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66341 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66341 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66341 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66342 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66342 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66342 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66342 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66343 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66343 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66343 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66343 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66344 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66344 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66344 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66345 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66345 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66345 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66346 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66346 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66346 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66347 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66347 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66347 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66348 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66348 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66348 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66350 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66350 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66350 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66350 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66351 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66351 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_CVTF16S_L; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_CVTF16S_H; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_FICEIL_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_FIROUND_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FITRUNC_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_FIRINT_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_CVTSF16_L; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_CVTSF16_H; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33056) + return OPCODE_SLLI; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33057) + return OPCODE_SRAI; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33176 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_SSAI; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33186) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33187) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33188) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33189) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4114) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4115) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4116) + return OPCODE_ADDI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4117) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4118) + return OPCODE_L16SI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4119) + return OPCODE_L16UI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4120) + return OPCODE_L32I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4121) + return OPCODE_L8UI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4122) + return OPCODE_S16I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4123) + return OPCODE_S32I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4124) + return OPCODE_S8I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4125) + return OPCODE_MOVI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4126) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4127) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4128) + return OPCODE_AE_SEL16I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4129 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4129 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4129 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4129 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRLI64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRLI24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SRLI32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SLAA32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S64_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S64_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_ADD32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADD16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_ADD24S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_ADD32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADD16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SUB32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SUB16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SUB24S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SUB32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SUB16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SUB64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADD64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_MAX64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_MIN64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_MOVT64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_MOVF64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get (insn) == 61) + return OPCODE_AE_LE16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get (insn) == 29) + return OPCODE_AE_EQ16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get (insn) == 25) + return OPCODE_AE_LT32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_LE32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_EQ32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRLA32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SRLA64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SRAA64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_LOOP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_LOOPGTZ; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_LOOPNEZ; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S64_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S64_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_AND; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_NAND; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_OR; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_XOR; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SRAI16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LT64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LE64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_EQ64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 112) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 116) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 120) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 124) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 133) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 69) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 197) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_get (insn) == 166) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 162) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 160) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 164) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 163) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 32) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 161) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 111) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 109) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 110) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 108) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 107) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 41) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 39) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 37) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 36) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 35) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LT16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 43) + return OPCODE_AE_SLAS24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 103) + return OPCODE_AE_SRLS24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 99) + return OPCODE_AE_SRAS24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_SLAS32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 104) + return OPCODE_AE_SRLS32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 100) + return OPCODE_AE_SRAS32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 44) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 45) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 98) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 105) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 101) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_SLAS64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 106) + return OPCODE_AE_SRLS64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 102) + return OPCODE_AE_SRAS64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 97) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 96) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 40) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_get (insn) == 2056) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BBSI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BALL_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BANY_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_BBC_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_BBS_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BEQ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BGEU_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BLTU_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 74) + return OPCODE_BLTZ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 78) + return OPCODE_BNEZ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16986637) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16986893) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16987149) + return OPCODE_SSL; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16987405) + return OPCODE_SSR; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16990675 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_NOP; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061888) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061889) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061890) + return OPCODE_DPFM_B; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061891) + return OPCODE_DPFM_BF; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061892) + return OPCODE_DPFR_B; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061893) + return OPCODE_DPFR_BF; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061894) + return OPCODE_DPFW_B; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061895) + return OPCODE_DPFW_BF; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061896) + return OPCODE_MOV_N; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061897) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061898) + return OPCODE_AE_ABS24S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061899) + return OPCODE_AE_ABS32; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061900) + return OPCODE_AE_ABS32S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061901) + return OPCODE_AE_ABS64; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061902) + return OPCODE_AE_ABS64S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061903) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061904) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061905) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061906) + return OPCODE_AE_NEG16S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061907) + return OPCODE_AE_NEG24S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061908) + return OPCODE_AE_NEG32; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061909) + return OPCODE_AE_NEG32S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061910) + return OPCODE_AE_NEG64; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061911) + return OPCODE_AE_NEG64S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061912) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061913 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061913 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061913 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061913 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061914 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061914 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061914 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061914 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061915 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061915 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061915 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061915 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061916 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061916 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061916 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061916 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_get (insn) == 52) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061918 && + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ALL4; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061918 && + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061918 && + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061918 && + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ANY8; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_get (insn) == 939984) + return OPCODE_NOP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 148) + return OPCODE_ADD; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 149) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 150) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 151) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 152) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 153) + return OPCODE_AND; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 154) + return OPCODE_MAX; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 155) + return OPCODE_MAXU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 156) + return OPCODE_MIN; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 157) + return OPCODE_MINU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 158) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 159) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 160) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 161) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 162) + return OPCODE_OR; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 163) + return OPCODE_SRC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 164) + return OPCODE_SUB; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 165) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 166) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 167) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 168) + return OPCODE_XOR; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 169) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 170) + return OPCODE_SEXT; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 171) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 172) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 173) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 174) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 175) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 176) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 177) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 178) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 179) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 180) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 181) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 182) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 183) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 184) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 185) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 186) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 187) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 188) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 189) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 190) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 191) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 192) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 193) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 194) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 195) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 196) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 197) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 198) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 199) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 200) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 201) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 202) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 203) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 204) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 205) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 206) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 207) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 208) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 209) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 210) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 211) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 212) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 213) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 214) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 215) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 216) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 217) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 218) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 219) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 220) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 221) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 222) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 223) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 224) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 225) + return OPCODE_SRLI; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 226 && + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 226 && + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 227 && + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 227 && + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_get (insn) == 72) + return OPCODE_SLLI; + if (Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_get (insn) == 73) + return OPCODE_SRAI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58669) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58685) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58701) + return OPCODE_SSL; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58717) + return OPCODE_SSR; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58733) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3680) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3681) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3682) + return OPCODE_MOV_N; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3683) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3684) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3685) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3686) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3687) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3688) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3689) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3690) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3691) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3692) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_get (insn) == 1832 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_get (insn) == 2493300) + return OPCODE_NOP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 452) + return OPCODE_ADD; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 453) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 454) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 455) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 456) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 457) + return OPCODE_AND; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 458) + return OPCODE_MAX; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 459) + return OPCODE_MAXU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 460) + return OPCODE_MIN; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 461) + return OPCODE_MINU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 462) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 463) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 464) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 465) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 466) + return OPCODE_OR; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 467) + return OPCODE_SUB; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 468) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 469) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 470) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 471) + return OPCODE_XOR; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 472) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 473) + return OPCODE_SEXT; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 474) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 475) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 476) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 477) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 478) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 479) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 480) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 481) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 482) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 483) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 484) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 485) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 486) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 487) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 488) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 489) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 490) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 491) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 492) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 493) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 494) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 495) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 496) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 497) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 498) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 499) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 500) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 501) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 502) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 503) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 504) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 505) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 506) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 507) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 508) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 509) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 510) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 511) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 512) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 513) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 514) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 515) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 516) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 517) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 518) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 519) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 520) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 521) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 522) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 523) + return OPCODE_AE_S32M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 524) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 525) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 526) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 527) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 528) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 529) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 530) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 531) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 532) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 533) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 534) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 535) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 536) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 537) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 538) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 539) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 540) + return OPCODE_AE_S64_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 541) + return OPCODE_AE_S64_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 542) + return OPCODE_AE_S64_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 543) + return OPCODE_AE_SBI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 544) + return OPCODE_AE_VLDL16T; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 545) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 546) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 547) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 548) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 549) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 550) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 551) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 552) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 553) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 554) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 555) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 556) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 557) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 558) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 559) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 560) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 561) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 562) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 563) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 564) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 565) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 566) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 567) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 568) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 569) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 570) + return OPCODE_AE_S32M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 571) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 572) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 573) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 574) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 575) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 576) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 577) + return OPCODE_SRLI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 578 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 578 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 579 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 579 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 592 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 592 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 593 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 593 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 594 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 594 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 595 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 595 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 596 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 596 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 596 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 597 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 597 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 597 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_SLL; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 600 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 600 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 600 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 16) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 601 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 601 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 602 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 602 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 603 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 603 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 604 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 604 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 605 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 605 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 606 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 606 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 607 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 607 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 608 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 609 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 609 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 609 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 609 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 610 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 610 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 610 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 610 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 611 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 611 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 611 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 611 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_MOVAB; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_MOVBA; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 31) + return OPCODE_AE_MOVB2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 31) + return OPCODE_AE_MOVB4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 617 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 617 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_get (insn) == 224) + return OPCODE_SLLI; + if (Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_get (insn) == 225) + return OPCODE_SRAI; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 145 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 145 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 145 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 145 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 146 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 146 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 146 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 146 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 147 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 147 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S64_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 147 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S64_IP; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 153 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 153 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 18) + return OPCODE_ADDI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 19) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 20) + return OPCODE_L16SI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 21) + return OPCODE_L16UI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 22) + return OPCODE_L32I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 23) + return OPCODE_L8UI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 24) + return OPCODE_S16I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 25) + return OPCODE_S32I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 26) + return OPCODE_S8I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 27) + return OPCODE_MOVI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 37 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 37 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 37 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_get (insn) == 623309) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_get (insn) == 153857) + return OPCODE_AE_VLDL16C; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9729) + return OPCODE_AE_DB; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9731 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9731 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9731 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9731 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9733) + return OPCODE_AE_SB; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9735 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9735 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9735 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9735 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9737) + return OPCODE_MOV_N; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9739 && + Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9739 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9739 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9739 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9741) + return OPCODE_AE_DBI; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9743 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9743 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9874 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_VLDSHT; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9878 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_RUR_AE_BITPTR; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9882 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVSARD7; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_get (insn) == 995350) + return OPCODE_NOP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 164) + return OPCODE_ADD; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 165) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 166) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 167) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 168) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 169) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 170) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 171) + return OPCODE_AND; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 172) + return OPCODE_MAX; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 173) + return OPCODE_MAXU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 174) + return OPCODE_MIN; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 175) + return OPCODE_MINU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 176) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 177) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 178) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 179) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 180) + return OPCODE_OR; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 181) + return OPCODE_SRC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 182) + return OPCODE_SUB; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 183) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 184) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 185) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 186) + return OPCODE_XOR; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 187) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 188) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 189) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 190) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 191) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 192) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 193) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 194) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 195) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 196) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 197) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 198) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 199) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 200) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 201) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 202) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 203) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 204) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 205) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 206) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 207) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 208) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 209) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 210) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 211) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 212) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 213) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 214) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 215) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 216) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 217) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 218) + return OPCODE_SEXT; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 219) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 220) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 221) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 222) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 223) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 224) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 225) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 226) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 227) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 228) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 229) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 230) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 231) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 232) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 233) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 234) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 235) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 236) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 237) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 238) + return OPCODE_SRLI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 239 && + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 239 && + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 240 && + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 240 && + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 13) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 12) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 11) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 9) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 242 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 242 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSAI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_SRA; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 5) + return OPCODE_SRL; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_get (insn) == 80) + return OPCODE_SLLI; + if (Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_get (insn) == 81) + return OPCODE_SRAI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 9) + return OPCODE_AE_SEL16I; + if (Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (insn) == 61954) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (insn) == 61955) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (insn) == 61970) + return OPCODE_SSL; + if (Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (insn) == 61971) + return OPCODE_SSR; + if (Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get (insn) == 3904) + return OPCODE_MOV_N; + if (Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get (insn) == 3905 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get (insn) == 3905 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOVEA; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_get (insn) == 2601477) + return OPCODE_NOP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 452) + return OPCODE_ADD; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 453) + return OPCODE_ADDX2; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 454) + return OPCODE_ADDX4; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 455) + return OPCODE_ADDX8; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 456) + return OPCODE_AND; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 457) + return OPCODE_MAX; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 458) + return OPCODE_MAXU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 459) + return OPCODE_MIN; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 460) + return OPCODE_MINU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 461) + return OPCODE_MOVEQZ; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 462) + return OPCODE_MOVGEZ; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 463) + return OPCODE_MOVLTZ; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 464) + return OPCODE_MOVNEZ; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 465) + return OPCODE_OR; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 466) + return OPCODE_SUB; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 467) + return OPCODE_SUBX2; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 468) + return OPCODE_SUBX4; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 469) + return OPCODE_SUBX8; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 470) + return OPCODE_XOR; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 471) + return OPCODE_CLAMPS; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 472) + return OPCODE_SEXT; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 473) + return OPCODE_AE_L16M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 474) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 475) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 476) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 477) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 478) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 479) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 480) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 481) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 482) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 483) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 484) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 485) + return OPCODE_AE_L16_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 486) + return OPCODE_AE_L16_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 487) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 488) + return OPCODE_AE_L16_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 489) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 490) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 491) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 492) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 493) + return OPCODE_AE_L32M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 494) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 495) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 496) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 497) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 498) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 499) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 500) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 501) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 502) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 503) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 504) + return OPCODE_AE_L32_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 505) + return OPCODE_AE_L32_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 506) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 507) + return OPCODE_AE_L32_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 508) + return OPCODE_AE_L64_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 509) + return OPCODE_AE_L64_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 510) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 511) + return OPCODE_AE_L64_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 512) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 513) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 514) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 515) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 516) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 517) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 518) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 519) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 520) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 521) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 522) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 523) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 524) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 525) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 526) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 527) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 528) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 529) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 530) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 531) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 532) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 533) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 534) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 535) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 536) + return OPCODE_AE_S32M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 537) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 538) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 539) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 540) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 541) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 542) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 543) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 544) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 545) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 546) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 547) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 548) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 549) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 550) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 551) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 552) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 553) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 554) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 555) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 556) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 557) + return OPCODE_AE_S64_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 558) + return OPCODE_AE_S64_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 559) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 560) + return OPCODE_AE_S64_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 561) + return OPCODE_AE_L16M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 562) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 563) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 564) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 565) + return OPCODE_AE_L16_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 566) + return OPCODE_AE_L16_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 567) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 568) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 569) + return OPCODE_AE_L32M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 570) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 571) + return OPCODE_AE_L32_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 572) + return OPCODE_AE_L32_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 573) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 574) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 575) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 576) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 577) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 578) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 579) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 580) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 581) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 582) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 583) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 584) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 585) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 586) + return OPCODE_AE_S32M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 587) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 588) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 589) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 590) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 591) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 592) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 593) + return OPCODE_SRLI; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 594) + return OPCODE_AE_ADD32; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 595) + return OPCODE_AE_ADD32S; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 604 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 604 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 604 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 604 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 608 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 608 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 609 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 609 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 610 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 610 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 611 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 611 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 612 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 612 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 613 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 613 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 614 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 614 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 615 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 615 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 616 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 616 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 616 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 617 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 617 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 617 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 618 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 618 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 618 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 619 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 619 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 619 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 620 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 620 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 620 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 621 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 621 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 621 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 622 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 622 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 622 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 623 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 623 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 623 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 624 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 624 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 624 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 624 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 625 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 625 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 625 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 625 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 626 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 626 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 626 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 626 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 627 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 627 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 627 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 627 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 628 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 628 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 628 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 628 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 629 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 629 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 629 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 629 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 630 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 630 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 630 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 630 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_get (insn) == 224) + return OPCODE_SLLI; + if (Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_get (insn) == 225) + return OPCODE_SRAI; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 149 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 149 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 149 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 149 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 150 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 150 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 150 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 150 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 151 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 151 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S64_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 151 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S64_IP; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 158 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 158 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 18) + return OPCODE_ADDI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 19) + return OPCODE_ADDMI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 20) + return OPCODE_L16SI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 21) + return OPCODE_L16UI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 22) + return OPCODE_L32I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 23) + return OPCODE_L8UI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_S16I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 25) + return OPCODE_S32I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 26) + return OPCODE_S8I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 27) + return OPCODE_MOVI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 38 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 38 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 38 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_EXTUI; + if (Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_get (insn) == 162364) + return OPCODE_AE_VLDL16C_IC1; + if (Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_get (insn) == 162365) + return OPCODE_AE_VLES16C_IC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40460) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40461) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40462) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40463) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40520) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40521) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40522) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40523) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40524) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40525) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40526) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40527) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40584) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40585) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40586) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40587) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40588) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40589) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40590) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40648 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40648 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get (insn) == 10114) + return OPCODE_MOV_N; + if (Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get (insn) == 10176 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_RUR_AE_BITPTR; + if (Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get (insn) == 10177 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_AE_MOVSARD7; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot0_20_0_Slot_ae_slot0_get (insn) == 1973269) + return OPCODE_NOP; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 210) + return OPCODE_ADD; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 211) + return OPCODE_ADDX2; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 212) + return OPCODE_ADDX4; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 213) + return OPCODE_ADDX8; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 214) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 215) + return OPCODE_AND; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 216 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 217 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 218 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 416) + return OPCODE_MAX; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 417) + return OPCODE_MAXU; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 418) + return OPCODE_MIN; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 419) + return OPCODE_MINU; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 420) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 421) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 422) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 423) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 424) + return OPCODE_OR; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 425) + return OPCODE_SRC; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 426) + return OPCODE_SUB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 427) + return OPCODE_SUBX2; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 428) + return OPCODE_SUBX4; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 429) + return OPCODE_SUBX8; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 430) + return OPCODE_XOR; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 431) + return OPCODE_MOVF; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 432) + return OPCODE_MOVT; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 433) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 434) + return OPCODE_SEXT; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 435) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 436) + return OPCODE_SRLI; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 437) + return OPCODE_ANDB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 438) + return OPCODE_ANDBC; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 439) + return OPCODE_ORB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 440) + return OPCODE_ORBC; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 441) + return OPCODE_XORB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 442 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_SRA; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_SRL; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_MOVAB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVBA; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 42) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 481 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 481 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae_slot0_20_13_Slot_ae_slot0_get (insn) == 104) + return OPCODE_SRAI; + if (Field_fld_ae_slot0_20_13_Slot_ae_slot0_get (insn) == 200 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 123) + return OPCODE_SSAI; + if (Field_fld_ae_slot0_20_14_Slot_ae_slot0_get (insn) == 111 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_DBI; + if (Field_fld_ae_slot0_20_14_Slot_ae_slot0_get (insn) == 116 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot0_20_15_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_L32I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_S16I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_S32I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SLAA32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S64_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S64_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_MOVT64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_MOVF64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SRLA32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SRLA64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SRAA64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 59) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 63) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S64_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 223) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 159) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 31) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 95) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 27) + return OPCODE_AE_LT16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 47) + return OPCODE_AE_LE16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_EQ16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_8_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LT32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_8_4_Slot_ae_slot0_get (insn) == 23) + return OPCODE_AE_LE32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_8_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_EQ32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_AND; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_OR; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_LT64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LE64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_EQ64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 135) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 139) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 143) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 195) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 207) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 199) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 203) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 131) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_0_Slot_ae_slot0_get (insn) == 74) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 199) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 197) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 135) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 72) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 129) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 194) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 192) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 130) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 128) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 66) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 64) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 67) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 131) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 134) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 195) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 69) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 196) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 193) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 70) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 133) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 71) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 198) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 132) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 68) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 65) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_OLT_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_MOVT_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVF_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_TRUNC_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_UFLOAT_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (insn) == 102527) + return OPCODE_SSA8B; + if (Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (insn) == 102783) + return OPCODE_SSA8L; + if (Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (insn) == 103035) + return OPCODE_SSL; + if (Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (insn) == 103039) + return OPCODE_SSR; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 3504 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 3508 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 3512 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7073) + return OPCODE_DPFW_B; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7075) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7077) + return OPCODE_MOV_N; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7079) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7081) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7083) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7085) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7087) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7088) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7089) + return OPCODE_DPFW_BF; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7090) + return OPCODE_DPFM_B; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7091) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7092) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7093) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7094) + return OPCODE_DPFM_BF; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7095) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7096) + return OPCODE_AE_DB; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7097) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7098) + return OPCODE_DPFR_B; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7099) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7100) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7101) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7102) + return OPCODE_DPFR_BF; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7103) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7104) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7108 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7108 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7108 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7120) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7124 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7124 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7124 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7136) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7140 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7140 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7140 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7152 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7152 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7152 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7152 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7156 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7156 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7156 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7696 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ALL4; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7700 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7704 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_0_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7704 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_0_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANY8; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7708 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 20) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7708 && + Field_fld_ae_slot0_5_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVALIGN; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot1_19_0_Slot_ae_slot1_get (insn) == 988784) + return OPCODE_NOP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 148) + return OPCODE_ADD; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 149) + return OPCODE_ADDX2; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 150) + return OPCODE_ADDX4; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 151) + return OPCODE_ADDX8; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 152) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 153) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 154) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 155) + return OPCODE_AND; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 156) + return OPCODE_MAX; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 157) + return OPCODE_MAXU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 158) + return OPCODE_MIN; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 159) + return OPCODE_MINU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 160) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 161) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 162) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 163) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 164) + return OPCODE_OR; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 165) + return OPCODE_SRC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 166) + return OPCODE_SUB; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 167) + return OPCODE_SUBX2; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 168) + return OPCODE_SUBX4; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 169) + return OPCODE_SUBX8; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 170) + return OPCODE_XOR; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 171) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 172) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 173) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 174) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 175) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 176) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 177) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 178) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 179) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 180) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 181) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 182) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 183) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 184) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 185) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 186) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 187) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 188) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 189) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 190) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 191) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 192) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 193) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 194) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 195) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 196) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 197) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 198) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 199) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 200) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 201) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 202) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 203) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 204) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 205) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 206) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 207) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 208) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 209) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 210) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 211) + return OPCODE_SEXT; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 212) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 213) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 214) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 215) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 216) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 217) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 218) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 219) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 220) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 221) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 222) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 223) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 224) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 225) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 226) + return OPCODE_SRLI; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 227 && + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 227 && + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 228 && + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 228 && + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_6_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_6_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SRA; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 5) + return OPCODE_SRL; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LB; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 240 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 240 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 241 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot1_19_13_Slot_ae_slot1_get (insn) == 72) + return OPCODE_SLLI; + if (Field_fld_ae_slot1_19_13_Slot_ae_slot1_get (insn) == 73) + return OPCODE_SRAI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot1_19_17_Slot_ae_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (insn) == 61735) + return OPCODE_SSA8B; + if (Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (insn) == 61751) + return OPCODE_SSA8L; + if (Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (insn) == 61767) + return OPCODE_SSL; + if (Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (insn) == 61783) + return OPCODE_SSR; + if (Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (insn) == 3696) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (insn) == 3697) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (insn) == 3698) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (insn) == 3699) + return OPCODE_MOV_N; + if (Field_fld_ae_slot1_19_9_Slot_ae_slot1_get (insn) == 1928 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 7) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_get (insn) == 18088096) + return OPCODE_NOP; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 257) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 258) + return OPCODE_AE_MULAF16X4SS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 259) + return OPCODE_AE_MULF16X4SS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 260) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 261) + return OPCODE_AE_MULSF16X4SS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULAC32; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULC32; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_MADD_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_MSUB_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_ADD_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 278 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 278 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 278 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 278 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 279 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 279 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 279 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 279 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_MUL_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_SUB_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 282 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 282 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 282 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 282 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 283 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 283 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 283 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 283 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 284 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 284 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 284 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 284 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 285 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 285 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 285 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 285 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 286 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 286 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 286 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 286 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 287 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 287 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 287 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 287 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 17 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 17 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 17 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 17 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_BEQI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_BEQ_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_BGEI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 11) + return OPCODE_BGEUI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 12) + return OPCODE_BGEU_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 13) + return OPCODE_BGE_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 14) + return OPCODE_BLTI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 15) + return OPCODE_BLTUI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 16) + return OPCODE_BLTU_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 17) + return OPCODE_BLT_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 18) + return OPCODE_BNALL_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 19) + return OPCODE_BNEI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 20) + return OPCODE_BNE_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 21) + return OPCODE_BNONE_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 22 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_BEQZ_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 22 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_BGEZ_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 22 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_BLTZ_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 22 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_BNEZ_W15; + if (Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_get (insn) == 23068680 && + Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_get (insn) == 1019904) + return OPCODE_NOP; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 32) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 33) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 34) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 35) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 36) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 37) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 38) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 39) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 40) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 41) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 42) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 43) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 44) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 45) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 46) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 47) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 48) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 49) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 50) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 51) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 52) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 53) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 54) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 55) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 56) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 57) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 58) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 59) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 60) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 61) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 62) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 63) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 64) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 65) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 66) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 67) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 68) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 69) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 70) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 71) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 72) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 73) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 74) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 75) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 76) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 77) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 78) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 79) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 80) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 81) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 82) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 83) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 84) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 85) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 86) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 87) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 88) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 89) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 90) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 91) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 92) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 93) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 94) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 95) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 96) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 97) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 98) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 99) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 100) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 101) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 102) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 103) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 104) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 105) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 106) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 107) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 108) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 109) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 110) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 111) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 112) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 113) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 114) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 115) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 116) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 117) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 118) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 119) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 120) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 121) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 122) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 123) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 124) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 125) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 126) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 127) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 128) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 129) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 130) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 131) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 132) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 133) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 134) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 135) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 136) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 137) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 138) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 139) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 140) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 141) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 142) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 143) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 144) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 145) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 146) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 147) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 148) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 149) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 150) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 151) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 152) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 153) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 154) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 155) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 156) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 157) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 158) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 159) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 160) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 161) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 162) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 163) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 164) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 165) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 166) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 167) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 168) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 169) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 170) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 171) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 172) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 173) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 174) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 175) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 176) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 177) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 178) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 179) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 180) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 181) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 182) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 183) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 184) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 185) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 186) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 187) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 188) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 189) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 190) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 191) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 192) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 193) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 194) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 195) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 196) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 197) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 198) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 199) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 200) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 201) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 202) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 203) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 204) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 205) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 206) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 207) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 208) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 209) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 210) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 211) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 212) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 213) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 214) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 215) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 216) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 217) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 218) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 219) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 220) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 221) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 222) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 223) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 224) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 225) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 226) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 227) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 228) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 229) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 230) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 231) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 232) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 233) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 234) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 235) + return OPCODE_AE_MULAC32; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 236) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 237) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 238) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 239) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 240) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 241) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 242) + return OPCODE_AE_MULC32; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 243) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 244) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 245) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 246) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 247) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 248) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 250) + return OPCODE_MSUB_S; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 251) + return OPCODE_MUL_S; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 252) + return OPCODE_SUB_S; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 253) + return OPCODE_MADD_S; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 254) + return OPCODE_ADD_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_get (insn) == 40960) + return OPCODE_NOP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 4) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 5) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 6) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 7) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 8 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 8 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 9 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 9 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_get (insn) == 28864) + return OPCODE_NOP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 4) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_get (insn) == 450) + return OPCODE_AE_LA64_PP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_get (insn) == 12289) + return OPCODE_NOP; + if (Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (insn) == 3 && + Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MUL32JS; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_get (insn) == 131072) + return OPCODE_NOP; + if (Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_get (insn) == 41104) + return OPCODE_NOP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 7 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 7 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 8 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 8 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 8 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 8 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 9 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 9 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 9 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 9 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 10 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 10 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 10 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_RIC; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_get (insn) == 32784) + return OPCODE_NOP; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 7 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 7 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 8 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_RIC; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_get (insn) == 262144) + return OPCODE_NOP; + if (Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ32X16; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_get (insn) == 262144) + return OPCODE_NOP; + if (Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAAAFQ32X16_S2; + if (Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16_S2; + if (Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16_S2; + if (Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ32X16_S2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot2_20_0_Slot_ae_slot2_get (insn) == 1531921) + return OPCODE_NOP; + if (Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (insn) == 1484 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_SEXT72; + if (Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (insn) == 1488) + return OPCODE_AE_ADD72X64; + if (Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (insn) == 1489) + return OPCODE_AE_SUB72X64; + if (Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (insn) == 1490) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 56) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 57) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 58) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 59) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 60) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 61) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 62) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 63) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 64) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 65) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 66) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 67) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 68) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 69) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 70) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 71) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 72) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 73) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 74) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 75) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 76) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 77) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 78) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 79) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 80) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 81) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 82) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 83) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 84) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 85) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 86) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 87) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 88) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 89) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 90) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 91) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 92) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 93) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 94) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 95) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 96) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 97) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 98) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 99) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 100) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 101) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 102) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 103) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 104) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 105) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 106) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 107) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 108) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 109) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 110) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 111) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 112) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 113) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 114) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 115) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 116) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 117) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 118) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 119) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 120) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 121) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 122) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 123) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 124) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 125) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 126) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 127) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 128) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 129) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 130) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 131) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 132) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 133) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 134) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 135) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 136) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 137) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 138) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 139) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 140) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 141) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 142) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 143) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 144) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 145) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 146) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 147) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 148) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 149) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 150) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 151) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 152) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 153) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 154) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 155) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 156) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 157) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 158) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 159) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 160) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 161) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 162) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 163) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 164) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 165) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 166) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 167) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 168) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 169) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 170) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 171) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 172) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 173) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 174) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 175) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 176) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 177) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 178) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 179) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 180) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 181) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 182) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 183) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 184) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 185) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 186) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 187) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 188) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 189) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 190) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 191) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 192) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 193) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 194) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 195) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 196) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 197) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 198) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 199) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 200) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 201) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 202) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 203) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 204) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 205) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 206) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 207) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 208) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 209) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 210) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 211) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 212) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 213) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 214) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 215) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 216) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 217) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 218) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 219) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 220) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 221) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 222) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 223) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 224) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 225) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 226) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 227) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 228) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 229) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 230) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 231) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 232) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 233) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 234) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 235) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 236) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 237) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 238) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 239) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 240) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 241) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 242) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 243) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 244) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 245) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 246) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 247) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 248) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 249) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 250) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 251) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 252) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 253) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 254) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 255) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 256) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 257) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 258) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 259) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 260) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 261) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 262) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 263) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 264) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 265) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 266) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 267) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 268) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 269) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 270) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 271) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 272) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 273) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 274) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 275) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 276) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 277) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 278) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 279) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 280) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 281) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 282) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 283) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 284) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 285) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 286) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 287) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 288) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 289) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 290) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 291) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 292) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 293) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 294) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 295) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 296) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 297) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 298) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 299) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 300) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 301) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 302) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 303) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 304) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 305) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 306) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 307) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 308) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 309) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 310) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 311) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 312) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 313) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 314) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 315) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 316) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 317) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 318) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 319) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 320) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 321) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 322) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 323) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 324) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 325) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 326) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 327) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 328) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 329) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 330) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 331) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 332) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 333) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 334) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 335) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 336) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 337) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 338) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 339) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 340) + return OPCODE_AE_ADD72; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 341) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 342) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 343) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 344) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 345) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 346) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 347) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 348) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 349) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 350) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 351) + return OPCODE_AE_SUB72; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 352) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 353) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 354) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 355) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 356) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 357) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 358) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 359) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 360) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 361) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 362) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 363) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 364) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 365) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 366) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 367) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 368) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 369) + return OPCODE_AE_MULFP16X4RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 370) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_2_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_2_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_PKSR24; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_2_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 15) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 14) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 13) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 373 && + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 374 && + Field_fld_ae_slot2_7_4_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 374 && + Field_fld_ae_slot2_7_0_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 374 && + Field_fld_ae_slot2_7_4_Slot_ae_slot2_get (insn) == 8) + return OPCODE_ABS_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 374 && + Field_fld_ae_slot2_7_4_Slot_ae_slot2_get (insn) == 9) + return OPCODE_NEG_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 375) + return OPCODE_MAX_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 376) + return OPCODE_MIN_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 377) + return OPCODE_ADD_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 378) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 379) + return OPCODE_MADD_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 380) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 381) + return OPCODE_MUL_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 382) + return OPCODE_SUB_S; + if (Field_fld_ae_slot2_20_13_Slot_ae_slot2_get (insn) == 196) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MUL32USEP_LH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL32USEP_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULA32USEP_LH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32USEP_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae_slot2_20_15_Slot_ae_slot2_get (insn) == 48) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot2_20_4_Slot_ae_slot2_get (insn) == 98160) + return OPCODE_AE_MOVFCRFSRV; + if (Field_fld_ae_slot2_20_4_Slot_ae_slot2_get (insn) == 98161) + return OPCODE_AE_MOVVFCRFSR; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5964) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5965) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5966) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5967) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5969) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5970) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5971) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5973) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5974) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5975) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5977) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5978) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5979) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5981) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5982) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5983) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6128) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6129) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6130) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6131) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6132) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6133) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6134) + return OPCODE_CONST_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (insn) == 461585) + return OPCODE_AE_CALCRNG1; + if (Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (insn) == 461589) + return OPCODE_AE_CALCRNG2; + if (Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (insn) == 461593) + return OPCODE_AE_CALCRNG3; + if (Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (insn) == 461597) + return OPCODE_NOP; + if (Field_fld_ae_slot3_20_10_Slot_ae_slot3_get (insn) == 1752) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 97) + return OPCODE_AE_MUL32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 101) + return OPCODE_AE_MUL32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 105) + return OPCODE_AE_MUL32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 109) + return OPCODE_AE_MUL32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 110) + return OPCODE_AE_MUL16_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 111) + return OPCODE_AE_MUL32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 116) + return OPCODE_AE_MUL32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 117) + return OPCODE_AE_MUL32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 118) + return OPCODE_AE_MUL32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 119) + return OPCODE_AE_MUL32_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 120) + return OPCODE_AE_MUL32_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 121) + return OPCODE_AE_MUL32_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 122) + return OPCODE_AE_MULA16_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 123) + return OPCODE_AE_MULA32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 124) + return OPCODE_AE_MULA32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 125) + return OPCODE_AE_MULA32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 126) + return OPCODE_AE_MULA32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 127) + return OPCODE_AE_MULA32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 128) + return OPCODE_AE_MULA32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 129) + return OPCODE_AE_MULA32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 130) + return OPCODE_AE_MULA32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 131) + return OPCODE_AE_MULA32_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 132) + return OPCODE_AE_MULA32_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 133) + return OPCODE_AE_MULA32_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 134) + return OPCODE_AE_MULAAAAQ16_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 135) + return OPCODE_AE_MULAAD32X16_H0_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 136) + return OPCODE_AE_MULAAD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 137) + return OPCODE_AE_MULAAD32X16_H2_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 138) + return OPCODE_AE_MULAAD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 139) + return OPCODE_AE_MULAAD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 140) + return OPCODE_AE_MULAAD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 141) + return OPCODE_AE_MULAAFD16SS_11_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 142) + return OPCODE_AE_MULAAFD16SS_13_02_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 143) + return OPCODE_AE_MULAAFD16SS_33_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 144) + return OPCODE_AE_MULAAFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 145) + return OPCODE_AE_MULAAFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 146) + return OPCODE_AE_MULAAFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 147) + return OPCODE_AE_MULAAFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 148) + return OPCODE_AE_MULAAFD32X16_H0_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 149) + return OPCODE_AE_MULAAFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 150) + return OPCODE_AE_MULAAFD32X16_H2_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 151) + return OPCODE_AE_MULAAFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 152) + return OPCODE_AE_MULAF16SS_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 153) + return OPCODE_AE_MULAF16SS_10_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 154) + return OPCODE_AE_MULAF16SS_11_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 155) + return OPCODE_AE_MULAF16SS_20_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 156) + return OPCODE_AE_MULAF16SS_21_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 157) + return OPCODE_AE_MULAF16SS_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 158) + return OPCODE_AE_MULAF16SS_30_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 159) + return OPCODE_AE_MULAF16SS_31_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 160) + return OPCODE_AE_MULAF16SS_32_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 161) + return OPCODE_AE_MULAF16SS_33_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 162) + return OPCODE_AE_MULAF32RA_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 163) + return OPCODE_AE_MULAF32RA_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 164) + return OPCODE_AE_MULAF32RA_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 165) + return OPCODE_AE_MULAF32R_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 166) + return OPCODE_AE_MULAF32R_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 167) + return OPCODE_AE_MULAF32R_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 168) + return OPCODE_AE_MULAF32S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 169) + return OPCODE_AE_MULAF32S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 170) + return OPCODE_AE_MULAF32S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 171) + return OPCODE_AE_MULAF32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 172) + return OPCODE_AE_MULAF32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 173) + return OPCODE_AE_MULAF32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 174) + return OPCODE_AE_MULAF32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 175) + return OPCODE_AE_MULAF32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 176) + return OPCODE_AE_MULAF32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 177) + return OPCODE_AE_MULAF32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 178) + return OPCODE_AE_MULAF32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 179) + return OPCODE_AE_MULAF48Q32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 180) + return OPCODE_AE_MULAF48Q32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 181) + return OPCODE_AE_MULAFP24X2RA_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 182) + return OPCODE_AE_MULAFP24X2R_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 183) + return OPCODE_AE_MULAFP32X16X2RAS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 184) + return OPCODE_AE_MULAFP32X16X2RAS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 185) + return OPCODE_AE_MULAFP32X16X2RS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 186) + return OPCODE_AE_MULAFP32X16X2RS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 187) + return OPCODE_AE_MULAFP32X16X2S_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 188) + return OPCODE_AE_MULAFP32X16X2S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 189) + return OPCODE_AE_MULAFP32X2RAS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 190) + return OPCODE_AE_MULAFP32X2RS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 191) + return OPCODE_AE_MULAP32X16X2_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 192) + return OPCODE_AE_MULAP32X16X2_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 193) + return OPCODE_AE_MULAP32X2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 194) + return OPCODE_AE_MULAQ32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 195) + return OPCODE_AE_MULAQ32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 196) + return OPCODE_AE_MULAS32F48P16S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 197) + return OPCODE_AE_MULAS32F48P16S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 198) + return OPCODE_AE_MULAS32F48P16S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 199) + return OPCODE_AE_MULASD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 200) + return OPCODE_AE_MULASD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 201) + return OPCODE_AE_MULASD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 202) + return OPCODE_AE_MULASD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 203) + return OPCODE_AE_MULASFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 204) + return OPCODE_AE_MULASFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 205) + return OPCODE_AE_MULASFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 206) + return OPCODE_AE_MULASFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 207) + return OPCODE_AE_MULASFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 208) + return OPCODE_AE_MULASFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 209) + return OPCODE_AE_MULF16SS_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 210) + return OPCODE_AE_MULF16SS_10_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 211) + return OPCODE_AE_MULF16SS_11_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 212) + return OPCODE_AE_MULF16SS_20_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 213) + return OPCODE_AE_MULF16SS_21_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 214) + return OPCODE_AE_MULF16SS_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 215) + return OPCODE_AE_MULF16SS_30_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 216) + return OPCODE_AE_MULF16SS_31_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 217) + return OPCODE_AE_MULF16SS_32_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 218) + return OPCODE_AE_MULF16SS_33_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 219) + return OPCODE_AE_MULF32RA_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 220) + return OPCODE_AE_MULF32RA_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 221) + return OPCODE_AE_MULF32RA_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 222) + return OPCODE_AE_MULF32R_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 223) + return OPCODE_AE_MULF32R_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 224) + return OPCODE_AE_MULF32R_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 225) + return OPCODE_AE_MULF32S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 226) + return OPCODE_AE_MULF32S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 227) + return OPCODE_AE_MULF32S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 228) + return OPCODE_AE_MULF32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 229) + return OPCODE_AE_MULF32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 230) + return OPCODE_AE_MULF32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 231) + return OPCODE_AE_MULF32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 232) + return OPCODE_AE_MULF32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 233) + return OPCODE_AE_MULF32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 234) + return OPCODE_AE_MULF32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 235) + return OPCODE_AE_MULF32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 236) + return OPCODE_AE_MULF48Q32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 237) + return OPCODE_AE_MULF48Q32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 238) + return OPCODE_AE_MULFP24X2RA_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 239) + return OPCODE_AE_MULFP24X2R_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 240) + return OPCODE_AE_MULFP32X16X2RAS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 241) + return OPCODE_AE_MULFP32X16X2RAS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 242) + return OPCODE_AE_MULFP32X16X2RS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 243) + return OPCODE_AE_MULFP32X16X2RS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 244) + return OPCODE_AE_MULFP32X16X2S_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 245) + return OPCODE_AE_MULFP32X16X2S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 246) + return OPCODE_AE_MULFP32X2RAS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 247) + return OPCODE_AE_MULFP32X2RS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 248) + return OPCODE_AE_MULP32X16X2_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 249) + return OPCODE_AE_MULP32X16X2_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 250) + return OPCODE_AE_MULP32X2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 251) + return OPCODE_AE_MULQ32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 252) + return OPCODE_AE_MULQ32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 253) + return OPCODE_AE_MULS32F48P16S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 254) + return OPCODE_AE_MULS32F48P16S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 255) + return OPCODE_AE_MULS32F48P16S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 256) + return OPCODE_AE_MULS32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 257) + return OPCODE_AE_MULS32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 258) + return OPCODE_AE_MULS32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 259) + return OPCODE_AE_MULS32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 260) + return OPCODE_AE_MULS32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 261) + return OPCODE_AE_MULS32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 262) + return OPCODE_AE_MULS32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 263) + return OPCODE_AE_MULS32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 264) + return OPCODE_AE_MULS32_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 265) + return OPCODE_AE_MULS32_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 266) + return OPCODE_AE_MULS32_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 267) + return OPCODE_AE_MULSAD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 268) + return OPCODE_AE_MULSAD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 269) + return OPCODE_AE_MULSAD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 270) + return OPCODE_AE_MULSAFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 271) + return OPCODE_AE_MULSAFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 272) + return OPCODE_AE_MULSAFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 273) + return OPCODE_AE_MULSAFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 274) + return OPCODE_AE_MULSF16SS_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 275) + return OPCODE_AE_MULSF16SS_10_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 276) + return OPCODE_AE_MULSF16SS_11_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 277) + return OPCODE_AE_MULSF16SS_20_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 278) + return OPCODE_AE_MULSF16SS_21_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 279) + return OPCODE_AE_MULSF16SS_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 280) + return OPCODE_AE_MULSF16SS_30_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 281) + return OPCODE_AE_MULSF16SS_31_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 282) + return OPCODE_AE_MULSF16SS_32_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 283) + return OPCODE_AE_MULSF16SS_33_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 284) + return OPCODE_AE_MULSF32RA_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 285) + return OPCODE_AE_MULSF32RA_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 286) + return OPCODE_AE_MULSF32RA_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 287) + return OPCODE_AE_MULSF32R_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 288) + return OPCODE_AE_MULSF32R_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 289) + return OPCODE_AE_MULSF32R_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 290) + return OPCODE_AE_MULSF32S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 291) + return OPCODE_AE_MULSF32S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 292) + return OPCODE_AE_MULSF32S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 293) + return OPCODE_AE_MULSF32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 294) + return OPCODE_AE_MULSF32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 295) + return OPCODE_AE_MULSF32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 296) + return OPCODE_AE_MULSF32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 297) + return OPCODE_AE_MULSF32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 298) + return OPCODE_AE_MULSF32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 299) + return OPCODE_AE_MULSF32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 300) + return OPCODE_AE_MULSF32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 301) + return OPCODE_AE_MULSF48Q32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 302) + return OPCODE_AE_MULSF48Q32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 303) + return OPCODE_AE_MULSFP24X2RA_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 304) + return OPCODE_AE_MULSFP24X2R_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 305) + return OPCODE_AE_MULSFP32X16X2RAS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 306) + return OPCODE_AE_MULSFP32X16X2RAS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 307) + return OPCODE_AE_MULSFP32X16X2RS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 308) + return OPCODE_AE_MULSFP32X16X2RS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 309) + return OPCODE_AE_MULSFP32X16X2S_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 310) + return OPCODE_AE_MULSFP32X16X2S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 311) + return OPCODE_AE_MULSFP32X2RAS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 312) + return OPCODE_AE_MULSFP32X2RS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 313) + return OPCODE_AE_MULSP32X16X2_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 314) + return OPCODE_AE_MULSP32X16X2_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 315) + return OPCODE_AE_MULSP32X2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 316) + return OPCODE_AE_MULSQ32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 317) + return OPCODE_AE_MULSQ32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 318) + return OPCODE_AE_MULSS32F48P16S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 319) + return OPCODE_AE_MULSS32F48P16S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 320) + return OPCODE_AE_MULSS32F48P16S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 321) + return OPCODE_AE_MULSSD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 322) + return OPCODE_AE_MULSSD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 323) + return OPCODE_AE_MULSSD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 324) + return OPCODE_AE_MULSSD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 325) + return OPCODE_AE_MULSSFD16SS_11_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 326) + return OPCODE_AE_MULSSFD16SS_13_02_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 327) + return OPCODE_AE_MULSSFD16SS_33_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 328) + return OPCODE_AE_MULSSFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 329) + return OPCODE_AE_MULSSFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 330) + return OPCODE_AE_MULSSFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 331) + return OPCODE_AE_MULSSFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 332) + return OPCODE_AE_MULSSFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 333) + return OPCODE_AE_MULSSFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 334) + return OPCODE_AE_MULZAAAAQ16_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 335) + return OPCODE_AE_MULZAAD32X16_H0_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 336) + return OPCODE_AE_MULZAAD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 337) + return OPCODE_AE_MULZAAD32X16_H2_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 338) + return OPCODE_AE_MULZAAD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 339) + return OPCODE_AE_MULZAAD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 340) + return OPCODE_AE_MULZAAD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 341) + return OPCODE_AE_MULZAAFD16SS_11_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 342) + return OPCODE_AE_MULZAAFD16SS_13_02_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 343) + return OPCODE_AE_MULZAAFD16SS_33_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 344) + return OPCODE_AE_MULZAAFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 345) + return OPCODE_AE_MULZAAFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 346) + return OPCODE_AE_MULZAAFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 347) + return OPCODE_AE_MULZAAFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 348) + return OPCODE_AE_MULZAAFD32X16_H0_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 349) + return OPCODE_AE_MULZAAFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 350) + return OPCODE_AE_MULZAAFD32X16_H2_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 351) + return OPCODE_AE_MULZAAFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 352) + return OPCODE_AE_MULZASD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 353) + return OPCODE_AE_MULZASD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 354) + return OPCODE_AE_MULZASD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 355) + return OPCODE_AE_MULZASD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 356) + return OPCODE_AE_MULZASFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 357) + return OPCODE_AE_MULZASFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 358) + return OPCODE_AE_MULZASFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 359) + return OPCODE_AE_MULZASFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 360) + return OPCODE_AE_MULZASFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 361) + return OPCODE_AE_MULZASFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 362) + return OPCODE_AE_MULZSAD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 363) + return OPCODE_AE_MULZSAD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 364) + return OPCODE_AE_MULZSAD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 365) + return OPCODE_AE_MULZSAFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 366) + return OPCODE_AE_MULZSAFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 367) + return OPCODE_AE_MULZSAFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 368) + return OPCODE_AE_MULZSAFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 369) + return OPCODE_AE_MULZSSD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 370) + return OPCODE_AE_MULZSSD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 371) + return OPCODE_AE_MULZSSD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 372) + return OPCODE_AE_MULZSSD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 373) + return OPCODE_AE_MULZSSFD16SS_11_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 374) + return OPCODE_AE_MULZSSFD16SS_13_02_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 375) + return OPCODE_AE_MULZSSFD16SS_33_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 376) + return OPCODE_AE_MULZSSFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 377) + return OPCODE_AE_MULZSSFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 378) + return OPCODE_AE_MULZSSFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 379) + return OPCODE_AE_MULZSSFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 380) + return OPCODE_AE_MULZSSFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 381) + return OPCODE_AE_MULZSSFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 382) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 383) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 384) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 385) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 386) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 387) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 388) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 389) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 390) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 391) + return OPCODE_AE_ADDRNG32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 392) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 393) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 394) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 395) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 396) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 397) + return OPCODE_AE_MAXABS32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 398) + return OPCODE_AE_MAXABS64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 399) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 400) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 401) + return OPCODE_AE_MINABS32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 402) + return OPCODE_AE_MINABS64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 403) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 404) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 405) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 406) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 407) + return OPCODE_AE_ROUND32X2F48SASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 408) + return OPCODE_AE_ROUND32X2F48SSYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 409) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 410) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 411) + return OPCODE_AE_ROUNDSP16Q48X2ASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 412) + return OPCODE_AE_ROUNDSP16Q48X2SYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 413) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 414) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 415) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 416) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 417) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 418) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 419) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 420) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 421) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 422) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 423) + return OPCODE_AE_SUBRNG32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 424) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 425) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 426) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 427) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 428) + return OPCODE_AE_AND; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 429) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 430) + return OPCODE_AE_OR; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 431) + return OPCODE_AE_SEXT32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 432) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 433) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 434) + return OPCODE_AE_MOVF64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 435) + return OPCODE_AE_MOVT64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 436 && + Field_fld_ae_slot3_0_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 436 && + Field_fld_ae_slot3_0_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 437 && + Field_fld_ae_slot3_1_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 437 && + Field_fld_ae_slot3_1_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_TRUNCP16; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_SATQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_SAT24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_ROUNDSQ32F48SYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_ROUNDSQ32F48ASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 440 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 440 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 440 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 441 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 441 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 441 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 442 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 442 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 442 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 443 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 443 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 443 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 444) + return OPCODE_ADD_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 445) + return OPCODE_MADD_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 446) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 447) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 480) + return OPCODE_MUL_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 481) + return OPCODE_SUB_S; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 241) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MUL32EP_HH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULA32EP_HH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAD32EP_HH_LL_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAD32USEP_HL_LH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULS32EP_HH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSSD32EP_HH_LL_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULZAAD32EP_HH_LL_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULZAAD32USEP_HL_LH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULZSSD32EP_HH_LL_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 28 && + Field_fld_ae_slot3_11_4_Slot_ae_slot3_get (insn) == 176 && + Field_fld_ae_slot3_1_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 28 && + Field_fld_ae_slot3_11_11_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SLAI72; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 110 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot3_20_15_Slot_ae_slot3_get (insn) == 58) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SRAI72; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 6 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1800) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1801) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1802) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1803 && + Field_fld_ae_slot3_3_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_RNG32X2; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1804) + return OPCODE_NEG_S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1816) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1817) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1818) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1832) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1833) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1834) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1848) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1849) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1850) + return OPCODE_AE_SHORTSWAP; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7012) + return OPCODE_AE_ROUNDSP16F24ASYM; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7013) + return OPCODE_AE_ROUNDSP16F24SYM; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7014) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7015) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7016) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7017) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7018) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7019) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7020) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7021) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7022) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7023) + return OPCODE_AE_SRAS32; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_ae_format88_Format_ae_slot3_32_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[1] & 0xf); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c0000) >> 18) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0x18000000) >> 27) << 12); + slotbuf[0] = (slotbuf[0] & ~0x1fc000) | (((insn[2] & 0xfe0000) >> 17) << 14); +} + +static void +Slot_ae_format88_Format_ae_slot3_32_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf) | (slotbuf[0] & 0xf); + insn[1] = (insn[1] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[1] = (insn[1] & ~0x3c0000) | (((slotbuf[0] & 0xf00) >> 8) << 18); + insn[1] = (insn[1] & ~0x18000000) | (((slotbuf[0] & 0x3000) >> 12) << 27); + insn[2] = (insn[2] & ~0xfe0000) | (((slotbuf[0] & 0x1fc000) >> 14) << 17); +} + +static void +Slot_ae_format88_Format_ae_slot2_28_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x20) >> 5) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x1c00) >> 10) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x2000) >> 13) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x4000000) >> 26) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1fc000) | (((insn[2] & 0x1fc00) >> 10) << 14); +} + +static void +Slot_ae_format88_Format_ae_slot2_28_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); + insn[1] = (insn[1] & ~0x20) | (((slotbuf[0] & 0x10) >> 4) << 5); + insn[1] = (insn[1] & ~0x1c00) | (((slotbuf[0] & 0xe0) >> 5) << 10); + insn[1] = (insn[1] & ~0x3c000) | (((slotbuf[0] & 0xf00) >> 8) << 14); + insn[1] = (insn[1] & ~0x2000) | (((slotbuf[0] & 0x1000) >> 12) << 13); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x2000) >> 13) << 26); + insn[2] = (insn[2] & ~0x1fc00) | (((slotbuf[0] & 0x1fc000) >> 14) << 10); +} + +static void +Slot_ae_format88_Format_ae_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xfff0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xff000) | (((insn[2] & 0x3fc) >> 2) << 12); +} + +static void +Slot_ae_format88_Format_ae_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0000) | ((slotbuf[0] & 0xfff) << 16); + insn[2] = (insn[2] & ~0x3fc) | (((slotbuf[0] & 0xff000) >> 12) << 2); +} + +static void +Slot_ae_format88_Format_ae_slot0_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c0) >> 6) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x10) >> 4) << 12); + slotbuf[0] = (slotbuf[0] & ~0xe000) | (((insn[0] & 0xe0) >> 5) << 13); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[1] & 0xe0000000) >> 29) << 16); + slotbuf[0] = (slotbuf[0] & ~0x180000) | ((insn[2] & 0x3) << 19); +} + +static void +Slot_ae_format88_Format_ae_slot0_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[1] = (insn[1] & ~0x3c0) | (((slotbuf[0] & 0xf00) >> 8) << 6); + insn[1] = (insn[1] & ~0x10) | (((slotbuf[0] & 0x1000) >> 12) << 4); + insn[0] = (insn[0] & ~0xe0) | (((slotbuf[0] & 0xe000) >> 13) << 5); + insn[1] = (insn[1] & ~0xe0000000) | (((slotbuf[0] & 0x70000) >> 16) << 29); + insn[2] = (insn[2] & ~0x3) | ((slotbuf[0] & 0x180000) >> 19); +} + +static void +Slot_ae_format88_2_Format_ae2_slot2_28_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); + slotbuf[0] = (slotbuf[0] & ~0xf0) | ((insn[1] & 0xf) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x20) >> 5) << 12); + slotbuf[0] = (slotbuf[0] & ~0xe000) | (((insn[1] & 0x1c00) >> 10) << 13); + slotbuf[0] = (slotbuf[0] & ~0xf0000) | (((insn[1] & 0x3c0000) >> 18) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[2] & 0xf800) >> 11) << 20); +} + +static void +Slot_ae_format88_2_Format_ae2_slot2_28_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); + insn[1] = (insn[1] & ~0xf) | ((slotbuf[0] & 0xf0) >> 4); + insn[1] = (insn[1] & ~0x3c000) | (((slotbuf[0] & 0xf00) >> 8) << 14); + insn[1] = (insn[1] & ~0x20) | (((slotbuf[0] & 0x1000) >> 12) << 5); + insn[1] = (insn[1] & ~0x1c00) | (((slotbuf[0] & 0xe000) >> 13) << 10); + insn[1] = (insn[1] & ~0x3c0000) | (((slotbuf[0] & 0xf0000) >> 16) << 18); + insn[2] = (insn[2] & ~0xf800) | (((slotbuf[0] & 0x1f00000) >> 20) << 11); +} + +static void +Slot_ae_format88_2_Format_ae2_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf000000) >> 24) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf00000) >> 20) << 8); + slotbuf[0] = (slotbuf[0] & ~0xff000) | (((insn[2] & 0x7f8) >> 3) << 12); +} + +static void +Slot_ae_format88_2_Format_ae2_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000) | ((slotbuf[0] & 0xf) << 16); + insn[0] = (insn[0] & ~0xf000000) | (((slotbuf[0] & 0xf0) >> 4) << 24); + insn[0] = (insn[0] & ~0xf00000) | (((slotbuf[0] & 0xf00) >> 8) << 20); + insn[2] = (insn[2] & ~0x7f8) | (((slotbuf[0] & 0xff000) >> 12) << 3); +} + +static void +Slot_ae_format88_2_Format_ae2_slot0_6_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c0) >> 6) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x10) >> 4) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2000) >> 13) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[0] & 0xc0) >> 6) << 14); + slotbuf[0] = (slotbuf[0] & ~0x3ff0000) | (((insn[1] & 0xffc00000) >> 22) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1c000000) | ((insn[2] & 0x7) << 26); +} + +static void +Slot_ae_format88_2_Format_ae2_slot0_6_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[1] = (insn[1] & ~0x3c0) | (((slotbuf[0] & 0xf00) >> 8) << 6); + insn[1] = (insn[1] & ~0x10) | (((slotbuf[0] & 0x1000) >> 12) << 4); + insn[1] = (insn[1] & ~0x2000) | (((slotbuf[0] & 0x2000) >> 13) << 13); + insn[0] = (insn[0] & ~0xc0) | (((slotbuf[0] & 0xc000) >> 14) << 6); + insn[1] = (insn[1] & ~0xffc00000) | (((slotbuf[0] & 0x3ff0000) >> 16) << 22); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x1c000000) >> 26); +} + +static void +Slot_ae_format48_Format_ae3_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf000000) >> 24) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf00000) >> 20) << 8); + slotbuf[0] = (slotbuf[0] & ~0xff000) | (((insn[1] & 0x3fc0) >> 6) << 12); +} + +static void +Slot_ae_format48_Format_ae3_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000) | ((slotbuf[0] & 0xf) << 16); + insn[0] = (insn[0] & ~0xf000000) | (((slotbuf[0] & 0xf0) >> 4) << 24); + insn[0] = (insn[0] & ~0xf00000) | (((slotbuf[0] & 0xf00) >> 8) << 20); + insn[1] = (insn[1] & ~0x3fc0) | (((slotbuf[0] & 0xff000) >> 12) << 6); +} + +static void +Slot_ae_format48_Format_ae3_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[0] & 0xf0000000) >> 28) << 12); + slotbuf[0] = (slotbuf[0] & ~0x3f0000) | ((insn[1] & 0x3f) << 16); +} + +static void +Slot_ae_format48_Format_ae3_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf000) >> 12) << 28); + insn[1] = (insn[1] & ~0x3f) | ((slotbuf[0] & 0x3f0000) >> 16); +} + +static void +Slot_ae_format48_2_Format_ae4_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf000000) >> 24) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf00000) >> 20) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0x3000) >> 12) << 12); +} + +static void +Slot_ae_format48_2_Format_ae4_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000) | ((slotbuf[0] & 0xf) << 16); + insn[0] = (insn[0] & ~0xf000000) | (((slotbuf[0] & 0xf0) >> 4) << 24); + insn[0] = (insn[0] & ~0xf00000) | (((slotbuf[0] & 0xf00) >> 8) << 20); + insn[1] = (insn[1] & ~0x3000) | (((slotbuf[0] & 0x3000) >> 12) << 12); +} + +static void +Slot_ae_format48_2_Format_ae4_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[0] & 0xf0000000) >> 28) << 12); + slotbuf[0] = (slotbuf[0] & ~0xfff0000) | ((insn[1] & 0xfff) << 16); +} + +static void +Slot_ae_format48_2_Format_ae4_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf000) >> 12) << 28); + insn[1] = (insn[1] & ~0xfff) | ((slotbuf[0] & 0xfff0000) >> 16); +} + +static void +Slot_ae_format48_3_Format_ae5_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xfff0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xff000) | (((insn[1] & 0x7f80) >> 7) << 12); +} + +static void +Slot_ae_format48_3_Format_ae5_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0000) | ((slotbuf[0] & 0xfff) << 16); + insn[1] = (insn[1] & ~0x7f80) | (((slotbuf[0] & 0xff000) >> 12) << 7); +} + +static void +Slot_ae_format48_3_Format_ae5_slot1_38_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[1] & 0x40) >> 6); +} + +static void +Slot_ae_format48_3_Format_ae5_slot1_38_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40) | ((slotbuf[0] & 0x1) << 6); +} + +static void +Slot_ae_format48_3_Format_ae5_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[0] & 0xf0000000) >> 28) << 12); + slotbuf[0] = (slotbuf[0] & ~0x3f0000) | ((insn[1] & 0x3f) << 16); +} + +static void +Slot_ae_format48_3_Format_ae5_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf000) >> 12) << 28); + insn[1] = (insn[1] & ~0x3f) | ((slotbuf[0] & 0x3f0000) >> 16); +} + +static void +Slot_ae_format88_3_Format_ae6_slot3_32_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[1] & 0x3c00000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0x3c0000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | ((insn[1] & 0xf) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[1] & 0x3c0) >> 6) << 12); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[2] & 0x18) >> 3) << 16); +} + +static void +Slot_ae_format88_3_Format_ae6_slot3_32_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3c00000) | ((slotbuf[0] & 0xf) << 22); + insn[1] = (insn[1] & ~0x3c0000) | (((slotbuf[0] & 0xf0) >> 4) << 18); + insn[1] = (insn[1] & ~0xf) | ((slotbuf[0] & 0xf00) >> 8); + insn[1] = (insn[1] & ~0x3c0) | (((slotbuf[0] & 0xf000) >> 12) << 6); + insn[2] = (insn[2] & ~0x18) | (((slotbuf[0] & 0x30000) >> 16) << 3); +} + +static void +Slot_ae_format88_3_Format_ae6_slot2_28_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[1] & 0x3c000) >> 14); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x20) >> 5) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x1c00) >> 10) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[2] & 0x6) >> 1) << 12); +} + +static void +Slot_ae_format88_3_Format_ae6_slot2_28_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3c000) | ((slotbuf[0] & 0xf) << 14); + insn[1] = (insn[1] & ~0x20) | (((slotbuf[0] & 0x10) >> 4) << 5); + insn[1] = (insn[1] & ~0x1c00) | (((slotbuf[0] & 0xe0) >> 5) << 10); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[2] = (insn[2] & ~0x6) | (((slotbuf[0] & 0x3000) >> 12) << 1); +} + +static void +Slot_ae_format88_3_Format_ae6_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xfff0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0xc0000000) >> 30) << 12); + slotbuf[0] = (slotbuf[0] & ~0x4000) | ((insn[2] & 0x1) << 14); +} + +static void +Slot_ae_format88_3_Format_ae6_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0000) | ((slotbuf[0] & 0xfff) << 16); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x3000) >> 12) << 30); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x4000) >> 14); +} + +static void +Slot_ae_format88_3_Format_ae6_slot0_6_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[1] & 0x10) >> 4) << 8); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x2000) >> 13) << 9); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[1] & 0x3c000000) >> 26) << 12); +} + +static void +Slot_ae_format88_3_Format_ae6_slot0_6_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[1] = (insn[1] & ~0x10) | (((slotbuf[0] & 0x100) >> 8) << 4); + insn[1] = (insn[1] & ~0x2000) | (((slotbuf[0] & 0x200) >> 9) << 13); + insn[0] = (insn[0] & ~0xc0) | (((slotbuf[0] & 0xc00) >> 10) << 6); + insn[1] = (insn[1] & ~0x3c000000) | (((slotbuf[0] & 0xf000) >> 12) << 26); +} + +static void +Slot_ae_format88_4_Format_ae7_slot3_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[1] & 0xf); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[1] & 0x3c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[2] & 0xe00) >> 9) << 16); +} + +static void +Slot_ae_format88_4_Format_ae7_slot3_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf) | (slotbuf[0] & 0xf); + insn[1] = (insn[1] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[1] = (insn[1] & ~0x3c000000) | (((slotbuf[0] & 0xf000) >> 12) << 26); + insn[2] = (insn[2] & ~0xe00) | (((slotbuf[0] & 0x70000) >> 16) << 9); +} + +static void +Slot_ae_format88_4_Format_ae7_slot2_20_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf00000) >> 20) << 4); + slotbuf[0] = (slotbuf[0] & ~0xff00) | (((insn[1] & 0x3fc000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[2] & 0x1c0) >> 6) << 16); +} + +static void +Slot_ae_format88_4_Format_ae7_slot2_20_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); + insn[0] = (insn[0] & ~0xf00000) | (((slotbuf[0] & 0xf0) >> 4) << 20); + insn[1] = (insn[1] & ~0x3fc000) | (((slotbuf[0] & 0xff00) >> 8) << 14); + insn[2] = (insn[2] & ~0x1c0) | (((slotbuf[0] & 0x70000) >> 16) << 6); +} + +static void +Slot_ae_format88_4_Format_ae7_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf000000) >> 24) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c00) >> 10) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[2] & 0x3c) >> 2) << 12); +} + +static void +Slot_ae_format88_4_Format_ae7_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000) | ((slotbuf[0] & 0xf) << 16); + insn[0] = (insn[0] & ~0xf000000) | (((slotbuf[0] & 0xf0) >> 4) << 24); + insn[1] = (insn[1] & ~0x3c00) | (((slotbuf[0] & 0xf00) >> 8) << 10); + insn[2] = (insn[2] & ~0x3c) | (((slotbuf[0] & 0xf000) >> 12) << 2); +} + +static void +Slot_ae_format88_4_Format_ae7_slot0_6_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x30) | (((insn[0] & 0xc0) >> 6) << 4); + slotbuf[0] = (slotbuf[0] & ~0xfc0) | (((insn[1] & 0x3f0) >> 4) << 6); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0xc0000000) >> 30) << 12); + slotbuf[0] = (slotbuf[0] & ~0xc000) | ((insn[2] & 0x3) << 14); +} + +static void +Slot_ae_format88_4_Format_ae7_slot0_6_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xc0) | (((slotbuf[0] & 0x30) >> 4) << 6); + insn[1] = (insn[1] & ~0x3f0) | (((slotbuf[0] & 0xfc0) >> 6) << 4); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x3000) >> 12) << 30); + insn[2] = (insn[2] & ~0x3) | ((slotbuf[0] & 0xc000) >> 14); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_r_disp_Slot_inst_get, + Field_r_3_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_ae_fld_fhba4_Slot_inst_get, + Field_ae_fld_fhba4_2_Slot_inst_get, + Field_ae_fld_tp7_Slot_inst_get, + Field_ae_fld_osa32_Slot_inst_get, + Field_ae_fld_osa64_Slot_inst_get, + Field_ae_fld_imm2_Slot_inst_get, + Field_ae_fld_immls64_Slot_inst_get, + Field_ae_fld_immls64pos_Slot_inst_get, + Field_ae_fld_immls64half_Slot_inst_get, + Field_ae_fld_immls32_Slot_inst_get, + Field_ae_fld_immls16_Slot_inst_get, + 0, + Field_inst_15_12_Slot_inst_get, + Field_inst_11_8_Slot_inst_get, + Field_inst_7_4_Slot_inst_get, + Field_inst_12_Slot_inst_get, + Field_inst_7_Slot_inst_get, + Field_inst_5_4_Slot_inst_get, + Field_inst_7_6_Slot_inst_get, + Field_inst_19_17_Slot_inst_get, + Field_inst_19_18_Slot_inst_get, + Field_inst_9_8_Slot_inst_get, + Field_inst_4_Slot_inst_get, + Field_ae_fld_ls_v_Slot_inst_get, + Field_ae_fld_ls_uu_Slot_inst_get, + Field_ae_fld_ls_su_Slot_inst_get, + Field_ae_fld_ls_av_Slot_inst_get, + Field_ae_fld_ls_v1_Slot_inst_get, + Field_ae_fld_ls_v2_Slot_inst_get, + Field_ae_fld_cmpp_v0_Slot_inst_get, + Field_ae_fld_cmpp_v1_Slot_inst_get, + Field_ae_fld_cmpp_v_Slot_inst_get, + Field_ae_fld_uu_v_Slot_inst_get, + Field_ae_fld_uu_uu_Slot_inst_get, + Field_ae_fld_dr_to_ar_v0_Slot_inst_get, + Field_ae_fld_cmov_v_Slot_inst_get, + Field_ae_fld_cmov_v0_Slot_inst_get, + Field_ae_fld_pks_d_Slot_inst_get, + Field_ae_fld_pks_s_Slot_inst_get, + Field_ae_fld_shift_d_Slot_inst_get, + Field_ae_fld_shift_d0_Slot_inst_get, + Field_ae_fld_shift_sd_Slot_inst_get, + Field_ae_fld_dr_to_dr_v_Slot_inst_get, + Field_ae_fld_dr_to_dr_v0_Slot_inst_get, + Field_ae_fld_dr_to_dr_v1_Slot_inst_get, + Field_ae_fld_to_dr_v_Slot_inst_get, + Field_ae_fld_to_dr_v0_Slot_inst_get, + Field_fld_ae_immls64neg_Slot_inst_get, + Field_ae_fld_selimm_Slot_inst_get, + 0, + Field_fld_ar_to_dr_imm_Slot_inst_get, + Field_ae_fld_arth_v_Slot_inst_get, + Field_ae_fld_arth_v0_Slot_inst_get, + Field_ae_fld_arth_v1_Slot_inst_get, + Field_ae_fld_ar_to_dr_v_Slot_inst_get, + Field_fld_inst_23_12_Slot_inst_get, + Field_fld_inst_23_16_Slot_inst_get, + Field_fld_inst_7_7_Slot_inst_get, + Field_fld_inst_11_8_Slot_inst_get, + Field_fld_inst_13_8_Slot_inst_get, + Field_fld_inst_12_8_Slot_inst_get, + Field_fld_inst_9_8_Slot_inst_get, + Field_fld_inst_4_4_Slot_inst_get, + Field_fld_inst_5_4_Slot_inst_get, + Field_fld_inst_7_4_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_vr_Slot_inst_get, + Field_fld_ae_sem_cmov_bt_Slot_inst_get, + Field_fld_ae_sem_cmov_arr_Slot_inst_get, + Field_fld_vfpu2_sem_mov_vt_Slot_inst_get, + Field_fld_vfpu2_sem_mov_vr_Slot_inst_get, + Field_fld_vfpu2_sem_spfma_vt_Slot_inst_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_inst_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_inst_get, + Field_fld_vfpu2_sem_spmisc_brt_Slot_inst_get, + Field_fld_vfpu2_sem_spmisc_vs_Slot_inst_get, + Field_fld_vfpu2_sem_spmisc_vr_Slot_inst_get, + Field_fld_vfpu2_sem_mov_i_imm4_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_op1_Slot_inst_get, + Field_dfp_fld_op2_Slot_inst_get, + Field_dfp_fld_r_0_Slot_inst_get, + Field_dfp_fld_r_2_1_Slot_inst_get, + Field_dfp_fld_r_3_Slot_inst_get, + Field_dfp_fld_r_3_1_Slot_inst_get, + Field_dfp_fld_s_0_Slot_inst_get, + Field_dfp_fld_s_3_1_Slot_inst_get, + Field_dfp_fld_op2_0_Slot_inst_get, + Field_dfp_fld_op2_1_0_Slot_inst_get, + Field_dfp_fld_op2_2_Slot_inst_get, + Field_dfp_fld_op2_3_Slot_inst_get, + Field_dfp_fld_op2_3_2_Slot_inst_get, + Field_dfp_fld_op2_3_1_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Field_fld_sigmoid_q15_x_Slot_inst_get, + Field_fld_sigmoid_q15_y_Slot_inst_get, + Field_fld_inst_3_0_Slot_inst_get, + Field_fld_sigmoid_fp32_x_Slot_inst_get, + Field_fld_sigmoid_fp32_y_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_r_disp_Slot_inst_set, + Field_r_3_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_ae_fld_fhba4_Slot_inst_set, + Field_ae_fld_fhba4_2_Slot_inst_set, + Field_ae_fld_tp7_Slot_inst_set, + Field_ae_fld_osa32_Slot_inst_set, + Field_ae_fld_osa64_Slot_inst_set, + Field_ae_fld_imm2_Slot_inst_set, + Field_ae_fld_immls64_Slot_inst_set, + Field_ae_fld_immls64pos_Slot_inst_set, + Field_ae_fld_immls64half_Slot_inst_set, + Field_ae_fld_immls32_Slot_inst_set, + Field_ae_fld_immls16_Slot_inst_set, + 0, + Field_inst_15_12_Slot_inst_set, + Field_inst_11_8_Slot_inst_set, + Field_inst_7_4_Slot_inst_set, + Field_inst_12_Slot_inst_set, + Field_inst_7_Slot_inst_set, + Field_inst_5_4_Slot_inst_set, + Field_inst_7_6_Slot_inst_set, + Field_inst_19_17_Slot_inst_set, + Field_inst_19_18_Slot_inst_set, + Field_inst_9_8_Slot_inst_set, + Field_inst_4_Slot_inst_set, + Field_ae_fld_ls_v_Slot_inst_set, + Field_ae_fld_ls_uu_Slot_inst_set, + Field_ae_fld_ls_su_Slot_inst_set, + Field_ae_fld_ls_av_Slot_inst_set, + Field_ae_fld_ls_v1_Slot_inst_set, + Field_ae_fld_ls_v2_Slot_inst_set, + Field_ae_fld_cmpp_v0_Slot_inst_set, + Field_ae_fld_cmpp_v1_Slot_inst_set, + Field_ae_fld_cmpp_v_Slot_inst_set, + Field_ae_fld_uu_v_Slot_inst_set, + Field_ae_fld_uu_uu_Slot_inst_set, + Field_ae_fld_dr_to_ar_v0_Slot_inst_set, + Field_ae_fld_cmov_v_Slot_inst_set, + Field_ae_fld_cmov_v0_Slot_inst_set, + Field_ae_fld_pks_d_Slot_inst_set, + Field_ae_fld_pks_s_Slot_inst_set, + Field_ae_fld_shift_d_Slot_inst_set, + Field_ae_fld_shift_d0_Slot_inst_set, + Field_ae_fld_shift_sd_Slot_inst_set, + Field_ae_fld_dr_to_dr_v_Slot_inst_set, + Field_ae_fld_dr_to_dr_v0_Slot_inst_set, + Field_ae_fld_dr_to_dr_v1_Slot_inst_set, + Field_ae_fld_to_dr_v_Slot_inst_set, + Field_ae_fld_to_dr_v0_Slot_inst_set, + Field_fld_ae_immls64neg_Slot_inst_set, + Field_ae_fld_selimm_Slot_inst_set, + 0, + Field_fld_ar_to_dr_imm_Slot_inst_set, + Field_ae_fld_arth_v_Slot_inst_set, + Field_ae_fld_arth_v0_Slot_inst_set, + Field_ae_fld_arth_v1_Slot_inst_set, + Field_ae_fld_ar_to_dr_v_Slot_inst_set, + Field_fld_inst_23_12_Slot_inst_set, + Field_fld_inst_23_16_Slot_inst_set, + Field_fld_inst_7_7_Slot_inst_set, + Field_fld_inst_11_8_Slot_inst_set, + Field_fld_inst_13_8_Slot_inst_set, + Field_fld_inst_12_8_Slot_inst_set, + Field_fld_inst_9_8_Slot_inst_set, + Field_fld_inst_4_4_Slot_inst_set, + Field_fld_inst_5_4_Slot_inst_set, + Field_fld_inst_7_4_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_vr_Slot_inst_set, + Field_fld_ae_sem_cmov_bt_Slot_inst_set, + Field_fld_ae_sem_cmov_arr_Slot_inst_set, + Field_fld_vfpu2_sem_mov_vt_Slot_inst_set, + Field_fld_vfpu2_sem_mov_vr_Slot_inst_set, + Field_fld_vfpu2_sem_spfma_vt_Slot_inst_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_inst_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_inst_set, + Field_fld_vfpu2_sem_spmisc_brt_Slot_inst_set, + Field_fld_vfpu2_sem_spmisc_vs_Slot_inst_set, + Field_fld_vfpu2_sem_spmisc_vr_Slot_inst_set, + Field_fld_vfpu2_sem_mov_i_imm4_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_op1_Slot_inst_set, + Field_dfp_fld_op2_Slot_inst_set, + Field_dfp_fld_r_0_Slot_inst_set, + Field_dfp_fld_r_2_1_Slot_inst_set, + Field_dfp_fld_r_3_Slot_inst_set, + Field_dfp_fld_r_3_1_Slot_inst_set, + Field_dfp_fld_s_0_Slot_inst_set, + Field_dfp_fld_s_3_1_Slot_inst_set, + Field_dfp_fld_op2_0_Slot_inst_set, + Field_dfp_fld_op2_1_0_Slot_inst_set, + Field_dfp_fld_op2_2_Slot_inst_set, + Field_dfp_fld_op2_3_Slot_inst_set, + Field_dfp_fld_op2_3_2_Slot_inst_set, + Field_dfp_fld_op2_3_1_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Field_fld_sigmoid_q15_x_Slot_inst_set, + Field_fld_sigmoid_q15_y_Slot_inst_set, + Field_fld_inst_3_0_Slot_inst_set, + Field_fld_sigmoid_fp32_x_Slot_inst_set, + Field_fld_sigmoid_fp32_y_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16a_get, + Field_dfp_fld_r_2_1_Slot_inst16a_get, + Field_dfp_fld_r_3_Slot_inst16a_get, + Field_dfp_fld_r_3_1_Slot_inst16a_get, + Field_dfp_fld_s_0_Slot_inst16a_get, + Field_dfp_fld_s_3_1_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16a_set, + Field_dfp_fld_r_2_1_Slot_inst16a_set, + Field_dfp_fld_r_3_Slot_inst16a_set, + Field_dfp_fld_r_3_1_Slot_inst16a_set, + Field_dfp_fld_s_0_Slot_inst16a_set, + Field_dfp_fld_s_3_1_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_get, + Field_ae_fld_inst16b_15_13_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16b_get, + Field_dfp_fld_r_2_1_Slot_inst16b_get, + Field_dfp_fld_r_3_Slot_inst16b_get, + Field_dfp_fld_r_3_1_Slot_inst16b_get, + Field_dfp_fld_s_0_Slot_inst16b_get, + Field_dfp_fld_s_3_1_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_set, + Field_ae_fld_inst16b_15_13_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16b_set, + Field_dfp_fld_r_2_1_Slot_inst16b_set, + Field_dfp_fld_r_3_Slot_inst16b_set, + Field_dfp_fld_r_3_1_Slot_inst16b_set, + Field_dfp_fld_s_0_Slot_inst16b_set, + Field_dfp_fld_s_3_1_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot3_get_field_fns[] = { + Field_t_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot3_get, + 0, + 0, + Field_t4_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_tp7_Slot_ae_slot3_get, + Field_ae_fld_osa32_Slot_ae_slot3_get, + Field_ae_fld_osa64_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_osa16_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_cmov_v_Slot_ae_slot3_get, + Field_ae_fld_cmov_v0_Slot_ae_slot3_get, + 0, + 0, + Field_ae_fld_shift_d_Slot_ae_slot3_get, + Field_ae_fld_shift_d0_Slot_ae_slot3_get, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot3_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot3_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot3_get, + Field_ae_fld_to_dr_v_Slot_ae_slot3_get, + Field_ae_fld_to_dr_v0_Slot_ae_slot3_get, + 0, + Field_ae_fld_selimm_Slot_ae_slot3_get, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot3_get, + Field_ae_fld_arth_v_Slot_ae_slot3_get, + Field_ae_fld_arth_v0_Slot_ae_slot3_get, + Field_ae_fld_arth_v1_Slot_ae_slot3_get, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_0_Slot_ae_slot3_get, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_get, + Field_fld_ae_slot3_3_0_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_slot3_1_0_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_8_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d1_Slot_ae_slot3_get, + Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae_slot3_get, + Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_12_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot3_get, + 0, + Field_fld_ae_slot3_11_4_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_acc_ep_Slot_ae_slot3_get, + Field_fld_ae_slot3_20_14_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_get, + Field_fld_ae_slot3_20_16_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get, + Field_fld_ae_slot3_11_11_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get, + 0, + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get, + 0, + 0, + 0, + Field_fld_ae_slot3_20_10_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_0_0_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_13_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot3_get, + 0, + Field_fld_ae_slot3_20_15_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot3_set_field_fns[] = { + Field_t_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot3_set, + 0, + 0, + Field_t4_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_tp7_Slot_ae_slot3_set, + Field_ae_fld_osa32_Slot_ae_slot3_set, + Field_ae_fld_osa64_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_osa16_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_cmov_v_Slot_ae_slot3_set, + Field_ae_fld_cmov_v0_Slot_ae_slot3_set, + 0, + 0, + Field_ae_fld_shift_d_Slot_ae_slot3_set, + Field_ae_fld_shift_d0_Slot_ae_slot3_set, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot3_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot3_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot3_set, + Field_ae_fld_to_dr_v_Slot_ae_slot3_set, + Field_ae_fld_to_dr_v0_Slot_ae_slot3_set, + 0, + Field_ae_fld_selimm_Slot_ae_slot3_set, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot3_set, + Field_ae_fld_arth_v_Slot_ae_slot3_set, + Field_ae_fld_arth_v0_Slot_ae_slot3_set, + Field_ae_fld_arth_v1_Slot_ae_slot3_set, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_0_Slot_ae_slot3_set, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_set, + Field_fld_ae_slot3_3_0_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_slot3_1_0_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_8_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d1_Slot_ae_slot3_set, + Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae_slot3_set, + Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_12_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot3_set, + 0, + Field_fld_ae_slot3_11_4_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_acc_ep_Slot_ae_slot3_set, + Field_fld_ae_slot3_20_14_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_set, + Field_fld_ae_slot3_20_16_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set, + Field_fld_ae_slot3_11_11_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set, + 0, + Field_fld_ae_slot3_7_4_Slot_ae_slot3_set, + 0, + 0, + 0, + Field_fld_ae_slot3_20_10_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_0_0_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_13_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_slot3_13_12_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot3_set, + 0, + Field_fld_ae_slot3_20_15_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_imm2_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_pks_d_Slot_ae_slot2_get, + Field_ae_fld_pks_s_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot2_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot2_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot2_get, + Field_ae_fld_to_dr_v_Slot_ae_slot2_get, + Field_ae_fld_to_dr_v0_Slot_ae_slot2_get, + 0, + 0, + Field_ae_fld_selimm_n_Slot_ae_slot2_get, + Field_fld_ar_to_dr_imm_Slot_ae_slot2_get, + Field_ae_fld_arth_v_Slot_ae_slot2_get, + Field_ae_fld_arth_v0_Slot_ae_slot2_get, + Field_ae_fld_arth_v1_Slot_ae_slot2_get, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_20_0_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x4_d0_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x4_q0_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_20_12_Slot_ae_slot2_get, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot2_get, + Field_fld_ae_slot2_7_0_Slot_ae_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_10_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x2_s1_acc_ep_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_14_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get, + 0, + Field_fld_ae_slot2_20_8_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_slot2_7_4_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_3_2_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot2_get, + 0, + Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_mov_i_imm4_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spmisc_vt_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spmisc_vsm_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_18_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spmisc_vtm_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_13_Slot_ae_slot2_get, + 0, + Field_fld_ae_slot2_20_15_Slot_ae_slot2_get, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_4_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_imm2_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_pks_d_Slot_ae_slot2_set, + Field_ae_fld_pks_s_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot2_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot2_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot2_set, + Field_ae_fld_to_dr_v_Slot_ae_slot2_set, + Field_ae_fld_to_dr_v0_Slot_ae_slot2_set, + 0, + 0, + Field_ae_fld_selimm_n_Slot_ae_slot2_set, + Field_fld_ar_to_dr_imm_Slot_ae_slot2_set, + Field_ae_fld_arth_v_Slot_ae_slot2_set, + Field_ae_fld_arth_v0_Slot_ae_slot2_set, + Field_ae_fld_arth_v1_Slot_ae_slot2_set, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_20_0_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x4_d0_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x4_q0_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_20_12_Slot_ae_slot2_set, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot2_set, + Field_fld_ae_slot2_7_0_Slot_ae_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_10_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x2_s1_acc_ep_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_14_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_set, + 0, + Field_fld_ae_slot2_20_8_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_slot2_7_4_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_3_2_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot2_set, + 0, + Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_mov_i_imm4_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spmisc_vt_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spmisc_vsm_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_18_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spmisc_vtm_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_13_Slot_ae_slot2_set, + 0, + Field_fld_ae_slot2_20_15_Slot_ae_slot2_set, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_4_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot1_get_field_fns[] = { + Field_t_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_get, + Field_s_Slot_ae_slot1_get, + Field_imm12b_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_get, + Field_r_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_get, + Field_sal_Slot_ae_slot1_get, + Field_sargt_Slot_ae_slot1_get, + 0, + Field_sas_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae_slot1_get, + Field_ae_fld_immls64pos_Slot_ae_slot1_get, + Field_ae_fld_immls64half_Slot_ae_slot1_get, + Field_ae_fld_immls32_Slot_ae_slot1_get, + Field_ae_fld_immls16_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_immls64neg_Slot_ae_slot1_get, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_12_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_16_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_17_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_0_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_13_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_4_Slot_ae_slot1_get, + 0, + 0, + Field_fld_ae_slot1_19_9_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get, + 0, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_fld_ae_slot1_19_8_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_7_6_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae_slot1_get, + Field_dfp_fld_r_3_Slot_ae_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae_slot1_get, + Field_dfp_fld_s_0_Slot_ae_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot1_set_field_fns[] = { + Field_t_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_set, + Field_s_Slot_ae_slot1_set, + Field_imm12b_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_set, + Field_r_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_set, + Field_sal_Slot_ae_slot1_set, + Field_sargt_Slot_ae_slot1_set, + 0, + Field_sas_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae_slot1_set, + Field_ae_fld_immls64pos_Slot_ae_slot1_set, + Field_ae_fld_immls64half_Slot_ae_slot1_set, + Field_ae_fld_immls32_Slot_ae_slot1_set, + Field_ae_fld_immls16_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_immls64neg_Slot_ae_slot1_set, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_12_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_16_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_17_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_0_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_13_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_4_Slot_ae_slot1_set, + 0, + 0, + Field_fld_ae_slot1_19_9_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set, + 0, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_fld_ae_slot1_19_8_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_7_6_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_7_7_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae_slot1_set, + Field_dfp_fld_r_3_Slot_ae_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae_slot1_set, + Field_dfp_fld_s_0_Slot_ae_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot0_get_field_fns[] = { + Field_t_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_get, + Field_s_Slot_ae_slot0_get, + Field_imm12b_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_sal_Slot_ae_slot0_get, + Field_sargt_Slot_ae_slot0_get, + 0, + Field_sas_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_get, + 0, + Field_r2_Slot_ae_slot0_get, + Field_t4_Slot_ae_slot0_get, + Field_s4_Slot_ae_slot0_get, + Field_r4_Slot_ae_slot0_get, + 0, + Field_s8_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae_slot0_get, + 0, + 0, + Field_ae_fld_osa32_Slot_ae_slot0_get, + Field_ae_fld_osa64_Slot_ae_slot0_get, + Field_ae_fld_imm2_Slot_ae_slot0_get, + Field_ae_fld_immls64_Slot_ae_slot0_get, + Field_ae_fld_immls64pos_Slot_ae_slot0_get, + Field_ae_fld_immls64half_Slot_ae_slot0_get, + Field_ae_fld_immls32_Slot_ae_slot0_get, + Field_ae_fld_immls16_Slot_ae_slot0_get, + Field_ae_fld_osa16_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae_slot0_get, + Field_ae_fld_ls_uu_Slot_ae_slot0_get, + Field_ae_fld_ls_su_Slot_ae_slot0_get, + Field_ae_fld_ls_av_Slot_ae_slot0_get, + Field_ae_fld_ls_v1_Slot_ae_slot0_get, + Field_ae_fld_ls_v2_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae_slot0_get, + Field_ae_fld_uu_uu_Slot_ae_slot0_get, + Field_ae_fld_dr_to_ar_v0_Slot_ae_slot0_get, + Field_ae_fld_cmov_v_Slot_ae_slot0_get, + Field_ae_fld_cmov_v0_Slot_ae_slot0_get, + Field_ae_fld_pks_d_Slot_ae_slot0_get, + Field_ae_fld_pks_s_Slot_ae_slot0_get, + Field_ae_fld_shift_d_Slot_ae_slot0_get, + Field_ae_fld_shift_d0_Slot_ae_slot0_get, + Field_ae_fld_shift_sd_Slot_ae_slot0_get, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot0_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot0_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot0_get, + Field_ae_fld_to_dr_v_Slot_ae_slot0_get, + Field_ae_fld_to_dr_v0_Slot_ae_slot0_get, + Field_fld_ae_immls64neg_Slot_ae_slot0_get, + Field_ae_fld_selimm_Slot_ae_slot0_get, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot0_get, + Field_ae_fld_arth_v_Slot_ae_slot0_get, + Field_ae_fld_arth_v0_Slot_ae_slot0_get, + Field_ae_fld_arth_v1_Slot_ae_slot0_get, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_0_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_15_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_20_13_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_fld_ae_slot0_20_4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_0_0_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_20_12_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_8_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_11_0_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_fld_ae_slot0_8_4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_5_2_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_20_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_sem_cmov_bt_Slot_ae_slot0_get, + Field_fld_ae_sem_cmov_arr_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spmisc_brt_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot0_get, + 0, + Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_arr_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae_slot0_get, + Field_dfp_fld_r_3_Slot_ae_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae_slot0_get, + Field_dfp_fld_s_0_Slot_ae_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot0_set_field_fns[] = { + Field_t_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_set, + Field_s_Slot_ae_slot0_set, + Field_imm12b_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_sal_Slot_ae_slot0_set, + Field_sargt_Slot_ae_slot0_set, + 0, + Field_sas_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_set, + 0, + Field_r2_Slot_ae_slot0_set, + Field_t4_Slot_ae_slot0_set, + Field_s4_Slot_ae_slot0_set, + Field_r4_Slot_ae_slot0_set, + 0, + Field_s8_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae_slot0_set, + 0, + 0, + Field_ae_fld_osa32_Slot_ae_slot0_set, + Field_ae_fld_osa64_Slot_ae_slot0_set, + Field_ae_fld_imm2_Slot_ae_slot0_set, + Field_ae_fld_immls64_Slot_ae_slot0_set, + Field_ae_fld_immls64pos_Slot_ae_slot0_set, + Field_ae_fld_immls64half_Slot_ae_slot0_set, + Field_ae_fld_immls32_Slot_ae_slot0_set, + Field_ae_fld_immls16_Slot_ae_slot0_set, + Field_ae_fld_osa16_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae_slot0_set, + Field_ae_fld_ls_uu_Slot_ae_slot0_set, + Field_ae_fld_ls_su_Slot_ae_slot0_set, + Field_ae_fld_ls_av_Slot_ae_slot0_set, + Field_ae_fld_ls_v1_Slot_ae_slot0_set, + Field_ae_fld_ls_v2_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae_slot0_set, + Field_ae_fld_uu_uu_Slot_ae_slot0_set, + Field_ae_fld_dr_to_ar_v0_Slot_ae_slot0_set, + Field_ae_fld_cmov_v_Slot_ae_slot0_set, + Field_ae_fld_cmov_v0_Slot_ae_slot0_set, + Field_ae_fld_pks_d_Slot_ae_slot0_set, + Field_ae_fld_pks_s_Slot_ae_slot0_set, + Field_ae_fld_shift_d_Slot_ae_slot0_set, + Field_ae_fld_shift_d0_Slot_ae_slot0_set, + Field_ae_fld_shift_sd_Slot_ae_slot0_set, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot0_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot0_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot0_set, + Field_ae_fld_to_dr_v_Slot_ae_slot0_set, + Field_ae_fld_to_dr_v0_Slot_ae_slot0_set, + Field_fld_ae_immls64neg_Slot_ae_slot0_set, + Field_ae_fld_selimm_Slot_ae_slot0_set, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot0_set, + Field_ae_fld_arth_v_Slot_ae_slot0_set, + Field_ae_fld_arth_v0_Slot_ae_slot0_set, + Field_ae_fld_arth_v1_Slot_ae_slot0_set, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_0_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_15_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_20_13_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_fld_ae_slot0_20_4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_0_0_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_20_12_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_8_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_11_0_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_4_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_fld_ae_slot0_8_4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_5_2_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_7_7_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_20_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_sem_cmov_bt_Slot_ae_slot0_set, + Field_fld_ae_sem_cmov_arr_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spmisc_brt_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot0_set, + 0, + Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_arr_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae_slot0_set, + Field_dfp_fld_r_3_Slot_ae_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae_slot0_set, + Field_dfp_fld_s_0_Slot_ae_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae2_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x4_d0_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x4_q0_Slot_ae2_slot2_get, + 0, + Field_fld_ae_sem_mul_x4_q1_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x4_d2_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get, + 0, + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get, + 0, + Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae2_slot2_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae2_slot2_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae2_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x4_d0_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x4_q0_Slot_ae2_slot2_set, + 0, + Field_fld_ae_sem_mul_x4_q1_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x4_d2_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set, + 0, + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_set, + 0, + Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae2_slot2_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae2_slot2_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot1_get_field_fns[] = { + Field_t_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_get, + Field_s_Slot_ae2_slot1_get, + Field_imm12b_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_get, + Field_r_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_get, + Field_sal_Slot_ae2_slot1_get, + Field_sargt_Slot_ae2_slot1_get, + 0, + Field_sas_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae2_slot1_get, + Field_ae_fld_immls64pos_Slot_ae2_slot1_get, + Field_ae_fld_immls64half_Slot_ae2_slot1_get, + Field_ae_fld_immls32_Slot_ae2_slot1_get, + Field_ae_fld_immls16_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae2_slot1_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot1_get, + 0, + Field_ae_fld_to_dr_v_Slot_ae2_slot1_get, + Field_ae_fld_to_dr_v0_Slot_ae2_slot1_get, + Field_fld_ae_immls64neg_Slot_ae2_slot1_get, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get, + 0, + 0, + Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae2_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae2_slot1_get, + Field_dfp_fld_r_3_Slot_ae2_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae2_slot1_get, + Field_dfp_fld_s_0_Slot_ae2_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot1_set_field_fns[] = { + Field_t_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_set, + Field_s_Slot_ae2_slot1_set, + Field_imm12b_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_set, + Field_r_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_set, + Field_sal_Slot_ae2_slot1_set, + Field_sargt_Slot_ae2_slot1_set, + 0, + Field_sas_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae2_slot1_set, + Field_ae_fld_immls64pos_Slot_ae2_slot1_set, + Field_ae_fld_immls64half_Slot_ae2_slot1_set, + Field_ae_fld_immls32_Slot_ae2_slot1_set, + Field_ae_fld_immls16_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae2_slot1_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot1_set, + 0, + Field_ae_fld_to_dr_v_Slot_ae2_slot1_set, + Field_ae_fld_to_dr_v0_Slot_ae2_slot1_set, + Field_fld_ae_immls64neg_Slot_ae2_slot1_set, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set, + 0, + 0, + Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae2_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae2_slot1_set, + Field_dfp_fld_r_3_Slot_ae2_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae2_slot1_set, + Field_dfp_fld_s_0_Slot_ae2_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot0_get_field_fns[] = { + Field_t_Slot_ae2_slot0_get, + 0, + Field_bbi_Slot_ae2_slot0_get, + 0, + Field_imm8_Slot_ae2_slot0_get, + Field_s_Slot_ae2_slot0_get, + Field_imm12b_Slot_ae2_slot0_get, + Field_imm16_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot0_get, + Field_r_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_get, + Field_sal_Slot_ae2_slot0_get, + Field_sargt_Slot_ae2_slot0_get, + 0, + Field_sas_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_get, + 0, + Field_r2_Slot_ae2_slot0_get, + Field_t4_Slot_ae2_slot0_get, + Field_s4_Slot_ae2_slot0_get, + Field_r4_Slot_ae2_slot0_get, + 0, + Field_s8_Slot_ae2_slot0_get, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_ae_fld_osa32_Slot_ae2_slot0_get, + Field_ae_fld_osa64_Slot_ae2_slot0_get, + 0, + Field_ae_fld_immls64_Slot_ae2_slot0_get, + Field_ae_fld_immls64pos_Slot_ae2_slot0_get, + Field_ae_fld_immls64half_Slot_ae2_slot0_get, + Field_ae_fld_immls32_Slot_ae2_slot0_get, + Field_ae_fld_immls16_Slot_ae2_slot0_get, + Field_ae_fld_osa16_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae2_slot0_get, + Field_ae_fld_ls_uu_Slot_ae2_slot0_get, + Field_ae_fld_ls_su_Slot_ae2_slot0_get, + Field_ae_fld_ls_av_Slot_ae2_slot0_get, + Field_ae_fld_ls_v1_Slot_ae2_slot0_get, + Field_ae_fld_ls_v2_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae2_slot0_get, + Field_ae_fld_uu_uu_Slot_ae2_slot0_get, + Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot0_get, + Field_ae_fld_cmov_v_Slot_ae2_slot0_get, + Field_ae_fld_cmov_v0_Slot_ae2_slot0_get, + 0, + 0, + Field_ae_fld_shift_d_Slot_ae2_slot0_get, + Field_ae_fld_shift_d0_Slot_ae2_slot0_get, + Field_ae_fld_shift_sd_Slot_ae2_slot0_get, + Field_ae_fld_dr_to_dr_v_Slot_ae2_slot0_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot0_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae2_slot0_get, + Field_ae_fld_to_dr_v_Slot_ae2_slot0_get, + Field_ae_fld_to_dr_v0_Slot_ae2_slot0_get, + Field_fld_ae_immls64neg_Slot_ae2_slot0_get, + Field_ae_fld_selimm_Slot_ae2_slot0_get, + 0, + Field_fld_ar_to_dr_imm_Slot_ae2_slot0_get, + Field_ae_fld_arth_v_Slot_ae2_slot0_get, + Field_ae_fld_arth_v0_Slot_ae2_slot0_get, + Field_ae_fld_arth_v1_Slot_ae2_slot0_get, + Field_ae_fld_ar_to_dr_v_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get, + 0, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get, + 0, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get, + 0, + Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get, + 0, + 0, + Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get, + 0, + 0, + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_get, + 0, + 0, + Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get, + 0, + 0, + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae2_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae2_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae2_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae2_slot0_get, + Field_dfp_fld_r_3_Slot_ae2_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae2_slot0_get, + Field_dfp_fld_s_0_Slot_ae2_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot0_set_field_fns[] = { + Field_t_Slot_ae2_slot0_set, + 0, + Field_bbi_Slot_ae2_slot0_set, + 0, + Field_imm8_Slot_ae2_slot0_set, + Field_s_Slot_ae2_slot0_set, + Field_imm12b_Slot_ae2_slot0_set, + Field_imm16_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot0_set, + Field_r_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_set, + Field_sal_Slot_ae2_slot0_set, + Field_sargt_Slot_ae2_slot0_set, + 0, + Field_sas_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_set, + 0, + Field_r2_Slot_ae2_slot0_set, + Field_t4_Slot_ae2_slot0_set, + Field_s4_Slot_ae2_slot0_set, + Field_r4_Slot_ae2_slot0_set, + 0, + Field_s8_Slot_ae2_slot0_set, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_ae_fld_osa32_Slot_ae2_slot0_set, + Field_ae_fld_osa64_Slot_ae2_slot0_set, + 0, + Field_ae_fld_immls64_Slot_ae2_slot0_set, + Field_ae_fld_immls64pos_Slot_ae2_slot0_set, + Field_ae_fld_immls64half_Slot_ae2_slot0_set, + Field_ae_fld_immls32_Slot_ae2_slot0_set, + Field_ae_fld_immls16_Slot_ae2_slot0_set, + Field_ae_fld_osa16_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae2_slot0_set, + Field_ae_fld_ls_uu_Slot_ae2_slot0_set, + Field_ae_fld_ls_su_Slot_ae2_slot0_set, + Field_ae_fld_ls_av_Slot_ae2_slot0_set, + Field_ae_fld_ls_v1_Slot_ae2_slot0_set, + Field_ae_fld_ls_v2_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae2_slot0_set, + Field_ae_fld_uu_uu_Slot_ae2_slot0_set, + Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot0_set, + Field_ae_fld_cmov_v_Slot_ae2_slot0_set, + Field_ae_fld_cmov_v0_Slot_ae2_slot0_set, + 0, + 0, + Field_ae_fld_shift_d_Slot_ae2_slot0_set, + Field_ae_fld_shift_d0_Slot_ae2_slot0_set, + Field_ae_fld_shift_sd_Slot_ae2_slot0_set, + Field_ae_fld_dr_to_dr_v_Slot_ae2_slot0_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot0_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae2_slot0_set, + Field_ae_fld_to_dr_v_Slot_ae2_slot0_set, + Field_ae_fld_to_dr_v0_Slot_ae2_slot0_set, + Field_fld_ae_immls64neg_Slot_ae2_slot0_set, + Field_ae_fld_selimm_Slot_ae2_slot0_set, + 0, + Field_fld_ar_to_dr_imm_Slot_ae2_slot0_set, + Field_ae_fld_arth_v_Slot_ae2_slot0_set, + Field_ae_fld_arth_v0_Slot_ae2_slot0_set, + Field_ae_fld_arth_v1_Slot_ae2_slot0_set, + Field_ae_fld_ar_to_dr_v_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set, + 0, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_set, + 0, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_set, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set, + 0, + Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set, + 0, + 0, + Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_set, + 0, + 0, + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_set, + 0, + 0, + Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set, + 0, + 0, + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae2_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae2_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae2_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae2_slot0_set, + Field_dfp_fld_r_3_Slot_ae2_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae2_slot0_set, + Field_dfp_fld_s_0_Slot_ae2_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot1_get_field_fns[] = { + Field_t_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_get, + Field_s_Slot_ae3_slot1_get, + Field_imm12b_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_get, + Field_r_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_get, + Field_sal_Slot_ae3_slot1_get, + Field_sargt_Slot_ae3_slot1_get, + 0, + Field_sas_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae3_slot1_get, + Field_ae_fld_immls64pos_Slot_ae3_slot1_get, + Field_ae_fld_immls64half_Slot_ae3_slot1_get, + Field_ae_fld_immls32_Slot_ae3_slot1_get, + Field_ae_fld_immls16_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae3_slot1_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae3_slot1_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae3_slot1_get, + Field_ae_fld_to_dr_v_Slot_ae3_slot1_get, + Field_ae_fld_to_dr_v0_Slot_ae3_slot1_get, + Field_fld_ae_immls64neg_Slot_ae3_slot1_get, + Field_ae_fld_selimm_Slot_ae3_slot1_get, + 0, + Field_fld_ar_to_dr_imm_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot1_get, + 0, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get, + Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot1_get, + Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae3_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae3_slot1_get, + Field_dfp_fld_r_3_Slot_ae3_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae3_slot1_get, + Field_dfp_fld_s_0_Slot_ae3_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot1_set_field_fns[] = { + Field_t_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_set, + Field_s_Slot_ae3_slot1_set, + Field_imm12b_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_set, + Field_r_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_set, + Field_sal_Slot_ae3_slot1_set, + Field_sargt_Slot_ae3_slot1_set, + 0, + Field_sas_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae3_slot1_set, + Field_ae_fld_immls64pos_Slot_ae3_slot1_set, + Field_ae_fld_immls64half_Slot_ae3_slot1_set, + Field_ae_fld_immls32_Slot_ae3_slot1_set, + Field_ae_fld_immls16_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae3_slot1_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae3_slot1_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae3_slot1_set, + Field_ae_fld_to_dr_v_Slot_ae3_slot1_set, + Field_ae_fld_to_dr_v0_Slot_ae3_slot1_set, + Field_fld_ae_immls64neg_Slot_ae3_slot1_set, + Field_ae_fld_selimm_Slot_ae3_slot1_set, + 0, + Field_fld_ar_to_dr_imm_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot1_set, + 0, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set, + Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot1_set, + Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae3_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae3_slot1_set, + Field_dfp_fld_r_3_Slot_ae3_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae3_slot1_set, + Field_dfp_fld_s_0_Slot_ae3_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot0_get_field_fns[] = { + Field_t_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot0_get, + Field_s_Slot_ae3_slot0_get, + Field_imm12b_Slot_ae3_slot0_get, + Field_imm16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot0_get, + Field_r_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_get, + Field_sal_Slot_ae3_slot0_get, + Field_sargt_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_get, + 0, + Field_r2_Slot_ae3_slot0_get, + Field_t4_Slot_ae3_slot0_get, + 0, + Field_r4_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae3_slot0_get, + Field_ae_fld_fhba4_2_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae3_slot0_get, + Field_ae_fld_immls64pos_Slot_ae3_slot0_get, + Field_ae_fld_immls64half_Slot_ae3_slot0_get, + Field_ae_fld_immls32_Slot_ae3_slot0_get, + Field_ae_fld_immls16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae3_slot0_get, + Field_ae_fld_ls_uu_Slot_ae3_slot0_get, + Field_ae_fld_ls_su_Slot_ae3_slot0_get, + Field_ae_fld_ls_av_Slot_ae3_slot0_get, + Field_ae_fld_ls_v1_Slot_ae3_slot0_get, + Field_ae_fld_ls_v2_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae3_slot0_get, + Field_ae_fld_uu_uu_Slot_ae3_slot0_get, + Field_ae_fld_dr_to_ar_v0_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_to_dr_v_Slot_ae3_slot0_get, + Field_ae_fld_to_dr_v0_Slot_ae3_slot0_get, + Field_fld_ae_immls64neg_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot0_get, + Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get, + 0, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae3_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae3_slot0_get, + Field_dfp_fld_r_3_Slot_ae3_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae3_slot0_get, + Field_dfp_fld_s_0_Slot_ae3_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot0_set_field_fns[] = { + Field_t_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot0_set, + Field_s_Slot_ae3_slot0_set, + Field_imm12b_Slot_ae3_slot0_set, + Field_imm16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot0_set, + Field_r_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_set, + Field_sal_Slot_ae3_slot0_set, + Field_sargt_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_set, + 0, + Field_r2_Slot_ae3_slot0_set, + Field_t4_Slot_ae3_slot0_set, + 0, + Field_r4_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae3_slot0_set, + Field_ae_fld_fhba4_2_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae3_slot0_set, + Field_ae_fld_immls64pos_Slot_ae3_slot0_set, + Field_ae_fld_immls64half_Slot_ae3_slot0_set, + Field_ae_fld_immls32_Slot_ae3_slot0_set, + Field_ae_fld_immls16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae3_slot0_set, + Field_ae_fld_ls_uu_Slot_ae3_slot0_set, + Field_ae_fld_ls_su_Slot_ae3_slot0_set, + Field_ae_fld_ls_av_Slot_ae3_slot0_set, + Field_ae_fld_ls_v1_Slot_ae3_slot0_set, + Field_ae_fld_ls_v2_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae3_slot0_set, + Field_ae_fld_uu_uu_Slot_ae3_slot0_set, + Field_ae_fld_dr_to_ar_v0_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_to_dr_v_Slot_ae3_slot0_set, + Field_ae_fld_to_dr_v0_Slot_ae3_slot0_set, + Field_fld_ae_immls64neg_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot0_set, + Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set, + 0, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae3_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae3_slot0_set, + Field_dfp_fld_r_3_Slot_ae3_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae3_slot0_set, + Field_dfp_fld_s_0_Slot_ae3_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot1_get_field_fns[] = { + Field_t_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_get, + 0, + Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae4_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae4_slot1_get, + Field_dfp_fld_r_3_Slot_ae4_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae4_slot1_get, + Field_dfp_fld_s_0_Slot_ae4_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot1_set_field_fns[] = { + Field_t_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_set, + 0, + Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae4_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae4_slot1_set, + Field_dfp_fld_r_3_Slot_ae4_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae4_slot1_set, + Field_dfp_fld_s_0_Slot_ae4_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot0_get_field_fns[] = { + Field_t_Slot_ae4_slot0_get, + 0, + Field_bbi_Slot_ae4_slot0_get, + 0, + 0, + Field_s_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get, + 0, + 0, + Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_get, + 0, + 0, + Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae4_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae4_slot0_get, + Field_dfp_fld_r_3_Slot_ae4_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae4_slot0_get, + Field_dfp_fld_s_0_Slot_ae4_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot0_set_field_fns[] = { + Field_t_Slot_ae4_slot0_set, + 0, + Field_bbi_Slot_ae4_slot0_set, + 0, + 0, + Field_s_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set, + 0, + 0, + Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_set, + 0, + 0, + Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae4_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae4_slot0_set, + Field_dfp_fld_r_3_Slot_ae4_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae4_slot0_set, + Field_dfp_fld_s_0_Slot_ae4_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae5_slot2_get, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae5_slot2_get, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae5_slot2_get, + Field_fld_ae_sem_mul_x4_d0_Slot_ae5_slot2_get, + Field_fld_ae_sem_mul_x4_q0_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae5_slot2_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae5_slot2_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae5_slot2_set, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae5_slot2_set, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae5_slot2_set, + Field_fld_ae_sem_mul_x4_d0_Slot_ae5_slot2_set, + Field_fld_ae_sem_mul_x4_q0_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae5_slot2_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae5_slot2_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot0_get_field_fns[] = { + Field_t_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae5_slot0_get, + Field_s_Slot_ae5_slot0_get, + Field_imm12b_Slot_ae5_slot0_get, + Field_imm16_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae5_slot0_get, + Field_r_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_get, + Field_sal_Slot_ae5_slot0_get, + Field_sargt_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae5_slot0_get, + Field_ae_fld_immls64pos_Slot_ae5_slot0_get, + Field_ae_fld_immls64half_Slot_ae5_slot0_get, + Field_ae_fld_immls32_Slot_ae5_slot0_get, + Field_ae_fld_immls16_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae5_slot0_get, + Field_ae_fld_ls_uu_Slot_ae5_slot0_get, + Field_ae_fld_ls_su_Slot_ae5_slot0_get, + Field_ae_fld_ls_av_Slot_ae5_slot0_get, + Field_ae_fld_ls_v1_Slot_ae5_slot0_get, + Field_ae_fld_ls_v2_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae5_slot0_get, + Field_ae_fld_uu_uu_Slot_ae5_slot0_get, + Field_ae_fld_dr_to_ar_v0_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_to_dr_v_Slot_ae5_slot0_get, + Field_ae_fld_to_dr_v0_Slot_ae5_slot0_get, + Field_fld_ae_immls64neg_Slot_ae5_slot0_get, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae5_slot0_get, + Field_ae_fld_arth_v_Slot_ae5_slot0_get, + Field_ae_fld_arth_v0_Slot_ae5_slot0_get, + Field_ae_fld_arth_v1_Slot_ae5_slot0_get, + Field_ae_fld_ar_to_dr_v_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_get, + 0, + 0, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get, + 0, + Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae5_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae5_slot0_get, + Field_dfp_fld_r_3_Slot_ae5_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae5_slot0_get, + Field_dfp_fld_s_0_Slot_ae5_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot0_set_field_fns[] = { + Field_t_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae5_slot0_set, + Field_s_Slot_ae5_slot0_set, + Field_imm12b_Slot_ae5_slot0_set, + Field_imm16_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae5_slot0_set, + Field_r_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_set, + Field_sal_Slot_ae5_slot0_set, + Field_sargt_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae5_slot0_set, + Field_ae_fld_immls64pos_Slot_ae5_slot0_set, + Field_ae_fld_immls64half_Slot_ae5_slot0_set, + Field_ae_fld_immls32_Slot_ae5_slot0_set, + Field_ae_fld_immls16_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae5_slot0_set, + Field_ae_fld_ls_uu_Slot_ae5_slot0_set, + Field_ae_fld_ls_su_Slot_ae5_slot0_set, + Field_ae_fld_ls_av_Slot_ae5_slot0_set, + Field_ae_fld_ls_v1_Slot_ae5_slot0_set, + Field_ae_fld_ls_v2_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae5_slot0_set, + Field_ae_fld_uu_uu_Slot_ae5_slot0_set, + Field_ae_fld_dr_to_ar_v0_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_to_dr_v_Slot_ae5_slot0_set, + Field_ae_fld_to_dr_v0_Slot_ae5_slot0_set, + Field_fld_ae_immls64neg_Slot_ae5_slot0_set, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae5_slot0_set, + Field_ae_fld_arth_v_Slot_ae5_slot0_set, + Field_ae_fld_arth_v0_Slot_ae5_slot0_set, + Field_ae_fld_arth_v1_Slot_ae5_slot0_set, + Field_ae_fld_ar_to_dr_v_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_set, + 0, + 0, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set, + 0, + Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae5_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae5_slot0_set, + Field_dfp_fld_r_3_Slot_ae5_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae5_slot0_set, + Field_dfp_fld_s_0_Slot_ae5_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_arth_v_Slot_ae6_slot3_get, + Field_ae_fld_arth_v0_Slot_ae6_slot3_get, + Field_ae_fld_arth_v1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_arth_v_Slot_ae6_slot3_set, + Field_ae_fld_arth_v0_Slot_ae6_slot3_set, + Field_ae_fld_arth_v1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_arth_v_Slot_ae6_slot2_get, + 0, + Field_ae_fld_arth_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae6_slot2_get, + Field_fld_ae_sem_mul_x4_d0_Slot_ae6_slot2_get, + Field_fld_ae_sem_mul_x4_q0_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_arth_v_Slot_ae6_slot2_set, + 0, + Field_ae_fld_arth_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae6_slot2_set, + Field_fld_ae_sem_mul_x4_d0_Slot_ae6_slot2_set, + Field_fld_ae_sem_mul_x4_q0_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot1_get_field_fns[] = { + Field_t_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae6_slot1_get, + Field_ae_fld_immls64pos_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae6_slot1_get, + Field_ae_fld_ls_uu_Slot_ae6_slot1_get, + 0, + Field_ae_fld_ls_av_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae6_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae6_slot1_get, + Field_dfp_fld_r_3_Slot_ae6_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae6_slot1_get, + Field_dfp_fld_s_0_Slot_ae6_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot1_set_field_fns[] = { + Field_t_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae6_slot1_set, + Field_ae_fld_immls64pos_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae6_slot1_set, + Field_ae_fld_ls_uu_Slot_ae6_slot1_set, + 0, + Field_ae_fld_ls_av_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae6_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae6_slot1_set, + Field_dfp_fld_r_3_Slot_ae6_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae6_slot1_set, + Field_dfp_fld_s_0_Slot_ae6_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot0_get_field_fns[] = { + Field_t_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae6_slot0_get, + Field_ae_fld_immls64pos_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae6_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot0_set_field_fns[] = { + Field_t_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae6_slot0_set, + Field_ae_fld_immls64pos_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae6_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae7_slot3_get, + Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d2_Slot_ae7_slot3_get, + Field_fld_ae_sem_mul_x2_s2_v1_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae7_slot3_set, + Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_set, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d2_Slot_ae7_slot3_set, + Field_fld_ae_sem_mul_x2_s2_v1_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae7_slot2_get, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae7_slot2_get, + Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae7_slot2_set, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_set, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae7_slot2_set, + Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot1_get_field_fns[] = { + Field_t_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae7_slot1_get, + Field_ae_fld_immls64pos_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae7_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot1_set_field_fns[] = { + Field_t_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae7_slot1_set, + Field_ae_fld_immls64pos_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae7_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot0_get_field_fns[] = { + Field_t_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae7_slot0_get, + Field_ae_fld_immls64pos_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae7_slot0_get, + Field_ae_fld_ls_uu_Slot_ae7_slot0_get, + 0, + Field_ae_fld_ls_av_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae7_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot0_set_field_fns[] = { + Field_t_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae7_slot0_set, + Field_ae_fld_immls64pos_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae7_slot0_set, + Field_ae_fld_ls_uu_Slot_ae7_slot0_set, + 0, + Field_ae_fld_ls_av_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae7_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "ae_slot3", "ae_format88", 3, + Slot_ae_format88_Format_ae_slot3_32_get, Slot_ae_format88_Format_ae_slot3_32_set, + Slot_ae_slot3_get_field_fns, Slot_ae_slot3_set_field_fns, + Slot_ae_slot3_decode, "nop" }, + { "ae_slot2", "ae_format88", 2, + Slot_ae_format88_Format_ae_slot2_28_get, Slot_ae_format88_Format_ae_slot2_28_set, + Slot_ae_slot2_get_field_fns, Slot_ae_slot2_set_field_fns, + Slot_ae_slot2_decode, "nop" }, + { "ae_slot1", "ae_format88", 1, + Slot_ae_format88_Format_ae_slot1_16_get, Slot_ae_format88_Format_ae_slot1_16_set, + Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, + Slot_ae_slot1_decode, "nop" }, + { "ae_slot0", "ae_format88", 0, + Slot_ae_format88_Format_ae_slot0_5_get, Slot_ae_format88_Format_ae_slot0_5_set, + Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, + Slot_ae_slot0_decode, "nop" }, + { "ae2_slot2", "ae_format88_2", 2, + Slot_ae_format88_2_Format_ae2_slot2_28_get, Slot_ae_format88_2_Format_ae2_slot2_28_set, + Slot_ae2_slot2_get_field_fns, Slot_ae2_slot2_set_field_fns, + Slot_ae2_slot2_decode, "nop" }, + { "ae2_slot1", "ae_format88_2", 1, + Slot_ae_format88_2_Format_ae2_slot1_16_get, Slot_ae_format88_2_Format_ae2_slot1_16_set, + Slot_ae2_slot1_get_field_fns, Slot_ae2_slot1_set_field_fns, + Slot_ae2_slot1_decode, "nop" }, + { "ae2_slot0", "ae_format88_2", 0, + Slot_ae_format88_2_Format_ae2_slot0_6_get, Slot_ae_format88_2_Format_ae2_slot0_6_set, + Slot_ae2_slot0_get_field_fns, Slot_ae2_slot0_set_field_fns, + Slot_ae2_slot0_decode, "nop" }, + { "ae3_slot1", "ae_format48", 1, + Slot_ae_format48_Format_ae3_slot1_16_get, Slot_ae_format48_Format_ae3_slot1_16_set, + Slot_ae3_slot1_get_field_fns, Slot_ae3_slot1_set_field_fns, + Slot_ae3_slot1_decode, "nop" }, + { "ae3_slot0", "ae_format48", 0, + Slot_ae_format48_Format_ae3_slot0_4_get, Slot_ae_format48_Format_ae3_slot0_4_set, + Slot_ae3_slot0_get_field_fns, Slot_ae3_slot0_set_field_fns, + Slot_ae3_slot0_decode, "nop" }, + { "ae4_slot1", "ae_format48_2", 1, + Slot_ae_format48_2_Format_ae4_slot1_16_get, Slot_ae_format48_2_Format_ae4_slot1_16_set, + Slot_ae4_slot1_get_field_fns, Slot_ae4_slot1_set_field_fns, + Slot_ae4_slot1_decode, "nop" }, + { "ae4_slot0", "ae_format48_2", 0, + Slot_ae_format48_2_Format_ae4_slot0_4_get, Slot_ae_format48_2_Format_ae4_slot0_4_set, + Slot_ae4_slot0_get_field_fns, Slot_ae4_slot0_set_field_fns, + Slot_ae4_slot0_decode, "nop" }, + { "ae5_slot2", "ae_format48_3", 2, + Slot_ae_format48_3_Format_ae5_slot2_16_get, Slot_ae_format48_3_Format_ae5_slot2_16_set, + Slot_ae5_slot2_get_field_fns, Slot_ae5_slot2_set_field_fns, + Slot_ae5_slot2_decode, "nop" }, + { "ae5_slot1", "ae_format48_3", 1, + Slot_ae_format48_3_Format_ae5_slot1_38_get, Slot_ae_format48_3_Format_ae5_slot1_38_set, + Slot_ae5_slot1_get_field_fns, Slot_ae5_slot1_set_field_fns, + Slot_ae5_slot1_decode, "nop" }, + { "ae5_slot0", "ae_format48_3", 0, + Slot_ae_format48_3_Format_ae5_slot0_4_get, Slot_ae_format48_3_Format_ae5_slot0_4_set, + Slot_ae5_slot0_get_field_fns, Slot_ae5_slot0_set_field_fns, + Slot_ae5_slot0_decode, "nop" }, + { "ae6_slot3", "ae_format88_3", 3, + Slot_ae_format88_3_Format_ae6_slot3_32_get, Slot_ae_format88_3_Format_ae6_slot3_32_set, + Slot_ae6_slot3_get_field_fns, Slot_ae6_slot3_set_field_fns, + Slot_ae6_slot3_decode, "nop" }, + { "ae6_slot2", "ae_format88_3", 2, + Slot_ae_format88_3_Format_ae6_slot2_28_get, Slot_ae_format88_3_Format_ae6_slot2_28_set, + Slot_ae6_slot2_get_field_fns, Slot_ae6_slot2_set_field_fns, + Slot_ae6_slot2_decode, "nop" }, + { "ae6_slot1", "ae_format88_3", 1, + Slot_ae_format88_3_Format_ae6_slot1_16_get, Slot_ae_format88_3_Format_ae6_slot1_16_set, + Slot_ae6_slot1_get_field_fns, Slot_ae6_slot1_set_field_fns, + Slot_ae6_slot1_decode, "nop" }, + { "ae6_slot0", "ae_format88_3", 0, + Slot_ae_format88_3_Format_ae6_slot0_6_get, Slot_ae_format88_3_Format_ae6_slot0_6_set, + Slot_ae6_slot0_get_field_fns, Slot_ae6_slot0_set_field_fns, + Slot_ae6_slot0_decode, "nop" }, + { "ae7_slot3", "ae_format88_4", 3, + Slot_ae_format88_4_Format_ae7_slot3_12_get, Slot_ae_format88_4_Format_ae7_slot3_12_set, + Slot_ae7_slot3_get_field_fns, Slot_ae7_slot3_set_field_fns, + Slot_ae7_slot3_decode, "nop" }, + { "ae7_slot2", "ae_format88_4", 2, + Slot_ae_format88_4_Format_ae7_slot2_20_get, Slot_ae_format88_4_Format_ae7_slot2_20_set, + Slot_ae7_slot2_get_field_fns, Slot_ae7_slot2_set_field_fns, + Slot_ae7_slot2_decode, "nop" }, + { "ae7_slot1", "ae_format88_4", 1, + Slot_ae_format88_4_Format_ae7_slot1_16_get, Slot_ae_format88_4_Format_ae7_slot1_16_set, + Slot_ae7_slot1_get_field_fns, Slot_ae7_slot1_set_field_fns, + Slot_ae7_slot1_decode, "nop" }, + { "ae7_slot0", "ae_format88_4", 0, + Slot_ae_format88_4_Format_ae7_slot0_6_get, Slot_ae_format88_4_Format_ae7_slot0_6_set, + Slot_ae7_slot0_get_field_fns, Slot_ae7_slot0_set_field_fns, + Slot_ae7_slot0_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_ae_format88_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x1f; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_ae_format88_2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_ae_format48_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0xc000; + insn[2] = 0; +} + +static void +Format_ae_format48_2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0x8000; + insn[2] = 0; +} + +static void +Format_ae_format48_3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_ae_format88_3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0x11000; +} + +static void +Format_ae_format88_4_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0x10000; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_ae_format88_slots[] = { 6, 5, 4, 3 }; + +static int Format_ae_format88_2_slots[] = { 9, 8, 7 }; + +static int Format_ae_format48_slots[] = { 11, 10 }; + +static int Format_ae_format48_2_slots[] = { 13, 12 }; + +static int Format_ae_format48_3_slots[] = { 16, 14, 15 }; + +static int Format_ae_format88_3_slots[] = { 20, 19, 18, 17 }; + +static int Format_ae_format88_4_slots[] = { 24, 21, 23, 22 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "ae_format88", 11, Format_ae_format88_encode, 4, Format_ae_format88_slots }, + { "ae_format88_2", 11, Format_ae_format88_2_encode, 3, Format_ae_format88_2_slots }, + { "ae_format48", 6, Format_ae_format48_encode, 2, Format_ae_format48_slots }, + { "ae_format48_2", 6, Format_ae_format48_2_encode, 2, Format_ae_format48_2_slots }, + { "ae_format48_3", 6, Format_ae_format48_3_encode, 3, Format_ae_format48_3_slots }, + { "ae_format88_3", 11, Format_ae_format88_3_encode, 4, Format_ae_format88_3_slots }, + { "ae_format88_4", 11, Format_ae_format88_4_encode, 4, Format_ae_format88_4_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0 && (insn[2] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0x1f) == 0x1f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0) + return 3; /* ae_format88 */ + if ((insn[0] & 0x3f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0xff0000) == 0) + return 4; /* ae_format88_2 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0xc000) == 0xc000 && (insn[2] & 0) == 0) + return 5; /* ae_format48 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0xc000) == 0x8000 && (insn[2] & 0) == 0) + return 6; /* ae_format48_2 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0x8000) == 0 && (insn[2] & 0) == 0) + return 7; /* ae_format48_3 */ + if ((insn[0] & 0x3f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0xffffe0) == 0x11000) + return 8; /* ae_format88_3 */ + if ((insn[0] & 0x3f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0xfff000) == 0x10000) + return 9; /* ae_format88_4 */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 11 /* insn_size */, 0, + 10, formats, format_decoder, length_decoder, + 25, slots, + 406 /* num_fields */, + 554, operands, + 1548, iclasses, + 1713, opcodes, 0, + 10, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 6, interfaces, 0, + 9, funcUnits, 0 +}; diff --git a/overlays/xtensa_nxp_rt600_adsp/binutils/include/xtensa-config.h b/overlays/xtensa_nxp_rt600_adsp/binutils/include/xtensa-config.h new file mode 100644 index 00000000..22016cae --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/binutils/include/xtensa-config.h @@ -0,0 +1,189 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 1 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 1 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 1 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 1 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 32 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_HAVE_PREDICTED_BRANCHES +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 32768 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 65536 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 256 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 256 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 8 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 8 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 4 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 11 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 260004 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 260004 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_nxp_rt600_adsp/gcc/include/xtensa-config.h b/overlays/xtensa_nxp_rt600_adsp/gcc/include/xtensa-config.h new file mode 100644 index 00000000..22016cae --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/gcc/include/xtensa-config.h @@ -0,0 +1,189 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 1 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 1 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 1 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 1 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 32 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_HAVE_PREDICTED_BRANCHES +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 32768 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 65536 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 256 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 256 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 8 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 8 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 4 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 11 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 260004 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 260004 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_nxp_rt600_adsp/gdb/bfd/xtensa-modules.c b/overlays/xtensa_nxp_rt600_adsp/gdb/bfd/xtensa-modules.c new file mode 100644 index 00000000..069e19f5 --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/gdb/bfd/xtensa-modules.c @@ -0,0 +1,113469 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2023 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "ansidecl.h" +#include +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "MEMCTL", 97, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "PREFCTL", 40, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "AE_OVF_SAR", 240, 1 }, + { "AE_BITHEAD", 241, 1 }, + { "AE_TS_FTS_BU_BP", 242, 1 }, + { "AE_CW_SD_NO", 243, 1 }, + { "AE_CBEGIN0", 246, 1 }, + { "AE_CEND0", 247, 1 }, + { "AE_CBEGIN1", 248, 1 }, + { "AE_CEND1", 249, 1 }, + { "FCR_FSR", -1, 1 }, + { "F64R_LO", 234, 1 }, + { "F64R_HI", 235, 1 }, + { "F64S", 236, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 74 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 249 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "DDR", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "INTERRUPT", 32, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EPS2", 13, 0 }, + { "EPS3", 13, 0 }, + { "EPS4", 13, 0 }, + { "EPS5", 13, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "MEMCTL", 1, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 32, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "PREFCTL", 13, 0 }, + { "CPENABLE", 2, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "ERI_RAW_INTERLOCK", 1, 0 }, + { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, + { "AE_CBEGIN0", 32, 0 }, + { "AE_CEND0", 32, 0 }, + { "AE_CBEGIN1", 32, 0 }, + { "AE_CEND1", 32, 0 }, + { "AE_SAR", 14, 0 }, + { "AE_CWRAP", 1, 0 }, + { "AE_BITHEAD", 32, 0 }, + { "AE_BITPTR", 4, 0 }, + { "AE_BITSUSED", 4, 0 }, + { "AE_TABLESIZE", 4, 0 }, + { "AE_FIRST_TS", 4, 0 }, + { "AE_NEXTOFFSET", 27, 0 }, + { "AE_SEARCHDONE", 1, 0 }, + { "RoundMode", 2, 0 }, + { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "F64R", 64, 0 }, + { "F64S", 32, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 83 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_DDR, + STATE_ICOUNT, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_MEMCTL, + STATE_SAR, + STATE_THREADPTR, + STATE_MISC0, + STATE_MISC1, + STATE_ACC, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_PREFCTL, + STATE_CPENABLE, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_ERI_RAW_INTERLOCK, + STATE_AE_OVERFLOW, + STATE_AE_CBEGIN0, + STATE_AE_CEND0, + STATE_AE_CBEGIN1, + STATE_AE_CEND1, + STATE_AE_SAR, + STATE_AE_CWRAP, + STATE_AE_BITHEAD, + STATE_AE_BITPTR, + STATE_AE_BITSUSED, + STATE_AE_TABLESIZE, + STATE_AE_FIRST_TS, + STATE_AE_NEXTOFFSET, + STATE_AE_SEARCHDONE, + STATE_RoundMode, + STATE_InvalidFlag, + STATE_DivZeroFlag, + STATE_OverflowFlag, + STATE_UnderflowFlag, + STATE_InexactFlag, + STATE_F64R, + STATE_F64S, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dfp_fld_op2_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_op2_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dfp_fld_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_dfp_fld_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dfp_fld_op2_3_2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_op2_3_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dfp_fld_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dfp_fld_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_dfp_fld_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dfp_fld_op2_3_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_op2_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_inst_15_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_inst_15_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_inst_7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_inst_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_inst_23_16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fld_inst_23_16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_inst_7_7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_inst_7_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_inst_4_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_inst_4_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_inst_5_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_inst_5_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_inst_7_6_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_inst_7_6_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_5_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_inst_5_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_13_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_inst_13_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_12_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_fld_inst_12_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_inst_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_inst_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_inst_7_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_inst_7_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_inst_9_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_inst_9_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_inst_9_8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_inst_9_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_inst_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_inst_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_inst_19_17_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_inst_19_17_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_inst_19_18_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + return tie_t; +} + +static void +Field_inst_19_18_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_fld_inst_7_4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_inst_7_4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_inst_3_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_inst_3_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_inst16b_15_13_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_ae_fld_inst16b_15_13_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_ae_fld_inst16b_12_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_ae_fld_inst16b_12_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 11) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 11) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 11) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_8_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot3_3_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot3_3_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot3_1_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_1_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_0_0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot3_0_0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot3_20_10_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 11) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_10_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot3_7_4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 11) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_13_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot3_13_12_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 11) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_14_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot3_11_4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot3_11_4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot3_11_11_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot3_11_11_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae_slot3_20_15_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 11) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot3_20_15_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot2_20_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 11) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 11) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_14_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 11) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_10_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 11) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_12_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot2_7_4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_7_4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 11) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_8_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_3_2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_3_2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot2_7_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot2_7_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot2_3_0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot2_9_8_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_20_4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 11) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot2_20_13_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 11) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_13_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot2_20_15_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 11) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_15_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot1_19_17_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_17_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_3_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_19_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot1_19_9_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_9_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot1_19_13_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot1_19_13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_7_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_slot1_7_6_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot1_7_6_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 11) >> 19); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 11) >> 23); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_20_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 11) >> 11); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 11) >> 15); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_20_13_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 11) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_13_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x1fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_20_15_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 11) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_15_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f8000) | (tie_t << 15); +} + +static unsigned +Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_3_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_0_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_0_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_5_2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_fld_ae_slot0_5_2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_4_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_8_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot0_11_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae_slot0_9_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_8_4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae_slot0_8_4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_7_7_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae_slot0_20_14_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 11) >> 25); + return tie_t; +} + +static void +Field_fld_ae_slot0_20_14_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_fld_ae_slot0_11_11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 7) >> 7); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 7) >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 7) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 21) | ((insn[0] << 3) >> 11); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 11) >> 11; + insn[0] = (insn[0] & ~0x1fffff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 3) >> 19); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x1fff0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 3) >> 15); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x1ffff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 3) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x1ffe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 3) >> 16); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x1fffe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 3) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000000) | (tie_t << 27); +} + +static unsigned +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); + return tie_t; +} + +static void +Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 24) >> 25); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe) | (tie_t << 1); +} + +static unsigned +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + return tie_t; +} + +static void +Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 10) >> 18); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 10) >> 22); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 10) >> 10); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 10) >> 12); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0x3ffffc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27); + return tie_t; +} + +static void +Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f) | (tie_t << 0); +} + +static unsigned +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 10) >> 14); + return tie_t; +} + +static void +Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 18) >> 18); + return tie_t; +} + +static void +Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 25) | ((insn[0] << 4) >> 7); + return tie_t; +} + +static void +Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 7) >> 7; + insn[0] = (insn[0] & ~0xffffff8) | (tie_t << 3); +} + +static unsigned +Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 29) >> 29); + return tie_t; +} + +static void +Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7) | (tie_t << 0); +} + +static unsigned +Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 4) >> 27); + return tie_t; +} + +static void +Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800000) | (tie_t << 23); +} + +static unsigned +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 4) >> 28); + return tie_t; +} + +static void +Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000000) | (tie_t << 24); +} + +static unsigned +Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 20) | ((insn[0] << 12) >> 12); + return tie_t; +} + +static void +Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 12) >> 12; + insn[0] = (insn[0] & ~0xfffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 10) >> 18); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 10) >> 22); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 10) >> 10); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0x3fffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 10) >> 16); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 10) >> 14); + return tie_t; +} + +static void +Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); + return tie_t; +} + +static void +Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 18) >> 18); + return tie_t; +} + +static void +Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 17) >> 23); + return tie_t; +} + +static void +Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 13) >> 13); + return tie_t; +} + +static void +Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 19) | ((insn[0] << 13) >> 13); + return tie_t; +} + +static void +Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 13) >> 13; + insn[0] = (insn[0] & ~0x7ffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); + return tie_t; +} + +static void +Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); +} + +static unsigned +Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_bbi_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm8_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_s_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_s_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_op2_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_op2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_r_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sae_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sal_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sargt_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_sas_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_sas_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_sas_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 21) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f0) | (tie_t << 4); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_t2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_t4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_s4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_s8_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 30) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2) | (tie_t << 1); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 5) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff000) | (tie_t << 12); +} + +static unsigned +Field_xt_wbr15_imm_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 9) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x7fff00) | (tie_t << 8); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_fhba4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_fhba4_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_fhba4_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_fhba4_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_fhba4_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_fhba4_2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_fhba4_2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_fhba4_2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_tp7_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_tp7_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_tp7_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_tp7_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_osa32_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_osa32_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_ae_fld_osa32_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_osa32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_osa32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_osa64_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa64_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_osa64_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa64_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_ae_fld_osa64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_osa64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_imm2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_ae_fld_imm2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_ae_fld_imm2_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_imm2_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_imm2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_imm2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_immls64_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls64_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64pos_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64pos_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_immls64half_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_ae_fld_immls64half_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls32_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls32_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_immls16_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_immls16_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_osa16_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa16_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_osa16_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_osa16_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_osa16_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_ls_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_uu_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_uu_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_su_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_su_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_su_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_su_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_ls_su_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_ls_su_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_av_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_av_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_av_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ls_v2_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ls_v2_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_cmpp_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmpp_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_cmpp_v1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmpp_v1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_cmpp_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmpp_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_uu_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_uu_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_uu_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_uu_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_uu_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_uu_uu_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_ae_fld_uu_uu_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_ar_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_ar_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_cmov_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_cmov_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_cmov_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_cmov_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_cmov_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_cmov_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_cmov_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_cmov_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_cmov_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_pks_d_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_d_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_pks_d_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_d_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_pks_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_pks_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_pks_s_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_s_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_pks_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_pks_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_shift_d_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_shift_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_shift_d_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_shift_d_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_shift_d0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_shift_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_shift_d0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_shift_d0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_d0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_shift_sd_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_sd_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_shift_sd_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_sd_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_shift_sd_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_shift_sd_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_dr_to_dr_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_dr_to_dr_v1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_dr_to_dr_v1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_to_dr_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_to_dr_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ae_immls64neg_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ae_immls64neg_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_selimm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_selimm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_selimm_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_selimm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_selimm_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_selimm_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_selimm_n_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_ae_fld_selimm_n_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_fld_ar_to_dr_imm_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26); + return tie_t; +} + +static void +Field_fld_ar_to_dr_imm_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v0_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v0_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_arth_v1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_ae_fld_arth_v1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_ae_fld_ar_to_dr_v_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ar_to_dr_v_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_rng_d_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_rng_d_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_d1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_d1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d1_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d1_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d1_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d1_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q0_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q0_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q0_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q0_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q0_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q0_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q0_Slot_ae6_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q0_Slot_ae6_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x4_q1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_q1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_mul_x4_d2_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x4_d2_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae7_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae7_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_d2_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_d2_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_v1_Slot_ae7_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_v1_Slot_ae7_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s1_acc_ep_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s1_acc_ep_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_mul_x2_s2_acc_ep_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_mul_x2_s2_acc_ep_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_shift_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_fld_ae_sem_dr_to_ar_vr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_dr_to_ar_vr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_sem_cmov_bt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_cmov_bt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_cmov_bt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_cmov_bt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_cmov_arr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_cmov_arr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_ae_sem_cmov_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_cmov_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vt_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vt_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vs_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vs_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_ae5_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_ae5_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_vr_Slot_ae2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_vr_Slot_ae2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_brt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_brt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_brt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_brt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vs_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vs_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_mov_i_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_i_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_mov_i_imm4_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_mov_i_imm4_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_sp32cvt_arr_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_sp32cvt_arr_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vt_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vt_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vsm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vsm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_fld_ae_slot2_20_18_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 11) >> 29); + return tie_t; +} + +static void +Field_fld_ae_slot2_20_18_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0000) | (tie_t << 18); +} + +static unsigned +Field_fld_vfpu2_sem_spmisc_vtm_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spmisc_vtm_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot3_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot3_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_r_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dfp_fld_r_0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dfp_fld_r_0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_2_1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_r_2_1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dfp_fld_r_3_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_r_3_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_r_3_1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_r_3_1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_s_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_s_0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_s_0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_0_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_s_0_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae3_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae3_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae3_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae3_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae4_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae4_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae4_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae4_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae5_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae5_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae6_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae6_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae6_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae6_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae7_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae7_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_s_3_1_Slot_ae7_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); + return tie_t; +} + +static void +Field_dfp_fld_s_3_1_Slot_ae7_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe) | (tie_t << 1); +} + +static unsigned +Field_dfp_fld_op2_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_op2_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dfp_fld_op2_1_0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + return tie_t; +} + +static void +Field_dfp_fld_op2_1_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_dfp_fld_op2_2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + return tie_t; +} + +static void +Field_dfp_fld_op2_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_fld_sigmoid_q15_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_sigmoid_q15_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_sigmoid_q15_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_sigmoid_q15_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_fld_sigmoid_fp32_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_fld_sigmoid_fp32_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_fld_sigmoid_fp32_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_fld_sigmoid_fp32_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_r_disp, + FIELD_r_3, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_r3, + FIELD_rbit2, + FIELD_rhi, + FIELD_t3, + FIELD_tbit2, + FIELD_tlo, + FIELD_w, + FIELD_y, + FIELD_x, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_s8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_ae_fld_fhba4, + FIELD_ae_fld_fhba4_2, + FIELD_ae_fld_tp7, + FIELD_ae_fld_osa32, + FIELD_ae_fld_osa64, + FIELD_ae_fld_imm2, + FIELD_ae_fld_immls64, + FIELD_ae_fld_immls64pos, + FIELD_ae_fld_immls64half, + FIELD_ae_fld_immls32, + FIELD_ae_fld_immls16, + FIELD_ae_fld_osa16, + FIELD_Inst_15_12, + FIELD_Inst_11_8, + FIELD_Inst_7_4, + FIELD_Inst_12, + FIELD_Inst_7, + FIELD_Inst_5_4, + FIELD_Inst_7_6, + FIELD_Inst_19_17, + FIELD_Inst_19_18, + FIELD_Inst_9_8, + FIELD_Inst_4, + FIELD_ae_fld_ls_v, + FIELD_ae_fld_ls_uu, + FIELD_ae_fld_ls_su, + FIELD_ae_fld_ls_av, + FIELD_ae_fld_ls_v1, + FIELD_ae_fld_ls_v2, + FIELD_ae_fld_cmpp_v0, + FIELD_ae_fld_cmpp_v1, + FIELD_ae_fld_cmpp_v, + FIELD_ae_fld_uu_v, + FIELD_ae_fld_uu_uu, + FIELD_ae_fld_dr_to_ar_v0, + FIELD_ae_fld_cmov_v, + FIELD_ae_fld_cmov_v0, + FIELD_ae_fld_pks_d, + FIELD_ae_fld_pks_s, + FIELD_ae_fld_shift_d, + FIELD_ae_fld_shift_d0, + FIELD_ae_fld_shift_sd, + FIELD_ae_fld_dr_to_dr_v, + FIELD_ae_fld_dr_to_dr_v0, + FIELD_ae_fld_dr_to_dr_v1, + FIELD_ae_fld_to_dr_v, + FIELD_ae_fld_to_dr_v0, + FIELD_fld_ae_immls64neg, + FIELD_ae_fld_selimm, + FIELD_ae_fld_selimm_N, + FIELD_fld_ar_to_dr_imm, + FIELD_ae_fld_arth_v, + FIELD_ae_fld_arth_v0, + FIELD_ae_fld_arth_v1, + FIELD_ae_fld_ar_to_dr_v, + FIELD_fld_Inst_23_12, + FIELD_fld_Inst_23_16, + FIELD_fld_Inst_7_7, + FIELD_fld_Inst_11_8, + FIELD_fld_Inst_13_8, + FIELD_fld_Inst_12_8, + FIELD_fld_Inst_9_8, + FIELD_fld_Inst_4_4, + FIELD_fld_Inst_5_4, + FIELD_fld_Inst_7_4, + FIELD_ae_fld_Inst16b_12, + FIELD_ae_fld_Inst16b_15_13, + FIELD_fld_ae4_slot0_7_4, + FIELD_fld_ae2_slot0_11_4, + FIELD_fld_ae2_slot0_7_4, + FIELD_fld_ae4_slot0_27_24, + FIELD_fld_ae2_slot0_11_9, + FIELD_fld_ae2_slot0_28_27, + FIELD_fld_ae4_slot0_27_23, + FIELD_fld_ae2_slot0_11_8, + FIELD_fld_ae5_slot0_21_8, + FIELD_fld_ae4_slot1_13_8, + FIELD_fld_ae3_slot1_19_8, + FIELD_fld_ae4_slot1_13_11, + FIELD_fld_ae5_slot0_3_0, + FIELD_fld_ae3_slot0_3_0, + FIELD_fld_ae3_slot1_3_0, + FIELD_fld_ae2_slot0_3_0, + FIELD_fld_ae2_slot1_3_0, + FIELD_fld_ae_slot0_3_0, + FIELD_fld_ae_slot1_3_0, + FIELD_fld_ae5_slot0_21_12, + FIELD_fld_ae4_slot1_13_12, + FIELD_fld_ae3_slot0_21_12, + FIELD_fld_ae3_slot1_19_12, + FIELD_fld_ae2_slot1_19_12, + FIELD_fld_ae_slot1_19_12, + FIELD_fld_ae5_slot0_21_16, + FIELD_fld_ae3_slot0_21_16, + FIELD_fld_ae3_slot1_19_16, + FIELD_fld_ae2_slot1_19_16, + FIELD_fld_ae_slot1_19_16, + FIELD_fld_ae5_slot0_21_17, + FIELD_fld_ae3_slot0_21_17, + FIELD_fld_ae3_slot1_19_17, + FIELD_fld_ae2_slot0_28_17, + FIELD_fld_ae2_slot1_19_17, + FIELD_fld_ae_slot1_19_17, + FIELD_fld_ae5_slot0_21_20, + FIELD_fld_ae3_slot0_21_20, + FIELD_fld_ae2_slot0_28_20, + FIELD_fld_ae5_slot0_7_4, + FIELD_fld_ae3_slot0_7_4, + FIELD_fld_ae7_slot0_15_0, + FIELD_fld_ae7_slot1_15_0, + FIELD_fld_ae7_slot2_18_0, + FIELD_fld_ae7_slot3_18_0, + FIELD_fld_ae6_slot0_15_0, + FIELD_fld_ae6_slot1_14_0, + FIELD_fld_ae6_slot2_13_0, + FIELD_fld_ae6_slot3_17_0, + FIELD_fld_ae5_slot0_21_0, + FIELD_fld_ae5_slot1_0_0, + FIELD_fld_ae5_slot2_19_0, + FIELD_fld_ae4_slot0_2_0, + FIELD_fld_ae4_slot0_27_3, + FIELD_fld_ae4_slot1_13_0, + FIELD_fld_ae3_slot0_21_0, + FIELD_fld_ae3_slot1_19_0, + FIELD_fld_ae2_slot1_19_0, + FIELD_fld_ae2_slot2_24_0, + FIELD_fld_ae_slot0_20_0, + FIELD_fld_ae_slot1_19_0, + FIELD_fld_ae_slot2_20_0, + FIELD_fld_ae3_slot1_7_4, + FIELD_fld_ae5_slot0_21_13, + FIELD_fld_ae3_slot0_21_13, + FIELD_fld_ae3_slot1_19_13, + FIELD_fld_ae2_slot0_28_13, + FIELD_fld_ae2_slot1_19_13, + FIELD_fld_ae_slot0_20_15, + FIELD_fld_ae_slot1_19_13, + FIELD_fld_ae_slot0_20_13, + FIELD_fld_ae3_slot1_19_4, + FIELD_fld_ae2_slot0_28_4, + FIELD_fld_ae2_slot1_19_4, + FIELD_fld_ae_slot0_20_4, + FIELD_fld_ae_slot1_19_4, + FIELD_fld_ae3_slot1_7_1, + FIELD_fld_ae2_slot1_19_9, + FIELD_fld_ae_slot1_19_9, + FIELD_fld_ae2_slot0_3_2, + FIELD_fld_ae_slot0_3_2, + FIELD_fld_ae2_slot0_0_0, + FIELD_fld_ae_slot0_0_0, + FIELD_fld_ae2_slot0_28_12, + FIELD_fld_ae_slot0_20_12, + FIELD_fld_ae7_slot0_7_4, + FIELD_fld_ae7_slot1_7_4, + FIELD_fld_ae5_slot0_11_8, + FIELD_fld_ae3_slot0_11_8, + FIELD_fld_ae5_slot0_21_6, + FIELD_fld_ae_sem_loads_stores_end, + FIELD_fld_ae2_slot1_7_4, + FIELD_fld_ae_slot1_7_4, + FIELD_fld_ae2_slot0_28_8, + FIELD_fld_ae2_slot1_19_8, + FIELD_fld_ae_slot0_20_8, + FIELD_fld_ae_slot1_19_8, + FIELD_fld_ae6_slot1_14_12, + FIELD_fld_ae6_slot2_3_0, + FIELD_fld_ae_sem_arithmetic_ds, + FIELD_fld_ae6_slot3_17_16, + FIELD_fld_ae_slot3_20_0, + FIELD_fld_ae_sem_rng_d, + FIELD_fld_ae_slot3_3_0, + FIELD_fld_ae3_slot0_8_8, + FIELD_fld_ae_slot0_8_8, + FIELD_fld_ae_slot3_1_0, + FIELD_fld_ae2_slot0_11_0, + FIELD_fld_ae_slot0_11_0, + FIELD_fld_ae2_slot1_7_0, + FIELD_fld_ae_slot0_7_0, + FIELD_fld_ae2_slot0_28_16, + FIELD_fld_ae_slot0_20_16, + FIELD_fld_ae_slot3_20_8, + FIELD_fld_ae2_slot0_9_4, + FIELD_fld_ae_slot0_9_4, + FIELD_fld_ae_sem_mul_x2_S1_d1, + FIELD_fld_ae_sem_mul_x2_S1_d0, + FIELD_fld_ae_sem_mul_x2_S1_q0, + FIELD_fld_ae_sem_mul_x2_S2_d1, + FIELD_fld_ae_sem_mul_x2_S2_d0, + FIELD_fld_ae_sem_mul_x2_S2_q0, + FIELD_fld_ae_sem_mul_x4_d1, + FIELD_fld_ae_sem_mul_x4_d0, + FIELD_fld_ae_sem_mul_x4_q0, + FIELD_fld_ae6_slot2_13_12, + FIELD_fld_ae_sem_mul_x4_q1, + FIELD_fld_ae2_slot2_24_16, + FIELD_fld_ae_sem_mul_x4_d2, + FIELD_fld_ae2_slot2_24_20, + FIELD_fld_ae7_slot2_18_16, + FIELD_fld_ae2_slot2_7_4, + FIELD_fld_ae7_slot3_18_16, + FIELD_fld_ae_sem_mul_x2_S1_d2, + FIELD_fld_ae_sem_mul_x2_S1_v1, + FIELD_fld_ae_sem_mul_x2_S2_d2, + FIELD_fld_ae_sem_mul_x2_S2_v1, + FIELD_fld_ae5_slot2_19_12, + FIELD_fld_ae_slot2_20_12, + FIELD_fld_ae_slot3_20_12, + FIELD_fld_ae5_slot0_21_4, + FIELD_fld_ae_sem_ep_ls_ei, + FIELD_fld_ae3_slot0_3_2, + FIELD_fld_ae3_slot1_3_2, + FIELD_fld_ae_sem_ep_ls_ar_s, + FIELD_fld_ae_sem_ep_ls_eo, + FIELD_fld_ae_slot2_7_0, + FIELD_fld_ae_slot3_11_4, + FIELD_fld_ae_sem_arithmetic_ep, + FIELD_fld_ae_slot2_3_0, + FIELD_fld_ae_sem_arithmetic_ep1, + FIELD_fld_ae_slot2_20_10, + FIELD_fld_ae_sem_mul_x2_S1_acc_ep, + FIELD_fld_ae_slot2_20_14, + FIELD_fld_ae_sem_mul_x2_S2_acc_ep, + FIELD_fld_ae_slot3_20_14, + FIELD_fld_ae_sem_shift_e, + FIELD_fld_ae_slot3_20_16, + FIELD_fld_ae_sem_shift_i8, + FIELD_fld_ae_slot3_11_11, + FIELD_fld_ae_sem_arithmetic_e, + FIELD_fld_ae_slot2_9_8, + FIELD_fld_ae_slot3_7_4, + FIELD_fld_ae_slot2_20_8, + FIELD_fld_ae_slot0_11_8, + FIELD_fld_ae_slot0_11_4, + FIELD_fld_ae_slot3_20_10, + FIELD_fld_ae_slot2_7_4, + FIELD_fld_ae2_slot0_8_4, + FIELD_fld_ae_slot0_8_4, + FIELD_fld_ae5_slot0_7_6, + FIELD_fld_ae3_slot0_5_4, + FIELD_fld_ae3_slot1_7_6, + FIELD_fld_ae2_slot1_7_6, + FIELD_fld_ae_slot1_7_6, + FIELD_fld_ae3_slot0_5_0, + FIELD_fld_ae3_slot0_4_0, + FIELD_fld_ae_slot0_4_0, + FIELD_fld_ae3_slot0_9_8, + FIELD_fld_ae_slot0_9_8, + FIELD_fld_ae7_slot0_15_12, + FIELD_fld_ae7_slot1_15_12, + FIELD_fld_ae5_slot0_5_4, + FIELD_fld_ae5_slot0_21_14, + FIELD_fld_ae3_slot0_7_6, + FIELD_fld_ae3_slot0_21_14, + FIELD_fld_ae7_slot0_7_7, + FIELD_fld_ae7_slot1_7_7, + FIELD_fld_ae6_slot1_7_7, + FIELD_fld_ae5_slot0_7_7, + FIELD_fld_ae3_slot0_5_5, + FIELD_fld_ae3_slot1_7_7, + FIELD_fld_ae2_slot0_4_4, + FIELD_fld_ae2_slot1_7_7, + FIELD_fld_ae_slot0_4_4, + FIELD_fld_ae_slot1_7_7, + FIELD_fld_ae6_slot0_15_12, + FIELD_fld_ae6_slot0_7_7, + FIELD_fld_ae7_slot0_7_6, + FIELD_fld_ae6_slot1_7_6, + FIELD_fld_ae6_slot1_14_6, + FIELD_fld_ae5_slot0_3_2, + FIELD_fld_ae3_slot0_5_2, + FIELD_fld_ae2_slot0_5_2, + FIELD_fld_ae_slot0_5_2, + FIELD_fld_ae3_slot0_21_2, + FIELD_fld_ae2_slot0_5_0, + FIELD_fld_ae_slot3_0_0, + FIELD_fld_ae_slot2_3_2, + FIELD_fld_ae_slot0_7_4, + FIELD_fld_ae2_slot0_7_0, + FIELD_fld_ae2_slot0_7_7, + FIELD_fld_ae_slot0_7_7, + FIELD_fld_ae_slot3_20_13, + FIELD_fld_ae2_slot0_5_4, + FIELD_fld_ae_slot0_5_4, + FIELD_fld_ae_slot3_13_12, + FIELD_fld_ae3_slot0_21_8, + FIELD_fld_ae_slot0_20_14, + FIELD_fld_ae_slot0_5_0, + FIELD_fld_ae3_slot0_21_4, + FIELD_fld_ae_sem_dr_to_ar_vr, + FIELD_fld_ae_sem_cmov_bt, + FIELD_fld_ae_sem_cmov_arr, + FIELD_fld_vfpu2_sem_mov_vt, + FIELD_fld_vfpu2_sem_mov_vr, + FIELD_fld_vfpu2_sem_spfma_vt, + FIELD_fld_vfpu2_sem_spfma_vs, + FIELD_fld_vfpu2_sem_spfma_vr, + FIELD_fld_vfpu2_sem_spmisc_brt, + FIELD_fld_vfpu2_sem_spmisc_vs, + FIELD_fld_vfpu2_sem_spmisc_vr, + FIELD_fld_vfpu2_sem_mov_i_imm4, + FIELD_fld_vfpu2_sem_sp32cvt_vr, + FIELD_fld_vfpu2_sem_sp32cvt_vt, + FIELD_fld_vfpu2_sem_sp32cvt_i_imm5, + FIELD_fld_vfpu2_sem_sp32cvt_arr, + FIELD_fld_ae_slot0_11_11, + FIELD_fld_vfpu2_sem_spmisc_vt, + FIELD_fld_vfpu2_sem_spmisc_vsM, + FIELD_fld_ae_slot2_20_18, + FIELD_fld_vfpu2_sem_spmisc_vtM, + FIELD_fld_vfpu2_sem_spfma_i_imm1, + FIELD_fld_vfpu2_sem_spfma_i_imm3, + FIELD_fld_ae_slot2_20_13, + FIELD_fld_ae_slot3_20_15, + FIELD_fld_ae_slot2_20_15, + FIELD_fld_ae_sem_movfpstate_v, + FIELD_fld_ae_slot2_20_4, + FIELD_dfp_fld_op1, + FIELD_dfp_fld_op2, + FIELD_dfp_fld_r_0, + FIELD_dfp_fld_r_2_1, + FIELD_dfp_fld_r_3, + FIELD_dfp_fld_r_3_1, + FIELD_dfp_fld_s_0, + FIELD_dfp_fld_s_3_1, + FIELD_dfp_fld_op2_0, + FIELD_dfp_fld_op2_1_0, + FIELD_dfp_fld_op2_2, + FIELD_dfp_fld_op2_3, + FIELD_dfp_fld_op2_3_2, + FIELD_dfp_fld_op2_3_1, + FIELD_bitindex, + FIELD_s3to1, + FIELD_fld_SIGMOID_Q15_x, + FIELD_fld_SIGMOID_Q15_y, + FIELD_fld_Inst_3_0, + FIELD_fld_SIGMOID_FP32_x, + FIELD_fld_SIGMOID_FP32_y, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__mr0, + FIELD__mr1, + FIELD__mr2, + FIELD__mr3, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + {"XT_LOADSTORE_UNIT", 2}, + { "mul_function", 1 }, + { "mul_S2_function", 1 }, + { "ae_add32x27", 1 }, + { "ae_shift32x4", 1 }, + { "ae_shift32x5", 1 }, + { "ae_leftshift32x5", 2 }, + { "ae_mulpp_32x32x2_1", 1 }, + { "ae_mulpp_32x32x2_2", 1 } +}; + +enum xtensa_funcUnit_id { + FUNCUNIT_XT_LOADSTORE_UNIT, + FUNCUNIT_mul_function, + FUNCUNIT_mul_S2_function, + FUNCUNIT_ae_add32x27, + FUNCUNIT_ae_shift32x4, + FUNCUNIT_ae_shift32x5, + FUNCUNIT_ae_leftshift32x5, + FUNCUNIT_ae_mulpp_32x32x2_1, + FUNCUNIT_ae_mulpp_32x32x2_2 +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_MR, + REGFILE_BR, + REGFILE_AE_DR, + REGFILE_AE_VALIGN, + REGFILE_AE_EP, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "MR", "m", REGFILE_MR, 32, 4 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "AE_DR", "aed", REGFILE_AE_DR, 64, 16 }, + { "AE_VALIGN", "u", REGFILE_AE_VALIGN, 64, 4 }, + { "AE_EP", "aep", REGFILE_AE_EP, 8, 4 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "ERI_RD_Out", 14, 0, 0, 'o' }, + { "ERI_RD_In", 32, 0, 1, 'i' }, + { "ERI_RD_Rdy", 1, 0, 0, 'i' }, + { "ERI_WR_Out", 46, 0, 2, 'o' }, + { "ERI_WR_In", 1, 0, 3, 'i' }, + { "IMPWIRE", 32, 0, 4, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_ERI_RD_Out, + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Rdy, + INTERFACE_ERI_WR_Out, + INTERFACE_ERI_WR_In, + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table bitmask8 */ +static const unsigned CONST_TBL_bitmask8_0[] = { + 0 & 0xff, + 0x1 & 0xff, + 0x3 & 0xff, + 0x7 & 0xff, + 0xf & 0xff, + 0x1f & 0xff, + 0x3f & 0xff, + 0x7f & 0xff, + 0 +}; + +/* constant table ae_ripimmtable */ +static const unsigned CONST_TBL_ae_ripimmtable_0[] = { + 0xffffffe0, + 0xffffffe8, + 0xfffffff0, + 0xfffffff8, + 0 +}; + +/* constant table ae_slai72table */ +static const unsigned CONST_TBL_ae_slai72table_0[] = { + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0 +}; + +/* constant table ae_seliencode */ +static const unsigned CONST_TBL_ae_seliencode_0[] = { + 0x4e5 & 0xfff, + 0x65 & 0xfff, + 0x77 & 0xfff, + 0x4f7 & 0xfff, + 0x72e & 0xfff, + 0x29c & 0xfff, + 0xaf & 0xfff, + 0xa6 & 0xfff, + 0x2ef & 0xfff, + 0x10d & 0xfff, + 0x599 & 0xfff, + 0x59f & 0xfff, + 0xb3e & 0xfff, + 0x18f & 0xfff, + 0x51d & 0xfff, + 0xa6 & 0xfff, + 0 +}; + +/* constant table xd_recip0_table128_8 */ +static const unsigned CONST_TBL_xd_recip0_table128_8_0[] = { + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf5 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf0 & 0xff, + 0xee & 0xff, + 0xed & 0xff, + 0xeb & 0xff, + 0xe9 & 0xff, + 0xe8 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xde & 0xff, + 0xdd & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd1 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb1 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xad & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa4 & 0xff, + 0xa3 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0 +}; + +/* constant table xd_rsqrt0_table128_8 */ +static const unsigned CONST_TBL_xd_rsqrt0_table128_8_0[] = { + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x80 & 0xff, + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf6 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf1 & 0xff, + 0xef & 0xff, + 0xed & 0xff, + 0xec & 0xff, + 0xea & 0xff, + 0xe9 & 0xff, + 0xe7 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xdf & 0xff, + 0xdd & 0xff, + 0xdc & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd6 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd2 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xce & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc9 & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc3 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0 +}; + +/* constant table vfpu2_table_mulmux */ +static const unsigned CONST_TBL_vfpu2_table_mulmux_0[] = { + 0xe & 0x3f, + 0x1e & 0x3f, + 0 +}; + +/* constant table vfpu2_table_maddmux */ +static const unsigned CONST_TBL_vfpu2_table_maddmux_0[] = { + 0xe & 0x3f, + 0x21 & 0x3f, + 0x3e & 0x3f, + 0x11 & 0x3f, + 0x1e & 0x3f, + 0x1 & 0x3f, + 0x2e & 0x3f, + 0x31 & 0x3f, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_MR_0_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +OperandSem_opnd_sem_MR_0_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_decode (uint32 *valp) +{ + unsigned immr_out_0; + unsigned immr_in_0; + immr_in_0 = *valp & 0xf; + immr_out_0 = immr_in_0; + *valp = immr_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_encode (uint32 *valp) +{ + unsigned immr_in_0; + unsigned immr_out_0; + immr_out_0 = *valp; + immr_in_0 = (immr_out_0 & 0xf); + *valp = immr_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_12_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_entry_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = ((0 << 4) | uimm4x16_in_0) << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = ((0 << 4) | uimmrx4_in_0) << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_1_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_2_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_3_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_5_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_imms_decode (uint32 *valp) +{ + unsigned imms_out_0; + unsigned imms_in_0; + imms_in_0 = *valp & 0xf; + imms_out_0 = imms_in_0; + *valp = imms_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_encode (uint32 *valp) +{ + unsigned imms_in_0; + unsigned imms_out_0; + imms_out_0 = *valp; + imms_in_0 = imms_out_0 & 0xf; + *valp = imms_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_out_0; + unsigned xt_wbr18_label_in_0; + xt_wbr18_label_in_0 = *valp & 0x3ffff; + xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); + *valp = xt_wbr18_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_label_in_0; + unsigned xt_wbr18_label_out_0; + xt_wbr18_label_out_0 = *valp; + xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64neg_decode (uint32 *valp) +{ + unsigned ae_immls64neg_out_0; + unsigned ae_immls64neg_in_0; + ae_immls64neg_in_0 = *valp & 0x3; + ae_immls64neg_out_0 = CONST_TBL_ae_ripimmtable_0[ae_immls64neg_in_0 & 0x3]; + *valp = ae_immls64neg_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64neg_encode (uint32 *valp) +{ + unsigned ae_immls64neg_in_0; + unsigned ae_immls64neg_out_0; + ae_immls64neg_out_0 = *valp; + ae_immls64neg_in_0 = (((ae_immls64neg_out_0 == (CONST_TBL_ae_ripimmtable_0[0]))) ? 0 : (((ae_immls64neg_out_0 == (CONST_TBL_ae_ripimmtable_0[1]))) ? 0x1 : (((ae_immls64neg_out_0 == (CONST_TBL_ae_ripimmtable_0[2]))) ? 0x2 : 0x3))) & 0x3; + *valp = ae_immls64neg_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64half_decode (uint32 *valp) +{ + unsigned ae_immls64half_out_0; + unsigned ae_immls64half_in_0; + ae_immls64half_in_0 = *valp & 0x7; + ae_immls64half_out_0 = (((int) ae_immls64half_in_0 << 29) >> 29) << 3; + *valp = ae_immls64half_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64half_encode (uint32 *valp) +{ + unsigned ae_immls64half_in_0; + unsigned ae_immls64half_out_0; + ae_immls64half_out_0 = *valp; + ae_immls64half_in_0 = ((ae_immls64half_out_0 >> 3) & 0x7); + *valp = ae_immls64half_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) +{ + unsigned ae_ohba_out_0; + unsigned ae_ohba_in_0; + ae_ohba_in_0 = *valp & 0xf; + ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); + *valp = ae_ohba_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) +{ + unsigned ae_ohba_in_0; + unsigned ae_ohba_out_0; + ae_ohba_out_0 = *valp; + ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); + *valp = ae_ohba_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_opnd_tp7_decode (uint32 *valp) +{ + unsigned ae_opnd_tp7_out_0; + unsigned ae_opnd_tp7_in_0; + ae_opnd_tp7_in_0 = *valp & 0xf; + ae_opnd_tp7_out_0 = ae_opnd_tp7_in_0 + 0x7; + *valp = ae_opnd_tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_opnd_tp7_encode (uint32 *valp) +{ + unsigned ae_opnd_tp7_in_0; + unsigned ae_opnd_tp7_out_0; + ae_opnd_tp7_out_0 = *valp; + ae_opnd_tp7_in_0 = (ae_opnd_tp7_out_0 - 0x7) & 0xf; + *valp = ae_opnd_tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_imm2_decode (uint32 *valp) +{ + unsigned ae_imm2_out_0; + unsigned ae_imm2_in_0; + ae_imm2_in_0 = *valp & 0x3; + ae_imm2_out_0 = (0 << 2) | ae_imm2_in_0; + *valp = ae_imm2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_imm2_encode (uint32 *valp) +{ + unsigned ae_imm2_in_0; + unsigned ae_imm2_out_0; + ae_imm2_out_0 = *valp; + ae_imm2_in_0 = (ae_imm2_out_0 & 0x3); + *valp = ae_imm2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa32_decode (uint32 *valp) +{ + unsigned ae_osa32_out_0; + unsigned ae_osa32_in_0; + ae_osa32_in_0 = *valp & 0x1f; + ae_osa32_out_0 = (0 << 5) | ae_osa32_in_0; + *valp = ae_osa32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa32_encode (uint32 *valp) +{ + unsigned ae_osa32_in_0; + unsigned ae_osa32_out_0; + ae_osa32_out_0 = *valp; + ae_osa32_in_0 = (ae_osa32_out_0 & 0x1f); + *valp = ae_osa32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa64_decode (uint32 *valp) +{ + unsigned ae_osa64_out_0; + unsigned ae_osa64_in_0; + ae_osa64_in_0 = *valp & 0x3f; + ae_osa64_out_0 = (0 << 6) | ae_osa64_in_0; + *valp = ae_osa64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa64_encode (uint32 *valp) +{ + unsigned ae_osa64_in_0; + unsigned ae_osa64_out_0; + ae_osa64_out_0 = *valp; + ae_osa64_in_0 = (ae_osa64_out_0 & 0x3f); + *valp = ae_osa64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64_decode (uint32 *valp) +{ + unsigned ae_immls64_out_0; + unsigned ae_immls64_in_0; + ae_immls64_in_0 = *valp & 0xf; + ae_immls64_out_0 = (((int) ae_immls64_in_0 << 28) >> 28) << 3; + *valp = ae_immls64_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64_encode (uint32 *valp) +{ + unsigned ae_immls64_in_0; + unsigned ae_immls64_out_0; + ae_immls64_out_0 = *valp; + ae_immls64_in_0 = ((ae_immls64_out_0 >> 3) & 0xf); + *valp = ae_immls64_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64pos_decode (uint32 *valp) +{ + unsigned ae_immls64pos_out_0; + unsigned ae_immls64pos_in_0; + ae_immls64pos_in_0 = *valp & 0x7; + ae_immls64pos_out_0 = ((0 << 3) | ae_immls64pos_in_0) << 3; + *valp = ae_immls64pos_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls64pos_encode (uint32 *valp) +{ + unsigned ae_immls64pos_in_0; + unsigned ae_immls64pos_out_0; + ae_immls64pos_out_0 = *valp; + ae_immls64pos_in_0 = ((ae_immls64pos_out_0 >> 3) & 0x7); + *valp = ae_immls64pos_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls32_decode (uint32 *valp) +{ + unsigned ae_immls32_out_0; + unsigned ae_immls32_in_0; + ae_immls32_in_0 = *valp & 0xf; + ae_immls32_out_0 = (((int) ae_immls32_in_0 << 28) >> 28) << 2; + *valp = ae_immls32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls32_encode (uint32 *valp) +{ + unsigned ae_immls32_in_0; + unsigned ae_immls32_out_0; + ae_immls32_out_0 = *valp; + ae_immls32_in_0 = ((ae_immls32_out_0 >> 2) & 0xf); + *valp = ae_immls32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls16_decode (uint32 *valp) +{ + unsigned ae_immls16_out_0; + unsigned ae_immls16_in_0; + ae_immls16_in_0 = *valp & 0xf; + ae_immls16_out_0 = (((int) ae_immls16_in_0 << 28) >> 28) << 1; + *valp = ae_immls16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_immls16_encode (uint32 *valp) +{ + unsigned ae_immls16_in_0; + unsigned ae_immls16_out_0; + ae_immls16_out_0 = *valp; + ae_immls16_in_0 = ((ae_immls16_out_0 >> 1) & 0xf); + *valp = ae_immls16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa16_decode (uint32 *valp) +{ + unsigned ae_osa16_out_0; + unsigned ae_osa16_in_0; + ae_osa16_in_0 = *valp & 0xf; + ae_osa16_out_0 = (0 << 4) | ae_osa16_in_0; + *valp = ae_osa16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa16_encode (uint32 *valp) +{ + unsigned ae_osa16_in_0; + unsigned ae_osa16_out_0; + ae_osa16_out_0 = *valp; + ae_osa16_in_0 = (ae_osa16_out_0 & 0xf); + *valp = ae_osa16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_selimm_N_decode (uint32 *valp) +{ + unsigned ae_selimm_N_out_0; + unsigned ae_selimm_N_in_0; + ae_selimm_N_in_0 = *valp & 0x3; + ae_selimm_N_out_0 = (0 << 2) | ae_selimm_N_in_0; + *valp = ae_selimm_N_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_selimm_N_encode (uint32 *valp) +{ + unsigned ae_selimm_N_in_0; + unsigned ae_selimm_N_out_0; + ae_selimm_N_out_0 = *valp; + ae_selimm_N_in_0 = (ae_selimm_N_out_0 & 0x3); + *valp = ae_selimm_N_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_movi_imm_decode (uint32 *valp) +{ + unsigned movi_imm_out_0; + unsigned movi_imm_in_0; + movi_imm_in_0 = *valp & 0x3f; + movi_imm_out_0 = ((((-(( ( ((((movi_imm_in_0 >> 4) & 0x3)) | 0xfffffffc)) == 0xffffffff))) & 0x3ffffff)) << 6) | movi_imm_in_0; + *valp = movi_imm_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_movi_imm_encode (uint32 *valp) +{ + unsigned movi_imm_in_0; + unsigned movi_imm_out_0; + movi_imm_out_0 = *valp; + movi_imm_in_0 = (movi_imm_out_0 & 0x3f); + *valp = movi_imm_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_DR_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_VALIGN_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_decode (uint32 *valp) +{ + unsigned ae_uimm2x2_out_0; + unsigned ae_uimm2x2_in_0; + ae_uimm2x2_in_0 = *valp & 0x1; + ae_uimm2x2_out_0 = (0 << 2) | (ae_uimm2x2_in_0 << 1) | 0; + *valp = ae_uimm2x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_uimm2x2_encode (uint32 *valp) +{ + unsigned ae_uimm2x2_in_0; + unsigned ae_uimm2x2_out_0; + ae_uimm2x2_out_0 = *valp; + ae_uimm2x2_in_0 = (((ae_uimm2x2_out_0 >> 1) & 1)) & 0x1; + *valp = ae_uimm2x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AE_EP_encode (uint32 *valp) +{ + int error = 0; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_out_0; + unsigned opnd_ae_sem_shift_i8_in_0; + opnd_ae_sem_shift_i8_in_0 = *valp & 0x7; + opnd_ae_sem_shift_i8_out_0 = CONST_TBL_ae_slai72table_0[opnd_ae_sem_shift_i8_in_0 & 0x7]; + *valp = opnd_ae_sem_shift_i8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode (uint32 *valp) +{ + unsigned opnd_ae_sem_shift_i8_in_0; + unsigned opnd_ae_sem_shift_i8_out_0; + opnd_ae_sem_shift_i8_out_0 = *valp; + switch (opnd_ae_sem_shift_i8_out_0) + { + case 0x1: opnd_ae_sem_shift_i8_in_0 = 0; break; + case 0x2: opnd_ae_sem_shift_i8_in_0 = 0x1; break; + case 0x3: opnd_ae_sem_shift_i8_in_0 = 0x2; break; + case 0x4: opnd_ae_sem_shift_i8_in_0 = 0x3; break; + case 0x5: opnd_ae_sem_shift_i8_in_0 = 0x4; break; + case 0x6: opnd_ae_sem_shift_i8_in_0 = 0x5; break; + case 0x7: opnd_ae_sem_shift_i8_in_0 = 0x6; break; + default: opnd_ae_sem_shift_i8_in_0 = 0x7; break; + } + *valp = opnd_ae_sem_shift_i8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa2_decode (uint32 *valp) +{ + unsigned ae_osa2_out_0; + unsigned ae_osa2_in_0; + ae_osa2_in_0 = *valp & 0x1; + ae_osa2_out_0 = (0 << 1) | ae_osa2_in_0; + *valp = ae_osa2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa2_encode (uint32 *valp) +{ + unsigned ae_osa2_in_0; + unsigned ae_osa2_out_0; + ae_osa2_out_0 = *valp; + ae_osa2_in_0 = (((ae_osa2_out_0 >> 0) & 1)) & 0x1; + *valp = ae_osa2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa8_decode (uint32 *valp) +{ + unsigned ae_osa8_out_0; + unsigned ae_osa8_in_0; + ae_osa8_in_0 = *valp & 0x7; + ae_osa8_out_0 = (0 << 3) | ae_osa8_in_0; + *valp = ae_osa8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ae_osa8_encode (uint32 *valp) +{ + unsigned ae_osa8_in_0; + unsigned ae_osa8_out_0; + ae_osa8_out_0 = *valp; + ae_osa8_in_0 = (ae_osa8_out_0 & 0x7); + *valp = ae_osa8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_2_decode (uint32 *valp) +{ + unsigned dfp_fld_op2_2_out_0; + unsigned dfp_fld_op2_2_in_0; + dfp_fld_op2_2_in_0 = *valp & 0x1; + dfp_fld_op2_2_out_0 = (0 << 1) | dfp_fld_op2_2_in_0; + *valp = dfp_fld_op2_2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_2_encode (uint32 *valp) +{ + unsigned dfp_fld_op2_2_in_0; + unsigned dfp_fld_op2_2_out_0; + dfp_fld_op2_2_out_0 = *valp; + dfp_fld_op2_2_in_0 = (((dfp_fld_op2_2_out_0 >> 0) & 1)) & 0x1; + *valp = dfp_fld_op2_2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_1_0_decode (uint32 *valp) +{ + unsigned dfp_fld_op2_1_0_out_0; + unsigned dfp_fld_op2_1_0_in_0; + dfp_fld_op2_1_0_in_0 = *valp & 0x3; + dfp_fld_op2_1_0_out_0 = (0 << 2) | dfp_fld_op2_1_0_in_0; + *valp = dfp_fld_op2_1_0_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_1_0_encode (uint32 *valp) +{ + unsigned dfp_fld_op2_1_0_in_0; + unsigned dfp_fld_op2_1_0_out_0; + dfp_fld_op2_1_0_out_0 = *valp; + dfp_fld_op2_1_0_in_0 = (dfp_fld_op2_1_0_out_0 & 0x3); + *valp = dfp_fld_op2_1_0_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_decode (uint32 *valp) +{ + unsigned dfp_fld_op2_out_0; + unsigned dfp_fld_op2_in_0; + dfp_fld_op2_in_0 = *valp & 0xf; + dfp_fld_op2_out_0 = (0 << 4) | dfp_fld_op2_in_0; + *valp = dfp_fld_op2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_dfp_fld_op2_encode (uint32 *valp) +{ + unsigned dfp_fld_op2_in_0; + unsigned dfp_fld_op2_out_0; + dfp_fld_op2_out_0 = *valp; + dfp_fld_op2_in_0 = (dfp_fld_op2_out_0 & 0xf); + *valp = dfp_fld_op2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_decode (uint32 *valp) +{ + unsigned bitindex_out_0; + unsigned bitindex_in_0; + bitindex_in_0 = *valp & 0x1f; + bitindex_out_0 = (0 << 5) | bitindex_in_0; + *valp = bitindex_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_encode (uint32 *valp) +{ + unsigned bitindex_in_0; + unsigned bitindex_out_0; + bitindex_out_0 = *valp; + bitindex_in_0 = (bitindex_out_0 & 0x1f); + *valp = bitindex_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa, + -1, 0 }, + { "immr", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode, + 0, 0, + -1, 0 }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0, + -1, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0, + -1, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0, + 0, 31 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0, + 0, 31 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode, + 0, 0, + 0, 31 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode, + 0, 0, + 0, 31 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode, + 0, 0, + 0, 31 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0, + -1, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0, + -1, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0, + -1, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa, + -1, 0 }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0, + -1, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0, + -1, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0, + -1, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0, + -1, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0, + -1, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0, + -1, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0, + -1, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0, + -1, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0, + -1, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0, + -1, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0, + -1, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0, + -1, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0, + -1, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0, + -1, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa, + -1, 0 }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa, + -1, 0 }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa, + -1, 0 }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa, + -1, 0 }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa, + -1, 0 }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0, + -1, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0, + -1, 0 }, + { "mx", FIELD_x, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, + 0, 0, + 0, 3 }, + { "my", FIELD_y, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, + 0, 0, + 0, 3 }, + { "mw", FIELD_w, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, + 0, 0, + 0, 3 }, + { "mr0", FIELD__mr0, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, + 0, 0, + 0, 3 }, + { "mr1", FIELD__mr1, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, + 0, 0, + 0, 3 }, + { "mr2", FIELD__mr2, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, + 0, 0, + 0, 3 }, + { "mr3", FIELD__mr3, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, + 0, 0, + 0, 3 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "imms1", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0, + -1, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0, + 0, 15 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0, + 0, 15 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0, + 0, 15 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0, + -1, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa, + -1, 0 }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa, + -1, 0 }, + { "ae_immls64neg", FIELD_fld_ae_immls64neg, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls64neg_encode, OperandSem_opnd_sem_ae_immls64neg_decode, + 0, 0, + -1, 0 }, + { "ae_immls64half", FIELD_ae_fld_immls64half, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls64half_encode, OperandSem_opnd_sem_ae_immls64half_decode, + 0, 0, + -1, 0 }, + { "ae_ohba", FIELD_ae_fld_fhba4, -1, 0, + 0, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, + 0, 0, + -1, 0 }, + { "ae_ohba2", FIELD_ae_fld_fhba4_2, -1, 0, + 0, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, + 0, 0, + -1, 0 }, + { "ae_opnd_tp7", FIELD_ae_fld_tp7, -1, 0, + 0, + OperandSem_opnd_sem_ae_opnd_tp7_encode, OperandSem_opnd_sem_ae_opnd_tp7_decode, + 0, 0, + -1, 0 }, + { "ae_imm2", FIELD_ae_fld_imm2, -1, 0, + 0, + OperandSem_opnd_sem_ae_imm2_encode, OperandSem_opnd_sem_ae_imm2_decode, + 0, 0, + -1, 0 }, + { "ae_osa32", FIELD_ae_fld_osa32, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa32_encode, OperandSem_opnd_sem_ae_osa32_decode, + 0, 0, + -1, 0 }, + { "ae_osa64", FIELD_ae_fld_osa64, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa64_encode, OperandSem_opnd_sem_ae_osa64_decode, + 0, 0, + -1, 0 }, + { "ae_immls64", FIELD_ae_fld_immls64, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls64_encode, OperandSem_opnd_sem_ae_immls64_decode, + 0, 0, + -1, 0 }, + { "ae_immls64pos", FIELD_ae_fld_immls64pos, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls64pos_encode, OperandSem_opnd_sem_ae_immls64pos_decode, + 0, 0, + -1, 0 }, + { "ae_immls32", FIELD_ae_fld_immls32, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls32_encode, OperandSem_opnd_sem_ae_immls32_decode, + 0, 0, + -1, 0 }, + { "ae_immls16", FIELD_ae_fld_immls16, -1, 0, + 0, + OperandSem_opnd_sem_ae_immls16_encode, OperandSem_opnd_sem_ae_immls16_decode, + 0, 0, + -1, 0 }, + { "ae_osa16", FIELD_ae_fld_osa16, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa16_encode, OperandSem_opnd_sem_ae_osa16_decode, + 0, 0, + -1, 0 }, + { "ae_selimm", FIELD_ae_fld_selimm, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa16_encode, OperandSem_opnd_sem_ae_osa16_decode, + 0, 0, + -1, 0 }, + { "ae_selimm.N", FIELD_ae_fld_selimm_N, -1, 0, + 0, + OperandSem_opnd_sem_ae_selimm_N_encode, OperandSem_opnd_sem_ae_selimm_N_decode, + 0, 0, + -1, 0 }, + { "movi_imm", FIELD_fld_ar_to_dr_imm, -1, 0, + 0, + OperandSem_opnd_sem_movi_imm_encode, OperandSem_opnd_sem_movi_imm_decode, + 0, 0, + -1, 0 }, + { "ae_arth_v", FIELD_ae_fld_arth_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_arth_v0", FIELD_ae_fld_arth_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_arth_v1", FIELD_ae_fld_arth_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ar_to_dr_v", FIELD_ae_fld_ar_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_to_dr_v", FIELD_ae_fld_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_to_dr_v0", FIELD_ae_fld_to_dr_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_dr_to_dr_v", FIELD_ae_fld_dr_to_dr_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_dr_to_dr_v0", FIELD_ae_fld_dr_to_dr_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_dr_to_dr_v1", FIELD_ae_fld_dr_to_dr_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_v", FIELD_ae_fld_ls_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_av", FIELD_ae_fld_ls_av, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_v1", FIELD_ae_fld_ls_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_v2", FIELD_ae_fld_ls_v2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_ls_uu", FIELD_ae_fld_ls_uu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "ae_ls_su", FIELD_ae_fld_ls_su, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "ae_uu_v", FIELD_ae_fld_uu_v, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "ae_uu_uu", FIELD_ae_fld_uu_uu, REGFILE_AE_VALIGN, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_VALIGN_encode, OperandSem_opnd_sem_AE_VALIGN_decode, + 0, 0, + 0, 3 }, + { "ae_dr_to_ar_v0", FIELD_ae_fld_dr_to_ar_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_cmov_v", FIELD_ae_fld_cmov_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_cmov_v0", FIELD_ae_fld_cmov_v0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_pks_d", FIELD_ae_fld_pks_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_pks_s", FIELD_ae_fld_pks_s, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_shift_d", FIELD_ae_fld_shift_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_shift_d0", FIELD_ae_fld_shift_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_shift_sd", FIELD_ae_fld_shift_sd, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "ae_uimm2x2", FIELD_ae_fld_Inst16b_12, -1, 0, + 0, + OperandSem_opnd_sem_ae_uimm2x2_encode, OperandSem_opnd_sem_ae_uimm2x2_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_d1", FIELD_fld_ae_sem_mul_x2_S1_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_d0", FIELD_fld_ae_sem_mul_x2_S1_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_q0", FIELD_fld_ae_sem_mul_x2_S1_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_d1", FIELD_fld_ae_sem_mul_x2_S2_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_d0", FIELD_fld_ae_sem_mul_x2_S2_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_q0", FIELD_fld_ae_sem_mul_x2_S2_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_d1", FIELD_fld_ae_sem_mul_x4_d1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_d0", FIELD_fld_ae_sem_mul_x4_d0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_q0", FIELD_fld_ae_sem_mul_x4_q0, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_q1", FIELD_fld_ae_sem_mul_x4_q1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x4_d2", FIELD_fld_ae_sem_mul_x4_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_d2", FIELD_fld_ae_sem_mul_x2_S1_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S1_v1", FIELD_fld_ae_sem_mul_x2_S1_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_d2", FIELD_fld_ae_sem_mul_x2_S2_d2, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_mul_x2_S2_v1", FIELD_fld_ae_sem_mul_x2_S2_v1, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_ep_ls_ei", FIELD_fld_ae_sem_ep_ls_ei, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_ep_ls_ar_s", FIELD_fld_ae_sem_ep_ls_ar_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_ae_sem_ep_ls_eo", FIELD_fld_ae_sem_ep_ls_eo, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_mul_x2_S1_acc_ep", FIELD_fld_ae_sem_mul_x2_S1_acc_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_mul_x2_S2_acc_ep", FIELD_fld_ae_sem_mul_x2_S2_acc_ep, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, + 0, + OperandSem_opnd_sem_opnd_ae_sem_shift_i8_encode, OperandSem_opnd_sem_opnd_ae_sem_shift_i8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, REGFILE_AE_EP, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_EP_encode, OperandSem_opnd_sem_AE_EP_decode, + 0, 0, + 0, 3 }, + { "opnd_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_cmov_bt", FIELD_fld_ae_sem_cmov_bt, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0, + 0, 15 }, + { "opnd_ae_sem_cmov_arr", FIELD_fld_ae_sem_cmov_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_vfpu2_sem_mov_vt", FIELD_fld_vfpu2_sem_mov_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_mov_vr", FIELD_fld_vfpu2_sem_mov_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spfma_vt", FIELD_fld_vfpu2_sem_spfma_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spfma_vs", FIELD_fld_vfpu2_sem_spfma_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spfma_vr", FIELD_fld_vfpu2_sem_spfma_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spmisc_brt", FIELD_fld_vfpu2_sem_spmisc_brt, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spmisc_vs", FIELD_fld_vfpu2_sem_spmisc_vs, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spmisc_vr", FIELD_fld_vfpu2_sem_spmisc_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_mov_i_imm4", FIELD_fld_vfpu2_sem_mov_i_imm4, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa16_encode, OperandSem_opnd_sem_ae_osa16_decode, + 0, 0, + -1, 0 }, + { "opnd_vfpu2_sem_spmisc_vt", FIELD_fld_vfpu2_sem_spmisc_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spmisc_vtM", FIELD_fld_vfpu2_sem_spmisc_vtM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_sp32cvt_vr", FIELD_fld_vfpu2_sem_sp32cvt_vr, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_sp32cvt_vt", FIELD_fld_vfpu2_sem_sp32cvt_vt, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_sp32cvt_i_imm5", FIELD_fld_vfpu2_sem_sp32cvt_i_imm5, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa32_encode, OperandSem_opnd_sem_ae_osa32_decode, + 0, 0, + -1, 0 }, + { "opnd_vfpu2_sem_sp32cvt_arr", FIELD_fld_vfpu2_sem_sp32cvt_arr, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_vfpu2_sem_spmisc_vsM", FIELD_fld_vfpu2_sem_spmisc_vsM, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_vfpu2_sem_spfma_i_imm1", FIELD_fld_vfpu2_sem_spfma_i_imm1, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa2_encode, OperandSem_opnd_sem_ae_osa2_decode, + 0, 0, + -1, 0 }, + { "opnd_vfpu2_sem_spfma_i_imm3", FIELD_fld_vfpu2_sem_spfma_i_imm3, -1, 0, + 0, + OperandSem_opnd_sem_ae_osa8_encode, OperandSem_opnd_sem_ae_osa8_decode, + 0, 0, + -1, 0 }, + { "opnd_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "dfp_fld_op2_2", FIELD_dfp_fld_op2_2, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_op2_1_0", FIELD_dfp_fld_op2_1_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_1_0_encode, OperandSem_opnd_sem_dfp_fld_op2_1_0_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_r_0", FIELD_dfp_fld_r_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_r_2_1", FIELD_dfp_fld_r_2_1, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_1_0_encode, OperandSem_opnd_sem_dfp_fld_op2_1_0_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_op2", FIELD_dfp_fld_op2, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_encode, OperandSem_opnd_sem_dfp_fld_op2_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_op2_0", FIELD_dfp_fld_op2_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0, + -1, 0 }, + { "dfp_fld_s_0", FIELD_dfp_fld_s_0, -1, 0, + 0, + OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode, + 0, 0, + -1, 0 }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, + 0, 0, + -1, 0 }, + { "opnd_SIGMOID_Q15_x", FIELD_fld_SIGMOID_Q15_x, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_SIGMOID_Q15_y", FIELD_fld_SIGMOID_Q15_y, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0, + 0, 31 }, + { "opnd_SIGMOID_FP32_x", FIELD_fld_SIGMOID_FP32_x, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "opnd_SIGMOID_FP32_y", FIELD_fld_SIGMOID_FP32_y, REGFILE_AE_DR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_DR_encode, OperandSem_opnd_sem_AE_DR_decode, + 0, 0, + 0, 15 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 }, + { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, + { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, + { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, + { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_fhba4", FIELD_ae_fld_fhba4, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_fhba4_2", FIELD_ae_fld_fhba4_2, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_tp7", FIELD_ae_fld_tp7, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_osa32", FIELD_ae_fld_osa32, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_osa64", FIELD_ae_fld_osa64, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_imm2", FIELD_ae_fld_imm2, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls64", FIELD_ae_fld_immls64, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls64pos", FIELD_ae_fld_immls64pos, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls64half", FIELD_ae_fld_immls64half, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls32", FIELD_ae_fld_immls32, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_immls16", FIELD_ae_fld_immls16, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_osa16", FIELD_ae_fld_osa16, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_15_12", FIELD_Inst_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_11_8", FIELD_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_7_4", FIELD_Inst_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_12", FIELD_Inst_12, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_7", FIELD_Inst_7, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_5_4", FIELD_Inst_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_7_6", FIELD_Inst_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_19_17", FIELD_Inst_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_19_18", FIELD_Inst_19_18, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_9_8", FIELD_Inst_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "Inst_4", FIELD_Inst_4, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_v", FIELD_ae_fld_ls_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_uu", FIELD_ae_fld_ls_uu, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_su", FIELD_ae_fld_ls_su, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_av", FIELD_ae_fld_ls_av, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_v1", FIELD_ae_fld_ls_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ls_v2", FIELD_ae_fld_ls_v2, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmpp_v0", FIELD_ae_fld_cmpp_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmpp_v1", FIELD_ae_fld_cmpp_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmpp_v", FIELD_ae_fld_cmpp_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_uu_v", FIELD_ae_fld_uu_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_uu_uu", FIELD_ae_fld_uu_uu, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_dr_to_ar_v0", FIELD_ae_fld_dr_to_ar_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmov_v", FIELD_ae_fld_cmov_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_cmov_v0", FIELD_ae_fld_cmov_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_pks_d", FIELD_ae_fld_pks_d, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_pks_s", FIELD_ae_fld_pks_s, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_shift_d", FIELD_ae_fld_shift_d, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_shift_d0", FIELD_ae_fld_shift_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_shift_sd", FIELD_ae_fld_shift_sd, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_dr_to_dr_v", FIELD_ae_fld_dr_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_dr_to_dr_v0", FIELD_ae_fld_dr_to_dr_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_dr_to_dr_v1", FIELD_ae_fld_dr_to_dr_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_to_dr_v", FIELD_ae_fld_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_to_dr_v0", FIELD_ae_fld_to_dr_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_immls64neg", FIELD_fld_ae_immls64neg, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_selimm", FIELD_ae_fld_selimm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_selimm.N", FIELD_ae_fld_selimm_N, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ar_to_dr_imm", FIELD_fld_ar_to_dr_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_arth_v", FIELD_ae_fld_arth_v, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_arth_v0", FIELD_ae_fld_arth_v0, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_arth_v1", FIELD_ae_fld_arth_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ar_to_dr_v", FIELD_ae_fld_ar_to_dr_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_23_16", FIELD_fld_Inst_23_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_7", FIELD_fld_Inst_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_11_8", FIELD_fld_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_13_8", FIELD_fld_Inst_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_12_8", FIELD_fld_Inst_12_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_9_8", FIELD_fld_Inst_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_4_4", FIELD_fld_Inst_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_5_4", FIELD_fld_Inst_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_7_4", FIELD_fld_Inst_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_12", FIELD_ae_fld_Inst16b_12, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_Inst16b_15_13", FIELD_ae_fld_Inst16b_15_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_7_4", FIELD_fld_ae4_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_4", FIELD_fld_ae2_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_4", FIELD_fld_ae2_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_27_24", FIELD_fld_ae4_slot0_27_24, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_9", FIELD_fld_ae2_slot0_11_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_27", FIELD_fld_ae2_slot0_28_27, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_27_23", FIELD_fld_ae4_slot0_27_23, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_8", FIELD_fld_ae2_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_8", FIELD_fld_ae5_slot0_21_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_13_8", FIELD_fld_ae4_slot1_13_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_8", FIELD_fld_ae3_slot1_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_13_11", FIELD_fld_ae4_slot1_13_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_0", FIELD_fld_ae5_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_0", FIELD_fld_ae3_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_0", FIELD_fld_ae3_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_3_0", FIELD_fld_ae2_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_3_0", FIELD_fld_ae2_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_0", FIELD_fld_ae_slot0_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_3_0", FIELD_fld_ae_slot1_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_12", FIELD_fld_ae5_slot0_21_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_13_12", FIELD_fld_ae4_slot1_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_12", FIELD_fld_ae3_slot0_21_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_12", FIELD_fld_ae3_slot1_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_12", FIELD_fld_ae2_slot1_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_12", FIELD_fld_ae_slot1_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_16", FIELD_fld_ae5_slot0_21_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_16", FIELD_fld_ae3_slot0_21_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_16", FIELD_fld_ae3_slot1_19_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_16", FIELD_fld_ae2_slot1_19_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_16", FIELD_fld_ae_slot1_19_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_17", FIELD_fld_ae5_slot0_21_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_17", FIELD_fld_ae3_slot0_21_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_17", FIELD_fld_ae3_slot1_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_17", FIELD_fld_ae2_slot0_28_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_17", FIELD_fld_ae2_slot1_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_17", FIELD_fld_ae_slot1_19_17, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_20", FIELD_fld_ae5_slot0_21_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_20", FIELD_fld_ae3_slot0_21_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_20", FIELD_fld_ae2_slot0_28_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_4", FIELD_fld_ae5_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_4", FIELD_fld_ae3_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_15_0", FIELD_fld_ae7_slot0_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_15_0", FIELD_fld_ae7_slot1_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_18_0", FIELD_fld_ae7_slot2_18_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_18_0", FIELD_fld_ae7_slot3_18_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_15_0", FIELD_fld_ae6_slot0_15_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_0", FIELD_fld_ae6_slot1_14_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_13_0", FIELD_fld_ae6_slot2_13_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_17_0", FIELD_fld_ae6_slot3_17_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_0", FIELD_fld_ae5_slot0_21_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot1_0_0", FIELD_fld_ae5_slot1_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_19_0", FIELD_fld_ae5_slot2_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_2_0", FIELD_fld_ae4_slot0_2_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot0_27_3", FIELD_fld_ae4_slot0_27_3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae4_slot1_13_0", FIELD_fld_ae4_slot1_13_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_0", FIELD_fld_ae3_slot0_21_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_0", FIELD_fld_ae3_slot1_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_0", FIELD_fld_ae2_slot1_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_0", FIELD_fld_ae2_slot2_24_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_0", FIELD_fld_ae_slot0_20_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_0", FIELD_fld_ae_slot1_19_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_0", FIELD_fld_ae_slot2_20_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_4", FIELD_fld_ae3_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_13", FIELD_fld_ae5_slot0_21_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_13", FIELD_fld_ae3_slot0_21_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_13", FIELD_fld_ae3_slot1_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_13", FIELD_fld_ae2_slot0_28_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_13", FIELD_fld_ae2_slot1_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_15", FIELD_fld_ae_slot0_20_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_13", FIELD_fld_ae_slot1_19_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_13", FIELD_fld_ae_slot0_20_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_19_4", FIELD_fld_ae3_slot1_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_4", FIELD_fld_ae2_slot0_28_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_4", FIELD_fld_ae2_slot1_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_4", FIELD_fld_ae_slot0_20_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_4", FIELD_fld_ae_slot1_19_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_1", FIELD_fld_ae3_slot1_7_1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_9", FIELD_fld_ae2_slot1_19_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_9", FIELD_fld_ae_slot1_19_9, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_3_2", FIELD_fld_ae2_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_3_2", FIELD_fld_ae_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_0_0", FIELD_fld_ae2_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_0_0", FIELD_fld_ae_slot0_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_12", FIELD_fld_ae2_slot0_28_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_12", FIELD_fld_ae_slot0_20_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_4", FIELD_fld_ae7_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_4", FIELD_fld_ae7_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_11_8", FIELD_fld_ae5_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_11_8", FIELD_fld_ae3_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_6", FIELD_fld_ae5_slot0_21_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_loads_stores_end", FIELD_fld_ae_sem_loads_stores_end, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_4", FIELD_fld_ae2_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_4", FIELD_fld_ae_slot1_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_8", FIELD_fld_ae2_slot0_28_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_19_8", FIELD_fld_ae2_slot1_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_8", FIELD_fld_ae_slot0_20_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_19_8", FIELD_fld_ae_slot1_19_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_12", FIELD_fld_ae6_slot1_14_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_3_0", FIELD_fld_ae6_slot2_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ds", FIELD_fld_ae_sem_arithmetic_ds, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot3_17_16", FIELD_fld_ae6_slot3_17_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_0", FIELD_fld_ae_slot3_20_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_rng_d", FIELD_fld_ae_sem_rng_d, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_3_0", FIELD_fld_ae_slot3_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_8_8", FIELD_fld_ae3_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_8_8", FIELD_fld_ae_slot0_8_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_1_0", FIELD_fld_ae_slot3_1_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_11_0", FIELD_fld_ae2_slot0_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_0", FIELD_fld_ae_slot0_11_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_0", FIELD_fld_ae2_slot1_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_0", FIELD_fld_ae_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_28_16", FIELD_fld_ae2_slot0_28_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_16", FIELD_fld_ae_slot0_20_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_8", FIELD_fld_ae_slot3_20_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_9_4", FIELD_fld_ae2_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_4", FIELD_fld_ae_slot0_9_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_d1", FIELD_fld_ae_sem_mul_x2_S1_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_d0", FIELD_fld_ae_sem_mul_x2_S1_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_q0", FIELD_fld_ae_sem_mul_x2_S1_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_d1", FIELD_fld_ae_sem_mul_x2_S2_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_d0", FIELD_fld_ae_sem_mul_x2_S2_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_q0", FIELD_fld_ae_sem_mul_x2_S2_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_d1", FIELD_fld_ae_sem_mul_x4_d1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_d0", FIELD_fld_ae_sem_mul_x4_d0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_q0", FIELD_fld_ae_sem_mul_x4_q0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot2_13_12", FIELD_fld_ae6_slot2_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_q1", FIELD_fld_ae_sem_mul_x4_q1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_16", FIELD_fld_ae2_slot2_24_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x4_d2", FIELD_fld_ae_sem_mul_x4_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_24_20", FIELD_fld_ae2_slot2_24_20, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot2_18_16", FIELD_fld_ae7_slot2_18_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot2_7_4", FIELD_fld_ae2_slot2_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot3_18_16", FIELD_fld_ae7_slot3_18_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_d2", FIELD_fld_ae_sem_mul_x2_S1_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_v1", FIELD_fld_ae_sem_mul_x2_S1_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_d2", FIELD_fld_ae_sem_mul_x2_S2_d2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_v1", FIELD_fld_ae_sem_mul_x2_S2_v1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot2_19_12", FIELD_fld_ae5_slot2_19_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_12", FIELD_fld_ae_slot2_20_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_12", FIELD_fld_ae_slot3_20_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_4", FIELD_fld_ae5_slot0_21_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_ep_ls_ei", FIELD_fld_ae_sem_ep_ls_ei, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_3_2", FIELD_fld_ae3_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_3_2", FIELD_fld_ae3_slot1_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_ep_ls_ar_s", FIELD_fld_ae_sem_ep_ls_ar_s, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_ep_ls_eo", FIELD_fld_ae_sem_ep_ls_eo, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_7_0", FIELD_fld_ae_slot2_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_11_4", FIELD_fld_ae_slot3_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep", FIELD_fld_ae_sem_arithmetic_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_3_0", FIELD_fld_ae_slot2_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_ep1", FIELD_fld_ae_sem_arithmetic_ep1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_10", FIELD_fld_ae_slot2_20_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S1_acc_ep", FIELD_fld_ae_sem_mul_x2_S1_acc_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_14", FIELD_fld_ae_slot2_20_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_mul_x2_S2_acc_ep", FIELD_fld_ae_sem_mul_x2_S2_acc_ep, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_14", FIELD_fld_ae_slot3_20_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_e", FIELD_fld_ae_sem_shift_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_16", FIELD_fld_ae_slot3_20_16, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_shift_i8", FIELD_fld_ae_sem_shift_i8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_11_11", FIELD_fld_ae_slot3_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_arithmetic_e", FIELD_fld_ae_sem_arithmetic_e, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_9_8", FIELD_fld_ae_slot2_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_7_4", FIELD_fld_ae_slot3_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_8", FIELD_fld_ae_slot2_20_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_8", FIELD_fld_ae_slot0_11_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_4", FIELD_fld_ae_slot0_11_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_10", FIELD_fld_ae_slot3_20_10, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_7_4", FIELD_fld_ae_slot2_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_8_4", FIELD_fld_ae2_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_8_4", FIELD_fld_ae_slot0_8_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_6", FIELD_fld_ae5_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_4", FIELD_fld_ae3_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_6", FIELD_fld_ae3_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_6", FIELD_fld_ae2_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_6", FIELD_fld_ae_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_0", FIELD_fld_ae3_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_4_0", FIELD_fld_ae3_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_0", FIELD_fld_ae_slot0_4_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_9_8", FIELD_fld_ae3_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_9_8", FIELD_fld_ae_slot0_9_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_15_12", FIELD_fld_ae7_slot0_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_15_12", FIELD_fld_ae7_slot1_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_5_4", FIELD_fld_ae5_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_21_14", FIELD_fld_ae5_slot0_21_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_7_6", FIELD_fld_ae3_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_14", FIELD_fld_ae3_slot0_21_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_7", FIELD_fld_ae7_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot1_7_7", FIELD_fld_ae7_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_7_7", FIELD_fld_ae6_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_7_7", FIELD_fld_ae5_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_5", FIELD_fld_ae3_slot0_5_5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot1_7_7", FIELD_fld_ae3_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_4_4", FIELD_fld_ae2_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot1_7_7", FIELD_fld_ae2_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_4_4", FIELD_fld_ae_slot0_4_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot1_7_7", FIELD_fld_ae_slot1_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_15_12", FIELD_fld_ae6_slot0_15_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot0_7_7", FIELD_fld_ae6_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae7_slot0_7_6", FIELD_fld_ae7_slot0_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_7_6", FIELD_fld_ae6_slot1_7_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae6_slot1_14_6", FIELD_fld_ae6_slot1_14_6, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae5_slot0_3_2", FIELD_fld_ae5_slot0_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_5_2", FIELD_fld_ae3_slot0_5_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_5_2", FIELD_fld_ae2_slot0_5_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_2", FIELD_fld_ae_slot0_5_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_2", FIELD_fld_ae3_slot0_21_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_5_0", FIELD_fld_ae2_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_0_0", FIELD_fld_ae_slot3_0_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_3_2", FIELD_fld_ae_slot2_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_4", FIELD_fld_ae_slot0_7_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_0", FIELD_fld_ae2_slot0_7_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_7_7", FIELD_fld_ae2_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_7_7", FIELD_fld_ae_slot0_7_7, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_13", FIELD_fld_ae_slot3_20_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae2_slot0_5_4", FIELD_fld_ae2_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_4", FIELD_fld_ae_slot0_5_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_13_12", FIELD_fld_ae_slot3_13_12, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_8", FIELD_fld_ae3_slot0_21_8, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_20_14", FIELD_fld_ae_slot0_20_14, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_5_0", FIELD_fld_ae_slot0_5_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae3_slot0_21_4", FIELD_fld_ae3_slot0_21_4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_dr_to_ar_vr", FIELD_fld_ae_sem_dr_to_ar_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_cmov_bt", FIELD_fld_ae_sem_cmov_bt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_cmov_arr", FIELD_fld_ae_sem_cmov_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_mov_vt", FIELD_fld_vfpu2_sem_mov_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_mov_vr", FIELD_fld_vfpu2_sem_mov_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_vt", FIELD_fld_vfpu2_sem_spfma_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_vs", FIELD_fld_vfpu2_sem_spfma_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_vr", FIELD_fld_vfpu2_sem_spfma_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_brt", FIELD_fld_vfpu2_sem_spmisc_brt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vs", FIELD_fld_vfpu2_sem_spmisc_vs, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vr", FIELD_fld_vfpu2_sem_spmisc_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_mov_i_imm4", FIELD_fld_vfpu2_sem_mov_i_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_sp32cvt_vr", FIELD_fld_vfpu2_sem_sp32cvt_vr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_sp32cvt_vt", FIELD_fld_vfpu2_sem_sp32cvt_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_sp32cvt_i_imm5", FIELD_fld_vfpu2_sem_sp32cvt_i_imm5, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_sp32cvt_arr", FIELD_fld_vfpu2_sem_sp32cvt_arr, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot0_11_11", FIELD_fld_ae_slot0_11_11, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vt", FIELD_fld_vfpu2_sem_spmisc_vt, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vsM", FIELD_fld_vfpu2_sem_spmisc_vsM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_18", FIELD_fld_ae_slot2_20_18, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spmisc_vtM", FIELD_fld_vfpu2_sem_spmisc_vtM, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_i_imm1", FIELD_fld_vfpu2_sem_spfma_i_imm1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_vfpu2_sem_spfma_i_imm3", FIELD_fld_vfpu2_sem_spfma_i_imm3, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_13", FIELD_fld_ae_slot2_20_13, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot3_20_15", FIELD_fld_ae_slot3_20_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_15", FIELD_fld_ae_slot2_20_15, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_sem_movfpstate_v", FIELD_fld_ae_sem_movfpstate_v, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_ae_slot2_20_4", FIELD_fld_ae_slot2_20_4, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op1", FIELD_dfp_fld_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_r_3", FIELD_dfp_fld_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_r_3_1", FIELD_dfp_fld_r_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_s_3_1", FIELD_dfp_fld_s_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op2_3", FIELD_dfp_fld_op2_3, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op2_3_2", FIELD_dfp_fld_op2_3_2, -1, 0, 0, 0, 0, 0, 0 }, + { "dfp_fld_op2_3_1", FIELD_dfp_fld_op2_3_1, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_SIGMOID_Q15_x", FIELD_fld_SIGMOID_Q15_x, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_SIGMOID_Q15_y", FIELD_fld_SIGMOID_Q15_y, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_Inst_3_0", FIELD_fld_Inst_3_0, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_SIGMOID_FP32_x", FIELD_fld_SIGMOID_FP32_x, -1, 0, 0, 0, 0, 0, 0 }, + { "fld_SIGMOID_FP32_y", FIELD_fld_SIGMOID_FP32_y, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_immr, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_immt, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_mx, + OPERAND_my, + OPERAND_mw, + OPERAND_mr0, + OPERAND_mr1, + OPERAND_mr2, + OPERAND_mr3, + OPERAND_imms, + OPERAND_imms1, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_ae_immls64neg, + OPERAND_ae_immls64half, + OPERAND_ae_ohba, + OPERAND_ae_ohba2, + OPERAND_ae_opnd_tp7, + OPERAND_ae_imm2, + OPERAND_ae_osa32, + OPERAND_ae_osa64, + OPERAND_ae_immls64, + OPERAND_ae_immls64pos, + OPERAND_ae_immls32, + OPERAND_ae_immls16, + OPERAND_ae_osa16, + OPERAND_ae_selimm, + OPERAND_ae_selimm_N, + OPERAND_movi_imm, + OPERAND_ae_arth_v, + OPERAND_ae_arth_v0, + OPERAND_ae_arth_v1, + OPERAND_ae_ar_to_dr_v, + OPERAND_ae_to_dr_v, + OPERAND_ae_to_dr_v0, + OPERAND_ae_dr_to_dr_v, + OPERAND_ae_dr_to_dr_v0, + OPERAND_ae_dr_to_dr_v1, + OPERAND_ae_ls_v, + OPERAND_ae_ls_av, + OPERAND_ae_ls_v1, + OPERAND_ae_ls_v2, + OPERAND_ae_ls_uu, + OPERAND_ae_ls_su, + OPERAND_ae_uu_v, + OPERAND_ae_uu_uu, + OPERAND_ae_dr_to_ar_v0, + OPERAND_ae_cmov_v, + OPERAND_ae_cmov_v0, + OPERAND_ae_pks_d, + OPERAND_ae_pks_s, + OPERAND_ae_shift_d, + OPERAND_ae_shift_d0, + OPERAND_ae_shift_sd, + OPERAND_ae_uimm2x2, + OPERAND_opnd_ae_sem_loads_stores_end, + OPERAND_opnd_ae_sem_arithmetic_ds, + OPERAND_opnd_ae_sem_rng_d, + OPERAND_opnd_ae_sem_mul_x2_S1_d1, + OPERAND_opnd_ae_sem_mul_x2_S1_d0, + OPERAND_opnd_ae_sem_mul_x2_S1_q0, + OPERAND_opnd_ae_sem_mul_x2_S2_d1, + OPERAND_opnd_ae_sem_mul_x2_S2_d0, + OPERAND_opnd_ae_sem_mul_x2_S2_q0, + OPERAND_opnd_ae_sem_mul_x4_d1, + OPERAND_opnd_ae_sem_mul_x4_d0, + OPERAND_opnd_ae_sem_mul_x4_q0, + OPERAND_opnd_ae_sem_mul_x4_q1, + OPERAND_opnd_ae_sem_mul_x4_d2, + OPERAND_opnd_ae_sem_mul_x2_S1_d2, + OPERAND_opnd_ae_sem_mul_x2_S1_v1, + OPERAND_opnd_ae_sem_mul_x2_S2_d2, + OPERAND_opnd_ae_sem_mul_x2_S2_v1, + OPERAND_opnd_ae_sem_ep_ls_ei, + OPERAND_opnd_ae_sem_ep_ls_ar_s, + OPERAND_opnd_ae_sem_ep_ls_eo, + OPERAND_opnd_ae_sem_arithmetic_ep, + OPERAND_opnd_ae_sem_arithmetic_ep1, + OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep, + OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep, + OPERAND_opnd_ae_sem_shift_e, + OPERAND_opnd_ae_sem_shift_i8, + OPERAND_opnd_ae_sem_arithmetic_e, + OPERAND_opnd_ae_sem_dr_to_ar_vr, + OPERAND_opnd_ae_sem_cmov_bt, + OPERAND_opnd_ae_sem_cmov_arr, + OPERAND_opnd_vfpu2_sem_mov_vt, + OPERAND_opnd_vfpu2_sem_mov_vr, + OPERAND_opnd_vfpu2_sem_spfma_vt, + OPERAND_opnd_vfpu2_sem_spfma_vs, + OPERAND_opnd_vfpu2_sem_spfma_vr, + OPERAND_opnd_vfpu2_sem_spmisc_brt, + OPERAND_opnd_vfpu2_sem_spmisc_vs, + OPERAND_opnd_vfpu2_sem_spmisc_vr, + OPERAND_opnd_vfpu2_sem_mov_i_imm4, + OPERAND_opnd_vfpu2_sem_spmisc_vt, + OPERAND_opnd_vfpu2_sem_spmisc_vtM, + OPERAND_opnd_vfpu2_sem_sp32cvt_vr, + OPERAND_opnd_vfpu2_sem_sp32cvt_vt, + OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5, + OPERAND_opnd_vfpu2_sem_sp32cvt_arr, + OPERAND_opnd_vfpu2_sem_spmisc_vsM, + OPERAND_opnd_vfpu2_sem_spfma_i_imm1, + OPERAND_opnd_vfpu2_sem_spfma_i_imm3, + OPERAND_opnd_ae_sem_movfpstate_v, + OPERAND_dfp_fld_op2_2, + OPERAND_dfp_fld_op2_1_0, + OPERAND_dfp_fld_r_0, + OPERAND_dfp_fld_r_2_1, + OPERAND_dfp_fld_op2, + OPERAND_dfp_fld_op2_0, + OPERAND_dfp_fld_s_0, + OPERAND_bitindex, + OPERAND_opnd_SIGMOID_Q15_x, + OPERAND_opnd_SIGMOID_Q15_y, + OPERAND_opnd_SIGMOID_FP32_x, + OPERAND_opnd_SIGMOID_FP32_y, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_r_disp, + OPERAND_r_3, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_r3, + OPERAND_rbit2, + OPERAND_rhi, + OPERAND_t3, + OPERAND_tbit2, + OPERAND_tlo, + OPERAND_w, + OPERAND_y, + OPERAND_x, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_s8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_ae_fld_fhba4, + OPERAND_ae_fld_fhba4_2, + OPERAND_ae_fld_tp7, + OPERAND_ae_fld_osa32, + OPERAND_ae_fld_osa64, + OPERAND_ae_fld_imm2, + OPERAND_ae_fld_immls64, + OPERAND_ae_fld_immls64pos, + OPERAND_ae_fld_immls64half, + OPERAND_ae_fld_immls32, + OPERAND_ae_fld_immls16, + OPERAND_ae_fld_osa16, + OPERAND_Inst_15_12, + OPERAND_Inst_11_8, + OPERAND_Inst_7_4, + OPERAND_Inst_12, + OPERAND_Inst_7, + OPERAND_Inst_5_4, + OPERAND_Inst_7_6, + OPERAND_Inst_19_17, + OPERAND_Inst_19_18, + OPERAND_Inst_9_8, + OPERAND_Inst_4, + OPERAND_ae_fld_ls_v, + OPERAND_ae_fld_ls_uu, + OPERAND_ae_fld_ls_su, + OPERAND_ae_fld_ls_av, + OPERAND_ae_fld_ls_v1, + OPERAND_ae_fld_ls_v2, + OPERAND_ae_fld_cmpp_v0, + OPERAND_ae_fld_cmpp_v1, + OPERAND_ae_fld_cmpp_v, + OPERAND_ae_fld_uu_v, + OPERAND_ae_fld_uu_uu, + OPERAND_ae_fld_dr_to_ar_v0, + OPERAND_ae_fld_cmov_v, + OPERAND_ae_fld_cmov_v0, + OPERAND_ae_fld_pks_d, + OPERAND_ae_fld_pks_s, + OPERAND_ae_fld_shift_d, + OPERAND_ae_fld_shift_d0, + OPERAND_ae_fld_shift_sd, + OPERAND_ae_fld_dr_to_dr_v, + OPERAND_ae_fld_dr_to_dr_v0, + OPERAND_ae_fld_dr_to_dr_v1, + OPERAND_ae_fld_to_dr_v, + OPERAND_ae_fld_to_dr_v0, + OPERAND_fld_ae_immls64neg, + OPERAND_ae_fld_selimm, + OPERAND_ae_fld_selimm_N, + OPERAND_fld_ar_to_dr_imm, + OPERAND_ae_fld_arth_v, + OPERAND_ae_fld_arth_v0, + OPERAND_ae_fld_arth_v1, + OPERAND_ae_fld_ar_to_dr_v, + OPERAND_fld_Inst_23_12, + OPERAND_fld_Inst_23_16, + OPERAND_fld_Inst_7_7, + OPERAND_fld_Inst_11_8, + OPERAND_fld_Inst_13_8, + OPERAND_fld_Inst_12_8, + OPERAND_fld_Inst_9_8, + OPERAND_fld_Inst_4_4, + OPERAND_fld_Inst_5_4, + OPERAND_fld_Inst_7_4, + OPERAND_ae_fld_Inst16b_12, + OPERAND_ae_fld_Inst16b_15_13, + OPERAND_fld_ae4_slot0_7_4, + OPERAND_fld_ae2_slot0_11_4, + OPERAND_fld_ae2_slot0_7_4, + OPERAND_fld_ae4_slot0_27_24, + OPERAND_fld_ae2_slot0_11_9, + OPERAND_fld_ae2_slot0_28_27, + OPERAND_fld_ae4_slot0_27_23, + OPERAND_fld_ae2_slot0_11_8, + OPERAND_fld_ae5_slot0_21_8, + OPERAND_fld_ae4_slot1_13_8, + OPERAND_fld_ae3_slot1_19_8, + OPERAND_fld_ae4_slot1_13_11, + OPERAND_fld_ae5_slot0_3_0, + OPERAND_fld_ae3_slot0_3_0, + OPERAND_fld_ae3_slot1_3_0, + OPERAND_fld_ae2_slot0_3_0, + OPERAND_fld_ae2_slot1_3_0, + OPERAND_fld_ae_slot0_3_0, + OPERAND_fld_ae_slot1_3_0, + OPERAND_fld_ae5_slot0_21_12, + OPERAND_fld_ae4_slot1_13_12, + OPERAND_fld_ae3_slot0_21_12, + OPERAND_fld_ae3_slot1_19_12, + OPERAND_fld_ae2_slot1_19_12, + OPERAND_fld_ae_slot1_19_12, + OPERAND_fld_ae5_slot0_21_16, + OPERAND_fld_ae3_slot0_21_16, + OPERAND_fld_ae3_slot1_19_16, + OPERAND_fld_ae2_slot1_19_16, + OPERAND_fld_ae_slot1_19_16, + OPERAND_fld_ae5_slot0_21_17, + OPERAND_fld_ae3_slot0_21_17, + OPERAND_fld_ae3_slot1_19_17, + OPERAND_fld_ae2_slot0_28_17, + OPERAND_fld_ae2_slot1_19_17, + OPERAND_fld_ae_slot1_19_17, + OPERAND_fld_ae5_slot0_21_20, + OPERAND_fld_ae3_slot0_21_20, + OPERAND_fld_ae2_slot0_28_20, + OPERAND_fld_ae5_slot0_7_4, + OPERAND_fld_ae3_slot0_7_4, + OPERAND_fld_ae7_slot0_15_0, + OPERAND_fld_ae7_slot1_15_0, + OPERAND_fld_ae7_slot2_18_0, + OPERAND_fld_ae7_slot3_18_0, + OPERAND_fld_ae6_slot0_15_0, + OPERAND_fld_ae6_slot1_14_0, + OPERAND_fld_ae6_slot2_13_0, + OPERAND_fld_ae6_slot3_17_0, + OPERAND_fld_ae5_slot0_21_0, + OPERAND_fld_ae5_slot1_0_0, + OPERAND_fld_ae5_slot2_19_0, + OPERAND_fld_ae4_slot0_2_0, + OPERAND_fld_ae4_slot0_27_3, + OPERAND_fld_ae4_slot1_13_0, + OPERAND_fld_ae3_slot0_21_0, + OPERAND_fld_ae3_slot1_19_0, + OPERAND_fld_ae2_slot1_19_0, + OPERAND_fld_ae2_slot2_24_0, + OPERAND_fld_ae_slot0_20_0, + OPERAND_fld_ae_slot1_19_0, + OPERAND_fld_ae_slot2_20_0, + OPERAND_fld_ae3_slot1_7_4, + OPERAND_fld_ae5_slot0_21_13, + OPERAND_fld_ae3_slot0_21_13, + OPERAND_fld_ae3_slot1_19_13, + OPERAND_fld_ae2_slot0_28_13, + OPERAND_fld_ae2_slot1_19_13, + OPERAND_fld_ae_slot0_20_15, + OPERAND_fld_ae_slot1_19_13, + OPERAND_fld_ae_slot0_20_13, + OPERAND_fld_ae3_slot1_19_4, + OPERAND_fld_ae2_slot0_28_4, + OPERAND_fld_ae2_slot1_19_4, + OPERAND_fld_ae_slot0_20_4, + OPERAND_fld_ae_slot1_19_4, + OPERAND_fld_ae3_slot1_7_1, + OPERAND_fld_ae2_slot1_19_9, + OPERAND_fld_ae_slot1_19_9, + OPERAND_fld_ae2_slot0_3_2, + OPERAND_fld_ae_slot0_3_2, + OPERAND_fld_ae2_slot0_0_0, + OPERAND_fld_ae_slot0_0_0, + OPERAND_fld_ae2_slot0_28_12, + OPERAND_fld_ae_slot0_20_12, + OPERAND_fld_ae7_slot0_7_4, + OPERAND_fld_ae7_slot1_7_4, + OPERAND_fld_ae5_slot0_11_8, + OPERAND_fld_ae3_slot0_11_8, + OPERAND_fld_ae5_slot0_21_6, + OPERAND_fld_ae_sem_loads_stores_end, + OPERAND_fld_ae2_slot1_7_4, + OPERAND_fld_ae_slot1_7_4, + OPERAND_fld_ae2_slot0_28_8, + OPERAND_fld_ae2_slot1_19_8, + OPERAND_fld_ae_slot0_20_8, + OPERAND_fld_ae_slot1_19_8, + OPERAND_fld_ae6_slot1_14_12, + OPERAND_fld_ae6_slot2_3_0, + OPERAND_fld_ae_sem_arithmetic_ds, + OPERAND_fld_ae6_slot3_17_16, + OPERAND_fld_ae_slot3_20_0, + OPERAND_fld_ae_sem_rng_d, + OPERAND_fld_ae_slot3_3_0, + OPERAND_fld_ae3_slot0_8_8, + OPERAND_fld_ae_slot0_8_8, + OPERAND_fld_ae_slot3_1_0, + OPERAND_fld_ae2_slot0_11_0, + OPERAND_fld_ae_slot0_11_0, + OPERAND_fld_ae2_slot1_7_0, + OPERAND_fld_ae_slot0_7_0, + OPERAND_fld_ae2_slot0_28_16, + OPERAND_fld_ae_slot0_20_16, + OPERAND_fld_ae_slot3_20_8, + OPERAND_fld_ae2_slot0_9_4, + OPERAND_fld_ae_slot0_9_4, + OPERAND_fld_ae_sem_mul_x2_S1_d1, + OPERAND_fld_ae_sem_mul_x2_S1_d0, + OPERAND_fld_ae_sem_mul_x2_S1_q0, + OPERAND_fld_ae_sem_mul_x2_S2_d1, + OPERAND_fld_ae_sem_mul_x2_S2_d0, + OPERAND_fld_ae_sem_mul_x2_S2_q0, + OPERAND_fld_ae_sem_mul_x4_d1, + OPERAND_fld_ae_sem_mul_x4_d0, + OPERAND_fld_ae_sem_mul_x4_q0, + OPERAND_fld_ae6_slot2_13_12, + OPERAND_fld_ae_sem_mul_x4_q1, + OPERAND_fld_ae2_slot2_24_16, + OPERAND_fld_ae_sem_mul_x4_d2, + OPERAND_fld_ae2_slot2_24_20, + OPERAND_fld_ae7_slot2_18_16, + OPERAND_fld_ae2_slot2_7_4, + OPERAND_fld_ae7_slot3_18_16, + OPERAND_fld_ae_sem_mul_x2_S1_d2, + OPERAND_fld_ae_sem_mul_x2_S1_v1, + OPERAND_fld_ae_sem_mul_x2_S2_d2, + OPERAND_fld_ae_sem_mul_x2_S2_v1, + OPERAND_fld_ae5_slot2_19_12, + OPERAND_fld_ae_slot2_20_12, + OPERAND_fld_ae_slot3_20_12, + OPERAND_fld_ae5_slot0_21_4, + OPERAND_fld_ae_sem_ep_ls_ei, + OPERAND_fld_ae3_slot0_3_2, + OPERAND_fld_ae3_slot1_3_2, + OPERAND_fld_ae_sem_ep_ls_ar_s, + OPERAND_fld_ae_sem_ep_ls_eo, + OPERAND_fld_ae_slot2_7_0, + OPERAND_fld_ae_slot3_11_4, + OPERAND_fld_ae_sem_arithmetic_ep, + OPERAND_fld_ae_slot2_3_0, + OPERAND_fld_ae_sem_arithmetic_ep1, + OPERAND_fld_ae_slot2_20_10, + OPERAND_fld_ae_sem_mul_x2_S1_acc_ep, + OPERAND_fld_ae_slot2_20_14, + OPERAND_fld_ae_sem_mul_x2_S2_acc_ep, + OPERAND_fld_ae_slot3_20_14, + OPERAND_fld_ae_sem_shift_e, + OPERAND_fld_ae_slot3_20_16, + OPERAND_fld_ae_sem_shift_i8, + OPERAND_fld_ae_slot3_11_11, + OPERAND_fld_ae_sem_arithmetic_e, + OPERAND_fld_ae_slot2_9_8, + OPERAND_fld_ae_slot3_7_4, + OPERAND_fld_ae_slot2_20_8, + OPERAND_fld_ae_slot0_11_8, + OPERAND_fld_ae_slot0_11_4, + OPERAND_fld_ae_slot3_20_10, + OPERAND_fld_ae_slot2_7_4, + OPERAND_fld_ae2_slot0_8_4, + OPERAND_fld_ae_slot0_8_4, + OPERAND_fld_ae5_slot0_7_6, + OPERAND_fld_ae3_slot0_5_4, + OPERAND_fld_ae3_slot1_7_6, + OPERAND_fld_ae2_slot1_7_6, + OPERAND_fld_ae_slot1_7_6, + OPERAND_fld_ae3_slot0_5_0, + OPERAND_fld_ae3_slot0_4_0, + OPERAND_fld_ae_slot0_4_0, + OPERAND_fld_ae3_slot0_9_8, + OPERAND_fld_ae_slot0_9_8, + OPERAND_fld_ae7_slot0_15_12, + OPERAND_fld_ae7_slot1_15_12, + OPERAND_fld_ae5_slot0_5_4, + OPERAND_fld_ae5_slot0_21_14, + OPERAND_fld_ae3_slot0_7_6, + OPERAND_fld_ae3_slot0_21_14, + OPERAND_fld_ae7_slot0_7_7, + OPERAND_fld_ae7_slot1_7_7, + OPERAND_fld_ae6_slot1_7_7, + OPERAND_fld_ae5_slot0_7_7, + OPERAND_fld_ae3_slot0_5_5, + OPERAND_fld_ae3_slot1_7_7, + OPERAND_fld_ae2_slot0_4_4, + OPERAND_fld_ae2_slot1_7_7, + OPERAND_fld_ae_slot0_4_4, + OPERAND_fld_ae_slot1_7_7, + OPERAND_fld_ae6_slot0_15_12, + OPERAND_fld_ae6_slot0_7_7, + OPERAND_fld_ae7_slot0_7_6, + OPERAND_fld_ae6_slot1_7_6, + OPERAND_fld_ae6_slot1_14_6, + OPERAND_fld_ae5_slot0_3_2, + OPERAND_fld_ae3_slot0_5_2, + OPERAND_fld_ae2_slot0_5_2, + OPERAND_fld_ae_slot0_5_2, + OPERAND_fld_ae3_slot0_21_2, + OPERAND_fld_ae2_slot0_5_0, + OPERAND_fld_ae_slot3_0_0, + OPERAND_fld_ae_slot2_3_2, + OPERAND_fld_ae_slot0_7_4, + OPERAND_fld_ae2_slot0_7_0, + OPERAND_fld_ae2_slot0_7_7, + OPERAND_fld_ae_slot0_7_7, + OPERAND_fld_ae_slot3_20_13, + OPERAND_fld_ae2_slot0_5_4, + OPERAND_fld_ae_slot0_5_4, + OPERAND_fld_ae_slot3_13_12, + OPERAND_fld_ae3_slot0_21_8, + OPERAND_fld_ae_slot0_20_14, + OPERAND_fld_ae_slot0_5_0, + OPERAND_fld_ae3_slot0_21_4, + OPERAND_fld_ae_sem_dr_to_ar_vr, + OPERAND_fld_ae_sem_cmov_bt, + OPERAND_fld_ae_sem_cmov_arr, + OPERAND_fld_vfpu2_sem_mov_vt, + OPERAND_fld_vfpu2_sem_mov_vr, + OPERAND_fld_vfpu2_sem_spfma_vt, + OPERAND_fld_vfpu2_sem_spfma_vs, + OPERAND_fld_vfpu2_sem_spfma_vr, + OPERAND_fld_vfpu2_sem_spmisc_brt, + OPERAND_fld_vfpu2_sem_spmisc_vs, + OPERAND_fld_vfpu2_sem_spmisc_vr, + OPERAND_fld_vfpu2_sem_mov_i_imm4, + OPERAND_fld_vfpu2_sem_sp32cvt_vr, + OPERAND_fld_vfpu2_sem_sp32cvt_vt, + OPERAND_fld_vfpu2_sem_sp32cvt_i_imm5, + OPERAND_fld_vfpu2_sem_sp32cvt_arr, + OPERAND_fld_ae_slot0_11_11, + OPERAND_fld_vfpu2_sem_spmisc_vt, + OPERAND_fld_vfpu2_sem_spmisc_vsM, + OPERAND_fld_ae_slot2_20_18, + OPERAND_fld_vfpu2_sem_spmisc_vtM, + OPERAND_fld_vfpu2_sem_spfma_i_imm1, + OPERAND_fld_vfpu2_sem_spfma_i_imm3, + OPERAND_fld_ae_slot2_20_13, + OPERAND_fld_ae_slot3_20_15, + OPERAND_fld_ae_slot2_20_15, + OPERAND_fld_ae_sem_movfpstate_v, + OPERAND_fld_ae_slot2_20_4, + OPERAND_dfp_fld_op1, + OPERAND_dfp_fld_r_3, + OPERAND_dfp_fld_r_3_1, + OPERAND_dfp_fld_s_3_1, + OPERAND_dfp_fld_op2_3, + OPERAND_dfp_fld_op2_3_2, + OPERAND_dfp_fld_op2_3_1, + OPERAND_s3to1, + OPERAND_fld_SIGMOID_Q15_x, + OPERAND_fld_SIGMOID_Q15_y, + OPERAND_fld_Inst_3_0, + OPERAND_fld_SIGMOID_FP32_x, + OPERAND_fld_SIGMOID_FP32_y +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSEXCM }, 'o' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = { + { { STATE_MEMCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32h_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpfb_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpdngrd_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { + { { STATE_PREFCTL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERI_RAW_INTERLOCK }, 'i' } +}; + +static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { + INTERFACE_ERI_RD_In, + INTERFACE_ERI_RD_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERI_RAW_INTERLOCK }, 'o' } +}; + +static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { + INTERFACE_ERI_WR_In, + INTERFACE_ERI_WR_Out +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_1_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_3_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wb15_4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_xt_wbr15_label }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { + { { STATE_AE_BITHEAD }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cw_sd_no_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { + { { STATE_AE_CEND0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cbegin1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_ae_cend1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_sext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_zext16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_ic_clamps16_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ITER_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2_1_0 }, 'i' }, + { { OPERAND_dfp_fld_op2_2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ITER_stateArgs[] = { + { { STATE_F64R }, 'm' }, + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64RND_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2_1_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64RND_stateArgs[] = { + { { STATE_F64R }, 'm' }, + { { STATE_F64S }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ADDC_F64SUBC_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dfp_fld_r_2_1 }, 'i' }, + { { OPERAND_dfp_fld_r_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64ADDC_F64SUBC_stateArgs[] = { + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64SIG_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPL_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPL_stateArgs[] = { + { { STATE_F64S }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPH_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64CMPH_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_F64R }, 'o' }, + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64NORM_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_op2_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_F64NORM_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_F64S }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_F64SEXP_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RF64R_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_dfp_fld_s_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RF64R_stateArgs[] = { + { { STATE_F64R }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WF64R_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dfp_fld_r_0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WF64R_stateArgs[] = { + { { STATE_F64R }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_lo_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_lo_stateArgs[] = { + { { STATE_F64R }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_lo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_lo_stateArgs[] = { + { { STATE_F64R }, 'm' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_hi_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64r_hi_stateArgs[] = { + { { STATE_F64R }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_hi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64r_hi_stateArgs[] = { + { { STATE_F64R }, 'm' } +}; + +static xtensa_arg_internal Iclass_rur_f64s_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_f64s_stateArgs[] = { + { { STATE_F64S }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64s_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_f64s_stateArgs[] = { + { { STATE_F64S }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_OVERFLOW_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SAR_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITPTR_stateArgs[] = { + { { STATE_AE_BITPTR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_BITSUSED_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_TABLESIZE_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_FIRST_TS_stateArgs[] = { + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_NEXTOFFSET_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_SEARCHDONE_stateArgs[] = { + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_RUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WUR_AE_CWRAP_stateArgs[] = { + { { STATE_AE_CWRAP }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L8X4F_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64neg }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64half }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_args[] = { + { { OPERAND_ae_ls_v }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X2M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2F24_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_I_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_IP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_X_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RNG_XP_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64pos }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16X4_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16M_L_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32F24_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32_L_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16_0_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S64_XP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_IU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32M_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_args[] = { + { { OPERAND_ae_uu_uu }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_ZALIGN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_args[] = { + { { OPERAND_ae_ls_su }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SALIGN64_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_args[] = { + { { OPERAND_ae_uu_uu }, 'o' }, + { { OPERAND_ae_uu_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVALIGN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA64_PP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4POS_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_args[] = { + { { OPERAND_ae_ls_uu }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4NEG_PC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_args[] = { + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64POS_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_args[] = { + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA64NEG_FP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_args[] = { + { { OPERAND_ae_ls_av }, 'o' }, + { { OPERAND_ae_ls_uu }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_LA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA16X4_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA32X2F24_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24_L_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_IP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_args[] = { + { { OPERAND_ae_ls_v }, 'i' }, + { { OPERAND_ae_ls_su }, 'm' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SA24X2_RIC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDICIRC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_opnd_ae_sem_loads_stores_end }, 'i' }, + { { OPERAND_ae_immls64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDCIRC_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_I_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_immls32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_X_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC_stateArgs[] = { + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_args[] = { + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24RA64S_XC1_stateArgs[] = { + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_args[] = { + { { OPERAND_ae_ls_v2 }, 'i' }, + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S32X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_args[] = { + { { OPERAND_ae_ls_v2 }, 'i' }, + { { OPERAND_ae_ls_v1 }, 'i' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_S24X2RA64S_IP_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDBRBA32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_BITSWAP_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32JS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_ds }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDANDSUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBRNG32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG3_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG2_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CALCRNG1_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_args[] = { + { { OPERAND_opnd_ae_sem_rng_d }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_RNG32X2_stateArgs[] = { + { { STATE_AE_SAR }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ae_selimm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' }, + { { OPERAND_ae_selimm_N }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEL16I_N_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHORTSWAP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB4_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB2_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA1X2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVBA2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB2_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVB4_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARA7X2_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_args[] = { + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVSARD7_stateArgs[] = { + { { STATE_AE_SAR }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVASAR_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVDA16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_movi_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24A32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT16X4_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT32X2F16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32X2D16_10_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTA32F24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTP24A16X2_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP24Q48X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_shift_sd }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_shift_sd }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32X2F64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_shift_sd }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_shift_sd }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCI32F64S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCP16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F64SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND32X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' }, + { { OPERAND_ae_arth_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' }, + { { OPERAND_ae_arth_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND16X4F32SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SSYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUND24X2F48SASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSP16F24ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_args[] = { + { { OPERAND_ae_to_dr_v }, 'o' }, + { { OPERAND_ae_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOV_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVF64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56A32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64A32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVTQ56P32S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT64F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_CVT48F32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT48S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SATQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MINABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAXABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48SYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ROUNDSQ32F48ASYM_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA32Q48_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAD16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRA64_32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_args[] = { + { { OPERAND_ae_pks_d }, 'm' }, + { { OPERAND_ae_pks_s }, 'i' }, + { { OPERAND_ae_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_args[] = { + { { OPERAND_ae_pks_d }, 'm' }, + { { OPERAND_ae_pks_s }, 'i' }, + { { OPERAND_ae_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSR24_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_args[] = { + { { OPERAND_ae_pks_d }, 'm' }, + { { OPERAND_ae_pks_s }, 'i' }, + { { OPERAND_ae_imm2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_PKSRF32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_TRUNCA16P24S_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSUB32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBADD32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS32S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS16S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_args[] = { + { { OPERAND_br4 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_args[] = { + { { OPERAND_br2 }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADDSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUBSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEGSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABSSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NEG64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ABS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_AND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NAND_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_OR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_dr_to_dr_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_XOR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI24_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS24_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI16R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI32R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS32_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA16RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS24S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA32RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLSQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRASQ56_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAAQ56_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAS64_stateArgs[] = { + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRLA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAISQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLASSQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAASQ56S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAS64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_AE_SAR }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAA64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LT64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LE64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_EQ64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MAX64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_ae_arth_v0 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MIN64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSA64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ16_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_dr_to_ar_v0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_NSAZ32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32F48P16S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32RA_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32R_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAS32F48P16S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32RA_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32R_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSS32F48P16S_HH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32RA_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32R_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32U_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_33_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_32_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_21_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_31_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_30_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_10_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_20_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_11_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16SS_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_33_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_32_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_21_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_31_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_30_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_10_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_20_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_11_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16SS_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_33_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_32_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_21_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_31_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_30_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_10_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_20_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_11_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16SS_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_33_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_13_02_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD16SS_11_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_33_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_13_02_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD16SS_11_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_33_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_13_02_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD16SS_11_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_33_22_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_13_02_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD16SS_11_00_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF48Q32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULQ32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF48Q32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAQ32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF48Q32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16S_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSQ32SP16U_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2RA_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP24X2R_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2RA_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP24X2R_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2RA_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP24X2R_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HH_LL_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32S_HL_LH_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32RA_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32X16_H3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULASD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSAD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZASD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSAD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H3_L2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSFD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32X16_H1_L0_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H2_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAFD32X16_H0_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H2_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAFD32X16_H0_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H2_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32X16_H0_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H2_L3_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32X16_H0_L1_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_H_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2S_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X16X2_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X16X2RAS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_H_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2S_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X16X2_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X16X2RAS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_H_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_H_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2S_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X16X2_L_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X16X2RAS_L_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULP32X2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP32X2RAS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAP32X2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFP32X2RAS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSP32X2_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSFP32X2RAS_S2_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFP16X4RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC24RA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32RAS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAC32X16_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFC32X16RAS_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSF16X4SS_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS16X4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_H_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2S_FIR_L_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X2RA_FIR_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_HL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x4_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_q1 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x4_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x4_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAFD32X16X2_FIR_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAFQ32X16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAFQ32X16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ32X16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_v1 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ32X16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL16_00_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA16_00_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAAAQ16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAAAQ16_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_args[] = { + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_H_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_args[] = { + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DIV64D32_L_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SHA32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL32T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16T_stateArgs[] = { + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_SEARCHDONE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IP_stateArgs[] = { + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLDL16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'm' }, + { { STATE_AE_TABLESIZE }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_FIRST_TS }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_SEARCHDONE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLDSHT_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_AE_FIRST_TS }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_AE_TABLESIZE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBK_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBKI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBS_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_LBSI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DB_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_ae_ohba }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_DBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL32T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLEL16T_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'o' }, + { { STATE_AE_NEXTOFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC_stateArgs[] = { + { { STATE_AE_CBEGIN0 }, 'i' }, + { { STATE_AE_CEND0 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IC1_stateArgs[] = { + { { STATE_AE_CBEGIN1 }, 'i' }, + { { STATE_AE_CEND1 }, 'i' }, + { { STATE_AE_CWRAP }, 'm' }, + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SB_IP_stateArgs[] = { + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ae_ohba2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBI_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_VLES16C_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'm' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_AE_NEXTOFFSET }, 'i' }, + { { STATE_AE_BITSUSED }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_AE_SBF_IP_stateArgs[] = { + { { STATE_AE_BITPTR }, 'i' }, + { { STATE_AE_BITHEAD }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_args[] = { + { { OPERAND_ae_dr_to_dr_v }, 'o' }, + { { OPERAND_ae_dr_to_dr_v0 }, 'i' }, + { { OPERAND_ae_opnd_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_opnd_ae_sem_ep_ls_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVAE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_args[] = { + { { OPERAND_opnd_ae_sem_ep_ls_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_ep_ls_ar_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEA_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_args[] = { + { { OPERAND_opnd_ae_sem_ep_ls_eo }, 'o' }, + { { OPERAND_opnd_ae_sem_ep_ls_ei }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVEEP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'o' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SEXT72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_opnd_ae_sem_arithmetic_ep1 }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_ADD72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_args[] = { + { { OPERAND_opnd_ae_sem_arithmetic_ep }, 'm' }, + { { OPERAND_ae_arth_v }, 'm' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SUB72X64_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32EP_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32EP_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULS32EP_HH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32EP_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZSSD32EP_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32EP_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULSSD32EP_HH_LL_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULAAD32USEP_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_S2_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S2_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S2_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULZAAD32USEP_HL_LH_S2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'o' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MUL32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_args[] = { + { { OPERAND_opnd_ae_sem_mul_x2_S1_acc_ep }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_q0 }, 'm' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_mul_x2_S1_d1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MULA32USEP_LL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_args[] = { + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_opnd_ae_sem_shift_e }, 'i' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_ae_osa64 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SRAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_args[] = { + { { OPERAND_opnd_ae_sem_shift_e }, 'o' }, + { { OPERAND_ae_shift_d }, 'o' }, + { { OPERAND_ae_shift_d0 }, 'i' }, + { { OPERAND_opnd_ae_sem_shift_i8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SLAI72_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_args[] = { + { { OPERAND_ae_arth_v }, 'o' }, + { { OPERAND_opnd_ae_sem_arithmetic_e }, 'i' }, + { { OPERAND_ae_arth_v1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_SAT64S_stateArgs[] = { + { { STATE_AE_OVERFLOW }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16SI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_L16UI_N_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_S16I_N_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ae_uimm2x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVFCRFSRV_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_args[] = { + { { OPERAND_opnd_ae_sem_movfpstate_v }, 'o' } +}; + +static xtensa_arg_internal Iclass_AE_MOVVFCRFSR_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_opnd_ae_sem_dr_to_ar_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_args[] = { + { { OPERAND_ae_ar_to_dr_v }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = { + { { OPERAND_ae_cmov_v }, 'm' }, + { { OPERAND_ae_cmov_v0 }, 'i' }, + { { OPERAND_opnd_ae_sem_cmov_arr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_arr }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_arr }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_SX2_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FICEIL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIFLOOR_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIROUND_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FITRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_FIRINT_S_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTSF16_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_L_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTF16S_H_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_mov_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUBN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_mov_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_mov_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_arr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_SX2_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_args[] = { + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_sp32cvt_i_imm5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_SX2_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_brt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_mov_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_mov_i_imm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vsM }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MIN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_MAX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_i_imm1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MULMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spfma_vt }, 'm' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vs }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_vr }, 'i' }, + { { OPERAND_opnd_vfpu2_sem_spfma_i_imm3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDMUX_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_args[] = { + { { OPERAND_opnd_vfpu2_sem_spmisc_vtM }, 'o' }, + { { OPERAND_opnd_vfpu2_sem_spmisc_vr }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONJC_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SIGMOID_Q15_args[] = { + { { OPERAND_opnd_SIGMOID_Q15_y }, 'o' }, + { { OPERAND_opnd_SIGMOID_Q15_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_SIGMOID_FP32_args[] = { + { { OPERAND_opnd_SIGMOID_FP32_y }, 'o' }, + { { OPERAND_opnd_SIGMOID_FP32_x }, 'i' } +}; + +static xtensa_arg_internal Iclass_SIGMOID_FP32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 1, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 1, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 1, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32h_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 16, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_dcache_dyn_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpfb_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_bpfnxt */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpdngrd_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_bpfctl */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prefctl_args, + 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_prefctl_args, + 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_prefctl_args, + 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, + { 2, Iclass_xt_iclass_wer_args, + 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, + { 2, Iclass_xt_iclass_wb15_0_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_1_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_2_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_3_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_wb15_4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_ae_ovf_sar_args, + 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ovf_sar_args, + 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_bithead_args, + 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_bithead_args, + 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_ts_fts_bu_bp_args, + 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_ts_fts_bu_bp_args, + 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cw_sd_no_args, + 4, Iclass_rur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cw_sd_no_args, + 4, Iclass_wur_ae_cw_sd_no_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin0_args, + 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin0_args, + 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend0_args, + 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend0_args, + 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cbegin1_args, + 2, Iclass_rur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cbegin1_args, + 2, Iclass_wur_ae_cbegin1_stateArgs, 0, 0 }, + { 1, Iclass_rur_ae_cend1_args, + 2, Iclass_rur_ae_cend1_stateArgs, 0, 0 }, + { 1, Iclass_wur_ae_cend1_args, + 2, Iclass_wur_ae_cend1_stateArgs, 0, 0 }, + { 2, Iclass_ic_sext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_zext16_args, + 0, 0, 0, 0 }, + { 2, Iclass_ic_clamps16_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_fcr_args, + 2, Iclass_rur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fcr_args, + 2, Iclass_wur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_rur_fsr_args, + 6, Iclass_rur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fsr_args, + 6, Iclass_wur_fsr_stateArgs, 0, 0 }, + { 5, Iclass_iclass_F64ITER_args, + 2, Iclass_iclass_F64ITER_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64RND_args, + 2, Iclass_iclass_F64RND_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64ADDC_F64SUBC_args, + 1, Iclass_iclass_F64ADDC_F64SUBC_stateArgs, 0, 0 }, + { 2, Iclass_iclass_F64SIG_args, + 0, 0, 0, 0 }, + { 3, Iclass_iclass_F64CMPL_args, + 1, Iclass_iclass_F64CMPL_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64CMPH_args, + 3, Iclass_iclass_F64CMPH_stateArgs, 0, 0 }, + { 4, Iclass_iclass_F64NORM_args, + 2, Iclass_iclass_F64NORM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_F64SEXP_args, + 0, 0, 0, 0 }, + { 2, Iclass_iclass_RF64R_args, + 1, Iclass_iclass_RF64R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_WF64R_args, + 1, Iclass_iclass_WF64R_stateArgs, 0, 0 }, + { 1, Iclass_rur_f64r_lo_args, + 1, Iclass_rur_f64r_lo_stateArgs, 0, 0 }, + { 1, Iclass_wur_f64r_lo_args, + 1, Iclass_wur_f64r_lo_stateArgs, 0, 0 }, + { 1, Iclass_rur_f64r_hi_args, + 1, Iclass_rur_f64r_hi_stateArgs, 0, 0 }, + { 1, Iclass_wur_f64r_hi_args, + 1, Iclass_wur_f64r_hi_stateArgs, 0, 0 }, + { 1, Iclass_rur_f64s_args, + 1, Iclass_rur_f64s_stateArgs, 0, 0 }, + { 1, Iclass_wur_f64s_args, + 1, Iclass_wur_f64s_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 1, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 1, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_OVERFLOW_args, + 2, Iclass_RUR_AE_OVERFLOW_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_OVERFLOW_args, + 2, Iclass_WUR_AE_OVERFLOW_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_SAR_args, + 2, Iclass_RUR_AE_SAR_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_SAR_args, + 2, Iclass_WUR_AE_SAR_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_BITPTR_args, + 2, Iclass_RUR_AE_BITPTR_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_BITPTR_args, + 2, Iclass_WUR_AE_BITPTR_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_BITSUSED_args, + 2, Iclass_RUR_AE_BITSUSED_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_BITSUSED_args, + 2, Iclass_WUR_AE_BITSUSED_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_TABLESIZE_args, + 2, Iclass_RUR_AE_TABLESIZE_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_TABLESIZE_args, + 2, Iclass_WUR_AE_TABLESIZE_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_FIRST_TS_args, + 2, Iclass_RUR_AE_FIRST_TS_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_FIRST_TS_args, + 2, Iclass_WUR_AE_FIRST_TS_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_NEXTOFFSET_args, + 2, Iclass_RUR_AE_NEXTOFFSET_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_NEXTOFFSET_args, + 2, Iclass_WUR_AE_NEXTOFFSET_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_SEARCHDONE_args, + 2, Iclass_RUR_AE_SEARCHDONE_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_SEARCHDONE_args, + 2, Iclass_WUR_AE_SEARCHDONE_stateArgs, 0, 0 }, + { 1, Iclass_RUR_AE_CWRAP_args, + 2, Iclass_RUR_AE_CWRAP_stateArgs, 0, 0 }, + { 1, Iclass_WUR_AE_CWRAP_args, + 2, Iclass_WUR_AE_CWRAP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4F_I_args, + 1, Iclass_AE_L8X4F_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L8X4F_IP_args, + 1, Iclass_AE_L8X4F_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_XC_args, + 3, Iclass_AE_L16M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_XC1_args, + 3, Iclass_AE_L16M_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_I_args, + 1, Iclass_AE_L16M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_IU_args, + 1, Iclass_AE_L16M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_X_args, + 1, Iclass_AE_L16M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16M_XU_args, + 1, Iclass_AE_L16M_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_XC_args, + 3, Iclass_AE_L16_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_XC1_args, + 3, Iclass_AE_L16_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_I_args, + 1, Iclass_AE_L16_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_IP_args, + 1, Iclass_AE_L16_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_X_args, + 1, Iclass_AE_L16_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16_XP_args, + 1, Iclass_AE_L16_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_XC_args, + 3, Iclass_AE_L32F24_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_XC1_args, + 3, Iclass_AE_L32F24_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_I_args, + 1, Iclass_AE_L32F24_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_IP_args, + 1, Iclass_AE_L32F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_X_args, + 1, Iclass_AE_L32F24_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32F24_XP_args, + 1, Iclass_AE_L32F24_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_XC_args, + 3, Iclass_AE_L32_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_XC1_args, + 3, Iclass_AE_L32_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_I_args, + 1, Iclass_AE_L32_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_IP_args, + 1, Iclass_AE_L32_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_X_args, + 1, Iclass_AE_L32_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32_XP_args, + 1, Iclass_AE_L32_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_XC_args, + 3, Iclass_AE_L32M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_I_args, + 1, Iclass_AE_L32M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_IU_args, + 1, Iclass_AE_L32M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_X_args, + 1, Iclass_AE_L32M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32M_XU_args, + 1, Iclass_AE_L32M_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_XC_args, + 3, Iclass_AE_L16X2M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_XC1_args, + 3, Iclass_AE_L16X2M_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_I_args, + 1, Iclass_AE_L16X2M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_IU_args, + 1, Iclass_AE_L16X2M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_X_args, + 1, Iclass_AE_L16X2M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X2M_XU_args, + 1, Iclass_AE_L16X2M_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_XC_args, + 3, Iclass_AE_L32X2F24_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_XC1_args, + 3, Iclass_AE_L32X2F24_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_I_args, + 1, Iclass_AE_L32X2F24_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_IP_args, + 1, Iclass_AE_L32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_RIP_args, + 1, Iclass_AE_L32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_RI_args, + 1, Iclass_AE_L32X2F24_RI_stateArgs, 0, 0 }, + { 2, Iclass_AE_L32X2F24_RIC_args, + 3, Iclass_AE_L32X2F24_RIC_stateArgs, 0, 0 }, + { 2, Iclass_AE_L32X2F24_RIC1_args, + 3, Iclass_AE_L32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_X_args, + 1, Iclass_AE_L32X2F24_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2F24_XP_args, + 1, Iclass_AE_L32X2F24_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_XC_args, + 3, Iclass_AE_L32X2_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_XC1_args, + 3, Iclass_AE_L32X2_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_I_args, + 1, Iclass_AE_L32X2_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_IP_args, + 1, Iclass_AE_L32X2_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_L32X2_RIC_args, + 3, Iclass_AE_L32X2_RIC_stateArgs, 0, 0 }, + { 2, Iclass_AE_L32X2_RIC1_args, + 3, Iclass_AE_L32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_X_args, + 1, Iclass_AE_L32X2_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L32X2_XP_args, + 1, Iclass_AE_L32X2_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_XC_args, + 3, Iclass_AE_L16X4_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_XC1_args, + 3, Iclass_AE_L16X4_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_I_args, + 1, Iclass_AE_L16X4_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_IP_args, + 1, Iclass_AE_L16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_X_args, + 1, Iclass_AE_L16X4_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16X4_XP_args, + 1, Iclass_AE_L16X4_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L64_XC_args, + 3, Iclass_AE_L64_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_L64_XC1_args, + 3, Iclass_AE_L64_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_L64_I_args, + 1, Iclass_AE_L64_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_L64_IP_args, + 1, Iclass_AE_L64_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_L64_X_args, + 1, Iclass_AE_L64_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_L64_XP_args, + 1, Iclass_AE_L64_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X2M_XC_args, + 3, Iclass_AE_S16X2M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X2M_XC1_args, + 3, Iclass_AE_S16X2M_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X2M_I_args, + 1, Iclass_AE_S16X2M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X2M_IU_args, + 1, Iclass_AE_S16X2M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X2M_X_args, + 1, Iclass_AE_S16X2M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X2M_XU_args, + 1, Iclass_AE_S16X2M_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_XC_args, + 3, Iclass_AE_S32X2F24_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_XC1_args, + 3, Iclass_AE_S32X2F24_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_I_args, + 1, Iclass_AE_S32X2F24_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_IP_args, + 1, Iclass_AE_S32X2F24_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2F24_RIP_args, + 1, Iclass_AE_S32X2F24_RIP_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2F24_RIC_args, + 3, Iclass_AE_S32X2F24_RIC_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2F24_RIC1_args, + 3, Iclass_AE_S32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_X_args, + 1, Iclass_AE_S32X2F24_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2F24_XP_args, + 1, Iclass_AE_S32X2F24_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_XC_args, + 3, Iclass_AE_S32X2_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_XC1_args, + 3, Iclass_AE_S32X2_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_I_args, + 1, Iclass_AE_S32X2_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_IP_args, + 1, Iclass_AE_S32X2_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2_RIC_args, + 3, Iclass_AE_S32X2_RIC_stateArgs, 0, 0 }, + { 2, Iclass_AE_S32X2_RIC1_args, + 3, Iclass_AE_S32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_X_args, + 1, Iclass_AE_S32X2_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2_XP_args, + 1, Iclass_AE_S32X2_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_I_args, + 2, Iclass_AE_S32X2RNG_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_IP_args, + 2, Iclass_AE_S32X2RNG_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_X_args, + 2, Iclass_AE_S32X2RNG_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RNG_XP_args, + 2, Iclass_AE_S32X2RNG_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XC_args, + 3, Iclass_AE_S16X4_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XC1_args, + 3, Iclass_AE_S16X4_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_I_args, + 1, Iclass_AE_S16X4_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_IP_args, + 1, Iclass_AE_S16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_X_args, + 1, Iclass_AE_S16X4_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16X4_XP_args, + 1, Iclass_AE_S16X4_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_XC_args, + 3, Iclass_AE_S16M_L_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_XC1_args, + 3, Iclass_AE_S16M_L_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_I_args, + 1, Iclass_AE_S16M_L_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_IU_args, + 1, Iclass_AE_S16M_L_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_X_args, + 1, Iclass_AE_S16M_L_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16M_L_XU_args, + 1, Iclass_AE_S16M_L_XU_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_XC_args, + 3, Iclass_AE_S32F24_L_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_XC1_args, + 3, Iclass_AE_S32F24_L_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_I_args, + 1, Iclass_AE_S32F24_L_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_IP_args, + 1, Iclass_AE_S32F24_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_X_args, + 1, Iclass_AE_S32F24_L_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32F24_L_XP_args, + 1, Iclass_AE_S32F24_L_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_XC_args, + 3, Iclass_AE_S32_L_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_XC1_args, + 3, Iclass_AE_S32_L_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_I_args, + 1, Iclass_AE_S32_L_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_IP_args, + 1, Iclass_AE_S32_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_X_args, + 1, Iclass_AE_S32_L_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32_L_XP_args, + 1, Iclass_AE_S32_L_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_XC_args, + 3, Iclass_AE_S16_0_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_XC1_args, + 3, Iclass_AE_S16_0_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_I_args, + 1, Iclass_AE_S16_0_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_IP_args, + 1, Iclass_AE_S16_0_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_X_args, + 1, Iclass_AE_S16_0_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S16_0_XP_args, + 1, Iclass_AE_S16_0_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XC_args, + 3, Iclass_AE_S64_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XC1_args, + 3, Iclass_AE_S64_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_I_args, + 1, Iclass_AE_S64_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_IP_args, + 1, Iclass_AE_S64_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_X_args, + 1, Iclass_AE_S64_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S64_XP_args, + 1, Iclass_AE_S64_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_XC_args, + 3, Iclass_AE_S32M_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_I_args, + 1, Iclass_AE_S32M_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_IU_args, + 1, Iclass_AE_S32M_IU_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_X_args, + 1, Iclass_AE_S32M_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32M_XU_args, + 1, Iclass_AE_S32M_XU_stateArgs, 0, 0 }, + { 1, Iclass_AE_ZALIGN64_args, + 1, Iclass_AE_ZALIGN64_stateArgs, 0, 0 }, + { 3, Iclass_AE_LALIGN64_I_args, + 1, Iclass_AE_LALIGN64_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_SALIGN64_I_args, + 1, Iclass_AE_SALIGN64_I_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVALIGN_args, + 1, Iclass_AE_MOVALIGN_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA64_PP_args, + 1, Iclass_AE_LA64_PP_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC_args, + 3, Iclass_AE_LA24POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC_args, + 3, Iclass_AE_LA24X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC_args, + 3, Iclass_AE_LA32X2POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC_args, + 3, Iclass_AE_LA16X4POS_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC_args, + 3, Iclass_AE_LA24NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC_args, + 3, Iclass_AE_LA24X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC_args, + 3, Iclass_AE_LA32X2NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC_args, + 3, Iclass_AE_LA16X4NEG_PC_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24POS_PC1_args, + 3, Iclass_AE_LA24POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2POS_PC1_args, + 3, Iclass_AE_LA24X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2POS_PC1_args, + 3, Iclass_AE_LA32X2POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4POS_PC1_args, + 3, Iclass_AE_LA16X4POS_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24NEG_PC1_args, + 3, Iclass_AE_LA24NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA24X2NEG_PC1_args, + 3, Iclass_AE_LA24X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA32X2NEG_PC1_args, + 3, Iclass_AE_LA32X2NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_LA16X4NEG_PC1_args, + 3, Iclass_AE_LA16X4NEG_PC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64POS_FP_args, + 1, Iclass_AE_SA64POS_FP_stateArgs, 0, 0 }, + { 2, Iclass_AE_SA64NEG_FP_args, + 1, Iclass_AE_SA64NEG_FP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC_args, + 3, Iclass_AE_LA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IC1_args, + 3, Iclass_AE_LA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_IP_args, + 1, Iclass_AE_LA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIP_args, + 1, Iclass_AE_LA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC_args, + 3, Iclass_AE_LA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2_RIC1_args, + 3, Iclass_AE_LA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC_args, + 3, Iclass_AE_LA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IC1_args, + 3, Iclass_AE_LA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_IP_args, + 1, Iclass_AE_LA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIP_args, + 1, Iclass_AE_LA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC_args, + 3, Iclass_AE_LA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA16X4_RIC1_args, + 3, Iclass_AE_LA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC_args, + 3, Iclass_AE_LA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IC1_args, + 3, Iclass_AE_LA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_IP_args, + 1, Iclass_AE_LA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIP_args, + 1, Iclass_AE_LA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC_args, + 3, Iclass_AE_LA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA32X2F24_RIC1_args, + 3, Iclass_AE_LA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC_args, + 3, Iclass_AE_LA24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IC1_args, + 3, Iclass_AE_LA24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_IP_args, + 1, Iclass_AE_LA24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIP_args, + 1, Iclass_AE_LA24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC_args, + 3, Iclass_AE_LA24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24_RIC1_args, + 3, Iclass_AE_LA24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC_args, + 3, Iclass_AE_LA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IC1_args, + 3, Iclass_AE_LA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_IP_args, + 1, Iclass_AE_LA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIP_args, + 1, Iclass_AE_LA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC_args, + 3, Iclass_AE_LA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_LA24X2_RIC1_args, + 3, Iclass_AE_LA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC_args, + 3, Iclass_AE_SA32X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IC1_args, + 3, Iclass_AE_SA32X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_IP_args, + 1, Iclass_AE_SA32X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIP_args, + 1, Iclass_AE_SA32X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC_args, + 3, Iclass_AE_SA32X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2_RIC1_args, + 3, Iclass_AE_SA32X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC_args, + 3, Iclass_AE_SA16X4_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IC1_args, + 3, Iclass_AE_SA16X4_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_IP_args, + 1, Iclass_AE_SA16X4_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIP_args, + 1, Iclass_AE_SA16X4_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC_args, + 3, Iclass_AE_SA16X4_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA16X4_RIC1_args, + 3, Iclass_AE_SA16X4_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC_args, + 3, Iclass_AE_SA32X2F24_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IC1_args, + 3, Iclass_AE_SA32X2F24_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_IP_args, + 1, Iclass_AE_SA32X2F24_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIP_args, + 1, Iclass_AE_SA32X2F24_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC_args, + 3, Iclass_AE_SA32X2F24_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA32X2F24_RIC1_args, + 3, Iclass_AE_SA32X2F24_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC_args, + 3, Iclass_AE_SA24_L_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IC1_args, + 3, Iclass_AE_SA24_L_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_IP_args, + 1, Iclass_AE_SA24_L_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIP_args, + 1, Iclass_AE_SA24_L_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC_args, + 3, Iclass_AE_SA24_L_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24_L_RIC1_args, + 3, Iclass_AE_SA24_L_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC_args, + 3, Iclass_AE_SA24X2_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IC1_args, + 3, Iclass_AE_SA24X2_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_IP_args, + 1, Iclass_AE_SA24X2_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIP_args, + 1, Iclass_AE_SA24X2_RIP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC_args, + 3, Iclass_AE_SA24X2_RIC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SA24X2_RIC1_args, + 3, Iclass_AE_SA24X2_RIC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDICIRC_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC1_args, + 3, Iclass_AE_ADDCIRC_XC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_ADDCIRC_XC_args, + 3, Iclass_AE_ADDCIRC_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_I_args, + 2, Iclass_AE_S32RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_IP_args, + 2, Iclass_AE_S32RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_X_args, + 2, Iclass_AE_S32RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XP_args, + 2, Iclass_AE_S32RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC_args, + 4, Iclass_AE_S32RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32RA64S_XC1_args, + 4, Iclass_AE_S32RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_I_args, + 2, Iclass_AE_S24RA64S_I_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_IP_args, + 2, Iclass_AE_S24RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_X_args, + 2, Iclass_AE_S24RA64S_X_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XP_args, + 2, Iclass_AE_S24RA64S_XP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC_args, + 4, Iclass_AE_S24RA64S_XC_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24RA64S_XC1_args, + 4, Iclass_AE_S24RA64S_XC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_S32X2RA64S_IP_args, + 2, Iclass_AE_S32X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_S24X2RA64S_IP_args, + 2, Iclass_AE_S24X2RA64S_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDBRBA32_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_BITSWAP_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MUL32JS_args, + 1, Iclass_AE_MUL32JS_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUB32S_args, + 2, Iclass_AE_ADDANDSUB32S_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADDANDSUBRNG32_args, + 2, Iclass_AE_ADDANDSUBRNG32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDRNG32_args, + 2, Iclass_AE_ADDRNG32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBRNG32_args, + 2, Iclass_AE_SUBRNG32_stateArgs, 0, 0 }, + { 0, 0 /* AE_CALCRNG3 */, + 2, Iclass_AE_CALCRNG3_stateArgs, 0, 0 }, + { 0, 0 /* AE_CALCRNG2 */, + 2, Iclass_AE_CALCRNG2_stateArgs, 0, 0 }, + { 0, 0 /* AE_CALCRNG1 */, + 2, Iclass_AE_CALCRNG1_stateArgs, 0, 0 }, + { 1, Iclass_AE_RNG32X2_args, + 2, Iclass_AE_RNG32X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_args, + 1, Iclass_AE_SEL16I_stateArgs, 0, 0 }, + { 4, Iclass_AE_SEL16I_N_args, + 1, Iclass_AE_SEL16I_N_stateArgs, 0, 0 }, + { 2, Iclass_AE_SHORTSWAP_args, + 1, Iclass_AE_SHORTSWAP_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAB4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVAB_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVBA1X2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA4_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVBA2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB2_args, + 0, 0, 0, 0 }, + { 2, Iclass_AE_MOVB4_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_MOVT16X4_args, + 1, Iclass_AE_MOVT16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF16X4_args, + 1, Iclass_AE_MOVF16X4_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT32X2_args, + 1, Iclass_AE_MOVT32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF32X2_args, + 1, Iclass_AE_MOVF32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVSARA7X2_args, + 2, Iclass_AE_MOVSARA7X2_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVSARD7_args, + 2, Iclass_AE_MOVSARD7_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVASAR_args, + 2, Iclass_AE_MOVASAR_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA32X2_args, + 1, Iclass_AE_MOVDA32X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA32_args, + 1, Iclass_AE_MOVDA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVDA16X2_args, + 1, Iclass_AE_MOVDA16X2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVDA16_args, + 1, Iclass_AE_MOVDA16_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVI_args, + 1, Iclass_AE_MOVI_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24A32X2_args, + 1, Iclass_AE_TRUNCP24A32X2_stateArgs, 0, 0 }, + { 3, Iclass_AE_SAT16X4_args, + 2, Iclass_AE_SAT16X4_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_32_args, + 1, Iclass_AE_CVT32X2F16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT32X2F16_10_args, + 1, Iclass_AE_CVT32X2F16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_32_args, + 1, Iclass_AE_SEXT32X2D16_32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT32X2D16_10_args, + 1, Iclass_AE_SEXT32X2D16_10_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_L_args, + 1, Iclass_AE_CVTA32F24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTA32F24S_H_args, + 1, Iclass_AE_CVTA32F24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LL_args, + 1, Iclass_AE_CVTP24A16X2_LL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_LH_args, + 1, Iclass_AE_CVTP24A16X2_LH_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HL_args, + 1, Iclass_AE_CVTP24A16X2_HL_stateArgs, 0, 0 }, + { 3, Iclass_AE_CVTP24A16X2_HH_args, + 1, Iclass_AE_CVTP24A16X2_HH_stateArgs, 0, 0 }, + { 3, Iclass_AE_TRUNCP24Q48X2_args, + 1, Iclass_AE_TRUNCP24Q48X2_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32X2F64S_args, + 2, Iclass_AE_TRUNCA32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32X2F64S_args, + 2, Iclass_AE_TRUNCI32X2F64S_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCA32F64S_L_args, + 2, Iclass_AE_TRUNCA32F64S_L_stateArgs, 0, 0 }, + { 4, Iclass_AE_TRUNCI32F64S_L_args, + 2, Iclass_AE_TRUNCI32F64S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCP16_args, + 1, Iclass_AE_TRUNCP16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SSYM_args, + 2, Iclass_AE_ROUND32X2F64SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F64SASYM_args, + 2, Iclass_AE_ROUND32X2F64SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SSYM_args, + 2, Iclass_AE_ROUND32X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND32X2F48SASYM_args, + 2, Iclass_AE_ROUND32X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SSYM_args, + 2, Iclass_AE_ROUND16X4F32SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND16X4F32SASYM_args, + 2, Iclass_AE_ROUND16X4F32SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SSYM_args, + 2, Iclass_AE_ROUND24X2F48SSYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUND24X2F48SASYM_args, + 2, Iclass_AE_ROUND24X2F48SASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2SYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2SYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_ROUNDSP16Q48X2ASYM_args, + 2, Iclass_AE_ROUNDSP16Q48X2ASYM_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS32S_args, + 2, Iclass_AE_MINABS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS32S_args, + 2, Iclass_AE_MAXABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24SYM_args, + 2, Iclass_AE_ROUNDSP16F24SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSP16F24ASYM_args, + 2, Iclass_AE_ROUNDSP16F24ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOV_args, + 1, Iclass_AE_MOV_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVT64_args, + 1, Iclass_AE_MOVT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MOVF64_args, + 1, Iclass_AE_MOVF64_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56A32S_args, + 1, Iclass_AE_CVTQ56A32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48A32_args, + 1, Iclass_AE_CVT48A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64A32_args, + 1, Iclass_AE_CVT64A32_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_L_args, + 1, Iclass_AE_CVTQ56P32S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVTQ56P32S_H_args, + 1, Iclass_AE_CVTQ56P32S_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT64F32_H_args, + 1, Iclass_AE_CVT64F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_L_args, + 1, Iclass_AE_CVT48F32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_CVT48F32_H_args, + 1, Iclass_AE_CVT48F32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT48S_args, + 2, Iclass_AE_SAT48S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SATQ56S_args, + 2, Iclass_AE_SATQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SAT24S_args, + 2, Iclass_AE_SAT24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCQ32_args, + 1, Iclass_AE_TRUNCQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MINABS64S_args, + 2, Iclass_AE_MINABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAXABS64S_args, + 2, Iclass_AE_MAXABS64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48SYM_args, + 2, Iclass_AE_ROUNDSQ32F48SYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_ROUNDSQ32F48ASYM_args, + 2, Iclass_AE_ROUNDSQ32F48ASYM_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA32Q48_args, + 1, Iclass_AE_TRUNCA32Q48_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_L_args, + 1, Iclass_AE_MOVAD32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD32_H_args, + 1, Iclass_AE_MOVAD32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_3_args, + 1, Iclass_AE_MOVAD16_3_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_2_args, + 1, Iclass_AE_MOVAD16_2_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_1_args, + 1, Iclass_AE_MOVAD16_1_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAD16_0_args, + 1, Iclass_AE_MOVAD16_0_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRA64_32_args, + 1, Iclass_AE_SRA64_32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR32_args, + 2, Iclass_AE_PKSR32_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSR24_args, + 2, Iclass_AE_PKSR24_stateArgs, 0, 0 }, + { 3, Iclass_AE_PKSRF32_args, + 2, Iclass_AE_PKSRF32_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_L_args, + 1, Iclass_AE_TRUNCA16P24S_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_TRUNCA16P24S_H_args, + 1, Iclass_AE_TRUNCA16P24S_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_args, + 1, Iclass_AE_ADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB32_args, + 1, Iclass_AE_SUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32_args, + 1, Iclass_AE_ADDSUB32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBADD32_args, + 1, Iclass_AE_SUBADD32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD16_args, + 1, Iclass_AE_ADD16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB16_args, + 1, Iclass_AE_SUB16_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32_HL_LH_args, + 1, Iclass_AE_ADD32_HL_LH_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32_args, + 1, Iclass_AE_NEG32_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS32_args, + 1, Iclass_AE_ABS32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD24S_args, + 2, Iclass_AE_ADD24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB24S_args, + 2, Iclass_AE_SUB24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32S_args, + 2, Iclass_AE_ADD32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB32S_args, + 2, Iclass_AE_SUB32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSUB32S_args, + 2, Iclass_AE_ADDSUB32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBADD32S_args, + 2, Iclass_AE_SUBADD32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD16S_args, + 2, Iclass_AE_ADD16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB16S_args, + 2, Iclass_AE_SUB16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD32S_HL_LH_args, + 2, Iclass_AE_ADD32S_HL_LH_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG24S_args, + 2, Iclass_AE_NEG24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS24S_args, + 2, Iclass_AE_ABS24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG32S_args, + 1, Iclass_AE_NEG32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS32S_args, + 1, Iclass_AE_ABS32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG16S_args, + 1, Iclass_AE_NEG16S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS16S_args, + 1, Iclass_AE_ABS16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT16_args, + 1, Iclass_AE_LT16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE16_args, + 1, Iclass_AE_LE16_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ16_args, + 1, Iclass_AE_EQ16_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT32_args, + 1, Iclass_AE_LT32_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE32_args, + 1, Iclass_AE_LE32_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ32_args, + 1, Iclass_AE_EQ32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN32_args, + 1, Iclass_AE_MIN32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX32_args, + 1, Iclass_AE_MAX32_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD64_args, + 1, Iclass_AE_ADD64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB64_args, + 1, Iclass_AE_SUB64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG64_args, + 1, Iclass_AE_NEG64_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS64_args, + 1, Iclass_AE_ABS64_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADDSQ56S_args, + 2, Iclass_AE_ADDSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUBSQ56S_args, + 2, Iclass_AE_SUBSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD64S_args, + 2, Iclass_AE_ADD64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB64S_args, + 2, Iclass_AE_SUB64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEGSQ56S_args, + 2, Iclass_AE_NEGSQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABSSQ56S_args, + 2, Iclass_AE_ABSSQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_NEG64S_args, + 2, Iclass_AE_NEG64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_ABS64S_args, + 2, Iclass_AE_ABS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_AND_args, + 1, Iclass_AE_AND_stateArgs, 0, 0 }, + { 3, Iclass_AE_NAND_args, + 1, Iclass_AE_NAND_stateArgs, 0, 0 }, + { 3, Iclass_AE_OR_args, + 1, Iclass_AE_OR_stateArgs, 0, 0 }, + { 3, Iclass_AE_XOR_args, + 1, Iclass_AE_XOR_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI24_args, + 1, Iclass_AE_SLAI24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI24_args, + 1, Iclass_AE_SRLI24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI24_args, + 1, Iclass_AE_SRAI24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS24_args, + 2, Iclass_AE_SLAS24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS24_args, + 2, Iclass_AE_SRLS24_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS24_args, + 2, Iclass_AE_SRAS24_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16_args, + 1, Iclass_AE_SRAI16_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI16R_args, + 1, Iclass_AE_SRAI16R_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI32_args, + 1, Iclass_AE_SLAI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI32_args, + 1, Iclass_AE_SRLI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32_args, + 1, Iclass_AE_SRAI32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI32R_args, + 1, Iclass_AE_SRAI32R_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS32_args, + 2, Iclass_AE_SLAS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS32_args, + 2, Iclass_AE_SRLS32_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS32_args, + 2, Iclass_AE_SRAS32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA32_args, + 1, Iclass_AE_SLAA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA32_args, + 1, Iclass_AE_SRLA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32_args, + 1, Iclass_AE_SRAA32_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI16S_args, + 2, Iclass_AE_SLAI16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA16S_args, + 2, Iclass_AE_SLAA16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16S_args, + 2, Iclass_AE_SRAA16S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA16RS_args, + 2, Iclass_AE_SRAA16RS_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI24S_args, + 2, Iclass_AE_SLAI24S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS24S_args, + 3, Iclass_AE_SLAS24S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI32S_args, + 2, Iclass_AE_SLAI32S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS32S_args, + 3, Iclass_AE_SLAS32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA32S_args, + 2, Iclass_AE_SLAA32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32S_args, + 2, Iclass_AE_SRAA32S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA32RS_args, + 2, Iclass_AE_SRAA32RS_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLASQ56_args, + 2, Iclass_AE_SLASQ56_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLSQ56_args, + 2, Iclass_AE_SRLSQ56_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRASQ56_args, + 2, Iclass_AE_SRASQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAAQ56_args, + 1, Iclass_AE_SLAAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLAQ56_args, + 1, Iclass_AE_SRLAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAAQ56_args, + 1, Iclass_AE_SRAAQ56_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI64_args, + 1, Iclass_AE_SLAI64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLI64_args, + 1, Iclass_AE_SRLI64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAI64_args, + 1, Iclass_AE_SRAI64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS64_args, + 2, Iclass_AE_SLAS64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRLS64_args, + 2, Iclass_AE_SRLS64_stateArgs, 0, 0 }, + { 2, Iclass_AE_SRAS64_args, + 2, Iclass_AE_SRAS64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA64_args, + 1, Iclass_AE_SLAA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRLA64_args, + 1, Iclass_AE_SRLA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SRAA64_args, + 1, Iclass_AE_SRAA64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAISQ56S_args, + 2, Iclass_AE_SLAISQ56S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLASSQ56S_args, + 3, Iclass_AE_SLASSQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAASQ56S_args, + 2, Iclass_AE_SLAASQ56S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAI64S_args, + 2, Iclass_AE_SLAI64S_stateArgs, 0, 0 }, + { 2, Iclass_AE_SLAS64S_args, + 3, Iclass_AE_SLAS64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_SLAA64S_args, + 2, Iclass_AE_SLAA64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_LT64_args, + 1, Iclass_AE_LT64_stateArgs, 0, 0 }, + { 3, Iclass_AE_LE64_args, + 1, Iclass_AE_LE64_stateArgs, 0, 0 }, + { 3, Iclass_AE_EQ64_args, + 1, Iclass_AE_EQ64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MAX64_args, + 1, Iclass_AE_MAX64_stateArgs, 0, 0 }, + { 3, Iclass_AE_MIN64_args, + 1, Iclass_AE_MIN64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSA64_args, + 1, Iclass_AE_NSA64_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSAZ16_0_args, + 1, Iclass_AE_NSAZ16_0_stateArgs, 0, 0 }, + { 2, Iclass_AE_NSAZ32_L_args, + 1, Iclass_AE_NSAZ32_L_stateArgs, 0, 0 }, + { 3, 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Iclass_AE_MULAC32_args, + 1, Iclass_AE_MULAC32_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFC24RA_args, + 1, Iclass_AE_MULAFC24RA_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFC32RAS_args, + 2, Iclass_AE_MULAFC32RAS_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC32X16_L_args, + 1, Iclass_AE_MULAC32X16_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFC32X16RAS_L_args, + 2, Iclass_AE_MULAFC32X16RAS_L_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAC32X16_H_args, + 1, Iclass_AE_MULAC32X16_H_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAFC32X16RAS_H_args, + 2, Iclass_AE_MULAFC32X16RAS_H_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULF16X4SS_args, + 2, Iclass_AE_MULF16X4SS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAF16X4SS_args, + 2, Iclass_AE_MULAF16X4SS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSF16X4SS_args, + 2, Iclass_AE_MULSF16X4SS_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL16X4_args, + 1, Iclass_AE_MUL16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA16X4_args, + 1, Iclass_AE_MULA16X4_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS16X4_args, + 1, Iclass_AE_MULS16X4_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X2S_FIR_H_args, + 2, Iclass_AE_MULFD32X2S_FIR_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X2RA_FIR_H_args, + 1, Iclass_AE_MULFD32X2RA_FIR_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X2S_FIR_L_args, + 2, Iclass_AE_MULFD32X2S_FIR_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X2RA_FIR_L_args, + 1, Iclass_AE_MULFD32X2RA_FIR_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X16X2_FIR_HH_args, + 1, Iclass_AE_MULFD32X16X2_FIR_HH_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X16X2_FIR_HL_args, + 1, Iclass_AE_MULFD32X16X2_FIR_HL_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X16X2_FIR_LH_args, + 1, Iclass_AE_MULFD32X16X2_FIR_LH_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULFD32X16X2_FIR_LL_args, + 1, Iclass_AE_MULFD32X16X2_FIR_LL_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X2S_FIR_H_args, + 2, Iclass_AE_MULAFD32X2S_FIR_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X2RA_FIR_H_args, + 1, Iclass_AE_MULAFD32X2RA_FIR_H_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X2S_FIR_L_args, + 2, Iclass_AE_MULAFD32X2S_FIR_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X2RA_FIR_L_args, + 1, Iclass_AE_MULAFD32X2RA_FIR_L_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X16X2_FIR_HH_args, + 1, Iclass_AE_MULAFD32X16X2_FIR_HH_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X16X2_FIR_HL_args, + 1, Iclass_AE_MULAFD32X16X2_FIR_HL_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X16X2_FIR_LH_args, + 1, Iclass_AE_MULAFD32X16X2_FIR_LH_stateArgs, 0, 0 }, + { 5, Iclass_AE_MULAFD32X16X2_FIR_LL_args, + 1, Iclass_AE_MULAFD32X16X2_FIR_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAFQ32X16_args, + 1, Iclass_AE_MULZAAAAFQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAFQ32X16_args, + 1, Iclass_AE_MULAAAAFQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAFQ32X16_S2_args, + 1, Iclass_AE_MULZAAAAFQ32X16_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAFQ32X16_S2_args, + 1, Iclass_AE_MULAAAAFQ32X16_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAQ32X16_args, + 1, Iclass_AE_MULZAAAAQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAQ32X16_args, + 1, Iclass_AE_MULAAAAQ32X16_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAAAQ32X16_S2_args, + 1, Iclass_AE_MULZAAAAQ32X16_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAAAQ32X16_S2_args, + 1, Iclass_AE_MULAAAAQ32X16_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL16_00_args, + 1, Iclass_AE_MUL16_00_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA16_00_args, + 1, Iclass_AE_MULA16_00_stateArgs, 0, 0 }, + { 3, Iclass_AE_MUL16_00_S2_args, + 1, Iclass_AE_MUL16_00_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULA16_00_S2_args, + 1, Iclass_AE_MULA16_00_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAAAQ16_args, + 1, Iclass_AE_MULZAAAAQ16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAAAQ16_args, + 1, Iclass_AE_MULAAAAQ16_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULZAAAAQ16_S2_args, + 1, Iclass_AE_MULZAAAAQ16_S2_stateArgs, 0, 0 }, + { 3, Iclass_AE_MULAAAAQ16_S2_args, + 1, Iclass_AE_MULAAAAQ16_S2_stateArgs, 0, 0 }, + { 2, Iclass_AE_DIV64D32_H_args, + 1, Iclass_AE_DIV64D32_H_stateArgs, 0, 0 }, + { 2, Iclass_AE_DIV64D32_L_args, + 1, Iclass_AE_DIV64D32_L_stateArgs, 0, 0 }, + { 2, Iclass_AE_SHA32_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_VLDL32T_args, + 5, Iclass_AE_VLDL32T_stateArgs, 0, 0 }, + { 3, Iclass_AE_VLDL16T_args, + 5, Iclass_AE_VLDL16T_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDL16C_args, + 8, Iclass_AE_VLDL16C_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDL16C_IP_args, + 8, Iclass_AE_VLDL16C_IP_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDL16C_IC_args, + 11, Iclass_AE_VLDL16C_IC_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDL16C_IC1_args, + 11, Iclass_AE_VLDL16C_IC1_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLDSHT_args, + 6, Iclass_AE_VLDSHT_stateArgs, 0, 0 }, + { 2, Iclass_AE_LB_args, + 3, Iclass_AE_LB_stateArgs, 0, 0 }, + { 2, Iclass_AE_LBI_args, + 3, Iclass_AE_LBI_stateArgs, 0, 0 }, + { 3, Iclass_AE_LBK_args, + 3, Iclass_AE_LBK_stateArgs, 0, 0 }, + { 3, Iclass_AE_LBKI_args, + 3, Iclass_AE_LBKI_stateArgs, 0, 0 }, + { 2, Iclass_AE_LBS_args, + 3, Iclass_AE_LBS_stateArgs, 0, 0 }, + { 2, Iclass_AE_LBSI_args, + 3, Iclass_AE_LBSI_stateArgs, 0, 0 }, + { 2, Iclass_AE_DB_args, + 3, Iclass_AE_DB_stateArgs, 0, 0 }, + { 2, Iclass_AE_DBI_args, + 3, Iclass_AE_DBI_stateArgs, 0, 0 }, + { 2, Iclass_AE_DB_IC_args, + 6, Iclass_AE_DB_IC_stateArgs, 0, 0 }, + { 2, Iclass_AE_DBI_IC_args, + 6, Iclass_AE_DBI_IC_stateArgs, 0, 0 }, + { 2, Iclass_AE_DB_IC1_args, + 6, Iclass_AE_DB_IC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_DBI_IC1_args, + 6, Iclass_AE_DBI_IC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_DB_IP_args, + 3, Iclass_AE_DB_IP_stateArgs, 0, 0 }, + { 2, Iclass_AE_DBI_IP_args, + 3, Iclass_AE_DBI_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_VLEL32T_args, + 3, Iclass_AE_VLEL32T_stateArgs, 0, 0 }, + { 3, Iclass_AE_VLEL16T_args, + 3, Iclass_AE_VLEL16T_stateArgs, 0, 0 }, + { 2, Iclass_AE_SB_args, + 4, Iclass_AE_SB_stateArgs, 0, 0 }, + { 3, Iclass_AE_SBI_args, + 3, Iclass_AE_SBI_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLES16C_args, + 5, Iclass_AE_VLES16C_stateArgs, 0, 0 }, + { 1, Iclass_AE_SBF_args, + 3, Iclass_AE_SBF_stateArgs, 0, 0 }, + { 2, Iclass_AE_SB_IC_args, + 7, Iclass_AE_SB_IC_stateArgs, 0, 0 }, + { 3, Iclass_AE_SBI_IC_args, + 6, Iclass_AE_SBI_IC_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLES16C_IC_args, + 8, Iclass_AE_VLES16C_IC_stateArgs, 0, 0 }, + { 1, Iclass_AE_SBF_IC_args, + 6, Iclass_AE_SBF_IC_stateArgs, 0, 0 }, + { 2, Iclass_AE_SB_IC1_args, + 7, Iclass_AE_SB_IC1_stateArgs, 0, 0 }, + { 3, Iclass_AE_SBI_IC1_args, + 6, Iclass_AE_SBI_IC1_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLES16C_IC1_args, + 8, Iclass_AE_VLES16C_IC1_stateArgs, 0, 0 }, + { 1, Iclass_AE_SBF_IC1_args, + 6, Iclass_AE_SBF_IC1_stateArgs, 0, 0 }, + { 2, Iclass_AE_SB_IP_args, + 4, Iclass_AE_SB_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SBI_IP_args, + 3, Iclass_AE_SBI_IP_stateArgs, 0, 0 }, + { 1, Iclass_AE_VLES16C_IP_args, + 5, Iclass_AE_VLES16C_IP_stateArgs, 0, 0 }, + { 1, Iclass_AE_SBF_IP_args, + 3, Iclass_AE_SBF_IP_stateArgs, 0, 0 }, + { 3, Iclass_AE_SEXT32_args, + 1, Iclass_AE_SEXT32_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVAE_args, + 1, Iclass_AE_MOVAE_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVEA_args, + 1, Iclass_AE_MOVEA_stateArgs, 0, 0 }, + { 2, Iclass_AE_MOVEEP_args, + 1, Iclass_AE_MOVEEP_stateArgs, 0, 0 }, + { 2, Iclass_AE_SEXT72_args, + 1, Iclass_AE_SEXT72_stateArgs, 0, 0 }, + { 4, Iclass_AE_ADD72_args, + 1, Iclass_AE_ADD72_stateArgs, 0, 0 }, + { 4, Iclass_AE_SUB72_args, + 1, Iclass_AE_SUB72_stateArgs, 0, 0 }, + { 3, Iclass_AE_ADD72X64_args, + 1, Iclass_AE_ADD72X64_stateArgs, 0, 0 }, + { 3, Iclass_AE_SUB72X64_args, + 1, Iclass_AE_SUB72X64_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32EP_HH_args, + 1, Iclass_AE_MUL32EP_HH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32EP_HH_S2_args, + 1, Iclass_AE_MUL32EP_HH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32EP_HH_args, + 1, Iclass_AE_MULA32EP_HH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32EP_HH_args, + 1, Iclass_AE_MULS32EP_HH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32EP_HH_S2_args, + 1, Iclass_AE_MULA32EP_HH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULS32EP_HH_S2_args, + 1, Iclass_AE_MULS32EP_HH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAD32EP_HH_LL_args, + 1, Iclass_AE_MULZAAD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZSSD32EP_HH_LL_args, + 1, Iclass_AE_MULZSSD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32EP_HH_LL_args, + 1, Iclass_AE_MULAAD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSSD32EP_HH_LL_args, + 1, Iclass_AE_MULSSD32EP_HH_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAD32EP_HH_LL_S2_args, + 1, Iclass_AE_MULZAAD32EP_HH_LL_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZSSD32EP_HH_LL_S2_args, + 1, Iclass_AE_MULZSSD32EP_HH_LL_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32EP_HH_LL_S2_args, + 1, Iclass_AE_MULAAD32EP_HH_LL_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULSSD32EP_HH_LL_S2_args, + 1, Iclass_AE_MULSSD32EP_HH_LL_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32USEP_HL_LH_args, + 1, Iclass_AE_MULAAD32USEP_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULAAD32USEP_HL_LH_S2_args, + 1, Iclass_AE_MULAAD32USEP_HL_LH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAD32USEP_HL_LH_args, + 1, Iclass_AE_MULZAAD32USEP_HL_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULZAAD32USEP_HL_LH_S2_args, + 1, Iclass_AE_MULZAAD32USEP_HL_LH_S2_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32USEP_LH_args, + 1, Iclass_AE_MUL32USEP_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32USEP_LH_args, + 1, Iclass_AE_MULA32USEP_LH_stateArgs, 0, 0 }, + { 4, Iclass_AE_MUL32USEP_LL_args, + 1, Iclass_AE_MUL32USEP_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_MULA32USEP_LL_args, + 1, Iclass_AE_MULA32USEP_LL_stateArgs, 0, 0 }, + { 4, Iclass_AE_SRAI72_args, + 1, Iclass_AE_SRAI72_stateArgs, 0, 0 }, + { 4, Iclass_AE_SLAI72_args, + 1, Iclass_AE_SLAI72_stateArgs, 0, 0 }, + { 3, Iclass_AE_SAT64S_args, + 2, Iclass_AE_SAT64S_stateArgs, 0, 0 }, + { 3, Iclass_AE_L16SI_N_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_L16UI_N_args, + 0, 0, 0, 0 }, + { 3, Iclass_AE_S16I_N_args, + 0, 0, 0, 0 }, + { 1, Iclass_AE_MOVFCRFSRV_args, + 7, Iclass_AE_MOVFCRFSRV_stateArgs, 0, 0 }, + { 1, Iclass_AE_MOVVFCRFSR_args, + 7, Iclass_AE_MOVVFCRFSR_stateArgs, 0, 0 }, + { 2, Iclass_RFR_args, + 1, Iclass_RFR_stateArgs, 0, 0 }, + { 2, Iclass_WFR_args, + 1, Iclass_WFR_stateArgs, 0, 0 }, + { 3, Iclass_MOVT_S_args, + 1, Iclass_MOVT_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVF_S_args, + 1, Iclass_MOVF_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVEQZ_S_args, + 1, Iclass_MOVEQZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVNEZ_S_args, + 1, Iclass_MOVNEZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVGEZ_S_args, + 1, Iclass_MOVGEZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVLTZ_S_args, + 1, Iclass_MOVLTZ_S_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC_S_args, + 3, Iclass_TRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC_S_args, + 3, Iclass_UTRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC_SX2_args, + 3, Iclass_TRUNC_SX2_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC_SX2_args, + 3, Iclass_UTRUNC_SX2_stateArgs, 0, 0 }, + { 2, Iclass_FICEIL_S_args, + 2, Iclass_FICEIL_S_stateArgs, 0, 0 }, + { 2, Iclass_FIFLOOR_S_args, + 2, Iclass_FIFLOOR_S_stateArgs, 0, 0 }, + { 2, Iclass_FIROUND_S_args, + 2, Iclass_FIROUND_S_stateArgs, 0, 0 }, + { 2, Iclass_FITRUNC_S_args, + 2, Iclass_FITRUNC_S_stateArgs, 0, 0 }, + { 2, Iclass_FIRINT_S_args, + 4, Iclass_FIRINT_S_stateArgs, 0, 0 }, + { 2, Iclass_CVTSF16_L_args, + 2, Iclass_CVTSF16_L_stateArgs, 0, 0 }, + { 2, Iclass_CVTSF16_H_args, + 2, Iclass_CVTSF16_H_stateArgs, 0, 0 }, + { 2, Iclass_CVTF16S_L_args, + 6, Iclass_CVTF16S_L_stateArgs, 0, 0 }, + { 2, Iclass_CVTF16S_H_args, + 6, Iclass_CVTF16S_H_stateArgs, 0, 0 }, + { 2, Iclass_ABS_S_args, + 1, Iclass_ABS_S_stateArgs, 0, 0 }, + { 3, Iclass_MUL_S_args, + 6, Iclass_MUL_S_stateArgs, 0, 0 }, + { 3, Iclass_MADD_S_args, + 6, Iclass_MADD_S_stateArgs, 0, 0 }, + { 3, Iclass_MSUB_S_args, + 6, Iclass_MSUB_S_stateArgs, 0, 0 }, + { 3, Iclass_MSUBN_S_args, + 1, Iclass_MSUBN_S_stateArgs, 0, 0 }, + { 3, Iclass_MADDN_S_args, + 1, Iclass_MADDN_S_stateArgs, 0, 0 }, + { 3, Iclass_ADD_S_args, + 6, Iclass_ADD_S_stateArgs, 0, 0 }, + { 3, Iclass_SUB_S_args, + 6, Iclass_SUB_S_stateArgs, 0, 0 }, + { 2, Iclass_NEG_S_args, + 1, Iclass_NEG_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_S_args, + 3, Iclass_FLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_S_args, + 3, Iclass_UFLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_SX2_args, + 3, Iclass_FLOAT_SX2_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_SX2_args, + 3, Iclass_UFLOAT_SX2_stateArgs, 0, 0 }, + { 3, Iclass_OLE_S_args, + 2, Iclass_OLE_S_stateArgs, 0, 0 }, + { 3, Iclass_OLT_S_args, + 2, Iclass_OLT_S_stateArgs, 0, 0 }, + { 3, Iclass_OEQ_S_args, + 2, Iclass_OEQ_S_stateArgs, 0, 0 }, + { 3, Iclass_UN_S_args, + 2, Iclass_UN_S_stateArgs, 0, 0 }, + { 3, Iclass_ULE_S_args, + 2, Iclass_ULE_S_stateArgs, 0, 0 }, + { 3, Iclass_ULT_S_args, + 2, Iclass_ULT_S_stateArgs, 0, 0 }, + { 3, Iclass_UEQ_S_args, + 2, Iclass_UEQ_S_stateArgs, 0, 0 }, + { 2, Iclass_CONST_S_args, + 1, Iclass_CONST_S_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_S_args, + 1, Iclass_NEXP01_S_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_S_args, + 2, Iclass_MKSADJ_S_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_S_args, + 3, Iclass_MKDADJ_S_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_S_args, + 1, Iclass_DIV0_S_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_S_args, + 1, Iclass_SQRT0_S_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_S_args, + 3, Iclass_RECIP0_S_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_S_args, + 3, Iclass_RSQRT0_S_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_S_args, + 5, Iclass_DIVN_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXP_S_args, + 1, Iclass_ADDEXP_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXPM_S_args, + 1, Iclass_ADDEXPM_S_stateArgs, 0, 0 }, + { 3, Iclass_MIN_S_args, + 2, Iclass_MIN_S_stateArgs, 0, 0 }, + { 3, Iclass_MAX_S_args, + 2, Iclass_MAX_S_stateArgs, 0, 0 }, + { 4, Iclass_MULMUX_S_args, + 6, Iclass_MULMUX_S_stateArgs, 0, 0 }, + { 4, Iclass_MADDMUX_S_args, + 6, Iclass_MADDMUX_S_stateArgs, 0, 0 }, + { 2, Iclass_CONJC_S_args, + 1, Iclass_CONJC_S_stateArgs, 0, 0 }, + { 2, Iclass_SIGMOID_Q15_args, + 0, 0, 0, 0 }, + { 2, Iclass_SIGMOID_FP32_args, + 1, Iclass_SIGMOID_FP32_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_mul32h, + ICLASS_xt_iclass_mac16_aa, + ICLASS_xt_iclass_mac16_ad, + ICLASS_xt_iclass_mac16_da, + ICLASS_xt_iclass_mac16_dd, + ICLASS_xt_iclass_mac16a_aa, + ICLASS_xt_iclass_mac16a_ad, + ICLASS_xt_iclass_mac16a_da, + ICLASS_xt_iclass_mac16a_dd, + ICLASS_xt_iclass_mac16al_da, + ICLASS_xt_iclass_mac16al_dd, + ICLASS_xt_iclass_mac16_l, + ICLASS_xt_iclass_rsr_m0, + ICLASS_xt_iclass_wsr_m0, + ICLASS_xt_iclass_xsr_m0, + ICLASS_xt_iclass_rsr_m1, + ICLASS_xt_iclass_wsr_m1, + ICLASS_xt_iclass_xsr_m1, + ICLASS_xt_iclass_rsr_m2, + ICLASS_xt_iclass_wsr_m2, + ICLASS_xt_iclass_xsr_m2, + ICLASS_xt_iclass_rsr_m3, + ICLASS_xt_iclass_wsr_m3, + ICLASS_xt_iclass_xsr_m3, + ICLASS_xt_iclass_rsr_acclo, + ICLASS_xt_iclass_wsr_acclo, + ICLASS_xt_iclass_xsr_acclo, + ICLASS_xt_iclass_rsr_acchi, + ICLASS_xt_iclass_wsr_acchi, + ICLASS_xt_iclass_xsr_acchi, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_dyn, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dpfb, + ICLASS_xt_iclass_bpfnxt, + ICLASS_xt_iclass_dpdngrd, + ICLASS_xt_iclass_bpfctl, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_rsr_prefctl, + ICLASS_xt_iclass_wsr_prefctl, + ICLASS_xt_iclass_xsr_prefctl, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_xt_iclass_wb15_0, + ICLASS_xt_iclass_wb15_1, + ICLASS_xt_iclass_wb15_2, + ICLASS_xt_iclass_wb15_3, + ICLASS_xt_iclass_wb15_4, + ICLASS_rur_ae_ovf_sar, + ICLASS_wur_ae_ovf_sar, + ICLASS_rur_ae_bithead, + ICLASS_wur_ae_bithead, + ICLASS_rur_ae_ts_fts_bu_bp, + ICLASS_wur_ae_ts_fts_bu_bp, + ICLASS_rur_ae_cw_sd_no, + ICLASS_wur_ae_cw_sd_no, + ICLASS_rur_ae_cbegin0, + ICLASS_wur_ae_cbegin0, + ICLASS_rur_ae_cend0, + ICLASS_wur_ae_cend0, + ICLASS_rur_ae_cbegin1, + ICLASS_wur_ae_cbegin1, + ICLASS_rur_ae_cend1, + ICLASS_wur_ae_cend1, + ICLASS_ic_sext16, + ICLASS_ic_zext16, + ICLASS_ic_clamps16, + ICLASS_rur_fcr, + ICLASS_wur_fcr, + ICLASS_rur_fsr, + ICLASS_wur_fsr, + ICLASS_iclass_F64ITER, + ICLASS_iclass_F64RND, + ICLASS_iclass_F64ADDC_F64SUBC, + ICLASS_iclass_F64SIG, + ICLASS_iclass_F64CMPL, + ICLASS_iclass_F64CMPH, + ICLASS_iclass_F64NORM, + ICLASS_iclass_F64SEXP, + ICLASS_iclass_RF64R, + ICLASS_iclass_WF64R, + ICLASS_rur_f64r_lo, + ICLASS_wur_f64r_lo, + ICLASS_rur_f64r_hi, + ICLASS_wur_f64r_hi, + ICLASS_rur_f64s, + ICLASS_wur_f64s, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE, + ICLASS_RUR_AE_OVERFLOW, + ICLASS_WUR_AE_OVERFLOW, + ICLASS_RUR_AE_SAR, + ICLASS_WUR_AE_SAR, + ICLASS_RUR_AE_BITPTR, + ICLASS_WUR_AE_BITPTR, + ICLASS_RUR_AE_BITSUSED, + ICLASS_WUR_AE_BITSUSED, + ICLASS_RUR_AE_TABLESIZE, + ICLASS_WUR_AE_TABLESIZE, + ICLASS_RUR_AE_FIRST_TS, + ICLASS_WUR_AE_FIRST_TS, + ICLASS_RUR_AE_NEXTOFFSET, + ICLASS_WUR_AE_NEXTOFFSET, + ICLASS_RUR_AE_SEARCHDONE, + ICLASS_WUR_AE_SEARCHDONE, + ICLASS_RUR_AE_CWRAP, + ICLASS_WUR_AE_CWRAP, + ICLASS_AE_L8X4F_I, + ICLASS_AE_L8X4F_IP, + ICLASS_AE_L16M_XC, + ICLASS_AE_L16M_XC1, + ICLASS_AE_L16M_I, + ICLASS_AE_L16M_IU, + ICLASS_AE_L16M_X, + ICLASS_AE_L16M_XU, + ICLASS_AE_L16_XC, + ICLASS_AE_L16_XC1, + ICLASS_AE_L16_I, + ICLASS_AE_L16_IP, + ICLASS_AE_L16_X, + ICLASS_AE_L16_XP, + ICLASS_AE_L32F24_XC, + ICLASS_AE_L32F24_XC1, + ICLASS_AE_L32F24_I, + ICLASS_AE_L32F24_IP, + ICLASS_AE_L32F24_X, + ICLASS_AE_L32F24_XP, + ICLASS_AE_L32_XC, + ICLASS_AE_L32_XC1, + ICLASS_AE_L32_I, + ICLASS_AE_L32_IP, + ICLASS_AE_L32_X, + ICLASS_AE_L32_XP, + ICLASS_AE_L32M_XC, + ICLASS_AE_L32M_I, + ICLASS_AE_L32M_IU, + ICLASS_AE_L32M_X, + ICLASS_AE_L32M_XU, + ICLASS_AE_L16X2M_XC, + ICLASS_AE_L16X2M_XC1, + ICLASS_AE_L16X2M_I, + ICLASS_AE_L16X2M_IU, + ICLASS_AE_L16X2M_X, + ICLASS_AE_L16X2M_XU, + ICLASS_AE_L32X2F24_XC, + ICLASS_AE_L32X2F24_XC1, + ICLASS_AE_L32X2F24_I, + ICLASS_AE_L32X2F24_IP, + ICLASS_AE_L32X2F24_RIP, + ICLASS_AE_L32X2F24_RI, + ICLASS_AE_L32X2F24_RIC, + ICLASS_AE_L32X2F24_RIC1, + ICLASS_AE_L32X2F24_X, + ICLASS_AE_L32X2F24_XP, + ICLASS_AE_L32X2_XC, + ICLASS_AE_L32X2_XC1, + ICLASS_AE_L32X2_I, + ICLASS_AE_L32X2_IP, + ICLASS_AE_L32X2_RIC, + ICLASS_AE_L32X2_RIC1, + ICLASS_AE_L32X2_X, + ICLASS_AE_L32X2_XP, + ICLASS_AE_L16X4_XC, + ICLASS_AE_L16X4_XC1, + ICLASS_AE_L16X4_I, + ICLASS_AE_L16X4_IP, + ICLASS_AE_L16X4_X, + ICLASS_AE_L16X4_XP, + ICLASS_AE_L64_XC, + ICLASS_AE_L64_XC1, + ICLASS_AE_L64_I, + ICLASS_AE_L64_IP, + ICLASS_AE_L64_X, + ICLASS_AE_L64_XP, + ICLASS_AE_S16X2M_XC, + ICLASS_AE_S16X2M_XC1, + ICLASS_AE_S16X2M_I, + ICLASS_AE_S16X2M_IU, + ICLASS_AE_S16X2M_X, + ICLASS_AE_S16X2M_XU, + ICLASS_AE_S32X2F24_XC, + ICLASS_AE_S32X2F24_XC1, + ICLASS_AE_S32X2F24_I, + ICLASS_AE_S32X2F24_IP, + ICLASS_AE_S32X2F24_RIP, + ICLASS_AE_S32X2F24_RIC, + ICLASS_AE_S32X2F24_RIC1, + ICLASS_AE_S32X2F24_X, + ICLASS_AE_S32X2F24_XP, + ICLASS_AE_S32X2_XC, + ICLASS_AE_S32X2_XC1, + ICLASS_AE_S32X2_I, + ICLASS_AE_S32X2_IP, + ICLASS_AE_S32X2_RIC, + ICLASS_AE_S32X2_RIC1, + ICLASS_AE_S32X2_X, + ICLASS_AE_S32X2_XP, + ICLASS_AE_S32X2RNG_I, + ICLASS_AE_S32X2RNG_IP, + ICLASS_AE_S32X2RNG_X, + ICLASS_AE_S32X2RNG_XP, + ICLASS_AE_S16X4_XC, + ICLASS_AE_S16X4_XC1, + ICLASS_AE_S16X4_I, + ICLASS_AE_S16X4_IP, + ICLASS_AE_S16X4_X, + ICLASS_AE_S16X4_XP, + ICLASS_AE_S16M_L_XC, + ICLASS_AE_S16M_L_XC1, + ICLASS_AE_S16M_L_I, + ICLASS_AE_S16M_L_IU, + ICLASS_AE_S16M_L_X, + ICLASS_AE_S16M_L_XU, + ICLASS_AE_S32F24_L_XC, + ICLASS_AE_S32F24_L_XC1, + ICLASS_AE_S32F24_L_I, + ICLASS_AE_S32F24_L_IP, + ICLASS_AE_S32F24_L_X, + ICLASS_AE_S32F24_L_XP, + ICLASS_AE_S32_L_XC, + ICLASS_AE_S32_L_XC1, + ICLASS_AE_S32_L_I, + ICLASS_AE_S32_L_IP, + ICLASS_AE_S32_L_X, + ICLASS_AE_S32_L_XP, + ICLASS_AE_S16_0_XC, + ICLASS_AE_S16_0_XC1, + ICLASS_AE_S16_0_I, + ICLASS_AE_S16_0_IP, + ICLASS_AE_S16_0_X, + ICLASS_AE_S16_0_XP, + ICLASS_AE_S64_XC, + ICLASS_AE_S64_XC1, + ICLASS_AE_S64_I, + ICLASS_AE_S64_IP, + ICLASS_AE_S64_X, + ICLASS_AE_S64_XP, + ICLASS_AE_S32M_XC, + ICLASS_AE_S32M_I, + ICLASS_AE_S32M_IU, + ICLASS_AE_S32M_X, + ICLASS_AE_S32M_XU, + ICLASS_AE_ZALIGN64, + ICLASS_AE_LALIGN64_I, + ICLASS_AE_SALIGN64_I, + ICLASS_AE_MOVALIGN, + ICLASS_AE_LA64_PP, + ICLASS_AE_LA24POS_PC, + ICLASS_AE_LA24X2POS_PC, + ICLASS_AE_LA32X2POS_PC, + ICLASS_AE_LA16X4POS_PC, + ICLASS_AE_LA24NEG_PC, + ICLASS_AE_LA24X2NEG_PC, + ICLASS_AE_LA32X2NEG_PC, + ICLASS_AE_LA16X4NEG_PC, + ICLASS_AE_LA24POS_PC1, + ICLASS_AE_LA24X2POS_PC1, + ICLASS_AE_LA32X2POS_PC1, + ICLASS_AE_LA16X4POS_PC1, + ICLASS_AE_LA24NEG_PC1, + ICLASS_AE_LA24X2NEG_PC1, + ICLASS_AE_LA32X2NEG_PC1, + ICLASS_AE_LA16X4NEG_PC1, + ICLASS_AE_SA64POS_FP, + ICLASS_AE_SA64NEG_FP, + ICLASS_AE_LA32X2_IC, + ICLASS_AE_LA32X2_IC1, + ICLASS_AE_LA32X2_IP, + ICLASS_AE_LA32X2_RIP, + ICLASS_AE_LA32X2_RIC, + ICLASS_AE_LA32X2_RIC1, + ICLASS_AE_LA16X4_IC, + ICLASS_AE_LA16X4_IC1, + ICLASS_AE_LA16X4_IP, + ICLASS_AE_LA16X4_RIP, + ICLASS_AE_LA16X4_RIC, + ICLASS_AE_LA16X4_RIC1, + ICLASS_AE_LA32X2F24_IC, + ICLASS_AE_LA32X2F24_IC1, + ICLASS_AE_LA32X2F24_IP, + ICLASS_AE_LA32X2F24_RIP, + ICLASS_AE_LA32X2F24_RIC, + ICLASS_AE_LA32X2F24_RIC1, + ICLASS_AE_LA24_IC, + ICLASS_AE_LA24_IC1, + ICLASS_AE_LA24_IP, + ICLASS_AE_LA24_RIP, + ICLASS_AE_LA24_RIC, + ICLASS_AE_LA24_RIC1, + ICLASS_AE_LA24X2_IC, + ICLASS_AE_LA24X2_IC1, + ICLASS_AE_LA24X2_IP, + ICLASS_AE_LA24X2_RIP, + ICLASS_AE_LA24X2_RIC, + ICLASS_AE_LA24X2_RIC1, + ICLASS_AE_SA32X2_IC, + ICLASS_AE_SA32X2_IC1, + ICLASS_AE_SA32X2_IP, + ICLASS_AE_SA32X2_RIP, + ICLASS_AE_SA32X2_RIC, + ICLASS_AE_SA32X2_RIC1, + ICLASS_AE_SA16X4_IC, + ICLASS_AE_SA16X4_IC1, + ICLASS_AE_SA16X4_IP, + ICLASS_AE_SA16X4_RIP, + ICLASS_AE_SA16X4_RIC, + ICLASS_AE_SA16X4_RIC1, + ICLASS_AE_SA32X2F24_IC, + ICLASS_AE_SA32X2F24_IC1, + ICLASS_AE_SA32X2F24_IP, + ICLASS_AE_SA32X2F24_RIP, + ICLASS_AE_SA32X2F24_RIC, + ICLASS_AE_SA32X2F24_RIC1, + ICLASS_AE_SA24_L_IC, + ICLASS_AE_SA24_L_IC1, + ICLASS_AE_SA24_L_IP, + ICLASS_AE_SA24_L_RIP, + ICLASS_AE_SA24_L_RIC, + ICLASS_AE_SA24_L_RIC1, + ICLASS_AE_SA24X2_IC, + ICLASS_AE_SA24X2_IC1, + ICLASS_AE_SA24X2_IP, + ICLASS_AE_SA24X2_RIP, + ICLASS_AE_SA24X2_RIC, + ICLASS_AE_SA24X2_RIC1, + ICLASS_AE_ADDICIRC, + ICLASS_AE_ADDCIRC_XC1, + ICLASS_AE_ADDCIRC_XC, + ICLASS_AE_S32RA64S_I, + ICLASS_AE_S32RA64S_IP, + ICLASS_AE_S32RA64S_X, + ICLASS_AE_S32RA64S_XP, + ICLASS_AE_S32RA64S_XC, + ICLASS_AE_S32RA64S_XC1, + ICLASS_AE_S24RA64S_I, + ICLASS_AE_S24RA64S_IP, + ICLASS_AE_S24RA64S_X, + ICLASS_AE_S24RA64S_XP, + ICLASS_AE_S24RA64S_XC, + ICLASS_AE_S24RA64S_XC1, + ICLASS_AE_S32X2RA64S_IP, + ICLASS_AE_S24X2RA64S_IP, + ICLASS_AE_ADDBRBA32, + ICLASS_AE_BITSWAP, + ICLASS_AE_MUL32JS, + ICLASS_AE_ADDANDSUB32S, + ICLASS_AE_ADDANDSUBRNG32, + ICLASS_AE_ADDRNG32, + ICLASS_AE_SUBRNG32, + ICLASS_AE_CALCRNG3, + ICLASS_AE_CALCRNG2, + ICLASS_AE_CALCRNG1, + ICLASS_AE_RNG32X2, + ICLASS_AE_SEL16I, + ICLASS_AE_SEL16I_N, + ICLASS_AE_SHORTSWAP, + ICLASS_AE_MOVAB4, + ICLASS_AE_MOVAB2, + ICLASS_AE_MOVAB, + ICLASS_AE_MOVBA, + ICLASS_AE_MOVBA1X2, + ICLASS_AE_MOVBA4, + ICLASS_AE_MOVBA2, + ICLASS_AE_MOVB2, + ICLASS_AE_MOVB4, + ICLASS_AE_MOVT16X4, + ICLASS_AE_MOVF16X4, + ICLASS_AE_MOVT32X2, + ICLASS_AE_MOVF32X2, + ICLASS_AE_MOVSARA7X2, + ICLASS_AE_MOVSARD7, + ICLASS_AE_MOVASAR, + ICLASS_AE_MOVDA32X2, + ICLASS_AE_MOVDA32, + ICLASS_AE_MOVDA16X2, + ICLASS_AE_MOVDA16, + ICLASS_AE_MOVI, + ICLASS_AE_TRUNCP24A32X2, + ICLASS_AE_SAT16X4, + ICLASS_AE_CVT32X2F16_32, + ICLASS_AE_CVT32X2F16_10, + ICLASS_AE_SEXT32X2D16_32, + ICLASS_AE_SEXT32X2D16_10, + ICLASS_AE_CVTA32F24S_L, + ICLASS_AE_CVTA32F24S_H, + ICLASS_AE_CVTP24A16X2_LL, + ICLASS_AE_CVTP24A16X2_LH, + ICLASS_AE_CVTP24A16X2_HL, + ICLASS_AE_CVTP24A16X2_HH, + ICLASS_AE_TRUNCP24Q48X2, + ICLASS_AE_TRUNCA32X2F64S, + ICLASS_AE_TRUNCI32X2F64S, + ICLASS_AE_TRUNCA32F64S_L, + ICLASS_AE_TRUNCI32F64S_L, + ICLASS_AE_TRUNCP16, + ICLASS_AE_ROUND32X2F64SSYM, + ICLASS_AE_ROUND32X2F64SASYM, + ICLASS_AE_ROUND32X2F48SSYM, + ICLASS_AE_ROUND32X2F48SASYM, + ICLASS_AE_ROUND16X4F32SSYM, + ICLASS_AE_ROUND16X4F32SASYM, + ICLASS_AE_ROUND24X2F48SSYM, + ICLASS_AE_ROUND24X2F48SASYM, + ICLASS_AE_ROUNDSP16Q48X2SYM, + ICLASS_AE_ROUNDSP16Q48X2ASYM, + ICLASS_AE_MINABS32S, + ICLASS_AE_MAXABS32S, + ICLASS_AE_ROUNDSP16F24SYM, + ICLASS_AE_ROUNDSP16F24ASYM, + ICLASS_AE_MOV, + ICLASS_AE_MOVT64, + ICLASS_AE_MOVF64, + ICLASS_AE_CVTQ56A32S, + ICLASS_AE_CVT48A32, + ICLASS_AE_CVT64A32, + ICLASS_AE_CVTQ56P32S_L, + ICLASS_AE_CVTQ56P32S_H, + ICLASS_AE_CVT64F32_H, + ICLASS_AE_CVT48F32_L, + ICLASS_AE_CVT48F32_H, + ICLASS_AE_SAT48S, + ICLASS_AE_SATQ56S, + ICLASS_AE_SAT24S, + ICLASS_AE_TRUNCQ32, + ICLASS_AE_MINABS64S, + ICLASS_AE_MAXABS64S, + ICLASS_AE_ROUNDSQ32F48SYM, + ICLASS_AE_ROUNDSQ32F48ASYM, + ICLASS_AE_TRUNCA32Q48, + ICLASS_AE_MOVAD32_L, + ICLASS_AE_MOVAD32_H, + ICLASS_AE_MOVAD16_3, + ICLASS_AE_MOVAD16_2, + ICLASS_AE_MOVAD16_1, + ICLASS_AE_MOVAD16_0, + ICLASS_AE_SRA64_32, + ICLASS_AE_PKSR32, + ICLASS_AE_PKSR24, + ICLASS_AE_PKSRF32, + ICLASS_AE_TRUNCA16P24S_L, + ICLASS_AE_TRUNCA16P24S_H, + ICLASS_AE_ADD32, + ICLASS_AE_SUB32, + ICLASS_AE_ADDSUB32, + ICLASS_AE_SUBADD32, + ICLASS_AE_ADD16, + ICLASS_AE_SUB16, + ICLASS_AE_ADD32_HL_LH, + ICLASS_AE_NEG32, + ICLASS_AE_ABS32, + ICLASS_AE_ADD24S, + ICLASS_AE_SUB24S, + ICLASS_AE_ADD32S, + ICLASS_AE_SUB32S, + ICLASS_AE_ADDSUB32S, + ICLASS_AE_SUBADD32S, + ICLASS_AE_ADD16S, + ICLASS_AE_SUB16S, + ICLASS_AE_ADD32S_HL_LH, + ICLASS_AE_NEG24S, + ICLASS_AE_ABS24S, + ICLASS_AE_NEG32S, + ICLASS_AE_ABS32S, + ICLASS_AE_NEG16S, + ICLASS_AE_ABS16S, + ICLASS_AE_LT16, + ICLASS_AE_LE16, + ICLASS_AE_EQ16, + ICLASS_AE_LT32, + ICLASS_AE_LE32, + ICLASS_AE_EQ32, + ICLASS_AE_MIN32, + ICLASS_AE_MAX32, + ICLASS_AE_ADD64, + ICLASS_AE_SUB64, + ICLASS_AE_NEG64, + ICLASS_AE_ABS64, + ICLASS_AE_ADDSQ56S, + ICLASS_AE_SUBSQ56S, + ICLASS_AE_ADD64S, + ICLASS_AE_SUB64S, + ICLASS_AE_NEGSQ56S, + ICLASS_AE_ABSSQ56S, + ICLASS_AE_NEG64S, + ICLASS_AE_ABS64S, + ICLASS_AE_AND, + ICLASS_AE_NAND, + ICLASS_AE_OR, + ICLASS_AE_XOR, + ICLASS_AE_SLAI24, + ICLASS_AE_SRLI24, + ICLASS_AE_SRAI24, + ICLASS_AE_SLAS24, + ICLASS_AE_SRLS24, + ICLASS_AE_SRAS24, + ICLASS_AE_SRAI16, + ICLASS_AE_SRAI16R, + ICLASS_AE_SLAI32, + ICLASS_AE_SRLI32, + ICLASS_AE_SRAI32, + ICLASS_AE_SRAI32R, + ICLASS_AE_SLAS32, + ICLASS_AE_SRLS32, + ICLASS_AE_SRAS32, + ICLASS_AE_SLAA32, + ICLASS_AE_SRLA32, + ICLASS_AE_SRAA32, + ICLASS_AE_SLAI16S, + ICLASS_AE_SLAA16S, + ICLASS_AE_SRAA16S, + ICLASS_AE_SRAA16RS, + ICLASS_AE_SLAI24S, + ICLASS_AE_SLAS24S, + ICLASS_AE_SLAI32S, + ICLASS_AE_SLAS32S, + ICLASS_AE_SLAA32S, + ICLASS_AE_SRAA32S, + ICLASS_AE_SRAA32RS, + ICLASS_AE_SLASQ56, + ICLASS_AE_SRLSQ56, + ICLASS_AE_SRASQ56, + ICLASS_AE_SLAAQ56, + ICLASS_AE_SRLAQ56, + ICLASS_AE_SRAAQ56, + ICLASS_AE_SLAI64, + ICLASS_AE_SRLI64, + ICLASS_AE_SRAI64, + ICLASS_AE_SLAS64, + ICLASS_AE_SRLS64, + ICLASS_AE_SRAS64, + ICLASS_AE_SLAA64, + ICLASS_AE_SRLA64, + ICLASS_AE_SRAA64, + ICLASS_AE_SLAISQ56S, + ICLASS_AE_SLASSQ56S, + ICLASS_AE_SLAASQ56S, + ICLASS_AE_SLAI64S, + ICLASS_AE_SLAS64S, + ICLASS_AE_SLAA64S, + ICLASS_AE_LT64, + ICLASS_AE_LE64, + ICLASS_AE_EQ64, + ICLASS_AE_MAX64, + ICLASS_AE_MIN64, + ICLASS_AE_NSA64, + ICLASS_AE_NSAZ16_0, + ICLASS_AE_NSAZ32_L, + ICLASS_AE_MULS32F48P16S_LL, + ICLASS_AE_MULF32S_LL, + ICLASS_AE_MUL32_LL, + ICLASS_AE_MULF32S_LL_S2, + ICLASS_AE_MUL32_LL_S2, + ICLASS_AE_MULS32F48P16S_LL_S2, + ICLASS_AE_MULF32R_LL, + ICLASS_AE_MULF32RA_LL, + ICLASS_AE_MULF32RA_LL_S2, + ICLASS_AE_MULF32R_LL_S2, + ICLASS_AE_MULS32F48P16S_LH, + ICLASS_AE_MULF32S_LH, + ICLASS_AE_MUL32_LH, + ICLASS_AE_MULF32S_LH_S2, + ICLASS_AE_MUL32_LH_S2, + ICLASS_AE_MULS32F48P16S_LH_S2, + ICLASS_AE_MULF32R_LH, + ICLASS_AE_MULF32RA_LH, + ICLASS_AE_MULF32RA_LH_S2, + ICLASS_AE_MULF32R_LH_S2, + ICLASS_AE_MULS32F48P16S_HH, + ICLASS_AE_MULF32S_HH, + ICLASS_AE_MUL32_HH, + ICLASS_AE_MULF32S_HH_S2, + ICLASS_AE_MUL32_HH_S2, + ICLASS_AE_MULS32F48P16S_HH_S2, + ICLASS_AE_MULF32R_HH, + ICLASS_AE_MULF32RA_HH, + ICLASS_AE_MULF32RA_HH_S2, + ICLASS_AE_MULF32R_HH_S2, + ICLASS_AE_MULAS32F48P16S_LL, + ICLASS_AE_MULAF32S_LL, + ICLASS_AE_MULA32_LL, + ICLASS_AE_MULAF32S_LL_S2, + ICLASS_AE_MULA32_LL_S2, + ICLASS_AE_MULAS32F48P16S_LL_S2, + ICLASS_AE_MULAF32R_LL, + ICLASS_AE_MULAF32RA_LL, + ICLASS_AE_MULAF32RA_LL_S2, + ICLASS_AE_MULAF32R_LL_S2, + ICLASS_AE_MULAS32F48P16S_LH, + ICLASS_AE_MULAF32S_LH, + ICLASS_AE_MULA32_LH, + ICLASS_AE_MULAF32S_LH_S2, + ICLASS_AE_MULA32_LH_S2, + ICLASS_AE_MULAS32F48P16S_LH_S2, + ICLASS_AE_MULAF32R_LH, + ICLASS_AE_MULAF32RA_LH, + ICLASS_AE_MULAF32RA_LH_S2, + ICLASS_AE_MULAF32R_LH_S2, + ICLASS_AE_MULAS32F48P16S_HH, + ICLASS_AE_MULAF32S_HH, + ICLASS_AE_MULA32_HH, + ICLASS_AE_MULAF32S_HH_S2, + ICLASS_AE_MULA32_HH_S2, + ICLASS_AE_MULAS32F48P16S_HH_S2, + ICLASS_AE_MULAF32R_HH, + ICLASS_AE_MULAF32RA_HH, + ICLASS_AE_MULAF32RA_HH_S2, + ICLASS_AE_MULAF32R_HH_S2, + ICLASS_AE_MULSS32F48P16S_LL, + ICLASS_AE_MULSF32S_LL, + ICLASS_AE_MULS32_LL, + ICLASS_AE_MULSF32S_LL_S2, + ICLASS_AE_MULS32_LL_S2, + ICLASS_AE_MULSS32F48P16S_LL_S2, + ICLASS_AE_MULSF32R_LL, + ICLASS_AE_MULSF32RA_LL, + ICLASS_AE_MULSF32RA_LL_S2, + ICLASS_AE_MULSF32R_LL_S2, + ICLASS_AE_MULSS32F48P16S_LH, + ICLASS_AE_MULSF32S_LH, + ICLASS_AE_MULS32_LH, + ICLASS_AE_MULSF32S_LH_S2, + ICLASS_AE_MULS32_LH_S2, + ICLASS_AE_MULSS32F48P16S_LH_S2, + ICLASS_AE_MULSF32R_LH, + ICLASS_AE_MULSF32RA_LH, + ICLASS_AE_MULSF32RA_LH_S2, + ICLASS_AE_MULSF32R_LH_S2, + ICLASS_AE_MULSS32F48P16S_HH, + ICLASS_AE_MULSF32S_HH, + ICLASS_AE_MULS32_HH, + ICLASS_AE_MULSF32S_HH_S2, + ICLASS_AE_MULS32_HH_S2, + ICLASS_AE_MULSS32F48P16S_HH_S2, + ICLASS_AE_MULSF32R_HH, + ICLASS_AE_MULSF32RA_HH, + ICLASS_AE_MULSF32RA_HH_S2, + ICLASS_AE_MULSF32R_HH_S2, + ICLASS_AE_MUL32U_LL, + ICLASS_AE_MULA32U_LL, + ICLASS_AE_MULS32U_LL, + ICLASS_AE_MULF16SS_33, + ICLASS_AE_MULF16SS_33_S2, + ICLASS_AE_MULF16SS_22, + ICLASS_AE_MULF16SS_22_S2, + ICLASS_AE_MULF16SS_32, + ICLASS_AE_MULF16SS_32_S2, + ICLASS_AE_MULF16SS_21, + ICLASS_AE_MULF16SS_21_S2, + ICLASS_AE_MULF16SS_31, + ICLASS_AE_MULF16SS_31_S2, + ICLASS_AE_MULF16SS_30, + ICLASS_AE_MULF16SS_30_S2, + ICLASS_AE_MULF16SS_10, + ICLASS_AE_MULF16SS_10_S2, + ICLASS_AE_MULF16SS_20, + ICLASS_AE_MULF16SS_20_S2, + ICLASS_AE_MULF16SS_11, + ICLASS_AE_MULF16SS_11_S2, + ICLASS_AE_MULF16SS_00, + ICLASS_AE_MULF16SS_00_S2, + ICLASS_AE_MULSF16SS_33, + ICLASS_AE_MULSF16SS_33_S2, + ICLASS_AE_MULSF16SS_22, + ICLASS_AE_MULSF16SS_22_S2, + ICLASS_AE_MULSF16SS_32, + ICLASS_AE_MULSF16SS_32_S2, + ICLASS_AE_MULSF16SS_21, + ICLASS_AE_MULSF16SS_21_S2, + ICLASS_AE_MULSF16SS_31, + ICLASS_AE_MULSF16SS_31_S2, + ICLASS_AE_MULSF16SS_30, + ICLASS_AE_MULSF16SS_30_S2, + ICLASS_AE_MULSF16SS_10, + ICLASS_AE_MULSF16SS_10_S2, + ICLASS_AE_MULSF16SS_20, + ICLASS_AE_MULSF16SS_20_S2, + ICLASS_AE_MULSF16SS_11, + ICLASS_AE_MULSF16SS_11_S2, + ICLASS_AE_MULSF16SS_00, + ICLASS_AE_MULSF16SS_00_S2, + ICLASS_AE_MULAF16SS_33, + ICLASS_AE_MULAF16SS_33_S2, + ICLASS_AE_MULAF16SS_22, + ICLASS_AE_MULAF16SS_22_S2, + ICLASS_AE_MULAF16SS_32, + ICLASS_AE_MULAF16SS_32_S2, + ICLASS_AE_MULAF16SS_21, + ICLASS_AE_MULAF16SS_21_S2, + ICLASS_AE_MULAF16SS_31, + ICLASS_AE_MULAF16SS_31_S2, + ICLASS_AE_MULAF16SS_30, + ICLASS_AE_MULAF16SS_30_S2, + ICLASS_AE_MULAF16SS_10, + ICLASS_AE_MULAF16SS_10_S2, + ICLASS_AE_MULAF16SS_20, + ICLASS_AE_MULAF16SS_20_S2, + ICLASS_AE_MULAF16SS_11, + ICLASS_AE_MULAF16SS_11_S2, + ICLASS_AE_MULAF16SS_00, + ICLASS_AE_MULAF16SS_00_S2, + ICLASS_AE_MULAAFD16SS_33_22, + ICLASS_AE_MULAAFD16SS_33_22_S2, + ICLASS_AE_MULAAFD16SS_13_02, + ICLASS_AE_MULAAFD16SS_13_02_S2, + ICLASS_AE_MULAAFD16SS_11_00, + ICLASS_AE_MULAAFD16SS_11_00_S2, + ICLASS_AE_MULSSFD16SS_33_22, + ICLASS_AE_MULSSFD16SS_33_22_S2, + ICLASS_AE_MULSSFD16SS_13_02, + ICLASS_AE_MULSSFD16SS_13_02_S2, + ICLASS_AE_MULSSFD16SS_11_00, + ICLASS_AE_MULSSFD16SS_11_00_S2, + ICLASS_AE_MULZAAFD16SS_33_22, + ICLASS_AE_MULZAAFD16SS_33_22_S2, + ICLASS_AE_MULZAAFD16SS_13_02, + ICLASS_AE_MULZAAFD16SS_13_02_S2, + ICLASS_AE_MULZAAFD16SS_11_00, + ICLASS_AE_MULZAAFD16SS_11_00_S2, + ICLASS_AE_MULZSSFD16SS_33_22, + ICLASS_AE_MULZSSFD16SS_33_22_S2, + ICLASS_AE_MULZSSFD16SS_13_02, + ICLASS_AE_MULZSSFD16SS_13_02_S2, + ICLASS_AE_MULZSSFD16SS_11_00, + ICLASS_AE_MULZSSFD16SS_11_00_S2, + ICLASS_AE_MULF48Q32SP16S_L, + ICLASS_AE_MULF48Q32SP16S_L_S2, + ICLASS_AE_MULF48Q32SP16U_L, + ICLASS_AE_MULF48Q32SP16U_L_S2, + ICLASS_AE_MULQ32SP16S_L, + ICLASS_AE_MULQ32SP16S_L_S2, + ICLASS_AE_MULQ32SP16U_L, + ICLASS_AE_MULQ32SP16U_L_S2, + ICLASS_AE_MULAF48Q32SP16S_L, + ICLASS_AE_MULAF48Q32SP16S_L_S2, + ICLASS_AE_MULAF48Q32SP16U_L, + ICLASS_AE_MULAF48Q32SP16U_L_S2, + ICLASS_AE_MULAQ32SP16S_L, + ICLASS_AE_MULAQ32SP16S_L_S2, + ICLASS_AE_MULAQ32SP16U_L, + ICLASS_AE_MULAQ32SP16U_L_S2, + ICLASS_AE_MULSF48Q32SP16S_L, + ICLASS_AE_MULSF48Q32SP16S_L_S2, + ICLASS_AE_MULSF48Q32SP16U_L, + ICLASS_AE_MULSF48Q32SP16U_L_S2, + ICLASS_AE_MULSQ32SP16S_L, + ICLASS_AE_MULSQ32SP16S_L_S2, + ICLASS_AE_MULSQ32SP16U_L, + ICLASS_AE_MULSQ32SP16U_L_S2, + ICLASS_AE_MULFP24X2RA, + ICLASS_AE_MULFP24X2R, + ICLASS_AE_MULFP24X2RA_S2, + ICLASS_AE_MULFP24X2R_S2, + ICLASS_AE_MULAFP24X2RA, + ICLASS_AE_MULAFP24X2R, + ICLASS_AE_MULAFP24X2RA_S2, + ICLASS_AE_MULAFP24X2R_S2, + ICLASS_AE_MULSFP24X2RA, + ICLASS_AE_MULSFP24X2R, + ICLASS_AE_MULSFP24X2RA_S2, + ICLASS_AE_MULSFP24X2R_S2, + ICLASS_AE_MULZAAFD32S_HH_LL, + ICLASS_AE_MULZAAFD32RA_HH_LL, + ICLASS_AE_MULZAAD32_HH_LL, + ICLASS_AE_MULZAAFD32S_HH_LL_S2, + ICLASS_AE_MULZAAFD32RA_HH_LL_S2, + ICLASS_AE_MULZAAD32_HH_LL_S2, + ICLASS_AE_MULZAAFD32S_HL_LH, + ICLASS_AE_MULZAAFD32RA_HL_LH, + ICLASS_AE_MULZAAD32_HL_LH, + ICLASS_AE_MULZAAFD32S_HL_LH_S2, + ICLASS_AE_MULZAAFD32RA_HL_LH_S2, + ICLASS_AE_MULZAAD32_HL_LH_S2, + ICLASS_AE_MULZASFD32S_HH_LL, + ICLASS_AE_MULZASFD32RA_HH_LL, + ICLASS_AE_MULZASD32_HH_LL, + ICLASS_AE_MULZASFD32S_HH_LL_S2, + ICLASS_AE_MULZASFD32RA_HH_LL_S2, + ICLASS_AE_MULZASD32_HH_LL_S2, + ICLASS_AE_MULZASFD32S_HL_LH, + ICLASS_AE_MULZASFD32RA_HL_LH, + ICLASS_AE_MULZASD32_HL_LH, + ICLASS_AE_MULZASFD32S_HL_LH_S2, + ICLASS_AE_MULZASFD32RA_HL_LH_S2, + ICLASS_AE_MULZASD32_HL_LH_S2, + ICLASS_AE_MULZSAFD32S_HH_LL, + ICLASS_AE_MULZSAFD32RA_HH_LL, + ICLASS_AE_MULZSAD32_HH_LL, + ICLASS_AE_MULZSAFD32S_HH_LL_S2, + ICLASS_AE_MULZSAFD32RA_HH_LL_S2, + ICLASS_AE_MULZSAD32_HH_LL_S2, + ICLASS_AE_MULZSSFD32S_HH_LL, + ICLASS_AE_MULZSSFD32RA_HH_LL, + ICLASS_AE_MULZSSD32_HH_LL, + ICLASS_AE_MULZSSFD32S_HH_LL_S2, + ICLASS_AE_MULZSSFD32RA_HH_LL_S2, + ICLASS_AE_MULZSSD32_HH_LL_S2, + ICLASS_AE_MULZSSFD32S_HL_LH, + ICLASS_AE_MULZSSFD32RA_HL_LH, + ICLASS_AE_MULZSSD32_HL_LH, + ICLASS_AE_MULZSSFD32S_HL_LH_S2, + ICLASS_AE_MULZSSFD32RA_HL_LH_S2, + ICLASS_AE_MULZSSD32_HL_LH_S2, + ICLASS_AE_MULAAFD32S_HH_LL, + ICLASS_AE_MULAAFD32RA_HH_LL, + ICLASS_AE_MULAAD32_HH_LL, + ICLASS_AE_MULAAFD32S_HH_LL_S2, + ICLASS_AE_MULAAFD32RA_HH_LL_S2, + ICLASS_AE_MULAAD32_HH_LL_S2, + ICLASS_AE_MULAAFD32S_HL_LH, + ICLASS_AE_MULAAFD32RA_HL_LH, + ICLASS_AE_MULAAD32_HL_LH, + ICLASS_AE_MULAAFD32S_HL_LH_S2, + ICLASS_AE_MULAAFD32RA_HL_LH_S2, + ICLASS_AE_MULAAD32_HL_LH_S2, + ICLASS_AE_MULASFD32S_HH_LL, + ICLASS_AE_MULASFD32RA_HH_LL, + ICLASS_AE_MULASD32_HH_LL, + ICLASS_AE_MULASFD32S_HH_LL_S2, + ICLASS_AE_MULASFD32RA_HH_LL_S2, + ICLASS_AE_MULASD32_HH_LL_S2, + ICLASS_AE_MULASFD32S_HL_LH, + ICLASS_AE_MULASFD32RA_HL_LH, + ICLASS_AE_MULASD32_HL_LH, + ICLASS_AE_MULASFD32S_HL_LH_S2, + ICLASS_AE_MULASFD32RA_HL_LH_S2, + ICLASS_AE_MULASD32_HL_LH_S2, + ICLASS_AE_MULSAFD32S_HH_LL, + ICLASS_AE_MULSAFD32RA_HH_LL, + ICLASS_AE_MULSAD32_HH_LL, + ICLASS_AE_MULSAFD32S_HH_LL_S2, + ICLASS_AE_MULSAFD32RA_HH_LL_S2, + ICLASS_AE_MULSAD32_HH_LL_S2, + ICLASS_AE_MULSSFD32S_HH_LL, + ICLASS_AE_MULSSFD32RA_HH_LL, + ICLASS_AE_MULSSD32_HH_LL, + ICLASS_AE_MULSSFD32S_HH_LL_S2, + ICLASS_AE_MULSSFD32RA_HH_LL_S2, + ICLASS_AE_MULSSD32_HH_LL_S2, + ICLASS_AE_MULSSFD32S_HL_LH, + ICLASS_AE_MULSSFD32RA_HL_LH, + ICLASS_AE_MULSSD32_HL_LH, + ICLASS_AE_MULSSFD32S_HL_LH_S2, + ICLASS_AE_MULSSFD32RA_HL_LH_S2, + ICLASS_AE_MULSSD32_HL_LH_S2, + ICLASS_AE_MULF32X16_L0, + ICLASS_AE_MUL32X16_L0, + ICLASS_AE_MULF32X16_L0_S2, + ICLASS_AE_MUL32X16_L0_S2, + ICLASS_AE_MULF32X16_L1, + ICLASS_AE_MUL32X16_L1, + ICLASS_AE_MULF32X16_L1_S2, + ICLASS_AE_MUL32X16_L1_S2, + ICLASS_AE_MULF32X16_L2, + ICLASS_AE_MUL32X16_L2, + ICLASS_AE_MULF32X16_L2_S2, + ICLASS_AE_MUL32X16_L2_S2, + ICLASS_AE_MULF32X16_L3, + ICLASS_AE_MUL32X16_L3, + ICLASS_AE_MULF32X16_L3_S2, + ICLASS_AE_MUL32X16_L3_S2, + ICLASS_AE_MULF32X16_H0, + ICLASS_AE_MUL32X16_H0, + ICLASS_AE_MULF32X16_H0_S2, + ICLASS_AE_MUL32X16_H0_S2, + ICLASS_AE_MULF32X16_H1, + ICLASS_AE_MUL32X16_H1, + ICLASS_AE_MULF32X16_H1_S2, + ICLASS_AE_MUL32X16_H1_S2, + ICLASS_AE_MULF32X16_H2, + ICLASS_AE_MUL32X16_H2, + ICLASS_AE_MULF32X16_H2_S2, + ICLASS_AE_MUL32X16_H2_S2, + ICLASS_AE_MULF32X16_H3, + ICLASS_AE_MUL32X16_H3, + ICLASS_AE_MULF32X16_H3_S2, + ICLASS_AE_MUL32X16_H3_S2, + ICLASS_AE_MULAF32X16_L0, + ICLASS_AE_MULA32X16_L0, + ICLASS_AE_MULAF32X16_L0_S2, + ICLASS_AE_MULA32X16_L0_S2, + ICLASS_AE_MULAF32X16_L1, + ICLASS_AE_MULA32X16_L1, + ICLASS_AE_MULAF32X16_L1_S2, + ICLASS_AE_MULA32X16_L1_S2, + ICLASS_AE_MULAF32X16_L2, + ICLASS_AE_MULA32X16_L2, + ICLASS_AE_MULAF32X16_L2_S2, + ICLASS_AE_MULA32X16_L2_S2, + ICLASS_AE_MULAF32X16_L3, + ICLASS_AE_MULA32X16_L3, + ICLASS_AE_MULAF32X16_L3_S2, + ICLASS_AE_MULA32X16_L3_S2, + ICLASS_AE_MULAF32X16_H0, + ICLASS_AE_MULA32X16_H0, + ICLASS_AE_MULAF32X16_H0_S2, + ICLASS_AE_MULA32X16_H0_S2, + ICLASS_AE_MULAF32X16_H1, + ICLASS_AE_MULA32X16_H1, + ICLASS_AE_MULAF32X16_H1_S2, + ICLASS_AE_MULA32X16_H1_S2, + ICLASS_AE_MULAF32X16_H2, + ICLASS_AE_MULA32X16_H2, + ICLASS_AE_MULAF32X16_H2_S2, + ICLASS_AE_MULA32X16_H2_S2, + ICLASS_AE_MULAF32X16_H3, + ICLASS_AE_MULA32X16_H3, + ICLASS_AE_MULAF32X16_H3_S2, + ICLASS_AE_MULA32X16_H3_S2, + ICLASS_AE_MULSF32X16_L0, + ICLASS_AE_MULS32X16_L0, + ICLASS_AE_MULSF32X16_L0_S2, + ICLASS_AE_MULS32X16_L0_S2, + ICLASS_AE_MULSF32X16_L1, + ICLASS_AE_MULS32X16_L1, + ICLASS_AE_MULSF32X16_L1_S2, + ICLASS_AE_MULS32X16_L1_S2, + ICLASS_AE_MULSF32X16_L2, + ICLASS_AE_MULS32X16_L2, + ICLASS_AE_MULSF32X16_L2_S2, + ICLASS_AE_MULS32X16_L2_S2, + ICLASS_AE_MULSF32X16_L3, + ICLASS_AE_MULS32X16_L3, + ICLASS_AE_MULSF32X16_L3_S2, + ICLASS_AE_MULS32X16_L3_S2, + ICLASS_AE_MULSF32X16_H0, + ICLASS_AE_MULS32X16_H0, + ICLASS_AE_MULSF32X16_H0_S2, + ICLASS_AE_MULS32X16_H0_S2, + ICLASS_AE_MULSF32X16_H1, + ICLASS_AE_MULS32X16_H1, + ICLASS_AE_MULSF32X16_H1_S2, + ICLASS_AE_MULS32X16_H1_S2, + ICLASS_AE_MULSF32X16_H2, + ICLASS_AE_MULS32X16_H2, + ICLASS_AE_MULSF32X16_H2_S2, + ICLASS_AE_MULS32X16_H2_S2, + ICLASS_AE_MULSF32X16_H3, + ICLASS_AE_MULS32X16_H3, + ICLASS_AE_MULSF32X16_H3_S2, + ICLASS_AE_MULS32X16_H3_S2, + ICLASS_AE_MULAAFD32X16_H3_L2, + ICLASS_AE_MULAAD32X16_H3_L2, + ICLASS_AE_MULAAFD32X16_H3_L2_S2, + ICLASS_AE_MULAAD32X16_H3_L2_S2, + ICLASS_AE_MULAAFD32X16_H1_L0, + ICLASS_AE_MULAAD32X16_H1_L0, + ICLASS_AE_MULAAFD32X16_H1_L0_S2, + ICLASS_AE_MULAAD32X16_H1_L0_S2, + ICLASS_AE_MULASFD32X16_H3_L2, + ICLASS_AE_MULASD32X16_H3_L2, + ICLASS_AE_MULASFD32X16_H3_L2_S2, + ICLASS_AE_MULASD32X16_H3_L2_S2, + ICLASS_AE_MULASFD32X16_H1_L0, + ICLASS_AE_MULASD32X16_H1_L0, + ICLASS_AE_MULASFD32X16_H1_L0_S2, + ICLASS_AE_MULASD32X16_H1_L0_S2, + ICLASS_AE_MULSAFD32X16_H3_L2, + ICLASS_AE_MULSAD32X16_H3_L2, + ICLASS_AE_MULSAFD32X16_H3_L2_S2, + ICLASS_AE_MULSAD32X16_H3_L2_S2, + ICLASS_AE_MULSAFD32X16_H1_L0, + ICLASS_AE_MULSAD32X16_H1_L0, + ICLASS_AE_MULSAFD32X16_H1_L0_S2, + ICLASS_AE_MULSAD32X16_H1_L0_S2, + ICLASS_AE_MULSSFD32X16_H3_L2, + ICLASS_AE_MULSSD32X16_H3_L2, + ICLASS_AE_MULSSFD32X16_H3_L2_S2, + ICLASS_AE_MULSSD32X16_H3_L2_S2, + ICLASS_AE_MULSSFD32X16_H1_L0, + ICLASS_AE_MULSSD32X16_H1_L0, + ICLASS_AE_MULSSFD32X16_H1_L0_S2, + ICLASS_AE_MULSSD32X16_H1_L0_S2, + ICLASS_AE_MULZAAFD32X16_H3_L2, + ICLASS_AE_MULZAAD32X16_H3_L2, + ICLASS_AE_MULZAAFD32X16_H3_L2_S2, + ICLASS_AE_MULZAAD32X16_H3_L2_S2, + ICLASS_AE_MULZAAFD32X16_H1_L0, + ICLASS_AE_MULZAAD32X16_H1_L0, + ICLASS_AE_MULZAAFD32X16_H1_L0_S2, + ICLASS_AE_MULZAAD32X16_H1_L0_S2, + ICLASS_AE_MULZASFD32X16_H3_L2, + ICLASS_AE_MULZASD32X16_H3_L2, + ICLASS_AE_MULZASFD32X16_H3_L2_S2, + ICLASS_AE_MULZASD32X16_H3_L2_S2, + ICLASS_AE_MULZASFD32X16_H1_L0, + ICLASS_AE_MULZASD32X16_H1_L0, + ICLASS_AE_MULZASFD32X16_H1_L0_S2, + ICLASS_AE_MULZASD32X16_H1_L0_S2, + ICLASS_AE_MULZSAFD32X16_H3_L2, + ICLASS_AE_MULZSAD32X16_H3_L2, + ICLASS_AE_MULZSAFD32X16_H3_L2_S2, + ICLASS_AE_MULZSAD32X16_H3_L2_S2, + ICLASS_AE_MULZSAFD32X16_H1_L0, + ICLASS_AE_MULZSAD32X16_H1_L0, + ICLASS_AE_MULZSAFD32X16_H1_L0_S2, + ICLASS_AE_MULZSAD32X16_H1_L0_S2, + ICLASS_AE_MULZSSFD32X16_H3_L2, + ICLASS_AE_MULZSSD32X16_H3_L2, + ICLASS_AE_MULZSSFD32X16_H3_L2_S2, + ICLASS_AE_MULZSSD32X16_H3_L2_S2, + ICLASS_AE_MULZSSFD32X16_H1_L0, + ICLASS_AE_MULZSSD32X16_H1_L0, + ICLASS_AE_MULZSSFD32X16_H1_L0_S2, + ICLASS_AE_MULZSSD32X16_H1_L0_S2, + ICLASS_AE_MULZAAFD32X16_H2_L3, + ICLASS_AE_MULZAAFD32X16_H0_L1, + ICLASS_AE_MULAAFD32X16_H2_L3, + ICLASS_AE_MULAAFD32X16_H0_L1, + ICLASS_AE_MULZAAD32X16_H2_L3, + ICLASS_AE_MULZAAD32X16_H0_L1, + ICLASS_AE_MULAAD32X16_H2_L3, + ICLASS_AE_MULAAD32X16_H0_L1, + ICLASS_AE_MULZAAFD32X16_H2_L3_S2, + ICLASS_AE_MULZAAFD32X16_H0_L1_S2, + ICLASS_AE_MULAAFD32X16_H2_L3_S2, + ICLASS_AE_MULAAFD32X16_H0_L1_S2, + ICLASS_AE_MULZAAD32X16_H2_L3_S2, + ICLASS_AE_MULZAAD32X16_H0_L1_S2, + ICLASS_AE_MULAAD32X16_H2_L3_S2, + ICLASS_AE_MULAAD32X16_H0_L1_S2, + ICLASS_AE_MULP32X16X2_H, + ICLASS_AE_MULFP32X16X2RS_H, + ICLASS_AE_MULFP32X16X2RAS_H, + ICLASS_AE_MULFP32X16X2S_H, + ICLASS_AE_MULFP32X16X2S_H_S2, + ICLASS_AE_MULP32X16X2_H_S2, + ICLASS_AE_MULFP32X16X2RS_H_S2, + ICLASS_AE_MULFP32X16X2RAS_H_S2, + ICLASS_AE_MULP32X16X2_L, + ICLASS_AE_MULFP32X16X2RS_L, + ICLASS_AE_MULFP32X16X2RAS_L, + ICLASS_AE_MULFP32X16X2S_L, + ICLASS_AE_MULFP32X16X2S_L_S2, + ICLASS_AE_MULP32X16X2_L_S2, + ICLASS_AE_MULFP32X16X2RS_L_S2, + ICLASS_AE_MULFP32X16X2RAS_L_S2, + ICLASS_AE_MULAP32X16X2_H, + ICLASS_AE_MULAFP32X16X2RS_H, + ICLASS_AE_MULAFP32X16X2RAS_H, + ICLASS_AE_MULAFP32X16X2S_H, + ICLASS_AE_MULAFP32X16X2S_H_S2, + ICLASS_AE_MULAP32X16X2_H_S2, + ICLASS_AE_MULAFP32X16X2RS_H_S2, + ICLASS_AE_MULAFP32X16X2RAS_H_S2, + ICLASS_AE_MULAP32X16X2_L, + ICLASS_AE_MULAFP32X16X2RS_L, + ICLASS_AE_MULAFP32X16X2RAS_L, + ICLASS_AE_MULAFP32X16X2S_L, + ICLASS_AE_MULAFP32X16X2S_L_S2, + ICLASS_AE_MULAP32X16X2_L_S2, + ICLASS_AE_MULAFP32X16X2RS_L_S2, + ICLASS_AE_MULAFP32X16X2RAS_L_S2, + ICLASS_AE_MULSP32X16X2_H, + ICLASS_AE_MULSFP32X16X2RS_H, + ICLASS_AE_MULSFP32X16X2RAS_H, + ICLASS_AE_MULSFP32X16X2S_H, + ICLASS_AE_MULSFP32X16X2S_H_S2, + ICLASS_AE_MULSP32X16X2_H_S2, + ICLASS_AE_MULSFP32X16X2RS_H_S2, + ICLASS_AE_MULSFP32X16X2RAS_H_S2, + ICLASS_AE_MULSP32X16X2_L, + ICLASS_AE_MULSFP32X16X2RS_L, + ICLASS_AE_MULSFP32X16X2RAS_L, + ICLASS_AE_MULSFP32X16X2S_L, + ICLASS_AE_MULSFP32X16X2S_L_S2, + ICLASS_AE_MULSP32X16X2_L_S2, + ICLASS_AE_MULSFP32X16X2RS_L_S2, + ICLASS_AE_MULSFP32X16X2RAS_L_S2, + ICLASS_AE_MULP32X2, + ICLASS_AE_MULFP32X2RS, + ICLASS_AE_MULFP32X2RAS, + ICLASS_AE_MULP32X2_S2, + ICLASS_AE_MULFP32X2RS_S2, + ICLASS_AE_MULFP32X2RAS_S2, + ICLASS_AE_MULAP32X2, + ICLASS_AE_MULAFP32X2RS, + ICLASS_AE_MULAFP32X2RAS, + ICLASS_AE_MULAP32X2_S2, + ICLASS_AE_MULAFP32X2RS_S2, + ICLASS_AE_MULAFP32X2RAS_S2, + ICLASS_AE_MULSP32X2, + ICLASS_AE_MULSFP32X2RS, + ICLASS_AE_MULSFP32X2RAS, + ICLASS_AE_MULSP32X2_S2, + ICLASS_AE_MULSFP32X2RS_S2, + ICLASS_AE_MULSFP32X2RAS_S2, + ICLASS_AE_MULFP16X4S, + ICLASS_AE_MULFP16X4RAS, + ICLASS_AE_MULC32, + ICLASS_AE_MULFC24RA, + ICLASS_AE_MULFC32RAS, + ICLASS_AE_MULC32X16_L, + ICLASS_AE_MULFC32X16RAS_L, + ICLASS_AE_MULC32X16_H, + ICLASS_AE_MULFC32X16RAS_H, + ICLASS_AE_MULAC32, + ICLASS_AE_MULAFC24RA, + ICLASS_AE_MULAFC32RAS, + ICLASS_AE_MULAC32X16_L, + ICLASS_AE_MULAFC32X16RAS_L, + ICLASS_AE_MULAC32X16_H, + ICLASS_AE_MULAFC32X16RAS_H, + ICLASS_AE_MULF16X4SS, + ICLASS_AE_MULAF16X4SS, + ICLASS_AE_MULSF16X4SS, + ICLASS_AE_MUL16X4, + ICLASS_AE_MULA16X4, + ICLASS_AE_MULS16X4, + ICLASS_AE_MULFD32X2S_FIR_H, + ICLASS_AE_MULFD32X2RA_FIR_H, + ICLASS_AE_MULFD32X2S_FIR_L, + ICLASS_AE_MULFD32X2RA_FIR_L, + ICLASS_AE_MULFD32X16X2_FIR_HH, + ICLASS_AE_MULFD32X16X2_FIR_HL, + ICLASS_AE_MULFD32X16X2_FIR_LH, + ICLASS_AE_MULFD32X16X2_FIR_LL, + ICLASS_AE_MULAFD32X2S_FIR_H, + ICLASS_AE_MULAFD32X2RA_FIR_H, + ICLASS_AE_MULAFD32X2S_FIR_L, + ICLASS_AE_MULAFD32X2RA_FIR_L, + ICLASS_AE_MULAFD32X16X2_FIR_HH, + ICLASS_AE_MULAFD32X16X2_FIR_HL, + ICLASS_AE_MULAFD32X16X2_FIR_LH, + ICLASS_AE_MULAFD32X16X2_FIR_LL, + ICLASS_AE_MULZAAAAFQ32X16, + ICLASS_AE_MULAAAAFQ32X16, + ICLASS_AE_MULZAAAAFQ32X16_S2, + ICLASS_AE_MULAAAAFQ32X16_S2, + ICLASS_AE_MULZAAAAQ32X16, + ICLASS_AE_MULAAAAQ32X16, + ICLASS_AE_MULZAAAAQ32X16_S2, + ICLASS_AE_MULAAAAQ32X16_S2, + ICLASS_AE_MUL16_00, + ICLASS_AE_MULA16_00, + ICLASS_AE_MUL16_00_S2, + ICLASS_AE_MULA16_00_S2, + ICLASS_AE_MULZAAAAQ16, + ICLASS_AE_MULAAAAQ16, + ICLASS_AE_MULZAAAAQ16_S2, + ICLASS_AE_MULAAAAQ16_S2, + ICLASS_AE_DIV64D32_H, + ICLASS_AE_DIV64D32_L, + ICLASS_AE_SHA32, + ICLASS_AE_VLDL32T, + ICLASS_AE_VLDL16T, + ICLASS_AE_VLDL16C, + ICLASS_AE_VLDL16C_IP, + ICLASS_AE_VLDL16C_IC, + ICLASS_AE_VLDL16C_IC1, + ICLASS_AE_VLDSHT, + ICLASS_AE_LB, + ICLASS_AE_LBI, + ICLASS_AE_LBK, + ICLASS_AE_LBKI, + ICLASS_AE_LBS, + ICLASS_AE_LBSI, + ICLASS_AE_DB, + ICLASS_AE_DBI, + ICLASS_AE_DB_IC, + ICLASS_AE_DBI_IC, + ICLASS_AE_DB_IC1, + ICLASS_AE_DBI_IC1, + ICLASS_AE_DB_IP, + ICLASS_AE_DBI_IP, + ICLASS_AE_VLEL32T, + ICLASS_AE_VLEL16T, + ICLASS_AE_SB, + ICLASS_AE_SBI, + ICLASS_AE_VLES16C, + ICLASS_AE_SBF, + ICLASS_AE_SB_IC, + ICLASS_AE_SBI_IC, + ICLASS_AE_VLES16C_IC, + ICLASS_AE_SBF_IC, + ICLASS_AE_SB_IC1, + ICLASS_AE_SBI_IC1, + ICLASS_AE_VLES16C_IC1, + ICLASS_AE_SBF_IC1, + ICLASS_AE_SB_IP, + ICLASS_AE_SBI_IP, + ICLASS_AE_VLES16C_IP, + ICLASS_AE_SBF_IP, + ICLASS_AE_SEXT32, + ICLASS_AE_MOVAE, + ICLASS_AE_MOVEA, + ICLASS_AE_MOVEEP, + ICLASS_AE_SEXT72, + ICLASS_AE_ADD72, + ICLASS_AE_SUB72, + ICLASS_AE_ADD72X64, + ICLASS_AE_SUB72X64, + ICLASS_AE_MUL32EP_HH, + ICLASS_AE_MUL32EP_HH_S2, + ICLASS_AE_MULA32EP_HH, + ICLASS_AE_MULS32EP_HH, + ICLASS_AE_MULA32EP_HH_S2, + ICLASS_AE_MULS32EP_HH_S2, + ICLASS_AE_MULZAAD32EP_HH_LL, + ICLASS_AE_MULZSSD32EP_HH_LL, + ICLASS_AE_MULAAD32EP_HH_LL, + ICLASS_AE_MULSSD32EP_HH_LL, + ICLASS_AE_MULZAAD32EP_HH_LL_S2, + ICLASS_AE_MULZSSD32EP_HH_LL_S2, + ICLASS_AE_MULAAD32EP_HH_LL_S2, + ICLASS_AE_MULSSD32EP_HH_LL_S2, + ICLASS_AE_MULAAD32USEP_HL_LH, + ICLASS_AE_MULAAD32USEP_HL_LH_S2, + ICLASS_AE_MULZAAD32USEP_HL_LH, + ICLASS_AE_MULZAAD32USEP_HL_LH_S2, + ICLASS_AE_MUL32USEP_LH, + ICLASS_AE_MULA32USEP_LH, + ICLASS_AE_MUL32USEP_LL, + ICLASS_AE_MULA32USEP_LL, + ICLASS_AE_SRAI72, + ICLASS_AE_SLAI72, + ICLASS_AE_SAT64S, + ICLASS_AE_L16SI_N, + ICLASS_AE_L16UI_N, + ICLASS_AE_S16I_N, + ICLASS_AE_MOVFCRFSRV, + ICLASS_AE_MOVVFCRFSR, + ICLASS_RFR, + ICLASS_WFR, + ICLASS_MOVT_S, + ICLASS_MOVF_S, + ICLASS_MOVEQZ_S, + ICLASS_MOVNEZ_S, + ICLASS_MOVGEZ_S, + ICLASS_MOVLTZ_S, + ICLASS_TRUNC_S, + ICLASS_UTRUNC_S, + ICLASS_TRUNC_SX2, + ICLASS_UTRUNC_SX2, + ICLASS_FICEIL_S, + ICLASS_FIFLOOR_S, + ICLASS_FIROUND_S, + ICLASS_FITRUNC_S, + ICLASS_FIRINT_S, + ICLASS_CVTSF16_L, + ICLASS_CVTSF16_H, + ICLASS_CVTF16S_L, + ICLASS_CVTF16S_H, + ICLASS_ABS_S, + ICLASS_MUL_S, + ICLASS_MADD_S, + ICLASS_MSUB_S, + ICLASS_MSUBN_S, + ICLASS_MADDN_S, + ICLASS_ADD_S, + ICLASS_SUB_S, + ICLASS_NEG_S, + ICLASS_FLOAT_S, + ICLASS_UFLOAT_S, + ICLASS_FLOAT_SX2, + ICLASS_UFLOAT_SX2, + ICLASS_OLE_S, + ICLASS_OLT_S, + ICLASS_OEQ_S, + ICLASS_UN_S, + ICLASS_ULE_S, + ICLASS_ULT_S, + ICLASS_UEQ_S, + ICLASS_CONST_S, + ICLASS_NEXP01_S, + ICLASS_MKSADJ_S, + ICLASS_MKDADJ_S, + ICLASS_DIV0_S, + ICLASS_SQRT0_S, + ICLASS_RECIP0_S, + ICLASS_RSQRT0_S, + ICLASS_DIVN_S, + ICLASS_ADDEXP_S, + ICLASS_ADDEXPM_S, + ICLASS_MIN_S, + ICLASS_MAX_S, + ICLASS_MULMUX_S, + ICLASS_MADDMUX_S, + ICLASS_CONJC_S, + ICLASS_SIGMOID_Q15, + ICLASS_SIGMOID_FP32 +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_addi_n_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_l32i_n_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_mov_n_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340800; +} + +static void +Opcode_mov_n_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6200; +} + +static void +Opcode_mov_n_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260900; +} + +static void +Opcode_mov_n_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_mov_n_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800; +} + +static void +Opcode_mov_n_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278200; +} + +static void +Opcode_mov_n_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba500; +} + +static void +Opcode_mov_n_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7300; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_movi_n_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10140000; +} + +static void +Opcode_addi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_addi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10150000; +} + +static void +Opcode_addmi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_addmi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_addmi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_addmi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_addmi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10244000; +} + +static void +Opcode_add_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_add_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_add_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_add_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_add_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4000; +} + +static void +Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_add_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10245000; +} + +static void +Opcode_addx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_addx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5000; +} + +static void +Opcode_addx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_addx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c5000; +} + +static void +Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_addx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10246000; +} + +static void +Opcode_addx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_addx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_addx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_addx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c6000; +} + +static void +Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_addx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10247000; +} + +static void +Opcode_addx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_addx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7000; +} + +static void +Opcode_addx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_addx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c7000; +} + +static void +Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_addx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10314000; +} + +static void +Opcode_sub_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_sub_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000; +} + +static void +Opcode_sub_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_sub_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000; +} + +static void +Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_sub_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10315000; +} + +static void +Opcode_subx2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_subx2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4000; +} + +static void +Opcode_subx2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_subx2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d3000; +} + +static void +Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_subx2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10316000; +} + +static void +Opcode_subx4_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_subx4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5000; +} + +static void +Opcode_subx4_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_subx4_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4000; +} + +static void +Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_subx4_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10317000; +} + +static void +Opcode_subx8_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_subx8_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6000; +} + +static void +Opcode_subx8_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_subx8_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d5000; +} + +static void +Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_subx8_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10249000; +} + +static void +Opcode_and_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_and_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_and_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_and_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_and_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10312000; +} + +static void +Opcode_or_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_or_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d2000; +} + +static void +Opcode_or_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_or_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000; +} + +static void +Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_or_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10318000; +} + +static void +Opcode_xor_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_xor_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7000; +} + +static void +Opcode_xor_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_xor_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d6000; +} + +static void +Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_xor_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100000; +} + +static void +Opcode_extui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_extui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_extui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_extui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10170000; +} + +static void +Opcode_l16ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l16ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_l16ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l16ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_l16ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10160000; +} + +static void +Opcode_l16si_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l16si_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l16si_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l16si_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l16si_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10180000; +} + +static void +Opcode_l32i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_l32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_l32i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_l32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_l32i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000000; +} + +static void +Opcode_l32r_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_l32r_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10190000; +} + +static void +Opcode_l8ui_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_l8ui_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_l8ui_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_l8ui_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_l8ui_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000c0; +} + +static void +Opcode_loop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_loop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_loopgtz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300020; +} + +static void +Opcode_loopgtz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250040; +} + +static void +Opcode_loopgtz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260010; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300060; +} + +static void +Opcode_loopnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250080; +} + +static void +Opcode_loopnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260020; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101d0000; +} + +static void +Opcode_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024e000; +} + +static void +Opcode_moveqz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_moveqz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_moveqz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_moveqz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd000; +} + +static void +Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_moveqz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024f000; +} + +static void +Opcode_movgez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_movgez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cf000; +} + +static void +Opcode_movgez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_movgez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ce000; +} + +static void +Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_movgez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10310000; +} + +static void +Opcode_movltz_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_movltz_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_movltz_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_movltz_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cf000; +} + +static void +Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_movltz_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10311000; +} + +static void +Opcode_movnez_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_movnez_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d1000; +} + +static void +Opcode_movnez_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_movnez_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_movnez_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342000; +} + +static void +Opcode_abs_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_abs_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268000; +} + +static void +Opcode_abs_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3000; +} + +static void +Opcode_abs_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c000; +} + +static void +Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_abs_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342001; +} + +static void +Opcode_neg_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7002; +} + +static void +Opcode_neg_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268002; +} + +static void +Opcode_neg_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3003; +} + +static void +Opcode_neg_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c001; +} + +static void +Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0003; +} + +static void +Opcode_neg_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6003; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d35; +} + +static void +Opcode_nop_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe57d0; +} + +static void +Opcode_nop_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11400a0; +} + +static void +Opcode_nop_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b74; +} + +static void +Opcode_nop_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3016; +} + +static void +Opcode_nop_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000040; +} + +static void +Opcode_nop_Slot_ae4_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3900; +} + +static void +Opcode_nop_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27b205; +} + +static void +Opcode_nop_Slot_ae5_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf9000; +} + +static void +Opcode_nop_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_nop_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c0; +} + +static void +Opcode_nop_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001; +} + +static void +Opcode_nop_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_nop_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa090; +} + +static void +Opcode_nop_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010; +} + +static void +Opcode_nop_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_nop_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c15; +} + +static void +Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1670; +} + +static void +Opcode_nop_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176011; +} + +static void +Opcode_nop_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b1d; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101a0000; +} + +static void +Opcode_s16i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_s16i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101b0000; +} + +static void +Opcode_s32i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_s32i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101c0000; +} + +static void +Opcode_s8i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_s8i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssa8b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103320d0; +} + +static void +Opcode_ssa8b_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe52d0; +} + +static void +Opcode_ssa8b_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2020; +} + +static void +Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1907f0; +} + +static void +Opcode_ssa8b_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1270; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103330d0; +} + +static void +Opcode_ssa8l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe53d0; +} + +static void +Opcode_ssa8l_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2030; +} + +static void +Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1917f0; +} + +static void +Opcode_ssa8l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1370; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103340d0; +} + +static void +Opcode_ssl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe54d0; +} + +static void +Opcode_ssl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2120; +} + +static void +Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1927b0; +} + +static void +Opcode_ssl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1470; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103350d0; +} + +static void +Opcode_ssr_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe55d0; +} + +static void +Opcode_ssr_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2130; +} + +static void +Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1927f0; +} + +static void +Opcode_ssr_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1570; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300d0; +} + +static void +Opcode_ssai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50d0; +} + +static void +Opcode_ssai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3006; +} + +static void +Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1907b0; +} + +static void +Opcode_ssai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1070; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d020; +} + +static void +Opcode_sll_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4080; +} + +static void +Opcode_sll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256010; +} + +static void +Opcode_sll_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1080; +} + +static void +Opcode_sll_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277080; +} + +static void +Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda020; +} + +static void +Opcode_sll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5080; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10313000; +} + +static void +Opcode_src_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_src_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_src_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342003; +} + +static void +Opcode_sra_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7003; +} + +static void +Opcode_sra_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268003; +} + +static void +Opcode_sra_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3004; +} + +static void +Opcode_sra_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c002; +} + +static void +Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0004; +} + +static void +Opcode_sra_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6004; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342004; +} + +static void +Opcode_srl_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7004; +} + +static void +Opcode_srl_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268004; +} + +static void +Opcode_srl_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3005; +} + +static void +Opcode_srl_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c003; +} + +static void +Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0006; +} + +static void +Opcode_srl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6005; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10240000; +} + +static void +Opcode_slli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_slli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_slli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_slli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_slli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10242000; +} + +static void +Opcode_srai_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_srai_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_srai_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_srai_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c2000; +} + +static void +Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_srai_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031f000; +} + +static void +Opcode_srli_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_srli_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241000; +} + +static void +Opcode_srli_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000; +} + +static void +Opcode_srli_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251000; +} + +static void +Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_srli_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20000; +} + +static void +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa20000; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770004; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750004; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760004; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740004; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730004; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710004; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720004; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370004; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350004; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360004; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340004; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670004; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660004; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640004; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270004; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250004; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240004; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790004; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0004; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0004; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0004; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0004; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0004; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0004; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390004; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0004; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0004; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0004; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0004; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0004; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0004; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690004; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0004; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0004; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0004; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0004; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0004; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0004; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290004; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0004; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0004; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0004; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0004; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0004; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0004; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0004; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590004; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490004; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0004; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0004; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0004; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0004; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90004; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0004; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900004; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800004; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612000; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32100; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132100; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612100; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32200; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132200; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612200; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32300; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132300; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612300; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611000; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31100; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131100; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611100; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10320000; +} + +static void +Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_andbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10321000; +} + +static void +Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10322000; +} + +static void +Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_orbc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10323000; +} + +static void +Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_xorb_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10324000; +} + +static void +Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_all4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341e00; +} + +static void +Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1004; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_any4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341e04; +} + +static void +Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1404; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_all8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341e08; +} + +static void +Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1804; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_any8_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341e09; +} + +static void +Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1805; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10319000; +} + +static void +Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_movt_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031a000; +} + +static void +Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7082; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfm_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193000; +} + +static void +Opcode_dpfm_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340200; +} + +static void +Opcode_dpfm_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb200; +} + +static void +Opcode_dpfm_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x197000; +} + +static void +Opcode_dpfm_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340300; +} + +static void +Opcode_dpfm_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb600; +} + +static void +Opcode_dpfr_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_dpfr_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340400; +} + +static void +Opcode_dpfr_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bba00; +} + +static void +Opcode_dpfr_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x195000; +} + +static void +Opcode_dpfr_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340500; +} + +static void +Opcode_dpfr_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbe00; +} + +static void +Opcode_dpfw_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_dpfw_b_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340600; +} + +static void +Opcode_dpfw_b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba100; +} + +static void +Opcode_dpfw_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_dpfw_bf_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340700; +} + +static void +Opcode_dpfw_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb100; +} + +static void +Opcode_pfnxt_f_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3430; +} + +static void +Opcode_dhi_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_dhwbi_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_dhwb_b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_pfend_a_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3030; +} + +static void +Opcode_pfend_o_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3130; +} + +static void +Opcode_pfwait_a_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3230; +} + +static void +Opcode_pfwait_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3330; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32800; +} + +static void +Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132800; +} + +static void +Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612800; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031b000; +} + +static void +Opcode_clamps_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_clamps_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8000; +} + +static void +Opcode_clamps_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_clamps_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d7000; +} + +static void +Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_clamps_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024a000; +} + +static void +Opcode_max_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_max_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_max_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_max_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c9000; +} + +static void +Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_max_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024b000; +} + +static void +Opcode_maxu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_maxu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb000; +} + +static void +Opcode_maxu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_maxu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ca000; +} + +static void +Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a1000; +} + +static void +Opcode_maxu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024c000; +} + +static void +Opcode_min_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_min_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_min_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_min_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cb000; +} + +static void +Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_min_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1024d000; +} + +static void +Opcode_minu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_minu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cd000; +} + +static void +Opcode_minu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_minu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc000; +} + +static void +Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a3000; +} + +static void +Opcode_minu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031c000; +} + +static void +Opcode_sext_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_sext_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d9000; +} + +static void +Opcode_sext_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_sext_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8000; +} + +static void +Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_sext_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_beqz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000a0; +} + +static void +Opcode_beqz_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000000; +} + +static void +Opcode_bgez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000e0; +} + +static void +Opcode_bgez_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000010; +} + +static void +Opcode_bltz_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004a0; +} + +static void +Opcode_bltz_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000020; +} + +static void +Opcode_bnez_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004e0; +} + +static void +Opcode_bnez_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000030; +} + +static void +Opcode_beqi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_beqi_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000000; +} + +static void +Opcode_bgei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000040; +} + +static void +Opcode_bgei_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000000; +} + +static void +Opcode_blti_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000c0; +} + +static void +Opcode_blti_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000000; +} + +static void +Opcode_bnei_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000060; +} + +static void +Opcode_bnei_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9800000; +} + +static void +Opcode_bgeui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000080; +} + +static void +Opcode_bgeui_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5800000; +} + +static void +Opcode_bltui_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000020; +} + +static void +Opcode_bltui_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7800000; +} + +static void +Opcode_bbci_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbci_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbsi_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_bbsi_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ball_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_ball_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000000; +} + +static void +Opcode_bany_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_bany_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800000; +} + +static void +Opcode_bbc_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900; +} + +static void +Opcode_bbc_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000000; +} + +static void +Opcode_bbs_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00; +} + +static void +Opcode_bbs_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800000; +} + +static void +Opcode_beq_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_beq_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4800000; +} + +static void +Opcode_bgeu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600; +} + +static void +Opcode_bgeu_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000000; +} + +static void +Opcode_bge_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00; +} + +static void +Opcode_bge_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800000; +} + +static void +Opcode_bltu_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00; +} + +static void +Opcode_bltu_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000000; +} + +static void +Opcode_blt_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_blt_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8800000; +} + +static void +Opcode_bnall_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700; +} + +static void +Opcode_bnall_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000000; +} + +static void +Opcode_bne_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00; +} + +static void +Opcode_bne_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000000; +} + +static void +Opcode_bnone_w15_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00; +} + +static void +Opcode_bnone_w15_Slot_ae4_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa800000; +} + +static void +Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f00; +} + +static void +Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f000; +} + +static void +Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f10; +} + +static void +Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f100; +} + +static void +Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f20; +} + +static void +Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f200; +} + +static void +Opcode_rur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f30; +} + +static void +Opcode_wur_ae_cw_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f300; +} + +static void +Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f60; +} + +static void +Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f600; +} + +static void +Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f70; +} + +static void +Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f700; +} + +static void +Opcode_rur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f80; +} + +static void +Opcode_wur_ae_cbegin1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f800; +} + +static void +Opcode_rur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30f90; +} + +static void +Opcode_wur_ae_cend1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3f900; +} + +static void +Opcode_ae_sext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d; +} + +static void +Opcode_ae_zext16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900d; +} + +static void +Opcode_ae_clamps16_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00d; +} + +static void +Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e80; +} + +static void +Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e800; +} + +static void +Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e90; +} + +static void +Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e900; +} + +static void +Opcode_f64iter_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000; +} + +static void +Opcode_f64rnd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_f64addc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb0000; +} + +static void +Opcode_f64subc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb8000; +} + +static void +Opcode_f64sig_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_f64cmpl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0000; +} + +static void +Opcode_f64cmph_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_f64norm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0000; +} + +static void +Opcode_f64sexp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_rf64r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbce00; +} + +static void +Opcode_wf64r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_rur_f64r_lo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30ea0; +} + +static void +Opcode_wur_f64r_lo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3ea00; +} + +static void +Opcode_rur_f64r_hi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30eb0; +} + +static void +Opcode_wur_f64r_hi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3eb00; +} + +static void +Opcode_rur_f64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30ec0; +} + +static void +Opcode_wur_f64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3ec00; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ea04; +} + +static void +Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67eb04; +} + +static void +Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ec04; +} + +static void +Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ed04; +} + +static void +Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ee04; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269601; +} + +static void +Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c00b; +} + +static void +Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67ef04; +} + +static void +Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f004; +} + +static void +Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f104; +} + +static void +Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f204; +} + +static void +Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f304; +} + +static void +Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f404; +} + +static void +Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f504; +} + +static void +Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f604; +} + +static void +Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f704; +} + +static void +Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f804; +} + +static void +Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67f904; +} + +static void +Opcode_rur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fa04; +} + +static void +Opcode_wur_ae_cwrap_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67fb04; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0200; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22d000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d000; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140200; +} + +static void +Opcode_ae_l8x4f_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0600; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22e000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e000; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140600; +} + +static void +Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250400; +} + +static void +Opcode_ae_l16m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0200; +} + +static void +Opcode_ae_l16m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250800; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1db000; +} + +static void +Opcode_ae_l16m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_l16m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10004; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0100; +} + +static void +Opcode_ae_l16m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x221000; +} + +static void +Opcode_ae_l16m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_l16m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231000; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_ae_l16m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_l16m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb20004; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0500; +} + +static void +Opcode_ae_l16m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x222000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x232000; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_ae_l16m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250000; +} + +static void +Opcode_ae_l16m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1db000; +} + +static void +Opcode_ae_l16m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_l16m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d9000; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0c00; +} + +static void +Opcode_ae_l16m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_l16m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30004; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250c00; +} + +static void +Opcode_ae_l16m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dd000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc000; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0600; +} + +static void +Opcode_ae_l16m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250700; +} + +static void +Opcode_ae_l16_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5000; +} + +static void +Opcode_ae_l16_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_l16_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6000; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0b00; +} + +static void +Opcode_ae_l16_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250b00; +} + +static void +Opcode_ae_l16_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7000; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0f00; +} + +static void +Opcode_ae_l16_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_l16_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00004; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0300; +} + +static void +Opcode_ae_l16_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x225000; +} + +static void +Opcode_ae_l16_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_l16_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x235000; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_ae_l16_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_l16_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40004; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0700; +} + +static void +Opcode_ae_l16_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x226000; +} + +static void +Opcode_ae_l16_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_l16_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x236000; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130700; +} + +static void +Opcode_ae_l16_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250300; +} + +static void +Opcode_ae_l16_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4000; +} + +static void +Opcode_ae_l16_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_l16_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e5000; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0700; +} + +static void +Opcode_ae_l16_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250f00; +} + +static void +Opcode_ae_l16_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e6000; +} + +static void +Opcode_ae_l16_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_l16_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8000; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_l16_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_l32f24_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb50004; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260400; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0800; +} + +static void +Opcode_ae_l32f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260800; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb000; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0c00; +} + +static void +Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_l32f24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb60004; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0b00; +} + +static void +Opcode_ae_l32f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x227000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x237000; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130b00; +} + +static void +Opcode_ae_l32f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_l32f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70004; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0f00; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130f00; +} + +static void +Opcode_ae_l32f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e7000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9000; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0400; +} + +static void +Opcode_ae_l32f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260c00; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e9000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec000; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0200; +} + +static void +Opcode_ae_l32f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_l32_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0004; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270000; +} + +static void +Opcode_ae_l32_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f4000; +} + +static void +Opcode_ae_l32_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_l32_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f9000; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100400; +} + +static void +Opcode_ae_l32_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270400; +} + +static void +Opcode_ae_l32_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100800; +} + +static void +Opcode_ae_l32_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_l32_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0004; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0800; +} + +static void +Opcode_ae_l32_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22b000; +} + +static void +Opcode_ae_l32_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ae_l32_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b000; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140800; +} + +static void +Opcode_ae_l32_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_l32_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe0004; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0c00; +} + +static void +Opcode_ae_l32_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ae_l32_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000; +} + +static void +Opcode_ae_l32_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140c00; +} + +static void +Opcode_ae_l32_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_l32_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf0004; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260f00; +} + +static void +Opcode_ae_l32_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3000; +} + +static void +Opcode_ae_l32_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_l32_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f8000; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_l32_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270800; +} + +static void +Opcode_ae_l32_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5000; +} + +static void +Opcode_ae_l32_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_l32_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fb000; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100c00; +} + +static void +Opcode_ae_l32_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260600; +} + +static void +Opcode_ae_l32m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1eb000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee000; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0a00; +} + +static void +Opcode_ae_l32m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l32m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80004; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0000; +} + +static void +Opcode_ae_l32m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x229000; +} + +static void +Opcode_ae_l32m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_l32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x239000; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_l32m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_l32m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc90004; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0400; +} + +static void +Opcode_ae_l32m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22a000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a000; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140400; +} + +static void +Opcode_ae_l32m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_l32m_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0004; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260200; +} + +static void +Opcode_ae_l32m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ea000; +} + +static void +Opcode_ae_l32m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_l32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed000; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0600; +} + +static void +Opcode_ae_l32m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_l32m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0004; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260a00; +} + +static void +Opcode_ae_l32m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef000; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0e00; +} + +static void +Opcode_ae_l32m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250600; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1df000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de000; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0e00; +} + +static void +Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250a00; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1df000; +} + +static void +Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_l16x2m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80004; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0900; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x223000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x233000; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130900; +} + +static void +Opcode_ae_l16x2m_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb90004; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0d00; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130d00; +} + +static void +Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_l16x2m_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0004; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250200; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1de000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dd000; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0a00; +} + +static void +Opcode_ae_l16x2m_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0004; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250e00; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0100; +} + +static void +Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40004; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260100; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ee000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1000; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0500; +} + +static void +Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260500; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2000; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0900; +} + +static void +Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc50004; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0010; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244040; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254010; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180050; +} + +static void +Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0010; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0084; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0600; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242020; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261080; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170e10; +} + +static void +Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3080; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0014; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0900; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1000; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260040; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170110; +} + +static void +Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0a00; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262080; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170100; +} + +static void +Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330700; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40e0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2560d0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10e0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770b0; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0870; +} + +static void +Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50e0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330740; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40f0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770c0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c08b0; +} + +static void +Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50f0; +} + +static void +Opcode_ae_l32x2f24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc60004; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260e00; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ed000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0100; +} + +static void +Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc70004; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260900; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ef000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f3000; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0d00; +} + +static void +Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_l32x2_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00004; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260300; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f1000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f5000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0700; +} + +static void +Opcode_ae_l32x2_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260700; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0b00; +} + +static void +Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_l32x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10004; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0090; +} + +static void +Opcode_ae_l32x2_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0020; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244080; +} + +static void +Opcode_ae_l32x2_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254020; +} + +static void +Opcode_ae_l32x2_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180090; +} + +static void +Opcode_ae_l32x2_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0020; +} + +static void +Opcode_ae_l32x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0084; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0e00; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243020; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170500; +} + +static void +Opcode_ae_l32x2_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4080; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330780; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257010; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10f0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770d0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa080; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c08f0; +} + +static void +Opcode_ae_l32x2_ric_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0060; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103307c0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5010; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770e0; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c30; +} + +static void +Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0070; +} + +static void +Opcode_ae_l32x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20004; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260d00; +} + +static void +Opcode_ae_l32x2_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f4000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0300; +} + +static void +Opcode_ae_l32x2_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_l32x2_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30004; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10260b00; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f2000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f7000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0f00; +} + +static void +Opcode_ae_l32x2_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250500; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0900; +} + +static void +Opcode_ae_l16x4_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250900; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e3000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0d00; +} + +static void +Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_l16x4_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0004; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0010; +} + +static void +Opcode_ae_l16x4_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180010; +} + +static void +Opcode_ae_l16x4_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_l16x4_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900084; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0200; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260080; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170e00; +} + +static void +Opcode_ae_l16x4_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250100; +} + +static void +Opcode_ae_l16x4_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0500; +} + +static void +Opcode_ae_l16x4_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_l16x4_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0004; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10250d00; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e3000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4000; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0300; +} + +static void +Opcode_ae_l16x4_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270200; +} + +static void +Opcode_ae_l64_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f7000; +} + +static void +Opcode_ae_l64_xc_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_l64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fd000; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100600; +} + +static void +Opcode_ae_l64_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270600; +} + +static void +Opcode_ae_l64_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fe000; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100a00; +} + +static void +Opcode_ae_l64_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_l64_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf0004; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00d0; +} + +static void +Opcode_ae_l64_i_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0030; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2440c0; +} + +static void +Opcode_ae_l64_i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000; +} + +static void +Opcode_ae_l64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254030; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800d0; +} + +static void +Opcode_ae_l64_i_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0030; +} + +static void +Opcode_ae_l64_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460004; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0030; +} + +static void +Opcode_ae_l64_ip_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0040; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248000; +} + +static void +Opcode_ae_l64_ip_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000; +} + +static void +Opcode_ae_l64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258000; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_l64_ip_Slot_ae7_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180030; +} + +static void +Opcode_ae_l64_ip_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0040; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270c00; +} + +static void +Opcode_ae_l64_x_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f6000; +} + +static void +Opcode_ae_l64_x_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_l64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc000; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100200; +} + +static void +Opcode_ae_l64_x_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270a00; +} + +static void +Opcode_ae_l64_xp_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f8000; +} + +static void +Opcode_ae_l64_xp_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_l64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ff000; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100e00; +} + +static void +Opcode_ae_l64_xp_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270300; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fd000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x205000; +} + +static void +Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100700; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270700; +} + +static void +Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206000; +} + +static void +Opcode_ae_s16x2m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80004; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0100; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x231000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241000; +} + +static void +Opcode_ae_s16x2m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140100; +} + +static void +Opcode_ae_s16x2m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd90004; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0500; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x232000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x242000; +} + +static void +Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140500; +} + +static void +Opcode_ae_s16x2m_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda0004; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270d00; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ae_s16x2m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100300; +} + +static void +Opcode_ae_s16x2m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb0004; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270b00; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fe000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x207000; +} + +static void +Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100b00; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0004; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290e00; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x212000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120e00; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290100; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x221000; +} + +static void +Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120100; +} + +static void +Opcode_ae_s32x2f24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed0004; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00b0; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248080; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258020; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800b0; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620084; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0610; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251020; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265080; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8080; +} + +static void +Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170d00; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330850; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257090; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c070; +} + +static void +Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0cf0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330050; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257050; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770f0; +} + +static void +Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c70; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330450; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c030; +} + +static void +Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0cb0; +} + +static void +Opcode_ae_s32x2f24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee0004; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290a00; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x211000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21f000; +} + +static void +Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120a00; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef0004; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290500; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x213000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x222000; +} + +static void +Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120500; +} + +static void +Opcode_ae_s32x2_xc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80004; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290700; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x217000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x226000; +} + +static void +Opcode_ae_s32x2_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120700; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290b00; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x227000; +} + +static void +Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120b00; +} + +static void +Opcode_ae_s32x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe90004; +} + +static void +Opcode_ae_s32x2_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_s32x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ae_s32x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620004; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0e10; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x253020; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267080; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9080; +} + +static void +Opcode_ae_s32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170700; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330c50; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2570d0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0b0; +} + +static void +Opcode_ae_s32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1903b0; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330090; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c0f0; +} + +static void +Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1903f0; +} + +static void +Opcode_ae_s32x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0004; +} + +static void +Opcode_ae_s32x2_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290300; +} + +static void +Opcode_ae_s32x2_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x225000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_s32x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120300; +} + +static void +Opcode_ae_s32x2_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb0004; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290f00; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x228000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_s32x2_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120f00; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00f0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2480c0; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258030; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800f0; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0a10; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252020; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266080; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170300; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290900; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x223000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120900; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290d00; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x215000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x224000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120d00; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x209000; +} + +static void +Opcode_ae_s16x4_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280400; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a000; +} + +static void +Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110400; +} + +static void +Opcode_ae_s16x4_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0004; +} + +static void +Opcode_ae_s16x4_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0070; +} + +static void +Opcode_ae_s16x4_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248040; +} + +static void +Opcode_ae_s16x4_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258010; +} + +static void +Opcode_ae_s16x4_i_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_s16x4_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180070; +} + +static void +Opcode_ae_s16x4_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800084; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0210; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250020; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264080; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_s16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170900; +} + +static void +Opcode_ae_s16x4_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270f00; +} + +static void +Opcode_ae_s16x4_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ff000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ae_s16x4_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100f00; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280800; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x201000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20b000; +} + +static void +Opcode_ae_s16x4_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110800; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270100; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fa000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x201000; +} + +static void +Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100500; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270500; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202000; +} + +static void +Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100900; +} + +static void +Opcode_ae_s16m_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd50004; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0a00; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22f000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f000; +} + +static void +Opcode_ae_s16m_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140a00; +} + +static void +Opcode_ae_s16m_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd60004; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0e00; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140e00; +} + +static void +Opcode_ae_s16m_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70004; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270e00; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f9000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_s16m_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100100; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10270900; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fb000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x203000; +} + +static void +Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100d00; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280300; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x209000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x215000; +} + +static void +Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110300; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280700; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x216000; +} + +static void +Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110700; +} + +static void +Opcode_ae_s32f24_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde0004; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0f00; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x238000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x248000; +} + +static void +Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140f00; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf0004; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x239000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x249000; +} + +static void +Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280d00; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x208000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x214000; +} + +static void +Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110d00; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280b00; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20a000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x217000; +} + +static void +Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110b00; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0400; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21a000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22a000; +} + +static void +Opcode_ae_s32_l_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0800; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22b000; +} + +static void +Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130800; +} + +static void +Opcode_ae_s32_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00004; +} + +static void +Opcode_ae_s32_l_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0a00; +} + +static void +Opcode_ae_s32_l_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23f000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24f000; +} + +static void +Opcode_ae_s32_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150a00; +} + +static void +Opcode_ae_s32_l_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe10004; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0e00; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250000; +} + +static void +Opcode_ae_s32_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150e00; +} + +static void +Opcode_ae_s32_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20004; +} + +static void +Opcode_ae_s32_l_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x219000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x229000; +} + +static void +Opcode_ae_s32_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_s32_l_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30004; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0c00; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21b000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22c000; +} + +static void +Opcode_ae_s32_l_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280200; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x203000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d000; +} + +static void +Opcode_ae_s16_0_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110200; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280600; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e000; +} + +static void +Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110600; +} + +static void +Opcode_ae_s16_0_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20004; +} + +static void +Opcode_ae_s16_0_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0900; +} + +static void +Opcode_ae_s16_0_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x233000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243000; +} + +static void +Opcode_ae_s16_0_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140900; +} + +static void +Opcode_ae_s16_0_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30004; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0d00; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x234000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244000; +} + +static void +Opcode_ae_s16_0_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140d00; +} + +static void +Opcode_ae_s16_0_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280c00; +} + +static void +Opcode_ae_s16_0_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ae_s16_0_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110c00; +} + +static void +Opcode_ae_s16_0_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40004; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280a00; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x204000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f000; +} + +static void +Opcode_ae_s16_0_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110a00; +} + +static void +Opcode_ae_s64_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0600; +} + +static void +Opcode_ae_s64_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21d000; +} + +static void +Opcode_ae_s64_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22e000; +} + +static void +Opcode_ae_s64_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130600; +} + +static void +Opcode_ae_s64_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0a00; +} + +static void +Opcode_ae_s64_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22f000; +} + +static void +Opcode_ae_s64_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130a00; +} + +static void +Opcode_ae_s64_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10004; +} + +static void +Opcode_ae_s64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300040; +} + +static void +Opcode_ae_s64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c040; +} + +static void +Opcode_ae_s64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c010; +} + +static void +Opcode_ae_s64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190040; +} + +static void +Opcode_ae_s64_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20004; +} + +static void +Opcode_ae_s64_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300080; +} + +static void +Opcode_ae_s64_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c080; +} + +static void +Opcode_ae_s64_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c020; +} + +static void +Opcode_ae_s64_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190080; +} + +static void +Opcode_ae_s64_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0200; +} + +static void +Opcode_ae_s64_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_ae_s64_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22d000; +} + +static void +Opcode_ae_s64_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_ae_s64_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102a0e00; +} + +static void +Opcode_ae_s64_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21e000; +} + +static void +Opcode_ae_s64_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_ae_s64_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130e00; +} + +static void +Opcode_ae_s32m_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x219000; +} + +static void +Opcode_ae_s32m_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_s32m_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40004; +} + +static void +Opcode_ae_s32m_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0400; +} + +static void +Opcode_ae_s32m_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23a000; +} + +static void +Opcode_ae_s32m_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24a000; +} + +static void +Opcode_ae_s32m_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150400; +} + +static void +Opcode_ae_s32m_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50004; +} + +static void +Opcode_ae_s32m_iu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0800; +} + +static void +Opcode_ae_s32m_iu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23b000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24b000; +} + +static void +Opcode_ae_s32m_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150800; +} + +static void +Opcode_ae_s32m_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe60004; +} + +static void +Opcode_ae_s32m_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280f00; +} + +static void +Opcode_ae_s32m_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20b000; +} + +static void +Opcode_ae_s32m_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x218000; +} + +static void +Opcode_ae_s32m_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110f00; +} + +static void +Opcode_ae_s32m_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe70004; +} + +static void +Opcode_ae_s32m_xu_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290400; +} + +static void +Opcode_ae_s32m_xu_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21a000; +} + +static void +Opcode_ae_s32m_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120400; +} + +static void +Opcode_ae_zalign64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x281304; +} + +static void +Opcode_ae_zalign64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d34; +} + +static void +Opcode_ae_zalign64_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b34; +} + +static void +Opcode_ae_zalign64_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27b204; +} + +static void +Opcode_ae_zalign64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c14; +} + +static void +Opcode_ae_lalign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032a020; +} + +static void +Opcode_ae_lalign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264000; +} + +static void +Opcode_ae_lalign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278000; +} + +static void +Opcode_ae_lalign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8020; +} + +static void +Opcode_ae_salign64_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032b020; +} + +static void +Opcode_ae_salign64_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264400; +} + +static void +Opcode_ae_salign64_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278100; +} + +static void +Opcode_ae_salign64_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9020; +} + +static void +Opcode_ae_movalign_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280304; +} + +static void +Opcode_ae_movalign_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d30; +} + +static void +Opcode_ae_movalign_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b30; +} + +static void +Opcode_ae_movalign_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27b200; +} + +static void +Opcode_ae_movalign_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1c04; +} + +static void +Opcode_ae_la64_pp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7720c4; +} + +static void +Opcode_ae_la64_pp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d00; +} + +static void +Opcode_ae_la64_pp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b00; +} + +static void +Opcode_ae_la64_pp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a300; +} + +static void +Opcode_ae_la64_pp_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7080; +} + +static void +Opcode_ae_la64_pp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb020; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341a20; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260330; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279280; +} + +static void +Opcode_ae_la24pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf020; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341b20; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260720; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279380; +} + +static void +Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd410; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7710c4; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341c20; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260730; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a280; +} + +static void +Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf410; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341920; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260320; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278380; +} + +static void +Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be420; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341a00; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260310; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279200; +} + +static void +Opcode_ae_la24neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341b00; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260700; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279300; +} + +static void +Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc410; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341c00; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260710; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a200; +} + +static void +Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be410; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341900; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260300; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278300; +} + +static void +Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc420; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341a30; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2792c0; +} + +static void +Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf030; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341b30; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2793c0; +} + +static void +Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd430; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341c30; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a2c0; +} + +static void +Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf430; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341930; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2783c0; +} + +static void +Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf420; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341a10; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279240; +} + +static void +Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf010; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341b10; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x279340; +} + +static void +Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc430; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341c10; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a240; +} + +static void +Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be430; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341910; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278340; +} + +static void +Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd420; +} + +static void +Opcode_ae_sa64pos_fp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7730c4; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d20; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b10; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a380; +} + +static void +Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb820; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341d10; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260b20; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a340; +} + +static void +Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb420; +} + +static void +Opcode_ae_la32x2_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0084; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032c010; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256030; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c0c0; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9040; +} + +static void +Opcode_ae_la32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0500; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d010; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d080; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9080; +} + +static void +Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0900; +} + +static void +Opcode_ae_la32x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00c4; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032e010; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257020; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d0c0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90c0; +} + +static void +Opcode_ae_la32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0d00; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10329020; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258020; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f080; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa040; +} + +static void +Opcode_ae_la32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0b00; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032f010; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x257030; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e080; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_ae_la32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0300; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10328020; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e0c0; +} + +static void +Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0700; +} + +static void +Opcode_ae_la16x4_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370084; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10325000; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261020; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261040; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_la16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170510; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10325010; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262040; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8040; +} + +static void +Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170910; +} + +static void +Opcode_ae_la16x4_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3700c4; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10325020; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261010; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263040; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8080; +} + +static void +Opcode_ae_la16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170d10; +} + +static void +Opcode_ae_la16x4_rip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350084; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10327000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x266040; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6040; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_ae_la16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170b10; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10325030; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x261030; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x264040; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80c0; +} + +static void +Opcode_ae_la16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170310; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10326000; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x265040; +} + +static void +Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170710; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0004; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032e000; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254030; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2690c0; +} + +static void +Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c00; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032f000; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a080; +} + +static void +Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0200; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0044; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10328010; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x255020; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a0c0; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6080; +} + +static void +Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0600; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032b010; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256020; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c080; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60c0; +} + +static void +Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0100; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10329010; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x255030; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b080; +} + +static void +Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0a00; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032a010; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b0c0; +} + +static void +Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0e00; +} + +static void +Opcode_ae_la24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10328000; +} + +static void +Opcode_ae_la24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263020; +} + +static void +Opcode_ae_la24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26d040; +} + +static void +Opcode_ae_la24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170730; +} + +static void +Opcode_ae_la24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10329000; +} + +static void +Opcode_ae_la24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26e040; +} + +static void +Opcode_ae_la24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170b30; +} + +static void +Opcode_ae_la24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032a000; +} + +static void +Opcode_ae_la24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263010; +} + +static void +Opcode_ae_la24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f040; +} + +static void +Opcode_ae_la24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170f30; +} + +static void +Opcode_ae_la24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d000; +} + +static void +Opcode_ae_la24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254020; +} + +static void +Opcode_ae_la24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269080; +} + +static void +Opcode_ae_la24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0800; +} + +static void +Opcode_ae_la24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032b000; +} + +static void +Opcode_ae_la24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263030; +} + +static void +Opcode_ae_la24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268080; +} + +static void +Opcode_ae_la24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0000; +} + +static void +Opcode_ae_la24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032c000; +} + +static void +Opcode_ae_la24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2680c0; +} + +static void +Opcode_ae_la24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0400; +} + +static void +Opcode_ae_la24x2_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0004; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10326010; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262020; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x267040; +} + +static void +Opcode_ae_la24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170f10; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10327010; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268040; +} + +static void +Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170130; +} + +static void +Opcode_ae_la24x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0044; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10326020; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262010; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269040; +} + +static void +Opcode_ae_la24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170530; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10327030; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263000; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26c040; +} + +static void +Opcode_ae_la24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170330; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10327020; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262030; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a040; +} + +static void +Opcode_ae_la24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170930; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10326030; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26b040; +} + +static void +Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170d30; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330500; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x251010; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2750c0; +} + +static void +Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0e10; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330900; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276000; +} + +static void +Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0110; +} + +static void +Opcode_ae_sa32x2_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00c4; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330d00; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252010; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276040; +} + +static void +Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0510; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330a00; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x254010; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277000; +} + +static void +Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0310; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330200; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x253010; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x276080; +} + +static void +Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0910; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330600; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2760c0; +} + +static void +Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0d10; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0d00; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258030; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26f0c0; +} + +static void +Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0f00; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0920; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270000; +} + +static void +Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0020; +} + +static void +Opcode_ae_sa16x4_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0084; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0d20; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x259020; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270040; +} + +static void +Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0420; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0b00; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a020; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271000; +} + +static void +Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0220; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0300; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x259030; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270080; +} + +static void +Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0820; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0700; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2700c0; +} + +static void +Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c20; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0f30; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e030; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274040; +} + +static void +Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0410; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330000; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274080; +} + +static void +Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0810; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f00c4; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330400; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25f020; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2740c0; +} + +static void +Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0c10; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330100; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250010; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275080; +} + +static void +Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0a10; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330800; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25f030; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275000; +} + +static void +Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0210; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330c00; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x275040; +} + +static void +Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0610; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0530; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c030; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2720c0; +} + +static void +Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0d20; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0930; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273000; +} + +static void +Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0320; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0d30; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25d020; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273040; +} + +static void +Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0720; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0b30; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25e020; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x274000; +} + +static void +Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0010; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0330; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25d030; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x273080; +} + +static void +Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0b20; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0730; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2730c0; +} + +static void +Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0f20; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0f00; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25a030; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271040; +} + +static void +Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0620; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0320; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x271080; +} + +static void +Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0a20; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0720; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25b020; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2710c0; +} + +static void +Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0e20; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0130; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25c020; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272080; +} + +static void +Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0920; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0b20; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25b030; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272000; +} + +static void +Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0120; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0f20; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x272040; +} + +static void +Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0520; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031e000; +} + +static void +Opcode_ae_addicirc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0050; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_ae_addicirc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0050; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6100; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb400; +} + +static void +Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7100; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb000; +} + +static void +Opcode_ae_addcirc_xc_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0c00; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23c000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24c000; +} + +static void +Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150c00; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0200; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23d000; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24d000; +} + +static void +Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150200; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290800; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20e000; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21b000; +} + +static void +Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120800; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290600; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21e000; +} + +static void +Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120600; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290c00; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f000; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21c000; +} + +static void +Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120c00; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10290200; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21d000; +} + +static void +Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120200; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0300; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x235000; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x245000; +} + +static void +Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140300; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0700; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x236000; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x246000; +} + +static void +Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140700; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280e00; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x205000; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110e00; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd0004; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280900; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x207000; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x213000; +} + +static void +Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110900; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280100; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x206000; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x211000; +} + +static void +Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110100; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10280500; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x212000; +} + +static void +Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110500; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0600; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23e000; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24e000; +} + +static void +Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150600; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30004; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102b0b00; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x237000; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x247000; +} + +static void +Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140b00; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10248000; +} + +static void +Opcode_ae_addbrba32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_addbrba32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_ae_addbrba32_Slot_ae6_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_addbrba32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342002; +} + +static void +Opcode_ae_bitswap_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7001; +} + +static void +Opcode_ae_bitswap_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3001; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0002; +} + +static void +Opcode_ae_bitswap_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6001; +} + +static void +Opcode_ae_mul32js_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_addandsub32s_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_addrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x187000; +} + +static void +Opcode_ae_subrng32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a7000; +} + +static void +Opcode_ae_calcrng3_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b19; +} + +static void +Opcode_ae_calcrng2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b15; +} + +static void +Opcode_ae_calcrng1_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b11; +} + +static void +Opcode_ae_rng32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b00; +} + +static void +Opcode_ae_sel16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00004; +} + +static void +Opcode_ae_sel16i_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200000; +} + +static void +Opcode_ae_sel16i_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_sel16i_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_sel16i_n_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_ae_shortswap_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73a00; +} + +static void +Opcode_ae_movab4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0814; +} + +static void +Opcode_ae_movab4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x258010; +} + +static void +Opcode_ae_movab4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000a; +} + +static void +Opcode_ae_movab2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0804; +} + +static void +Opcode_ae_movab2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800f; +} + +static void +Opcode_ae_movab2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0008; +} + +static void +Opcode_ae_movab_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260804; +} + +static void +Opcode_ae_movab_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800d; +} + +static void +Opcode_ae_movab_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0007; +} + +static void +Opcode_ae_movba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0804; +} + +static void +Opcode_ae_movba_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268005; +} + +static void +Opcode_ae_movba_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0005; +} + +static void +Opcode_ae_movba1x2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260000; +} + +static void +Opcode_ae_movba1x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba000; +} + +static void +Opcode_ae_movba4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241704; +} + +static void +Opcode_ae_movba4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269001; +} + +static void +Opcode_ae_movba4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1002; +} + +static void +Opcode_ae_movba2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240704; +} + +static void +Opcode_ae_movba2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269000; +} + +static void +Opcode_ae_movba2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_ae_movb2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680804; +} + +static void +Opcode_ae_movb2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26801f; +} + +static void +Opcode_ae_movb4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0834; +} + +static void +Opcode_ae_movb4_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26811f; +} + +static void +Opcode_ae_movt16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330300; +} + +static void +Opcode_ae_movt16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0f10; +} + +static void +Opcode_ae_movt16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5001; +} + +static void +Opcode_ae_movf16x4_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330e00; +} + +static void +Opcode_ae_movf16x4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0b10; +} + +static void +Opcode_ae_movf16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b5000; +} + +static void +Opcode_ae_movt32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0014; +} + +static void +Opcode_ae_movt32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0500; +} + +static void +Opcode_ae_movt32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170f00; +} + +static void +Opcode_ae_movt32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4001; +} + +static void +Opcode_ae_movf32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0014; +} + +static void +Opcode_ae_movf32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0100; +} + +static void +Opcode_ae_movf32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170b00; +} + +static void +Opcode_ae_movf32x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b4000; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbc00; +} + +static void +Opcode_ae_movsara7x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7200; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a6; +} + +static void +Opcode_ae_movsard7_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe56d0; +} + +static void +Opcode_ae_movsard7_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269a01; +} + +static void +Opcode_ae_movsard7_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c10b; +} + +static void +Opcode_ae_movsard7_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d004a; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342006; +} + +static void +Opcode_ae_movasar_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7005; +} + +static void +Opcode_ae_movasar_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e002a; +} + +static void +Opcode_ae_movda32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150004; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0400; +} + +static void +Opcode_ae_movda32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_ae_movda32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0034; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032e060; +} + +static void +Opcode_ae_movda32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40d0; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256090; +} + +static void +Opcode_ae_movda32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10d0; +} + +static void +Opcode_ae_movda32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2770a0; +} + +static void +Opcode_ae_movda32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0830; +} + +static void +Opcode_ae_movda32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50d0; +} + +static void +Opcode_ae_movda16x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140004; +} + +static void +Opcode_ae_movda16_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0024; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032e020; +} + +static void +Opcode_ae_movda16_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40c0; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x256050; +} + +static void +Opcode_ae_movda16_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10c0; +} + +static void +Opcode_ae_movda16_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277090; +} + +static void +Opcode_ae_movda16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190df0; +} + +static void +Opcode_ae_movda16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50c0; +} + +static void +Opcode_ae_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0084; +} + +static void +Opcode_ae_movi_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032c020; +} + +static void +Opcode_ae_movi_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4040; +} + +static void +Opcode_ae_movi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x255010; +} + +static void +Opcode_ae_movi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1040; +} + +static void +Opcode_ae_movi_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x277040; +} + +static void +Opcode_ae_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0710; +} + +static void +Opcode_ae_movi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5040; +} + +static void +Opcode_ae_movi_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174800; +} + +static void +Opcode_ae_movi_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6000; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1031d000; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0800; +} + +static void +Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_ae_sat16x4_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19d000; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a2; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6400; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0002; +} + +static void +Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73900; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a0; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6300; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72900; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0014; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a4; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6c00; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0004; +} + +static void +Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72a00; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a3; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6b00; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0003; +} + +static void +Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71a00; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330022; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5030; +} + +static void +Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0002; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330020; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5020; +} + +static void +Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130004; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1da000; +} + +static void +Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120004; +} + +static void +Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110004; +} + +static void +Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100004; +} + +static void +Opcode_ae_truncp24q48x2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0004; +} + +static void +Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00004; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10130000; +} + +static void +Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101f0000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10120000; +} + +static void +Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101e0000; +} + +static void +Opcode_ae_truncp16_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0004; +} + +static void +Opcode_ae_truncp16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70e0; +} + +static void +Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19a000; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160900; +} + +static void +Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199000; +} + +static void +Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x198000; +} + +static void +Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x197000; +} + +static void +Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x194000; +} + +static void +Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x193000; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160500; +} + +static void +Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x196000; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160100; +} + +static void +Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x195000; +} + +static void +Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19c000; +} + +static void +Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19b000; +} + +static void +Opcode_ae_minabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x191000; +} + +static void +Opcode_ae_maxabs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18d000; +} + +static void +Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6500; +} + +static void +Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6400; +} + +static void +Opcode_ae_mov_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0014; +} + +static void +Opcode_ae_mov_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103300a1; +} + +static void +Opcode_ae_mov_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6a00; +} + +static void +Opcode_ae_mov_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800e; +} + +static void +Opcode_ae_mov_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2010; +} + +static void +Opcode_ae_mov_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c00a; +} + +static void +Opcode_ae_mov_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0001; +} + +static void +Opcode_ae_mov_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_ae_mov_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70a00; +} + +static void +Opcode_ae_movt64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600004; +} + +static void +Opcode_ae_movt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0c00; +} + +static void +Opcode_ae_movt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170a00; +} + +static void +Opcode_ae_movt64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b3000; +} + +static void +Opcode_ae_movf64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0800; +} + +static void +Opcode_ae_movf64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170600; +} + +static void +Opcode_ae_movf64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b2000; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d0e0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40b0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10b0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1909f0; +} + +static void +Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50b0; +} + +static void +Opcode_ae_cvt48a32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0014; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d060; +} + +static void +Opcode_ae_cvt48a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4090; +} + +static void +Opcode_ae_cvt48a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1090; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1901f0; +} + +static void +Opcode_ae_cvt48a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5090; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1032d0a0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40a0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10a0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1905f0; +} + +static void +Opcode_ae_cvt64a32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50a0; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0034; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006f; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6900; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d000a; +} + +static void +Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70d0; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0024; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006d; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6800; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0008; +} + +static void +Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70c0; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006e; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6700; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c7; +} + +static void +Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70b0; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006c; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6600; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c5; +} + +static void +Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70a0; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006b; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6500; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0087; +} + +static void +Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7090; +} + +static void +Opcode_ae_sat48s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0a04; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175e00; +} + +static void +Opcode_ae_sat48s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7070; +} + +static void +Opcode_ae_satq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7080; +} + +static void +Opcode_ae_sat24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7060; +} + +static void +Opcode_ae_truncq32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0024; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0048; +} + +static void +Opcode_ae_truncq32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b70f0; +} + +static void +Opcode_ae_minabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x192000; +} + +static void +Opcode_ae_maxabs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18e000; +} + +static void +Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7050; +} + +static void +Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7040; +} + +static void +Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250034; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330029; +} + +static void +Opcode_ae_trunca32q48_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50c0; +} + +static void +Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0081; +} + +static void +Opcode_ae_movad32_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500c4; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330027; +} + +static void +Opcode_ae_movad32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5090; +} + +static void +Opcode_ae_movad32_l_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800c; +} + +static void +Opcode_ae_movad32_l_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c009; +} + +static void +Opcode_ae_movad32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c2; +} + +static void +Opcode_ae_movad32_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500b4; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330025; +} + +static void +Opcode_ae_movad32_h_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5080; +} + +static void +Opcode_ae_movad32_h_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800b; +} + +static void +Opcode_ae_movad32_h_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c008; +} + +static void +Opcode_ae_movad32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c0; +} + +static void +Opcode_ae_movad16_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500a4; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330026; +} + +static void +Opcode_ae_movad16_3_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5070; +} + +static void +Opcode_ae_movad16_3_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26800a; +} + +static void +Opcode_ae_movad16_3_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c007; +} + +static void +Opcode_ae_movad16_3_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0082; +} + +static void +Opcode_ae_movad16_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250094; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330024; +} + +static void +Opcode_ae_movad16_2_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5060; +} + +static void +Opcode_ae_movad16_2_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268009; +} + +static void +Opcode_ae_movad16_2_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c006; +} + +static void +Opcode_ae_movad16_2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0080; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330023; +} + +static void +Opcode_ae_movad16_1_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5050; +} + +static void +Opcode_ae_movad16_1_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268008; +} + +static void +Opcode_ae_movad16_1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c005; +} + +static void +Opcode_ae_movad16_1_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0042; +} + +static void +Opcode_ae_movad16_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250084; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330021; +} + +static void +Opcode_ae_movad16_0_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5040; +} + +static void +Opcode_ae_movad16_0_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268007; +} + +static void +Opcode_ae_movad16_0_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27c004; +} + +static void +Opcode_ae_movad16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0040; +} + +static void +Opcode_ae_sra64_32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230070; +} + +static void +Opcode_ae_sra64_32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0070; +} + +static void +Opcode_ae_pksr32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270204; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0030; +} + +static void +Opcode_ae_pksr32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x173004; +} + +static void +Opcode_ae_pksr24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260204; +} + +static void +Opcode_ae_pksr24_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x173000; +} + +static void +Opcode_ae_pksrf32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680104; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0430; +} + +static void +Opcode_ae_pksrf32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x173008; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250024; +} + +static void +Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0043; +} + +static void +Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250014; +} + +static void +Opcode_ae_add32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300004; +} + +static void +Opcode_ae_add32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0d00; +} + +static void +Opcode_ae_add32_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x252000; +} + +static void +Opcode_ae_add32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150d00; +} + +static void +Opcode_ae_add32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e000; +} + +static void +Opcode_ae_add32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181000; +} + +static void +Opcode_ae_sub32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0004; +} + +static void +Opcode_ae_sub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0d00; +} + +static void +Opcode_ae_sub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160b00; +} + +static void +Opcode_ae_sub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000; +} + +static void +Opcode_ae_sub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a1000; +} + +static void +Opcode_ae_addsub32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0800; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160800; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ae_addsub32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x189000; +} + +static void +Opcode_ae_subadd32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0f00; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170800; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_subadd32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a5000; +} + +static void +Opcode_ae_add16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0100; +} + +static void +Opcode_ae_add16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150100; +} + +static void +Opcode_ae_add16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b000; +} + +static void +Opcode_ae_add16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_ae_sub16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0100; +} + +static void +Opcode_ae_sub16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160d00; +} + +static void +Opcode_ae_sub16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ae_sub16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19e000; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0b00; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150b00; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000; +} + +static void +Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x184000; +} + +static void +Opcode_ae_neg32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341400; +} + +static void +Opcode_ae_neg32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1baf00; +} + +static void +Opcode_ae_neg32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175300; +} + +static void +Opcode_ae_neg32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb030; +} + +static void +Opcode_ae_abs32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340b00; +} + +static void +Opcode_ae_abs32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb900; +} + +static void +Opcode_ae_abs32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174e00; +} + +static void +Opcode_ae_abs32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba010; +} + +static void +Opcode_ae_add24s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320004; +} + +static void +Opcode_ae_add24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0900; +} + +static void +Opcode_ae_add24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150900; +} + +static void +Opcode_ae_add24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d000; +} + +static void +Opcode_ae_add24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_sub24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0900; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160700; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ae_sub24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_ae_add32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400004; +} + +static void +Opcode_ae_add32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0300; +} + +static void +Opcode_ae_add32s_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x253000; +} + +static void +Opcode_ae_add32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150300; +} + +static void +Opcode_ae_add32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f000; +} + +static void +Opcode_ae_add32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182000; +} + +static void +Opcode_ae_sub32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0004; +} + +static void +Opcode_ae_sub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0300; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160f00; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ae_sub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a2000; +} + +static void +Opcode_ae_addsub32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0c00; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160c00; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x157000; +} + +static void +Opcode_ae_addsub32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18a000; +} + +static void +Opcode_ae_subadd32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0000; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170c00; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161000; +} + +static void +Opcode_ae_subadd32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a6000; +} + +static void +Opcode_ae_add16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330004; +} + +static void +Opcode_ae_add16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0500; +} + +static void +Opcode_ae_add16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150500; +} + +static void +Opcode_ae_add16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c000; +} + +static void +Opcode_ae_add16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f000; +} + +static void +Opcode_ae_sub16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0004; +} + +static void +Opcode_ae_sub16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0500; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160300; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000; +} + +static void +Opcode_ae_sub16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19f000; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0700; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150700; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183000; +} + +static void +Opcode_ae_neg24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341300; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbb00; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175200; +} + +static void +Opcode_ae_neg24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb020; +} + +static void +Opcode_ae_abs24s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0104; +} + +static void +Opcode_ae_abs24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340a00; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba900; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174d00; +} + +static void +Opcode_ae_abs24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9010; +} + +static void +Opcode_ae_neg32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0704; +} + +static void +Opcode_ae_neg32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341500; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbf00; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175600; +} + +static void +Opcode_ae_neg32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7000; +} + +static void +Opcode_ae_abs32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0304; +} + +static void +Opcode_ae_abs32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340c00; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bad00; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174f00; +} + +static void +Opcode_ae_abs32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb010; +} + +static void +Opcode_ae_neg16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0604; +} + +static void +Opcode_ae_neg16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341200; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bab00; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175d00; +} + +static void +Opcode_ae_neg16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba030; +} + +static void +Opcode_ae_abs16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0204; +} + +static void +Opcode_ae_abs16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340900; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb500; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174c00; +} + +static void +Opcode_ae_abs16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8010; +} + +static void +Opcode_ae_lt16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330010; +} + +static void +Opcode_ae_lt16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1901b0; +} + +static void +Opcode_ae_le16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e03d0; +} + +static void +Opcode_ae_le16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1902f0; +} + +static void +Opcode_ae_eq16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e01d0; +} + +static void +Opcode_ae_eq16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900f0; +} + +static void +Opcode_ae_lt32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x541004; +} + +static void +Opcode_ae_lt32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0190; +} + +static void +Opcode_ae_lt32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900b0; +} + +static void +Opcode_ae_le32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0150; +} + +static void +Opcode_ae_le32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190170; +} + +static void +Opcode_ae_eq32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540004; +} + +static void +Opcode_ae_eq32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0110; +} + +static void +Opcode_ae_eq32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190070; +} + +static void +Opcode_ae_min32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530004; +} + +static void +Opcode_ae_min32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0a00; +} + +static void +Opcode_ae_min32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160a00; +} + +static void +Opcode_ae_min32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18f000; +} + +static void +Opcode_ae_max32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520004; +} + +static void +Opcode_ae_max32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0200; +} + +static void +Opcode_ae_max32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160200; +} + +static void +Opcode_ae_max32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18b000; +} + +static void +Opcode_ae_add64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x310004; +} + +static void +Opcode_ae_add64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102c0f00; +} + +static void +Opcode_ae_add64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150f00; +} + +static void +Opcode_ae_add64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ae_add64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x185000; +} + +static void +Opcode_ae_sub64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d0004; +} + +static void +Opcode_ae_sub64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0700; +} + +static void +Opcode_ae_sub64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_sub64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d000; +} + +static void +Opcode_ae_sub64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a3000; +} + +static void +Opcode_ae_neg64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0504; +} + +static void +Opcode_ae_neg64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341600; +} + +static void +Opcode_ae_neg64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_ae_neg64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175700; +} + +static void +Opcode_ae_neg64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7010; +} + +static void +Opcode_ae_abs64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270804; +} + +static void +Opcode_ae_abs64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340d00; +} + +static void +Opcode_ae_abs64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bbd00; +} + +static void +Opcode_ae_abs64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175100; +} + +static void +Opcode_ae_abs64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8020; +} + +static void +Opcode_ae_addsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0400; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160400; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155000; +} + +static void +Opcode_ae_addsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_ae_subsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102e0400; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170200; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ae_subsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a8000; +} + +static void +Opcode_ae_add64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x153000; +} + +static void +Opcode_ae_add64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x186000; +} + +static void +Opcode_ae_sub64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0b00; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170400; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ae_sub64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a4000; +} + +static void +Opcode_ae_negsq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341800; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175b00; +} + +static void +Opcode_ae_negsq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7030; +} + +static void +Opcode_ae_abssq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340f00; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb300; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175900; +} + +static void +Opcode_ae_abssq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9020; +} + +static void +Opcode_ae_neg64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341700; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175a00; +} + +static void +Opcode_ae_neg64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b7020; +} + +static void +Opcode_ae_abs64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10340e00; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba300; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175500; +} + +static void +Opcode_ae_abs64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8030; +} + +static void +Opcode_ae_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410004; +} + +static void +Opcode_ae_and_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300030; +} + +static void +Opcode_ae_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190050; +} + +static void +Opcode_ae_and_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ac000; +} + +static void +Opcode_ae_nand_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300070; +} + +static void +Opcode_ae_nand_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190090; +} + +static void +Opcode_ae_nand_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ad000; +} + +static void +Opcode_ae_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160004; +} + +static void +Opcode_ae_or_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000b0; +} + +static void +Opcode_ae_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900d0; +} + +static void +Opcode_ae_or_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ae000; +} + +static void +Opcode_ae_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0004; +} + +static void +Opcode_ae_xor_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000f0; +} + +static void +Opcode_ae_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190030; +} + +static void +Opcode_ae_xor_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b1000; +} + +static void +Opcode_ae_slai24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940004; +} + +static void +Opcode_ae_slai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220020; +} + +static void +Opcode_ae_slai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0020; +} + +static void +Opcode_ae_slai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000; +} + +static void +Opcode_ae_srli24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230080; +} + +static void +Opcode_ae_srli24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0080; +} + +static void +Opcode_ae_srli24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66000; +} + +static void +Opcode_ae_srai24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0004; +} + +static void +Opcode_ae_srai24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220030; +} + +static void +Opcode_ae_srai24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0030; +} + +static void +Opcode_ae_srai24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_ae_slas24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240b04; +} + +static void +Opcode_ae_slas24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002b; +} + +static void +Opcode_ae_slas24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0083; +} + +static void +Opcode_ae_slas24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6600; +} + +static void +Opcode_ae_srls24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330067; +} + +static void +Opcode_ae_srls24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0007; +} + +static void +Opcode_ae_srls24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72800; +} + +static void +Opcode_ae_sras24_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240e04; +} + +static void +Opcode_ae_sras24_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330063; +} + +static void +Opcode_ae_sras24_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0086; +} + +static void +Opcode_ae_sras24_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6e00; +} + +static void +Opcode_ae_srai16_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300090; +} + +static void +Opcode_ae_srai16_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900e0; +} + +static void +Opcode_ae_srai16_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1aa000; +} + +static void +Opcode_ae_srai16r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000d0; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190010; +} + +static void +Opcode_ae_srai16r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ab000; +} + +static void +Opcode_ae_slai32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x960004; +} + +static void +Opcode_ae_slai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220010; +} + +static void +Opcode_ae_slai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0010; +} + +static void +Opcode_ae_slai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ae_srli32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x920004; +} + +static void +Opcode_ae_srli32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230020; +} + +static void +Opcode_ae_srli32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0020; +} + +static void +Opcode_ae_srli32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a000; +} + +static void +Opcode_ae_srai32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e0004; +} + +static void +Opcode_ae_srai32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102200b0; +} + +static void +Opcode_ae_srai32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00b0; +} + +static void +Opcode_ae_srai32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e000; +} + +static void +Opcode_ae_srai32r_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230000; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_srai32r_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62000; +} + +static void +Opcode_ae_slas32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002e; +} + +static void +Opcode_ae_slas32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c3; +} + +static void +Opcode_ae_slas32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6800; +} + +static void +Opcode_ae_srls32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330068; +} + +static void +Opcode_ae_srls32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0045; +} + +static void +Opcode_ae_srls32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73800; +} + +static void +Opcode_ae_sras32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330064; +} + +static void +Opcode_ae_sras32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c4; +} + +static void +Opcode_ae_sras32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6f00; +} + +static void +Opcode_ae_slaa32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200004; +} + +static void +Opcode_ae_slaa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300e0; +} + +static void +Opcode_ae_slaa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00e0; +} + +static void +Opcode_ae_srla32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0060; +} + +static void +Opcode_ae_srla32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180060; +} + +static void +Opcode_ae_sraa32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70004; +} + +static void +Opcode_ae_sraa32_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0000; +} + +static void +Opcode_ae_sraa32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ae_slai16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300050; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900a0; +} + +static void +Opcode_ae_slai16s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a9000; +} + +static void +Opcode_ae_slaa16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230004; +} + +static void +Opcode_ae_slaa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300a0; +} + +static void +Opcode_ae_slaa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00a0; +} + +static void +Opcode_ae_sraa16s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300f0; +} + +static void +Opcode_ae_sraa16s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00f0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300b0; +} + +static void +Opcode_ae_sraa16rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00b0; +} + +static void +Opcode_ae_slai24s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980004; +} + +static void +Opcode_ae_slai24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102200a0; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00a0; +} + +static void +Opcode_ae_slai24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000; +} + +static void +Opcode_ae_slas24s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002c; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c1; +} + +static void +Opcode_ae_slas24s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6700; +} + +static void +Opcode_ae_slai32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0004; +} + +static void +Opcode_ae_slai32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220090; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0090; +} + +static void +Opcode_ae_slai32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a000; +} + +static void +Opcode_ae_slas32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002d; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0004; +} + +static void +Opcode_ae_slas32s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6900; +} + +static void +Opcode_ae_slaa32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50004; +} + +static void +Opcode_ae_slaa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230010; +} + +static void +Opcode_ae_slaa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0010; +} + +static void +Opcode_ae_sraa32s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820004; +} + +static void +Opcode_ae_sraa32s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0080; +} + +static void +Opcode_ae_sraa32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180080; +} + +static void +Opcode_ae_sraa32rs_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0040; +} + +static void +Opcode_ae_sraa32rs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180040; +} + +static void +Opcode_ae_slasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240c04; +} + +static void +Opcode_ae_slasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330062; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0046; +} + +static void +Opcode_ae_slasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6c00; +} + +static void +Opcode_ae_srlsq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330069; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0085; +} + +static void +Opcode_ae_srlsq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71900; +} + +static void +Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240f04; +} + +static void +Opcode_ae_srasq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330065; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0005; +} + +static void +Opcode_ae_srasq56_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71800; +} + +static void +Opcode_ae_slaaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210004; +} + +static void +Opcode_ae_slaaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102300d0; +} + +static void +Opcode_ae_slaaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00d0; +} + +static void +Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610004; +} + +static void +Opcode_ae_srlaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00e0; +} + +static void +Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800e0; +} + +static void +Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910004; +} + +static void +Opcode_ae_sraaq56_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f0020; +} + +static void +Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180020; +} + +static void +Opcode_ae_slai64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880004; +} + +static void +Opcode_ae_slai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210000; +} + +static void +Opcode_ae_slai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ae_slai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ae_srli64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10220000; +} + +static void +Opcode_ae_srli64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_srli64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ae_srai64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0004; +} + +static void +Opcode_ae_srai64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210030; +} + +static void +Opcode_ae_srai64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0030; +} + +static void +Opcode_ae_srai64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53000; +} + +static void +Opcode_ae_slas64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002f; +} + +static void +Opcode_ae_slas64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0006; +} + +static void +Opcode_ae_slas64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6a00; +} + +static void +Opcode_ae_srls64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033006a; +} + +static void +Opcode_ae_srls64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0047; +} + +static void +Opcode_ae_srls64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70900; +} + +static void +Opcode_ae_sras64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330066; +} + +static void +Opcode_ae_sras64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d00c6; +} + +static void +Opcode_ae_sras64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70800; +} + +static void +Opcode_ae_slaa64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220004; +} + +static void +Opcode_ae_slaa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230050; +} + +static void +Opcode_ae_slaa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0050; +} + +static void +Opcode_ae_srla64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00a0; +} + +static void +Opcode_ae_srla64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800a0; +} + +static void +Opcode_ae_sraa64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810004; +} + +static void +Opcode_ae_sraa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102f00c0; +} + +static void +Opcode_ae_sraa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800c0; +} + +static void +Opcode_ae_slaisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840004; +} + +static void +Opcode_ae_slaisq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210010; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0010; +} + +static void +Opcode_ae_slaisq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52000; +} + +static void +Opcode_ae_slassq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330061; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0084; +} + +static void +Opcode_ae_slassq56s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6d00; +} + +static void +Opcode_ae_slaasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60004; +} + +static void +Opcode_ae_slaasq56s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230030; +} + +static void +Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0030; +} + +static void +Opcode_ae_slai64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10210020; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0020; +} + +static void +Opcode_ae_slai64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x51000; +} + +static void +Opcode_ae_slas64s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240d04; +} + +static void +Opcode_ae_slas64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330060; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0044; +} + +static void +Opcode_ae_slas64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b6b00; +} + +static void +Opcode_ae_slaa64s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10230090; +} + +static void +Opcode_ae_slaa64s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0090; +} + +static void +Opcode_ae_lt64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510004; +} + +static void +Opcode_ae_lt64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10300010; +} + +static void +Opcode_ae_lt64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190060; +} + +static void +Opcode_ae_le64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500004; +} + +static void +Opcode_ae_le64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000e0; +} + +static void +Opcode_ae_le64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190020; +} + +static void +Opcode_ae_eq64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000a0; +} + +static void +Opcode_ae_eq64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1900c0; +} + +static void +Opcode_ae_max64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0600; +} + +static void +Opcode_ae_max64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160600; +} + +static void +Opcode_ae_max64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18c000; +} + +static void +Opcode_ae_min64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102d0e00; +} + +static void +Opcode_ae_min64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160e00; +} + +static void +Opcode_ae_min64_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190000; +} + +static void +Opcode_ae_nsa64_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500d4; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10330028; +} + +static void +Opcode_ae_nsa64_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50a0; +} + +static void +Opcode_ae_nsa64_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0001; +} + +static void +Opcode_ae_nsaz16_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500e4; +} + +static void +Opcode_ae_nsaz16_0_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0003; +} + +static void +Opcode_ae_nsaz32_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2500f4; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1033002a; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe50b0; +} + +static void +Opcode_ae_nsaz32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0041; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0010; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b000; +} + +static void +Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080050; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000; +} + +static void +Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_mul32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600c0; +} + +static void +Opcode_ae_mul32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_ae_mul32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000; +} + +static void +Opcode_ae_mulf32s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_mul32_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79000; +} + +static void +Opcode_ae_muls32f48p16s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff000; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080020; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c000; +} + +static void +Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f0070; +} + +static void +Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_ae_mulf32ra_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_mulf32r_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0000; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a000; +} + +static void +Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080040; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000; +} + +static void +Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_mul32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600b0; +} + +static void +Opcode_ae_mul32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_ae_mul32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43000; +} + +static void +Opcode_ae_mulf32s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_mul32_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78000; +} + +static void +Opcode_ae_muls32f48p16s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080010; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b000; +} + +static void +Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f0060; +} + +static void +Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_ae_mulf32ra_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_mulf32r_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900f0; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79000; +} + +static void +Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080030; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d000; +} + +static void +Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_mul32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600a0; +} + +static void +Opcode_ae_mul32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_ae_mul32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000; +} + +static void +Opcode_ae_mulf32s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_mul32_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77000; +} + +static void +Opcode_ae_muls32f48p16s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfd000; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080000; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a000; +} + +static void +Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f0050; +} + +static void +Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_ae_mulf32ra_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_mulf32r_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0050; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e000; +} + +static void +Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150050; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76000; +} + +static void +Opcode_ae_mula32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070090; +} + +static void +Opcode_ae_mula32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19000; +} + +static void +Opcode_ae_mula32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x51000; +} + +static void +Opcode_ae_mulaf32s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_ae_mula32_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85000; +} + +static void +Opcode_ae_mulas32f48p16s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140060; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f000; +} + +static void +Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73000; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130070; +} + +static void +Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ae_mulaf32ra_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_ae_mulaf32r_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0040; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d000; +} + +static void +Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91000; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150040; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75000; +} + +static void +Opcode_ae_mula32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070080; +} + +static void +Opcode_ae_mula32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_ae_mula32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ae_mulaf32s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_ae_mula32_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000; +} + +static void +Opcode_ae_mulas32f48p16s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140050; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000; +} + +static void +Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72000; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130060; +} + +static void +Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f000; +} + +static void +Opcode_ae_mulaf32ra_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_ae_mulaf32r_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b0070; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140070; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74000; +} + +static void +Opcode_ae_mula32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070070; +} + +static void +Opcode_ae_mula32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17000; +} + +static void +Opcode_ae_mula32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f000; +} + +static void +Opcode_ae_mulaf32s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_ae_mula32_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83000; +} + +static void +Opcode_ae_mulas32f48p16s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140040; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d000; +} + +static void +Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71000; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130050; +} + +static void +Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e000; +} + +static void +Opcode_ae_mulaf32ra_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_ae_mulaf32r_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0080; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d000; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00c0; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93000; +} + +static void +Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1000; +} + +static void +Opcode_ae_muls32_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00d0; +} + +static void +Opcode_ae_muls32_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87000; +} + +static void +Opcode_ae_muls32_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_mulsf32s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124000; +} + +static void +Opcode_ae_muls32_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a000; +} + +static void +Opcode_ae_mulss32f48p16s_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0090; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0060; +} + +static void +Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000; +} + +static void +Opcode_ae_mulsf32ra_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e000; +} + +static void +Opcode_ae_mulsf32r_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x121000; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0070; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00b0; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_muls32_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00c0; +} + +static void +Opcode_ae_muls32_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000; +} + +static void +Opcode_ae_muls32_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_mulsf32s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123000; +} + +static void +Opcode_ae_muls32_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109000; +} + +static void +Opcode_ae_mulss32f48p16s_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0080; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000; +} + +static void +Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0050; +} + +static void +Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000; +} + +static void +Opcode_ae_mulsf32ra_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d000; +} + +static void +Opcode_ae_mulsf32r_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0060; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b000; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00a0; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91000; +} + +static void +Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef000; +} + +static void +Opcode_ae_muls32_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00b0; +} + +static void +Opcode_ae_muls32_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85000; +} + +static void +Opcode_ae_muls32_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_mulsf32s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x122000; +} + +static void +Opcode_ae_muls32_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ae_mulss32f48p16s_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0070; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000; +} + +static void +Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0040; +} + +static void +Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000; +} + +static void +Opcode_ae_mulsf32ra_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c000; +} + +static void +Opcode_ae_mulsf32r_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f000; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060010; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_mul32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600e0; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000; +} + +static void +Opcode_ae_mula32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0020; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c000; +} + +static void +Opcode_ae_muls32u_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_ae_mulf16ss_33_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_ae_mulf16ss_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_ae_mulf16ss_32_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_ae_mulf16ss_21_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_ae_mulf16ss_31_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_ae_mulf16ss_30_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_ae_mulf16ss_10_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ae_mulf16ss_20_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_ae_mulf16ss_11_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f0040; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59000; +} + +static void +Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_ae_mulf16ss_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ae_mulsf16ss_33_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b000; +} + +static void +Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_mulsf16ss_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x117000; +} + +static void +Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_mulsf16ss_32_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a000; +} + +static void +Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_mulsf16ss_21_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x116000; +} + +static void +Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_mulsf16ss_31_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x119000; +} + +static void +Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_mulsf16ss_30_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_mulsf16ss_10_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x113000; +} + +static void +Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_mulsf16ss_20_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x115000; +} + +static void +Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_mulsf16ss_11_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x114000; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0030; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000; +} + +static void +Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_mulsf16ss_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x112000; +} + +static void +Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d000; +} + +static void +Opcode_ae_mulaf16ss_33_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69000; +} + +static void +Opcode_ae_mulaf16ss_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c000; +} + +static void +Opcode_ae_mulaf16ss_32_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68000; +} + +static void +Opcode_ae_mulaf16ss_21_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b000; +} + +static void +Opcode_ae_mulaf16ss_31_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a000; +} + +static void +Opcode_ae_mulaf16ss_30_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000; +} + +static void +Opcode_ae_mulaf16ss_10_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67000; +} + +static void +Opcode_ae_mulaf16ss_20_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66000; +} + +static void +Opcode_ae_mulaf16ss_11_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130040; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000; +} + +static void +Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000; +} + +static void +Opcode_ae_mulaf16ss_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100070; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23000; +} + +static void +Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b000; +} + +static void +Opcode_ae_mulaafd16ss_33_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100060; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22000; +} + +static void +Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a000; +} + +static void +Opcode_ae_mulaafd16ss_13_02_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100050; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21000; +} + +static void +Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59000; +} + +static void +Opcode_ae_mulaafd16ss_11_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00f0; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x114000; +} + +static void +Opcode_ae_mulssfd16ss_33_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147000; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00e0; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x113000; +} + +static void +Opcode_ae_mulssfd16ss_13_02_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x146000; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00d0; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x112000; +} + +static void +Opcode_ae_mulssfd16ss_11_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145000; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00f0; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124000; +} + +static void +Opcode_ae_mulzaafd16ss_33_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x157000; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00e0; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x123000; +} + +static void +Opcode_ae_mulzaafd16ss_13_02_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x156000; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00d0; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x122000; +} + +static void +Opcode_ae_mulzaafd16ss_11_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x155000; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100d0; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000; +} + +static void +Opcode_ae_mulzssfd16ss_33_22_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x177000; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100c0; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe3000; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143000; +} + +static void +Opcode_ae_mulzssfd16ss_13_02_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176000; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100b0; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142000; +} + +static void +Opcode_ae_mulzssfd16ss_11_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175000; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800e0; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68000; +} + +static void +Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_mulf48q32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800f0; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69000; +} + +static void +Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_mulf48q32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900d0; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77000; +} + +static void +Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_mulq32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb000; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900e0; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78000; +} + +static void +Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_mulq32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1170060; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f000; +} + +static void +Opcode_ae_mulaf48q32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1170070; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_mulaf48q32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b0050; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a000; +} + +static void +Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e000; +} + +static void +Opcode_ae_mulaq32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b0060; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b000; +} + +static void +Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f000; +} + +static void +Opcode_ae_mulaq32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0050; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000; +} + +static void +Opcode_ae_mulsf48q32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d000; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0060; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d000; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb000; +} + +static void +Opcode_ae_mulsf48q32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e000; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0040; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x109000; +} + +static void +Opcode_ae_mulsq32sp16s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0050; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a000; +} + +static void +Opcode_ae_mulsq32sp16u_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d000; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090010; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b000; +} + +static void +Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090000; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a000; +} + +static void +Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_mulfp24x2ra_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000; +} + +static void +Opcode_ae_mulfp24x2r_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef000; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180050; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180040; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81000; +} + +static void +Opcode_ae_mulafp24x2ra_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_mulafp24x2r_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0080; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f000; +} + +static void +Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfd000; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0070; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9e000; +} + +static void +Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000; +} + +static void +Opcode_ae_mulsfp24x2ra_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f000; +} + +static void +Opcode_ae_mulsfp24x2r_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0020; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127000; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0000; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x125000; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00b0; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_ae_mulzaafd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15a000; +} + +static void +Opcode_ae_mulzaafd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158000; +} + +static void +Opcode_ae_mulzaad32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x153000; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0030; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0010; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126000; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00c0; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x121000; +} + +static void +Opcode_ae_mulzaafd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15b000; +} + +static void +Opcode_ae_mulzaafd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159000; +} + +static void +Opcode_ae_mulzaad32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00e0; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd5000; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133000; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00c0; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00a0; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12f000; +} + +static void +Opcode_ae_mulzasfd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ae_mulzasfd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ae_mulzasd32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00f0; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6000; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134000; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00d0; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f00b0; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_ae_mulzasfd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x167000; +} + +static void +Opcode_ae_mulzasfd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x165000; +} + +static void +Opcode_ae_mulzasd32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x163000; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000c0; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000b0; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000a0; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_ae_mulzsafd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_ae_mulzsafd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16d000; +} + +static void +Opcode_ae_mulzsad32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120080; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x147000; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100e0; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x145000; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110090; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140000; +} + +static void +Opcode_ae_mulzssfd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_ae_mulzssfd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_ae_mulzssd32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x173000; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120090; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100f0; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x146000; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11100a0; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141000; +} + +static void +Opcode_ae_mulzssfd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000; +} + +static void +Opcode_ae_mulzssfd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000; +} + +static void +Opcode_ae_mulzssd32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110060; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26000; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e000; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110040; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c000; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700f0; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f000; +} + +static void +Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57000; +} + +static void +Opcode_ae_mulaafd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x92000; +} + +static void +Opcode_ae_mulaafd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_ae_mulaad32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110070; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27000; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f000; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110050; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25000; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d000; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100040; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58000; +} + +static void +Opcode_ae_mulaafd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93000; +} + +static void +Opcode_ae_mulaafd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91000; +} + +static void +Opcode_ae_mulaad32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e0040; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55000; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d0060; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53000; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d0040; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x51000; +} + +static void +Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_ae_mulasfd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_mulasfd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_mulasd32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9000; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e0050; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56000; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d0070; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54000; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d0050; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52000; +} + +static void +Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_ae_mulasfd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_mulasfd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_mulasd32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca000; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0000; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00f0; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb000; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00e0; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda000; +} + +static void +Opcode_ae_mulsafd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f000; +} + +static void +Opcode_ae_mulsafd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e000; +} + +static void +Opcode_ae_mulsad32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d000; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0020; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x117000; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0000; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x115000; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00b0; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_mulssfd32s_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a000; +} + +static void +Opcode_ae_mulssfd32ra_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148000; +} + +static void +Opcode_ae_mulssd32_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143000; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0030; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x118000; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0010; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x116000; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00c0; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x111000; +} + +static void +Opcode_ae_mulssfd32s_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14b000; +} + +static void +Opcode_ae_mulssfd32ra_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x149000; +} + +static void +Opcode_ae_mulssd32_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144000; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800a0; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000; +} + +static void +Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb4000; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060060; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_ae_mulf32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8000; +} + +static void +Opcode_ae_mul32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d000; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800b0; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000; +} + +static void +Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5000; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060070; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_ae_mulf32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000; +} + +static void +Opcode_ae_mul32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74000; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800c0; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66000; +} + +static void +Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6000; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060080; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_mulf32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000; +} + +static void +Opcode_ae_mul32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75000; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10800d0; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x67000; +} + +static void +Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060090; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41000; +} + +static void +Opcode_ae_mulf32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000; +} + +static void +Opcode_ae_mul32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76000; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080060; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060020; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_ae_mulf32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4000; +} + +static void +Opcode_ae_mul32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f000; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080070; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61000; +} + +static void +Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060030; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_ae_mulf32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe5000; +} + +static void +Opcode_ae_mul32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61000; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080080; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62000; +} + +static void +Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060040; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_ae_mulf32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6000; +} + +static void +Opcode_ae_mul32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x65000; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1080090; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63000; +} + +static void +Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb3000; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060050; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_ae_mulf32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe7000; +} + +static void +Opcode_ae_mul32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x69000; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1160060; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37000; +} + +static void +Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b000; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070030; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000; +} + +static void +Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b000; +} + +static void +Opcode_ae_mulaf32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf000; +} + +static void +Opcode_ae_mula32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f000; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1160070; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c000; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070040; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000; +} + +static void +Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_ae_mulaf32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_mula32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1170040; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d000; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070050; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15000; +} + +static void +Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d000; +} + +static void +Opcode_ae_mulaf32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_mula32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81000; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1170050; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e000; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070060; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16000; +} + +static void +Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e000; +} + +static void +Opcode_ae_mulaf32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb2000; +} + +static void +Opcode_ae_mula32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150060; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33000; +} + +static void +Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77000; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600f0; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf000; +} + +static void +Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47000; +} + +static void +Opcode_ae_mulaf32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab000; +} + +static void +Opcode_ae_mula32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b000; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150070; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78000; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070000; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ae_mulaf32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac000; +} + +static void +Opcode_ae_mula32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c000; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1160040; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35000; +} + +static void +Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x79000; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070010; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000; +} + +static void +Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x49000; +} + +static void +Opcode_ae_mulaf32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad000; +} + +static void +Opcode_ae_mula32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d000; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1160050; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a000; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1070020; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12000; +} + +static void +Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a000; +} + +static void +Opcode_ae_mulaf32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xae000; +} + +static void +Opcode_ae_mula32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e000; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0010; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98000; +} + +static void +Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0070; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81000; +} + +static void +Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1000; +} + +static void +Opcode_ae_mulsf32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x129000; +} + +static void +Opcode_ae_muls32x16_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104000; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0020; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99000; +} + +static void +Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7000; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0080; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82000; +} + +static void +Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd2000; +} + +static void +Opcode_ae_mulsf32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a000; +} + +static void +Opcode_ae_muls32x16_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105000; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0030; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a000; +} + +static void +Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0090; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83000; +} + +static void +Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd3000; +} + +static void +Opcode_ae_mulsf32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b000; +} + +static void +Opcode_ae_muls32x16_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106000; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0040; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf9000; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a00a0; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000; +} + +static void +Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4000; +} + +static void +Opcode_ae_mulsf32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c000; +} + +static void +Opcode_ae_muls32x16_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107000; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00d0; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0030; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d000; +} + +static void +Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_mulsf32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x125000; +} + +static void +Opcode_ae_muls32x16_h0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00e0; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3000; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0040; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e000; +} + +static void +Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_mulsf32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x126000; +} + +static void +Opcode_ae_muls32x16_h1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101000; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b00f0; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0050; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f000; +} + +static void +Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_mulsf32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x127000; +} + +static void +Opcode_ae_muls32x16_h2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102000; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0000; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf5000; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10a0060; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_mulsf32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x128000; +} + +static void +Opcode_ae_muls32x16_h3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120070; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b000; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x63000; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700e0; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e000; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56000; +} + +static void +Opcode_ae_mulaafd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x97000; +} + +static void +Opcode_ae_mulaad32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120050; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29000; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61000; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700c0; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54000; +} + +static void +Opcode_ae_mulaafd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95000; +} + +static void +Opcode_ae_mulaad32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e0070; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58000; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c000; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0070; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_ae_mulasfd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_mulasd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8000; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e0060; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57000; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b000; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c0060; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f000; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x93000; +} + +static void +Opcode_ae_mulasfd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_mulasd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc7000; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0020; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9000; +} + +static void +Opcode_ae_mulsafd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x111000; +} + +static void +Opcode_ae_mulsad32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c000; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b0010; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_mulsafd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x110000; +} + +static void +Opcode_ae_mulsad32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10b000; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0050; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a000; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d00a0; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb1000; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f000; +} + +static void +Opcode_ae_mulssfd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14d000; +} + +static void +Opcode_ae_mulssd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142000; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0040; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x119000; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0090; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0000; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e000; +} + +static void +Opcode_ae_mulssfd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14c000; +} + +static void +Opcode_ae_mulssd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141000; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0070; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce000; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12c000; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e00a0; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11f000; +} + +static void +Opcode_ae_mulzaafd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f000; +} + +static void +Opcode_ae_mulzaad32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x152000; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0050; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc000; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12a000; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0080; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d000; +} + +static void +Opcode_ae_mulzaafd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15d000; +} + +static void +Opcode_ae_mulzaad32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150000; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100090; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8000; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0090; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12e000; +} + +static void +Opcode_ae_mulzasfd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000; +} + +static void +Opcode_ae_mulzasd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x161000; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100080; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd7000; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135000; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0080; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf000; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12d000; +} + +static void +Opcode_ae_mulzasfd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ae_mulzasd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160000; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000e0; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd000; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d000; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ae_mulzsafd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_mulzsad32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b000; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000d0; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc000; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137000; +} + +static void +Opcode_ae_mulzsafd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16f000; +} + +static void +Opcode_ae_mulzsad32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200b0; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea000; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14a000; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1110080; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf000; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_ae_mulzssfd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d000; +} + +static void +Opcode_ae_mulzssd32x16_h3_l2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200a0; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe9000; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x149000; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11000f0; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xde000; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_ae_mulzssfd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_ae_mulzssd32x16_h1_l0_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171000; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0060; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd000; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12b000; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10f0040; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb000; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x129000; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120060; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a000; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62000; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1120040; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0090; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e000; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0070; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c000; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700d0; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d000; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x55000; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700b0; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b000; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53000; +} + +static void +Opcode_ae_mulzaafd32x16_h2_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15e000; +} + +static void +Opcode_ae_mulzaafd32x16_h0_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15c000; +} + +static void +Opcode_ae_mulaafd32x16_h2_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96000; +} + +static void +Opcode_ae_mulaafd32x16_h0_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x94000; +} + +static void +Opcode_ae_mulzaad32x16_h2_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x151000; +} + +static void +Opcode_ae_mulzaad32x16_h0_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14f000; +} + +static void +Opcode_ae_mulaad32x16_h2_l3_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000; +} + +static void +Opcode_ae_mulaad32x16_h0_l1_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87000; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900a0; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74000; +} + +static void +Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc4000; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090040; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e000; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090020; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c000; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090060; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_mulfp32x16x2s_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ae_mulp32x16x2_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000; +} + +static void +Opcode_ae_mulfp32x16x2rs_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000; +} + +static void +Opcode_ae_mulfp32x16x2ras_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900b0; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x75000; +} + +static void +Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5000; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090050; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f000; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090030; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090070; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x71000; +} + +static void +Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_mulfp32x16x2s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf5000; +} + +static void +Opcode_ae_mulp32x16x2_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf9000; +} + +static void +Opcode_ae_mulfp32x16x2rs_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3000; +} + +static void +Opcode_ae_mulfp32x16x2ras_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1000; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a0060; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47000; +} + +static void +Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1190040; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85000; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180060; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83000; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1190060; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43000; +} + +static void +Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x87000; +} + +static void +Opcode_ae_mulafp32x16x2s_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb000; +} + +static void +Opcode_ae_mulap32x16x2_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf000; +} + +static void +Opcode_ae_mulafp32x16x2rs_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb9000; +} + +static void +Opcode_ae_mulafp32x16x2ras_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb7000; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a0070; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c000; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1190050; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42000; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1180070; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x84000; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1190070; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44000; +} + +static void +Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88000; +} + +static void +Opcode_ae_mulafp32x16x2s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc000; +} + +static void +Opcode_ae_mulap32x16x2_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_ae_mulafp32x16x2rs_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba000; +} + +static void +Opcode_ae_mulafp32x16x2ras_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb8000; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0010; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8000; +} + +static void +Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x106000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00b0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa2000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c0090; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00d0; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa4000; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102000; +} + +static void +Opcode_ae_mulsfp32x16x2s_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135000; +} + +static void +Opcode_ae_mulsp32x16x2_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x133000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_h_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0020; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x107000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00c0; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa3000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00a0; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa1000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff000; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00e0; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5000; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103000; +} + +static void +Opcode_ae_mulsfp32x16x2s_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_ae_mulsp32x16x2_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_ae_mulsfp32x16x2rs_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134000; +} + +static void +Opcode_ae_mulsfp32x16x2ras_l_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_ae_mulp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10900c0; +} + +static void +Opcode_ae_mulp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76000; +} + +static void +Opcode_ae_mulp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc6000; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090090; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x73000; +} + +static void +Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3000; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1090080; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72000; +} + +static void +Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2000; +} + +static void +Opcode_ae_mulp32x2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000; +} + +static void +Opcode_ae_mulfp32x2rs_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7000; +} + +static void +Opcode_ae_mulfp32x2ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000; +} + +static void +Opcode_ae_mulap32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b0040; +} + +static void +Opcode_ae_mulap32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x49000; +} + +static void +Opcode_ae_mulap32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d000; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a0050; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46000; +} + +static void +Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a000; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11a0040; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x45000; +} + +static void +Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x89000; +} + +static void +Opcode_ae_mulap32x2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1000; +} + +static void +Opcode_ae_mulafp32x2rs_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbe000; +} + +static void +Opcode_ae_mulafp32x2ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0030; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa000; +} + +static void +Opcode_ae_mulsp32x2_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x108000; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10d0000; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa7000; +} + +static void +Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105000; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c00f0; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6000; +} + +static void +Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x104000; +} + +static void +Opcode_ae_mulsp32x2_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_ae_mulsfp32x2rs_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_ae_mulsfp32x2ras_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x137000; +} + +static void +Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x172000; +} + +static void +Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x171000; +} + +static void +Opcode_ae_mulc32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300b0; +} + +static void +Opcode_ae_mulc32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000; +} + +static void +Opcode_ae_mulc32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300e0; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf5000; +} + +static void +Opcode_ae_mulfc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16d000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300f0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6000; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulfc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16e000; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300d0; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4000; +} + +static void +Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16c000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140090; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170000; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300c0; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3000; +} + +static void +Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1140080; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16f000; +} + +static void +Opcode_ae_mulac32_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200c0; +} + +static void +Opcode_ae_mulac32_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xeb000; +} + +static void +Opcode_ae_mulac32_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x163000; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200f0; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xee000; +} + +static void +Opcode_ae_mulafc24ra_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x166000; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130080; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef000; +} + +static void +Opcode_ae_mulafc32ras_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x167000; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200e0; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xed000; +} + +static void +Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x165000; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11300a0; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1000; +} + +static void +Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x169000; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11200d0; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec000; +} + +static void +Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1130090; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168000; +} + +static void +Opcode_ae_mulf16x4ss_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1030000; +} + +static void +Opcode_ae_mulaf16x4ss_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1020000; +} + +static void +Opcode_ae_mulsf16x4ss_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1050000; +} + +static void +Opcode_ae_mul16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000000; +} + +static void +Opcode_ae_mula16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1010000; +} + +static void +Opcode_ae_muls16x4_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1040000; +} + +static void +Opcode_ae_mulfd32x2s_fir_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_ae_mulfd32x2ra_fir_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_ae_mulfd32x2s_fir_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_ae_mulfd32x2ra_fir_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_ae_mulafd32x2s_fir_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_ae_mulafd32x2ra_fir_h_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ae_mulafd32x2s_fir_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700000; +} + +static void +Opcode_ae_mulafd32x2ra_fir_l_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100020; +} + +static void +Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100000; +} + +static void +Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulzaaaafq32x16_s2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mulaaaafq32x16_s2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100030; +} + +static void +Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1100010; +} + +static void +Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_mulzaaaaq32x16_s2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulaaaaq32x16_s2_Slot_ae7_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_mul16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1060000; +} + +static void +Opcode_ae_mul16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_ae_mula16_00_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10600d0; +} + +static void +Opcode_ae_mula16_00_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd000; +} + +static void +Opcode_ae_mula16_00_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x45000; +} + +static void +Opcode_ae_mul16_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e000; +} + +static void +Opcode_ae_mula16_00_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a000; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10e0060; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd000; +} + +static void +Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11b000; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10700a0; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a000; +} + +static void +Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52000; +} + +static void +Opcode_ae_mulzaaaaq16_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14e000; +} + +static void +Opcode_ae_mulaaaaq16_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x86000; +} + +static void +Opcode_ae_div64d32_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341000; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba700; +} + +static void +Opcode_ae_div64d32_h_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b9030; +} + +static void +Opcode_ae_div64d32_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0404; +} + +static void +Opcode_ae_div64d32_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10341100; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb700; +} + +static void +Opcode_ae_div64d32_l_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ba020; +} + +static void +Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360084; +} + +static void +Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0004; +} + +static void +Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0004; +} + +static void +Opcode_ae_vldl16t_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e064; +} + +static void +Opcode_ae_vldl16c_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x259010; +} + +static void +Opcode_ae_vldl16c_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e084; +} + +static void +Opcode_ae_vldl16c_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e074; +} + +static void +Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a3c0; +} + +static void +Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x341004; +} + +static void +Opcode_ae_vldsht_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x269201; +} + +static void +Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690204; +} + +static void +Opcode_ae_lb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268001; +} + +static void +Opcode_ae_lb_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3002; +} + +static void +Opcode_ae_lb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0001; +} + +static void +Opcode_ae_lb_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6002; +} + +static void +Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690304; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x268006; +} + +static void +Opcode_ae_lbi_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf2000; +} + +static void +Opcode_ae_lbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0009; +} + +static void +Opcode_ae_lbi_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1060; +} + +static void +Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830004; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8000; +} + +static void +Opcode_ae_lbk_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa9000; +} + +static void +Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce0004; +} + +static void +Opcode_ae_lbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690604; +} + +static void +Opcode_ae_lbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690704; +} + +static void +Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x774004; +} + +static void +Opcode_ae_db_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260100; +} + +static void +Opcode_ae_db_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bb800; +} + +static void +Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x775004; +} + +static void +Opcode_ae_dbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260d00; +} + +static void +Opcode_ae_dbi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc400; +} + +static void +Opcode_ae_db_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x776004; +} + +static void +Opcode_ae_dbi_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x777004; +} + +static void +Opcode_ae_db_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b4004; +} + +static void +Opcode_ae_dbi_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x744004; +} + +static void +Opcode_ae_db_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x778004; +} + +static void +Opcode_ae_dbi_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x779004; +} + +static void +Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00004; +} + +static void +Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10004; +} + +static void +Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77a004; +} + +static void +Opcode_ae_sb_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260500; +} + +static void +Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630004; +} + +static void +Opcode_ae_sbi_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21f000; +} + +static void +Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e004; +} + +static void +Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e014; +} + +static void +Opcode_ae_sb_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77b004; +} + +static void +Opcode_ae_sbi_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x560004; +} + +static void +Opcode_ae_vles16c_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e024; +} + +static void +Opcode_ae_sbf_ic_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e034; +} + +static void +Opcode_ae_sb_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a4004; +} + +static void +Opcode_ae_sbi_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0004; +} + +static void +Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27a3d0; +} + +static void +Opcode_ae_sbf_ic1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e0c4; +} + +static void +Opcode_ae_sb_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77c004; +} + +static void +Opcode_ae_sbi_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570004; +} + +static void +Opcode_ae_vles16c_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e044; +} + +static void +Opcode_ae_sbf_ip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x77e054; +} + +static void +Opcode_ae_sext32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170004; +} + +static void +Opcode_ae_sext32_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1af000; +} + +static void +Opcode_ae_movae_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260f00; +} + +static void +Opcode_ae_movae_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4100; +} + +static void +Opcode_ae_movea_Slot_ae3_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260f04; +} + +static void +Opcode_ae_movea_Slot_ae3_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4104; +} + +static void +Opcode_ae_moveep_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176010; +} + +static void +Opcode_ae_moveep_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70b01; +} + +static void +Opcode_ae_sext72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300c; +} + +static void +Opcode_ae_add72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154000; +} + +static void +Opcode_ae_sub72_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15f000; +} + +static void +Opcode_ae_add72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174000; +} + +static void +Opcode_ae_sub72x64_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x174400; +} + +static void +Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_mul32ep_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_ae_mula32ep_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000; +} + +static void +Opcode_ae_muls32ep_hh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000; +} + +static void +Opcode_ae_mulzaad32ep_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_ae_mulzssd32ep_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ae_mulaad32ep_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000; +} + +static void +Opcode_ae_mulssd32ep_hh_ll_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000; +} + +static void +Opcode_ae_mulaad32usep_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000; +} + +static void +Opcode_ae_mulzaad32usep_hl_lh_s2_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000; +} + +static void +Opcode_ae_srai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_ae_slai72_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175000; +} + +static void +Opcode_ae_sat64s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b8000; +} + +static void +Opcode_ae_l16si_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d; +} + +static void +Opcode_ae_l16ui_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d; +} + +static void +Opcode_ae_s16i_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600d; +} + +static void +Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f700; +} + +static void +Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f710; +} + +static void +Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0040; +} + +static void +Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0050; +} + +static void +Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb0000; +} + +static void +Opcode_movt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0d00; +} + +static void +Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0000; +} + +static void +Opcode_movf_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0300; +} + +static void +Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b0000; +} + +static void +Opcode_moveqz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0400; +} + +static void +Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b0000; +} + +static void +Opcode_movnez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0b00; +} + +static void +Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0000; +} + +static void +Opcode_movgez_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0700; +} + +static void +Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0000; +} + +static void +Opcode_movltz_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0900; +} + +static void +Opcode_trunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0200; +} + +static void +Opcode_utrunc_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0100; +} + +static void +Opcode_trunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1034a000; +} + +static void +Opcode_utrunc_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10346000; +} + +static void +Opcode_ficeil_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343001; +} + +static void +Opcode_fifloor_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343003; +} + +static void +Opcode_firound_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343002; +} + +static void +Opcode_fitrunc_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343000; +} + +static void +Opcode_firint_s_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343004; +} + +static void +Opcode_cvtsf16_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343007; +} + +static void +Opcode_cvtsf16_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10343005; +} + +static void +Opcode_cvtf16s_l_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342007; +} + +static void +Opcode_cvtf16s_h_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10342005; +} + +static void +Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0010; +} + +static void +Opcode_abs_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176080; +} + +static void +Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_mul_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11800d0; +} + +static void +Opcode_mul_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfb000; +} + +static void +Opcode_mul_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17d000; +} + +static void +Opcode_mul_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_madd_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11500a0; +} + +static void +Opcode_madd_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfd000; +} + +static void +Opcode_madd_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17b000; +} + +static void +Opcode_madd_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bd000; +} + +static void +Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_msub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150090; +} + +static void +Opcode_msub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa000; +} + +static void +Opcode_msub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17c000; +} + +static void +Opcode_msub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bf000; +} + +static void +Opcode_msubn_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1be000; +} + +static void +Opcode_maddn_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_maddn_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17a000; +} + +static void +Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_add_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1150080; +} + +static void +Opcode_add_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfe000; +} + +static void +Opcode_add_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x179000; +} + +static void +Opcode_add_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1bc000; +} + +static void +Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_sub_s_Slot_ae2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11900d0; +} + +static void +Opcode_sub_s_Slot_ae5_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc000; +} + +static void +Opcode_sub_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17e000; +} + +static void +Opcode_sub_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e1000; +} + +static void +Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0060; +} + +static void +Opcode_neg_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x176090; +} + +static void +Opcode_neg_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c00; +} + +static void +Opcode_float_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0800; +} + +static void +Opcode_ufloat_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0a00; +} + +static void +Opcode_float_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10348000; +} + +static void +Opcode_ufloat_sx2_Slot_ae2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10344000; +} + +static void +Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ole_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0f10; +} + +static void +Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_olt_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0010; +} + +static void +Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0000; +} + +static void +Opcode_oeq_s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0f00; +} + +static void +Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_const_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0030; +} + +static void +Opcode_const_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f600; +} + +static void +Opcode_nexp01_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f200; +} + +static void +Opcode_mksadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f100; +} + +static void +Opcode_mkdadj_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300f; +} + +static void +Opcode_div0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f000; +} + +static void +Opcode_sqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f500; +} + +static void +Opcode_recip0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f300; +} + +static void +Opcode_rsqrt0_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17f400; +} + +static void +Opcode_divn_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_addexp_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300e; +} + +static void +Opcode_addexpm_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x17300d; +} + +static void +Opcode_min_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178000; +} + +static void +Opcode_max_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x177000; +} + +static void +Opcode_mulmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x188000; +} + +static void +Opcode_mulmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e2000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_maddmux_s_Slot_ae_slot3_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0000; +} + +static void +Opcode_conjc_s_Slot_ae_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x175f00; +} + +static void +Opcode_sigmoid_q15_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60100; +} + +static void +Opcode_sigmoid_fp32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addi_n_Slot_ae4_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32i_n_Slot_ae4_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0, Opcode_mov_n_Slot_ae_slot1_encode, Opcode_mov_n_Slot_ae_slot0_encode, 0, Opcode_mov_n_Slot_ae2_slot1_encode, Opcode_mov_n_Slot_ae2_slot0_encode, Opcode_mov_n_Slot_ae3_slot1_encode, Opcode_mov_n_Slot_ae3_slot0_encode, Opcode_mov_n_Slot_ae4_slot1_encode, 0, 0, 0, Opcode_mov_n_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movi_n_Slot_ae4_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, 0, 0, Opcode_addi_Slot_ae_slot1_encode, Opcode_addi_Slot_ae_slot0_encode, 0, Opcode_addi_Slot_ae2_slot1_encode, Opcode_addi_Slot_ae2_slot0_encode, Opcode_addi_Slot_ae3_slot1_encode, Opcode_addi_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, 0, 0, Opcode_addmi_Slot_ae_slot1_encode, Opcode_addmi_Slot_ae_slot0_encode, 0, Opcode_addmi_Slot_ae2_slot1_encode, Opcode_addmi_Slot_ae2_slot0_encode, Opcode_addmi_Slot_ae3_slot1_encode, Opcode_addmi_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addmi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, 0, 0, Opcode_add_Slot_ae_slot1_encode, Opcode_add_Slot_ae_slot0_encode, 0, Opcode_add_Slot_ae2_slot1_encode, Opcode_add_Slot_ae2_slot0_encode, Opcode_add_Slot_ae3_slot1_encode, Opcode_add_Slot_ae3_slot0_encode, Opcode_add_Slot_ae4_slot1_encode, 0, 0, 0, Opcode_add_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, 0, 0, Opcode_addx2_Slot_ae_slot1_encode, Opcode_addx2_Slot_ae_slot0_encode, 0, Opcode_addx2_Slot_ae2_slot1_encode, Opcode_addx2_Slot_ae2_slot0_encode, Opcode_addx2_Slot_ae3_slot1_encode, Opcode_addx2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, 0, 0, Opcode_addx4_Slot_ae_slot1_encode, Opcode_addx4_Slot_ae_slot0_encode, 0, Opcode_addx4_Slot_ae2_slot1_encode, Opcode_addx4_Slot_ae2_slot0_encode, Opcode_addx4_Slot_ae3_slot1_encode, Opcode_addx4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, 0, 0, Opcode_addx8_Slot_ae_slot1_encode, Opcode_addx8_Slot_ae_slot0_encode, 0, Opcode_addx8_Slot_ae2_slot1_encode, Opcode_addx8_Slot_ae2_slot0_encode, Opcode_addx8_Slot_ae3_slot1_encode, Opcode_addx8_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_addx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, 0, 0, Opcode_sub_Slot_ae_slot1_encode, Opcode_sub_Slot_ae_slot0_encode, 0, Opcode_sub_Slot_ae2_slot1_encode, Opcode_sub_Slot_ae2_slot0_encode, Opcode_sub_Slot_ae3_slot1_encode, Opcode_sub_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_sub_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, 0, 0, Opcode_subx2_Slot_ae_slot1_encode, Opcode_subx2_Slot_ae_slot0_encode, 0, Opcode_subx2_Slot_ae2_slot1_encode, Opcode_subx2_Slot_ae2_slot0_encode, Opcode_subx2_Slot_ae3_slot1_encode, Opcode_subx2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_subx2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, 0, 0, Opcode_subx4_Slot_ae_slot1_encode, Opcode_subx4_Slot_ae_slot0_encode, 0, Opcode_subx4_Slot_ae2_slot1_encode, Opcode_subx4_Slot_ae2_slot0_encode, Opcode_subx4_Slot_ae3_slot1_encode, Opcode_subx4_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_subx4_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, 0, 0, Opcode_subx8_Slot_ae_slot1_encode, Opcode_subx8_Slot_ae_slot0_encode, 0, Opcode_subx8_Slot_ae2_slot1_encode, Opcode_subx8_Slot_ae2_slot0_encode, Opcode_subx8_Slot_ae3_slot1_encode, Opcode_subx8_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_subx8_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, 0, 0, Opcode_and_Slot_ae_slot1_encode, Opcode_and_Slot_ae_slot0_encode, 0, Opcode_and_Slot_ae2_slot1_encode, Opcode_and_Slot_ae2_slot0_encode, Opcode_and_Slot_ae3_slot1_encode, Opcode_and_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_and_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, 0, 0, Opcode_or_Slot_ae_slot1_encode, Opcode_or_Slot_ae_slot0_encode, 0, Opcode_or_Slot_ae2_slot1_encode, Opcode_or_Slot_ae2_slot0_encode, Opcode_or_Slot_ae3_slot1_encode, Opcode_or_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_or_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, 0, 0, Opcode_xor_Slot_ae_slot1_encode, Opcode_xor_Slot_ae_slot0_encode, 0, Opcode_xor_Slot_ae2_slot1_encode, Opcode_xor_Slot_ae2_slot0_encode, Opcode_xor_Slot_ae3_slot1_encode, Opcode_xor_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_xor_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, 0, 0, Opcode_extui_Slot_ae_slot1_encode, 0, 0, Opcode_extui_Slot_ae2_slot1_encode, Opcode_extui_Slot_ae2_slot0_encode, Opcode_extui_Slot_ae3_slot1_encode, Opcode_extui_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_extui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, 0, 0, Opcode_l16ui_Slot_ae_slot1_encode, 0, 0, Opcode_l16ui_Slot_ae2_slot1_encode, Opcode_l16ui_Slot_ae2_slot0_encode, Opcode_l16ui_Slot_ae3_slot1_encode, Opcode_l16ui_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l16ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, 0, 0, Opcode_l16si_Slot_ae_slot1_encode, Opcode_l16si_Slot_ae_slot0_encode, 0, Opcode_l16si_Slot_ae2_slot1_encode, Opcode_l16si_Slot_ae2_slot0_encode, Opcode_l16si_Slot_ae3_slot1_encode, Opcode_l16si_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l16si_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, 0, 0, Opcode_l32i_Slot_ae_slot1_encode, Opcode_l32i_Slot_ae_slot0_encode, 0, Opcode_l32i_Slot_ae2_slot1_encode, Opcode_l32i_Slot_ae2_slot0_encode, Opcode_l32i_Slot_ae3_slot1_encode, Opcode_l32i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32r_Slot_ae2_slot0_encode, 0, Opcode_l32r_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l32r_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, 0, 0, Opcode_l8ui_Slot_ae_slot1_encode, 0, 0, Opcode_l8ui_Slot_ae2_slot1_encode, Opcode_l8ui_Slot_ae2_slot0_encode, Opcode_l8ui_Slot_ae3_slot1_encode, Opcode_l8ui_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_l8ui_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loop_Slot_ae2_slot0_encode, 0, Opcode_loop_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_loop_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopgtz_Slot_ae2_slot0_encode, 0, Opcode_loopgtz_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_loopgtz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_loopnez_Slot_ae2_slot0_encode, 0, Opcode_loopnez_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_loopnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, 0, 0, Opcode_movi_Slot_ae_slot1_encode, Opcode_movi_Slot_ae_slot0_encode, 0, Opcode_movi_Slot_ae2_slot1_encode, Opcode_movi_Slot_ae2_slot0_encode, Opcode_movi_Slot_ae3_slot1_encode, Opcode_movi_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, 0, 0, Opcode_moveqz_Slot_ae_slot1_encode, Opcode_moveqz_Slot_ae_slot0_encode, 0, Opcode_moveqz_Slot_ae2_slot1_encode, Opcode_moveqz_Slot_ae2_slot0_encode, Opcode_moveqz_Slot_ae3_slot1_encode, Opcode_moveqz_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_moveqz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, 0, 0, Opcode_movgez_Slot_ae_slot1_encode, Opcode_movgez_Slot_ae_slot0_encode, 0, Opcode_movgez_Slot_ae2_slot1_encode, Opcode_movgez_Slot_ae2_slot0_encode, Opcode_movgez_Slot_ae3_slot1_encode, Opcode_movgez_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_movgez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, 0, 0, Opcode_movltz_Slot_ae_slot1_encode, Opcode_movltz_Slot_ae_slot0_encode, 0, Opcode_movltz_Slot_ae2_slot1_encode, Opcode_movltz_Slot_ae2_slot0_encode, Opcode_movltz_Slot_ae3_slot1_encode, Opcode_movltz_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_movltz_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, 0, 0, Opcode_movnez_Slot_ae_slot1_encode, Opcode_movnez_Slot_ae_slot0_encode, 0, Opcode_movnez_Slot_ae2_slot1_encode, Opcode_movnez_Slot_ae2_slot0_encode, Opcode_movnez_Slot_ae3_slot1_encode, Opcode_movnez_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_movnez_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, 0, 0, Opcode_abs_Slot_ae_slot1_encode, Opcode_abs_Slot_ae_slot0_encode, 0, Opcode_abs_Slot_ae2_slot1_encode, Opcode_abs_Slot_ae2_slot0_encode, Opcode_abs_Slot_ae3_slot1_encode, Opcode_abs_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_abs_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, 0, 0, Opcode_neg_Slot_ae_slot1_encode, Opcode_neg_Slot_ae_slot0_encode, 0, Opcode_neg_Slot_ae2_slot1_encode, Opcode_neg_Slot_ae2_slot0_encode, Opcode_neg_Slot_ae3_slot1_encode, Opcode_neg_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_neg_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot3_encode, Opcode_nop_Slot_ae_slot2_encode, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode, Opcode_nop_Slot_ae2_slot2_encode, Opcode_nop_Slot_ae2_slot1_encode, Opcode_nop_Slot_ae2_slot0_encode, Opcode_nop_Slot_ae3_slot1_encode, Opcode_nop_Slot_ae3_slot0_encode, Opcode_nop_Slot_ae4_slot1_encode, Opcode_nop_Slot_ae4_slot0_encode, Opcode_nop_Slot_ae5_slot2_encode, Opcode_nop_Slot_ae5_slot1_encode, Opcode_nop_Slot_ae5_slot0_encode, Opcode_nop_Slot_ae6_slot3_encode, Opcode_nop_Slot_ae6_slot2_encode, Opcode_nop_Slot_ae6_slot1_encode, Opcode_nop_Slot_ae6_slot0_encode, Opcode_nop_Slot_ae7_slot3_encode, Opcode_nop_Slot_ae7_slot2_encode, Opcode_nop_Slot_ae7_slot1_encode, Opcode_nop_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode, 0, 0, Opcode_s16i_Slot_ae2_slot0_encode, 0, Opcode_s16i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_s16i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode, 0, 0, Opcode_s32i_Slot_ae2_slot0_encode, 0, Opcode_s32i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_s32i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s8i_Slot_ae2_slot0_encode, 0, Opcode_s8i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_s8i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot1_encode, Opcode_ssa8b_Slot_ae_slot0_encode, 0, Opcode_ssa8b_Slot_ae2_slot1_encode, Opcode_ssa8b_Slot_ae2_slot0_encode, Opcode_ssa8b_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot1_encode, Opcode_ssa8l_Slot_ae_slot0_encode, 0, Opcode_ssa8l_Slot_ae2_slot1_encode, Opcode_ssa8l_Slot_ae2_slot0_encode, Opcode_ssa8l_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssl_Slot_ae_slot1_encode, Opcode_ssl_Slot_ae_slot0_encode, 0, Opcode_ssl_Slot_ae2_slot1_encode, Opcode_ssl_Slot_ae2_slot0_encode, Opcode_ssl_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssr_Slot_ae_slot1_encode, Opcode_ssr_Slot_ae_slot0_encode, 0, Opcode_ssr_Slot_ae2_slot1_encode, Opcode_ssr_Slot_ae2_slot0_encode, Opcode_ssr_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssai_Slot_ae_slot1_encode, Opcode_ssai_Slot_ae_slot0_encode, 0, Opcode_ssai_Slot_ae2_slot1_encode, Opcode_ssai_Slot_ae2_slot0_encode, Opcode_ssai_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, 0, 0, Opcode_sll_Slot_ae_slot1_encode, Opcode_sll_Slot_ae_slot0_encode, 0, Opcode_sll_Slot_ae2_slot1_encode, Opcode_sll_Slot_ae2_slot0_encode, Opcode_sll_Slot_ae3_slot1_encode, Opcode_sll_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_sll_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, 0, 0, Opcode_src_Slot_ae_slot1_encode, Opcode_src_Slot_ae_slot0_encode, 0, Opcode_src_Slot_ae2_slot1_encode, Opcode_src_Slot_ae2_slot0_encode, Opcode_src_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, 0, 0, Opcode_sra_Slot_ae_slot1_encode, Opcode_sra_Slot_ae_slot0_encode, 0, Opcode_sra_Slot_ae2_slot1_encode, Opcode_sra_Slot_ae2_slot0_encode, Opcode_sra_Slot_ae3_slot1_encode, Opcode_sra_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_sra_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, 0, 0, Opcode_srl_Slot_ae_slot1_encode, Opcode_srl_Slot_ae_slot0_encode, 0, Opcode_srl_Slot_ae2_slot1_encode, Opcode_srl_Slot_ae2_slot0_encode, Opcode_srl_Slot_ae3_slot1_encode, Opcode_srl_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_srl_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, 0, 0, Opcode_slli_Slot_ae_slot1_encode, Opcode_slli_Slot_ae_slot0_encode, 0, Opcode_slli_Slot_ae2_slot1_encode, Opcode_slli_Slot_ae2_slot0_encode, Opcode_slli_Slot_ae3_slot1_encode, Opcode_slli_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_slli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, 0, 0, Opcode_srai_Slot_ae_slot1_encode, Opcode_srai_Slot_ae_slot0_encode, 0, Opcode_srai_Slot_ae2_slot1_encode, Opcode_srai_Slot_ae2_slot0_encode, Opcode_srai_Slot_ae3_slot1_encode, Opcode_srai_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_srai_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, 0, 0, Opcode_srli_Slot_ae_slot1_encode, Opcode_srli_Slot_ae_slot0_encode, 0, Opcode_srli_Slot_ae2_slot1_encode, Opcode_srli_Slot_ae2_slot0_encode, Opcode_srli_Slot_ae3_slot1_encode, Opcode_srli_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_srli_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { + Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { + Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode, 0, 0, Opcode_andb_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode, 0, 0, Opcode_andbc_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode, 0, 0, Opcode_orb_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode, 0, 0, Opcode_orbc_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode, 0, 0, Opcode_xorb_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode, 0, 0, Opcode_all4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode, 0, 0, Opcode_any4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode, 0, 0, Opcode_all8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode, 0, 0, Opcode_any8_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode, 0, 0, Opcode_movf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode, 0, 0, Opcode_movt_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { + Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfm_b_encode_fns[] = { + Opcode_dpfm_b_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfm_b_Slot_ae_slot0_encode, 0, 0, Opcode_dpfm_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfm_bf_encode_fns[] = { + Opcode_dpfm_bf_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfm_bf_Slot_ae_slot0_encode, 0, 0, Opcode_dpfm_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_b_encode_fns[] = { + Opcode_dpfr_b_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfr_b_Slot_ae_slot0_encode, 0, 0, Opcode_dpfr_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_bf_encode_fns[] = { + Opcode_dpfr_bf_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfr_bf_Slot_ae_slot0_encode, 0, 0, Opcode_dpfr_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_b_encode_fns[] = { + Opcode_dpfw_b_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfw_b_Slot_ae_slot0_encode, 0, 0, Opcode_dpfw_b_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_bf_encode_fns[] = { + Opcode_dpfw_bf_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_dpfw_bf_Slot_ae_slot0_encode, 0, 0, Opcode_dpfw_bf_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfnxt_f_encode_fns[] = { + Opcode_pfnxt_f_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_b_encode_fns[] = { + Opcode_dhi_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_b_encode_fns[] = { + Opcode_dhwbi_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_b_encode_fns[] = { + Opcode_dhwb_b_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfend_a_encode_fns[] = { + Opcode_pfend_a_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfend_o_encode_fns[] = { + Opcode_pfend_o_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfwait_a_encode_fns[] = { + Opcode_pfwait_a_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pfwait_r_encode_fns[] = { + Opcode_pfwait_r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { + Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { + Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { + Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, 0, 0, Opcode_clamps_Slot_ae_slot1_encode, Opcode_clamps_Slot_ae_slot0_encode, 0, Opcode_clamps_Slot_ae2_slot1_encode, Opcode_clamps_Slot_ae2_slot0_encode, Opcode_clamps_Slot_ae3_slot1_encode, Opcode_clamps_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_clamps_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, 0, 0, Opcode_max_Slot_ae_slot1_encode, Opcode_max_Slot_ae_slot0_encode, 0, Opcode_max_Slot_ae2_slot1_encode, Opcode_max_Slot_ae2_slot0_encode, Opcode_max_Slot_ae3_slot1_encode, Opcode_max_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_max_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, 0, 0, Opcode_maxu_Slot_ae_slot1_encode, Opcode_maxu_Slot_ae_slot0_encode, 0, Opcode_maxu_Slot_ae2_slot1_encode, Opcode_maxu_Slot_ae2_slot0_encode, Opcode_maxu_Slot_ae3_slot1_encode, Opcode_maxu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_maxu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, 0, 0, Opcode_min_Slot_ae_slot1_encode, Opcode_min_Slot_ae_slot0_encode, 0, Opcode_min_Slot_ae2_slot1_encode, Opcode_min_Slot_ae2_slot0_encode, Opcode_min_Slot_ae3_slot1_encode, Opcode_min_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_min_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, 0, 0, Opcode_minu_Slot_ae_slot1_encode, Opcode_minu_Slot_ae_slot0_encode, 0, Opcode_minu_Slot_ae2_slot1_encode, Opcode_minu_Slot_ae2_slot0_encode, Opcode_minu_Slot_ae3_slot1_encode, Opcode_minu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_minu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, 0, 0, Opcode_sext_Slot_ae_slot1_encode, Opcode_sext_Slot_ae_slot0_encode, 0, Opcode_sext_Slot_ae2_slot1_encode, Opcode_sext_Slot_ae2_slot0_encode, Opcode_sext_Slot_ae3_slot1_encode, Opcode_sext_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_sext_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_beqz_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bgez_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bltz_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bnez_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_beqi_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bgei_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_blti_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bnei_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bgeui_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bltui_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bbci_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bbsi_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_ball_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bany_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bbc_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bbs_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_beq_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bgeu_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bge_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bltu_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_blt_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bnall_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bne_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_w15_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w15_Slot_ae2_slot0_encode, 0, 0, 0, Opcode_bnone_w15_Slot_ae4_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { + Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { + Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { + Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { + Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { + Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cw_sd_no_encode_fns[] = { + Opcode_rur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cw_sd_no_encode_fns[] = { + Opcode_wur_ae_cw_sd_no_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { + Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { + Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { + Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { + Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin1_encode_fns[] = { + Opcode_rur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin1_encode_fns[] = { + Opcode_wur_ae_cbegin1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cend1_encode_fns[] = { + Opcode_rur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cend1_encode_fns[] = { + Opcode_wur_ae_cend1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext16_encode_fns[] = { + 0, 0, Opcode_ae_sext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zext16_encode_fns[] = { + 0, 0, Opcode_ae_zext16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_clamps16_encode_fns[] = { + 0, 0, Opcode_ae_clamps16_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { + Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { + Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { + Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { + Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64iter_encode_fns[] = { + Opcode_f64iter_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64rnd_encode_fns[] = { + Opcode_f64rnd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64addc_encode_fns[] = { + Opcode_f64addc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64subc_encode_fns[] = { + Opcode_f64subc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64sig_encode_fns[] = { + Opcode_f64sig_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64cmpl_encode_fns[] = { + Opcode_f64cmpl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64cmph_encode_fns[] = { + Opcode_f64cmph_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64norm_encode_fns[] = { + Opcode_f64norm_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_f64sexp_encode_fns[] = { + Opcode_f64sexp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rf64r_encode_fns[] = { + Opcode_rf64r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wf64r_encode_fns[] = { + Opcode_wf64r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_f64r_lo_encode_fns[] = { + Opcode_rur_f64r_lo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_f64r_lo_encode_fns[] = { + Opcode_wur_f64r_lo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_f64r_hi_encode_fns[] = { + Opcode_rur_f64r_hi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_f64r_hi_encode_fns[] = { + Opcode_wur_f64r_hi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_f64s_encode_fns[] = { + Opcode_rur_f64s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_f64s_encode_fns[] = { + Opcode_wur_f64s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { + Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { + Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { + Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { + Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { + Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rur_ae_bitptr_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_rur_ae_bitptr_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { + Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { + Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { + Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { + Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { + Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { + Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { + Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { + Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { + Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { + Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { + Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_ae_cwrap_encode_fns[] = { + Opcode_rur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_ae_cwrap_encode_fns[] = { + Opcode_wur_ae_cwrap_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_i_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae_slot0_encode, 0, Opcode_ae_l8x4f_i_Slot_ae2_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_i_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l8x4f_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l8x4f_ip_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l8x4f_ip_Slot_ae2_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae2_slot0_encode, Opcode_ae_l8x4f_ip_Slot_ae3_slot1_encode, Opcode_ae_l8x4f_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l8x4f_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae_slot1_encode, Opcode_ae_l16m_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_xc_Slot_ae2_slot1_encode, Opcode_ae_l16m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16m_xc1_Slot_ae2_slot1_encode, Opcode_ae_l16m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_i_encode_fns[] = { + Opcode_ae_l16m_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16m_i_Slot_ae_slot1_encode, Opcode_ae_l16m_i_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_i_Slot_ae2_slot1_encode, Opcode_ae_l16m_i_Slot_ae2_slot0_encode, Opcode_ae_l16m_i_Slot_ae3_slot1_encode, Opcode_ae_l16m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_iu_encode_fns[] = { + Opcode_ae_l16m_iu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae_slot1_encode, Opcode_ae_l16m_iu_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_iu_Slot_ae2_slot1_encode, Opcode_ae_l16m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16m_x_Slot_ae_slot1_encode, Opcode_ae_l16m_x_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_x_Slot_ae2_slot1_encode, Opcode_ae_l16m_x_Slot_ae2_slot0_encode, Opcode_ae_l16m_x_Slot_ae3_slot1_encode, Opcode_ae_l16m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16m_xu_encode_fns[] = { + Opcode_ae_l16m_xu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae_slot1_encode, Opcode_ae_l16m_xu_Slot_ae_slot0_encode, 0, Opcode_ae_l16m_xu_Slot_ae2_slot1_encode, Opcode_ae_l16m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae_slot1_encode, Opcode_ae_l16_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l16_xc_Slot_ae2_slot1_encode, Opcode_ae_l16_xc_Slot_ae2_slot0_encode, Opcode_ae_l16_xc_Slot_ae3_slot1_encode, Opcode_ae_l16_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae_slot1_encode, Opcode_ae_l16_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l16_xc1_Slot_ae2_slot1_encode, Opcode_ae_l16_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_i_encode_fns[] = { + Opcode_ae_l16_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16_i_Slot_ae_slot1_encode, Opcode_ae_l16_i_Slot_ae_slot0_encode, 0, Opcode_ae_l16_i_Slot_ae2_slot1_encode, Opcode_ae_l16_i_Slot_ae2_slot0_encode, Opcode_ae_l16_i_Slot_ae3_slot1_encode, Opcode_ae_l16_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_ip_encode_fns[] = { + Opcode_ae_l16_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae_slot1_encode, Opcode_ae_l16_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l16_ip_Slot_ae2_slot1_encode, Opcode_ae_l16_ip_Slot_ae2_slot0_encode, Opcode_ae_l16_ip_Slot_ae3_slot1_encode, Opcode_ae_l16_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16_x_Slot_ae_slot1_encode, Opcode_ae_l16_x_Slot_ae_slot0_encode, 0, Opcode_ae_l16_x_Slot_ae2_slot1_encode, Opcode_ae_l16_x_Slot_ae2_slot0_encode, Opcode_ae_l16_x_Slot_ae3_slot1_encode, Opcode_ae_l16_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16_xp_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae_slot1_encode, Opcode_ae_l16_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l16_xp_Slot_ae2_slot1_encode, Opcode_ae_l16_xp_Slot_ae2_slot0_encode, Opcode_ae_l16_xp_Slot_ae3_slot1_encode, Opcode_ae_l16_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc_encode_fns[] = { + Opcode_ae_l32f24_xc_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_xc_Slot_ae2_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae_slot1_encode, Opcode_ae_l32f24_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_xc1_Slot_ae2_slot1_encode, Opcode_ae_l32f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_i_encode_fns[] = { + Opcode_ae_l32f24_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae_slot1_encode, Opcode_ae_l32f24_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_i_Slot_ae2_slot1_encode, Opcode_ae_l32f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32f24_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_ip_encode_fns[] = { + Opcode_ae_l32f24_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_ip_Slot_ae2_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae_slot1_encode, Opcode_ae_l32f24_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_x_Slot_ae2_slot1_encode, Opcode_ae_l32f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32f24_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32f24_xp_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l32f24_xp_Slot_ae2_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32f24_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc_encode_fns[] = { + Opcode_ae_l32_xc_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae_slot1_encode, Opcode_ae_l32_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32_xc_Slot_ae2_slot1_encode, Opcode_ae_l32_xc_Slot_ae2_slot0_encode, Opcode_ae_l32_xc_Slot_ae3_slot1_encode, Opcode_ae_l32_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae_slot1_encode, Opcode_ae_l32_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l32_xc1_Slot_ae2_slot1_encode, Opcode_ae_l32_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_i_encode_fns[] = { + Opcode_ae_l32_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32_i_Slot_ae_slot1_encode, Opcode_ae_l32_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32_i_Slot_ae2_slot1_encode, Opcode_ae_l32_i_Slot_ae2_slot0_encode, Opcode_ae_l32_i_Slot_ae3_slot1_encode, Opcode_ae_l32_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_ip_encode_fns[] = { + Opcode_ae_l32_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae_slot1_encode, Opcode_ae_l32_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l32_ip_Slot_ae2_slot1_encode, Opcode_ae_l32_ip_Slot_ae2_slot0_encode, Opcode_ae_l32_ip_Slot_ae3_slot1_encode, Opcode_ae_l32_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_x_encode_fns[] = { + Opcode_ae_l32_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32_x_Slot_ae_slot1_encode, Opcode_ae_l32_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32_x_Slot_ae2_slot1_encode, Opcode_ae_l32_x_Slot_ae2_slot0_encode, Opcode_ae_l32_x_Slot_ae3_slot1_encode, Opcode_ae_l32_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32_xp_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae_slot1_encode, Opcode_ae_l32_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l32_xp_Slot_ae2_slot1_encode, Opcode_ae_l32_xp_Slot_ae2_slot0_encode, Opcode_ae_l32_xp_Slot_ae3_slot1_encode, Opcode_ae_l32_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae_slot1_encode, Opcode_ae_l32m_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_xc_Slot_ae2_slot1_encode, Opcode_ae_l32m_xc_Slot_ae2_slot0_encode, Opcode_ae_l32m_xc_Slot_ae3_slot1_encode, Opcode_ae_l32m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_i_encode_fns[] = { + Opcode_ae_l32m_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32m_i_Slot_ae_slot1_encode, Opcode_ae_l32m_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_i_Slot_ae2_slot1_encode, Opcode_ae_l32m_i_Slot_ae2_slot0_encode, Opcode_ae_l32m_i_Slot_ae3_slot1_encode, Opcode_ae_l32m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_iu_encode_fns[] = { + Opcode_ae_l32m_iu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae_slot1_encode, Opcode_ae_l32m_iu_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_iu_Slot_ae2_slot1_encode, Opcode_ae_l32m_iu_Slot_ae2_slot0_encode, Opcode_ae_l32m_iu_Slot_ae3_slot1_encode, Opcode_ae_l32m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_x_encode_fns[] = { + Opcode_ae_l32m_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32m_x_Slot_ae_slot1_encode, Opcode_ae_l32m_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_x_Slot_ae2_slot1_encode, Opcode_ae_l32m_x_Slot_ae2_slot0_encode, Opcode_ae_l32m_x_Slot_ae3_slot1_encode, Opcode_ae_l32m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32m_xu_encode_fns[] = { + Opcode_ae_l32m_xu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae_slot1_encode, Opcode_ae_l32m_xu_Slot_ae_slot0_encode, 0, Opcode_ae_l32m_xu_Slot_ae2_slot1_encode, Opcode_ae_l32m_xu_Slot_ae2_slot0_encode, Opcode_ae_l32m_xu_Slot_ae3_slot1_encode, Opcode_ae_l32m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_xc_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae_slot1_encode, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_i_encode_fns[] = { + Opcode_ae_l16x2m_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_i_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_i_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_iu_encode_fns[] = { + Opcode_ae_l16x2m_iu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_iu_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_iu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_x_encode_fns[] = { + Opcode_ae_l16x2m_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_x_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_x_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x2m_xu_encode_fns[] = { + Opcode_ae_l16x2m_xu_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae_slot0_encode, 0, Opcode_ae_l16x2m_xu_Slot_ae2_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae2_slot0_encode, Opcode_ae_l16x2m_xu_Slot_ae3_slot1_encode, Opcode_ae_l16x2m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc_encode_fns[] = { + Opcode_ae_l32x2f24_xc_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_xc_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_i_encode_fns[] = { + Opcode_ae_l32x2f24_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_i_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ip_encode_fns[] = { + Opcode_ae_l32x2f24_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_ip_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_rip_encode_fns[] = { + Opcode_ae_l32x2f24_rip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_rip_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_rip_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ri_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_ri_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ri_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ri_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_ri_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_ric_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_ric1_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_x_encode_fns[] = { + Opcode_ae_l32x2f24_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_x_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2f24_xp_encode_fns[] = { + Opcode_ae_l32x2f24_xp_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2f24_xp_Slot_ae2_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2f24_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2f24_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc_encode_fns[] = { + Opcode_ae_l32x2_xc_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_xc_Slot_ae2_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xc_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc_Slot_ae7_slot1_encode, Opcode_ae_l32x2_xc_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae_slot1_encode, Opcode_ae_l32x2_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_xc1_Slot_ae2_slot1_encode, Opcode_ae_l32x2_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_xc1_Slot_ae7_slot1_encode, Opcode_ae_l32x2_xc1_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_i_encode_fns[] = { + Opcode_ae_l32x2_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae_slot1_encode, Opcode_ae_l32x2_i_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_i_Slot_ae2_slot1_encode, Opcode_ae_l32x2_i_Slot_ae2_slot0_encode, Opcode_ae_l32x2_i_Slot_ae3_slot1_encode, Opcode_ae_l32x2_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l32x2_i_Slot_ae6_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_i_Slot_ae7_slot1_encode, Opcode_ae_l32x2_i_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ip_encode_fns[] = { + Opcode_ae_l32x2_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_ip_Slot_ae2_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ip_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l32x2_ip_Slot_ae6_slot1_encode, 0, 0, 0, Opcode_ae_l32x2_ip_Slot_ae7_slot1_encode, Opcode_ae_l32x2_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_ric_Slot_ae2_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae2_slot0_encode, Opcode_ae_l32x2_ric_Slot_ae3_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric_Slot_ae7_slot1_encode, Opcode_ae_l32x2_ric_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae_slot1_encode, Opcode_ae_l32x2_ric1_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_ric1_Slot_ae2_slot1_encode, Opcode_ae_l32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_x_encode_fns[] = { + Opcode_ae_l32x2_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae_slot1_encode, Opcode_ae_l32x2_x_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_x_Slot_ae2_slot1_encode, Opcode_ae_l32x2_x_Slot_ae2_slot0_encode, Opcode_ae_l32x2_x_Slot_ae3_slot1_encode, Opcode_ae_l32x2_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_x_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l32x2_x_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l32x2_xp_encode_fns[] = { + Opcode_ae_l32x2_xp_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l32x2_xp_Slot_ae2_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae2_slot0_encode, Opcode_ae_l32x2_xp_Slot_ae3_slot1_encode, Opcode_ae_l32x2_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l32x2_xp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l32x2_xp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_xc_Slot_ae2_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xc_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc_Slot_ae7_slot1_encode, Opcode_ae_l16x4_xc_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae_slot1_encode, Opcode_ae_l16x4_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_xc1_Slot_ae2_slot1_encode, Opcode_ae_l16x4_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l16x4_xc1_Slot_ae7_slot1_encode, Opcode_ae_l16x4_xc1_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_i_encode_fns[] = { + Opcode_ae_l16x4_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae_slot1_encode, Opcode_ae_l16x4_i_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_i_Slot_ae2_slot1_encode, Opcode_ae_l16x4_i_Slot_ae2_slot0_encode, Opcode_ae_l16x4_i_Slot_ae3_slot1_encode, Opcode_ae_l16x4_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l16x4_i_Slot_ae6_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_i_Slot_ae7_slot1_encode, Opcode_ae_l16x4_i_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_ip_encode_fns[] = { + Opcode_ae_l16x4_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_ip_Slot_ae2_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae2_slot0_encode, Opcode_ae_l16x4_ip_Slot_ae3_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_l16x4_ip_Slot_ae6_slot1_encode, 0, 0, 0, Opcode_ae_l16x4_ip_Slot_ae7_slot1_encode, Opcode_ae_l16x4_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae_slot1_encode, Opcode_ae_l16x4_x_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_x_Slot_ae2_slot1_encode, Opcode_ae_l16x4_x_Slot_ae2_slot0_encode, Opcode_ae_l16x4_x_Slot_ae3_slot1_encode, Opcode_ae_l16x4_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16x4_xp_encode_fns[] = { + Opcode_ae_l16x4_xp_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l16x4_xp_Slot_ae2_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae2_slot0_encode, Opcode_ae_l16x4_xp_Slot_ae3_slot1_encode, Opcode_ae_l16x4_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l16x4_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l64_xc_Slot_ae_slot1_encode, Opcode_ae_l64_xc_Slot_ae_slot0_encode, 0, Opcode_ae_l64_xc_Slot_ae2_slot1_encode, Opcode_ae_l64_xc_Slot_ae2_slot0_encode, Opcode_ae_l64_xc_Slot_ae3_slot1_encode, Opcode_ae_l64_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae_slot1_encode, Opcode_ae_l64_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_l64_xc1_Slot_ae2_slot1_encode, Opcode_ae_l64_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_i_encode_fns[] = { + Opcode_ae_l64_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l64_i_Slot_ae_slot1_encode, Opcode_ae_l64_i_Slot_ae_slot0_encode, 0, Opcode_ae_l64_i_Slot_ae2_slot1_encode, Opcode_ae_l64_i_Slot_ae2_slot0_encode, Opcode_ae_l64_i_Slot_ae3_slot1_encode, Opcode_ae_l64_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_ip_encode_fns[] = { + Opcode_ae_l64_ip_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae_slot1_encode, Opcode_ae_l64_ip_Slot_ae_slot0_encode, 0, Opcode_ae_l64_ip_Slot_ae2_slot1_encode, Opcode_ae_l64_ip_Slot_ae2_slot0_encode, Opcode_ae_l64_ip_Slot_ae3_slot1_encode, Opcode_ae_l64_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_l64_ip_Slot_ae7_slot1_encode, Opcode_ae_l64_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_x_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l64_x_Slot_ae_slot1_encode, Opcode_ae_l64_x_Slot_ae_slot0_encode, 0, Opcode_ae_l64_x_Slot_ae2_slot1_encode, Opcode_ae_l64_x_Slot_ae2_slot0_encode, Opcode_ae_l64_x_Slot_ae3_slot1_encode, Opcode_ae_l64_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l64_xp_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_l64_xp_Slot_ae_slot1_encode, Opcode_ae_l64_xp_Slot_ae_slot0_encode, 0, Opcode_ae_l64_xp_Slot_ae2_slot1_encode, Opcode_ae_l64_xp_Slot_ae2_slot0_encode, Opcode_ae_l64_xp_Slot_ae3_slot1_encode, Opcode_ae_l64_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_l64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_i_encode_fns[] = { + Opcode_ae_s16x2m_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_iu_encode_fns[] = { + Opcode_ae_s16x2m_iu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_x_encode_fns[] = { + Opcode_ae_s16x2m_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x2m_xu_encode_fns[] = { + Opcode_ae_s16x2m_xu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x2m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x2m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc_encode_fns[] = { + Opcode_ae_s32x2f24_xc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_i_encode_fns[] = { + Opcode_ae_s32x2f24_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_i_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ip_encode_fns[] = { + Opcode_ae_s32x2f24_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2f24_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_x_encode_fns[] = { + Opcode_ae_s32x2f24_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2f24_xp_encode_fns[] = { + Opcode_ae_s32x2f24_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2f24_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2f24_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc_encode_fns[] = { + Opcode_ae_s32x2_xc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_i_encode_fns[] = { + Opcode_ae_s32x2_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_i_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ip_encode_fns[] = { + Opcode_ae_s32x2_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_x_encode_fns[] = { + Opcode_ae_s32x2_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_x_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2_xp_encode_fns[] = { + Opcode_ae_s32x2_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2rng_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_i_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2rng_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2rng_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_x_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2rng_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2rng_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s32x2rng_xp_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_i_encode_fns[] = { + Opcode_ae_s16x4_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_i_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_ip_encode_fns[] = { + Opcode_ae_s16x4_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, Opcode_ae_s16x4_ip_Slot_ae6_slot0_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16x4_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16x4_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s16x4_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16x4_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_i_encode_fns[] = { + Opcode_ae_s16m_l_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_iu_encode_fns[] = { + Opcode_ae_s16m_l_iu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_x_encode_fns[] = { + Opcode_ae_s16m_l_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16m_l_xu_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae2_slot0_encode, 0, Opcode_ae_s16m_l_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16m_l_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_i_encode_fns[] = { + Opcode_ae_s32f24_l_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_ip_encode_fns[] = { + Opcode_ae_s32f24_l_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32f24_l_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32f24_l_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32f24_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_i_encode_fns[] = { + Opcode_ae_s32_l_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_ip_encode_fns[] = { + Opcode_ae_s32_l_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_x_encode_fns[] = { + Opcode_ae_s32_l_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32_l_xp_encode_fns[] = { + Opcode_ae_s32_l_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32_l_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32_l_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32_l_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_i_encode_fns[] = { + Opcode_ae_s16_0_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_ip_encode_fns[] = { + Opcode_ae_s16_0_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16_0_xp_encode_fns[] = { + Opcode_ae_s16_0_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s16_0_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s16_0_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s16_0_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_i_encode_fns[] = { + Opcode_ae_s64_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s64_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_ip_encode_fns[] = { + Opcode_ae_s64_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s64_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s64_xp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s64_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s64_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s64_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_i_encode_fns[] = { + Opcode_ae_s32m_i_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_iu_encode_fns[] = { + Opcode_ae_s32m_iu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_iu_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_iu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_iu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_x_encode_fns[] = { + Opcode_ae_s32m_x_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32m_xu_encode_fns[] = { + Opcode_ae_s32m_xu_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32m_xu_Slot_ae2_slot0_encode, 0, Opcode_ae_s32m_xu_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32m_xu_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_zalign64_encode_fns[] = { + Opcode_ae_zalign64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_zalign64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_zalign64_Slot_ae2_slot0_encode, 0, Opcode_ae_zalign64_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_zalign64_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lalign64_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_lalign64_i_Slot_ae2_slot0_encode, 0, Opcode_ae_lalign64_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_lalign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_salign64_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_salign64_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_salign64_i_Slot_ae2_slot0_encode, 0, Opcode_ae_salign64_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_salign64_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movalign_encode_fns[] = { + Opcode_ae_movalign_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movalign_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movalign_Slot_ae2_slot0_encode, 0, Opcode_ae_movalign_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movalign_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la64_pp_encode_fns[] = { + Opcode_ae_la64_pp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la64_pp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae2_slot0_encode, 0, Opcode_ae_la64_pp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la64_pp_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la64_pp_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24pos_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la24pos_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2pos_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc_encode_fns[] = { + Opcode_ae_la32x2pos_pc_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2pos_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4pos_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24neg_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la24neg_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2neg_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2neg_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4neg_pc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24pos_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2pos_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2pos_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4pos_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4pos_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24neg_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2neg_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2neg_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4neg_pc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4neg_pc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64pos_fp_encode_fns[] = { + Opcode_ae_sa64pos_fp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae2_slot0_encode, 0, Opcode_ae_sa64pos_fp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa64pos_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa64neg_fp_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae2_slot0_encode, 0, Opcode_ae_sa64neg_fp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa64neg_fp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic_encode_fns[] = { + Opcode_ae_la32x2_ic_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ic1_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ip_encode_fns[] = { + Opcode_ae_la32x2_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la32x2_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la32x2_rip_Slot_ae6_slot1_encode, 0, 0, 0, 0, Opcode_ae_la32x2_rip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic_encode_fns[] = { + Opcode_ae_la16x4_ic_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ic1_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ip_encode_fns[] = { + Opcode_ae_la16x4_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la16x4_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_rip_encode_fns[] = { + Opcode_ae_la16x4_rip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la16x4_rip_Slot_ae6_slot1_encode, 0, 0, 0, 0, Opcode_ae_la16x4_rip_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la16x4_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric_Slot_ae7_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ae_la16x4_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic_encode_fns[] = { + Opcode_ae_la32x2f24_ic_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2f24_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ip_encode_fns[] = { + Opcode_ae_la32x2f24_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2f24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, Opcode_ae_la32x2f24_rip_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la32x2f24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la32x2f24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la24_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic_encode_fns[] = { + Opcode_ae_la24x2_ic_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ip_encode_fns[] = { + Opcode_ae_la24x2_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_la24x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_la24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_la24x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_la24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ip_encode_fns[] = { + Opcode_ae_sa32x2_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa16x4_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ip_encode_fns[] = { + Opcode_ae_sa16x4_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa16x4_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa16x4_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa16x4_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa16x4_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa16x4_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa16x4_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2f24_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ip_encode_fns[] = { + Opcode_ae_sa32x2f24_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2f24_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2f24_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa32x2f24_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa32x2f24_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa32x2f24_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24_l_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24_l_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24_l_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24_l_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24_l_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24_l_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa24_l_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24x2_ic_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ic_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24x2_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_rip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24x2_rip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_rip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae2_slot0_encode, 0, Opcode_ae_sa24x2_ric_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_sa24x2_ric_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sa24x2_ric1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_sa24x2_ric1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addicirc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addicirc_Slot_ae_slot1_encode, Opcode_ae_addicirc_Slot_ae_slot0_encode, 0, Opcode_ae_addicirc_Slot_ae2_slot1_encode, Opcode_ae_addicirc_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc1_Slot_ae_slot1_encode, Opcode_ae_addcirc_xc1_Slot_ae_slot0_encode, 0, Opcode_ae_addcirc_xc1_Slot_ae2_slot1_encode, Opcode_ae_addcirc_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addcirc_xc_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addcirc_xc_Slot_ae_slot1_encode, Opcode_ae_addcirc_xc_Slot_ae_slot0_encode, 0, Opcode_ae_addcirc_xc_Slot_ae2_slot1_encode, Opcode_ae_addcirc_xc_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xp_encode_fns[] = { + Opcode_ae_s32ra64s_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s32ra64s_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32ra64s_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s32ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_i_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_i_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_ip_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_x_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_x_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_x_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xp_encode_fns[] = { + Opcode_ae_s24ra64s_xp_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_xp_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_xp_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae2_slot0_encode, 0, Opcode_ae_s24ra64s_xc_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24ra64s_xc1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_s24ra64s_xc1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s32x2ra64s_ip_encode_fns[] = { + Opcode_ae_s32x2ra64s_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s32x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s24x2ra64s_ip_encode_fns[] = { + Opcode_ae_s24x2ra64s_ip_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae_slot0_encode, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae2_slot0_encode, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_s24x2ra64s_ip_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot1_encode, Opcode_ae_addbrba32_Slot_ae_slot0_encode, 0, Opcode_ae_addbrba32_Slot_ae2_slot1_encode, Opcode_ae_addbrba32_Slot_ae2_slot0_encode, Opcode_ae_addbrba32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae6_slot1_encode, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_bitswap_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_bitswap_Slot_ae_slot1_encode, Opcode_ae_bitswap_Slot_ae_slot0_encode, 0, Opcode_ae_bitswap_Slot_ae2_slot1_encode, Opcode_ae_bitswap_Slot_ae2_slot0_encode, Opcode_ae_bitswap_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32js_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32js_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsub32s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsub32s_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addandsubrng32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_addandsubrng32_Slot_ae6_slot3_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addrng32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subrng32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subrng32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng3_encode_fns[] = { + 0, 0, 0, Opcode_ae_calcrng3_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng2_encode_fns[] = { + 0, 0, 0, Opcode_ae_calcrng2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_calcrng1_encode_fns[] = { + 0, 0, 0, Opcode_ae_calcrng1_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_rng32x2_encode_fns[] = { + 0, 0, 0, Opcode_ae_rng32x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_encode_fns[] = { + Opcode_ae_sel16i_Slot_inst_encode, 0, 0, Opcode_ae_sel16i_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sel16i_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sel16i_Slot_ae2_slot0_encode, Opcode_ae_sel16i_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sel16i_n_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sel16i_n_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_shortswap_encode_fns[] = { + 0, 0, 0, Opcode_ae_shortswap_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab4_encode_fns[] = { + Opcode_ae_movab4_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movab4_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movab4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab2_encode_fns[] = { + Opcode_ae_movab2_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movab2_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movab2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movab_encode_fns[] = { + Opcode_ae_movab_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movab_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movab_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba_encode_fns[] = { + Opcode_ae_movba_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movba_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movba_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba1x2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_movba1x2_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movba1x2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba4_encode_fns[] = { + Opcode_ae_movba4_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movba4_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movba4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movba2_encode_fns[] = { + Opcode_ae_movba2_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movba2_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_movba2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb2_encode_fns[] = { + Opcode_ae_movb2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb2_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movb4_encode_fns[] = { + Opcode_ae_movb4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movb4_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movt16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movt16x4_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movt16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf16x4_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movf16x4_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movf16x4_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt32x2_encode_fns[] = { + Opcode_ae_movt32x2_Slot_inst_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movt32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf32x2_encode_fns[] = { + Opcode_ae_movf32x2_Slot_inst_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movf32x2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsara7x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_movsara7x2_Slot_ae_slot1_encode, Opcode_ae_movsara7x2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movsard7_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_movsard7_Slot_ae_slot0_encode, 0, Opcode_ae_movsard7_Slot_ae2_slot1_encode, Opcode_ae_movsard7_Slot_ae2_slot0_encode, 0, Opcode_ae_movsard7_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movsard7_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movasar_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_movasar_Slot_ae_slot0_encode, 0, Opcode_ae_movasar_Slot_ae2_slot1_encode, Opcode_ae_movasar_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32x2_encode_fns[] = { + Opcode_ae_movda32x2_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_movda32x2_Slot_ae_slot1_encode, Opcode_ae_movda32x2_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda32_encode_fns[] = { + Opcode_ae_movda32_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_movda32_Slot_ae_slot1_encode, Opcode_ae_movda32_Slot_ae_slot0_encode, 0, Opcode_ae_movda32_Slot_ae2_slot1_encode, Opcode_ae_movda32_Slot_ae2_slot0_encode, Opcode_ae_movda32_Slot_ae3_slot1_encode, Opcode_ae_movda32_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movda32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16x2_encode_fns[] = { + Opcode_ae_movda16x2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movda16_encode_fns[] = { + Opcode_ae_movda16_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_movda16_Slot_ae_slot1_encode, Opcode_ae_movda16_Slot_ae_slot0_encode, 0, Opcode_ae_movda16_Slot_ae2_slot1_encode, Opcode_ae_movda16_Slot_ae2_slot0_encode, Opcode_ae_movda16_Slot_ae3_slot1_encode, Opcode_ae_movda16_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movda16_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movi_encode_fns[] = { + Opcode_ae_movi_Slot_inst_encode, 0, 0, Opcode_ae_movi_Slot_ae_slot3_encode, Opcode_ae_movi_Slot_ae_slot2_encode, Opcode_ae_movi_Slot_ae_slot1_encode, Opcode_ae_movi_Slot_ae_slot0_encode, 0, Opcode_ae_movi_Slot_ae2_slot1_encode, Opcode_ae_movi_Slot_ae2_slot0_encode, Opcode_ae_movi_Slot_ae3_slot1_encode, Opcode_ae_movi_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movi_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot1_encode, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode, 0, Opcode_ae_truncp24a32x2_Slot_ae2_slot1_encode, Opcode_ae_truncp24a32x2_Slot_ae2_slot0_encode, Opcode_ae_truncp24a32x2_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat16x4_encode_fns[] = { + 0, 0, 0, Opcode_ae_sat16x4_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_32_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt32x2f16_32_Slot_ae_slot0_encode, 0, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot1_encode, Opcode_ae_cvt32x2f16_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt32x2f16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt32x2f16_10_Slot_ae_slot0_encode, 0, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot1_encode, Opcode_ae_cvt32x2f16_10_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_32_encode_fns[] = { + Opcode_ae_sext32x2d16_32_Slot_inst_encode, 0, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sext32x2d16_32_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_32_Slot_ae2_slot1_encode, Opcode_ae_sext32x2d16_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32x2d16_10_encode_fns[] = { + 0, 0, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sext32x2d16_10_Slot_ae_slot0_encode, 0, Opcode_ae_sext32x2d16_10_Slot_ae2_slot1_encode, Opcode_ae_sext32x2d16_10_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_cvta32f24s_l_Slot_ae_slot0_encode, 0, Opcode_ae_cvta32f24s_l_Slot_ae2_slot1_encode, Opcode_ae_cvta32f24s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvta32f24s_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_cvta32f24s_h_Slot_ae_slot0_encode, 0, Opcode_ae_cvta32f24s_h_Slot_ae2_slot1_encode, Opcode_ae_cvta32f24s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { + Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { + Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { + Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { + Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { + Opcode_ae_truncp24q48x2_Slot_inst_encode, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32x2f64s_encode_fns[] = { + Opcode_ae_trunca32x2f64s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_trunca32x2f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32x2f64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32x2f64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32f64s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_trunca32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunci32f64s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_trunci32f64s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { + Opcode_ae_truncp16_Slot_inst_encode, 0, 0, Opcode_ae_truncp16_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f64ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f64sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot3_encode, 0, 0, Opcode_ae_round32x2f64sasym_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f48ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round32x2f48sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round32x2f48sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round16x4f32ssym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round16x4f32sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round16x4f32sasym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48ssym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot3_encode, 0, 0, Opcode_ae_round24x2f48ssym_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_round24x2f48sasym_encode_fns[] = { + 0, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot3_encode, 0, 0, Opcode_ae_round24x2f48sasym_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16q48x2sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48x2asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16q48x2asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxabs32s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16f24sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsp16f24asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsp16f24asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mov_encode_fns[] = { + Opcode_ae_mov_Slot_inst_encode, 0, 0, Opcode_ae_mov_Slot_ae_slot3_encode, Opcode_ae_mov_Slot_ae_slot2_encode, 0, Opcode_ae_mov_Slot_ae_slot0_encode, 0, Opcode_ae_mov_Slot_ae2_slot1_encode, Opcode_ae_mov_Slot_ae2_slot0_encode, Opcode_ae_mov_Slot_ae3_slot1_encode, Opcode_ae_mov_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_mov_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movt64_encode_fns[] = { + Opcode_ae_movt64_Slot_inst_encode, 0, 0, Opcode_ae_movt64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movt64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movt64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movf64_encode_fns[] = { + 0, 0, 0, Opcode_ae_movf64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_movf64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_movf64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56a32s_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_cvtq56a32s_Slot_ae_slot1_encode, Opcode_ae_cvtq56a32s_Slot_ae_slot0_encode, 0, Opcode_ae_cvtq56a32s_Slot_ae2_slot1_encode, Opcode_ae_cvtq56a32s_Slot_ae2_slot0_encode, Opcode_ae_cvtq56a32s_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48a32_encode_fns[] = { + Opcode_ae_cvt48a32_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_cvt48a32_Slot_ae_slot1_encode, Opcode_ae_cvt48a32_Slot_ae_slot0_encode, 0, Opcode_ae_cvt48a32_Slot_ae2_slot1_encode, Opcode_ae_cvt48a32_Slot_ae2_slot0_encode, Opcode_ae_cvt48a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64a32_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_ae_cvt64a32_Slot_ae_slot1_encode, Opcode_ae_cvt64a32_Slot_ae_slot0_encode, 0, Opcode_ae_cvt64a32_Slot_ae2_slot1_encode, Opcode_ae_cvt64a32_Slot_ae2_slot0_encode, Opcode_ae_cvt64a32_Slot_ae3_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_l_encode_fns[] = { + Opcode_ae_cvtq56p32s_l_Slot_inst_encode, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvtq56p32s_l_Slot_ae_slot0_encode, 0, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot1_encode, Opcode_ae_cvtq56p32s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvtq56p32s_h_encode_fns[] = { + Opcode_ae_cvtq56p32s_h_Slot_inst_encode, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvtq56p32s_h_Slot_ae_slot0_encode, 0, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot1_encode, Opcode_ae_cvtq56p32s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt64f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt64f32_h_Slot_ae_slot0_encode, 0, Opcode_ae_cvt64f32_h_Slot_ae2_slot1_encode, Opcode_ae_cvt64f32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_l_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt48f32_l_Slot_ae_slot0_encode, 0, Opcode_ae_cvt48f32_l_Slot_ae2_slot1_encode, Opcode_ae_cvt48f32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_cvt48f32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_cvt48f32_h_Slot_ae_slot0_encode, 0, Opcode_ae_cvt48f32_h_Slot_ae2_slot1_encode, Opcode_ae_cvt48f32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat48s_encode_fns[] = { + Opcode_ae_sat48s_Slot_inst_encode, 0, 0, Opcode_ae_sat48s_Slot_ae_slot3_encode, Opcode_ae_sat48s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_satq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_satq56s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sat24s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { + Opcode_ae_truncq32_Slot_inst_encode, 0, 0, Opcode_ae_truncq32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_truncq32_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_minabs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_minabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_maxabs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_maxabs64s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48sym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsq32f48sym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_roundsq32f48asym_encode_fns[] = { + 0, 0, 0, Opcode_ae_roundsq32f48asym_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { + Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode, 0, Opcode_ae_trunca32q48_Slot_ae2_slot1_encode, Opcode_ae_trunca32q48_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_l_encode_fns[] = { + Opcode_ae_movad32_l_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae_slot0_encode, 0, Opcode_ae_movad32_l_Slot_ae2_slot1_encode, Opcode_ae_movad32_l_Slot_ae2_slot0_encode, 0, Opcode_ae_movad32_l_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad32_l_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad32_h_encode_fns[] = { + Opcode_ae_movad32_h_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad32_h_Slot_ae_slot0_encode, 0, Opcode_ae_movad32_h_Slot_ae2_slot1_encode, Opcode_ae_movad32_h_Slot_ae2_slot0_encode, 0, Opcode_ae_movad32_h_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad32_h_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_3_encode_fns[] = { + Opcode_ae_movad16_3_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad16_3_Slot_ae_slot0_encode, 0, Opcode_ae_movad16_3_Slot_ae2_slot1_encode, Opcode_ae_movad16_3_Slot_ae2_slot0_encode, 0, Opcode_ae_movad16_3_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad16_3_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_2_encode_fns[] = { + Opcode_ae_movad16_2_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad16_2_Slot_ae_slot0_encode, 0, Opcode_ae_movad16_2_Slot_ae2_slot1_encode, Opcode_ae_movad16_2_Slot_ae2_slot0_encode, 0, Opcode_ae_movad16_2_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad16_2_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_movad16_1_Slot_ae_slot0_encode, 0, Opcode_ae_movad16_1_Slot_ae2_slot1_encode, Opcode_ae_movad16_1_Slot_ae2_slot0_encode, 0, Opcode_ae_movad16_1_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad16_1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movad16_0_encode_fns[] = { + Opcode_ae_movad16_0_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae_slot0_encode, 0, Opcode_ae_movad16_0_Slot_ae2_slot1_encode, Opcode_ae_movad16_0_Slot_ae2_slot0_encode, 0, Opcode_ae_movad16_0_Slot_ae3_slot0_encode, 0, 0, 0, 0, Opcode_ae_movad16_0_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sra64_32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sra64_32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sra64_32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr32_encode_fns[] = { + Opcode_ae_pksr32_Slot_inst_encode, 0, 0, 0, Opcode_ae_pksr32_Slot_ae_slot2_encode, 0, Opcode_ae_pksr32_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksr24_encode_fns[] = { + Opcode_ae_pksr24_Slot_inst_encode, 0, 0, 0, Opcode_ae_pksr24_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_pksrf32_encode_fns[] = { + Opcode_ae_pksrf32_Slot_inst_encode, 0, 0, 0, Opcode_ae_pksrf32_Slot_ae_slot2_encode, 0, Opcode_ae_pksrf32_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { + Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { + Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_encode_fns[] = { + Opcode_ae_add32_Slot_inst_encode, 0, 0, Opcode_ae_add32_Slot_ae_slot3_encode, Opcode_ae_add32_Slot_ae_slot2_encode, 0, Opcode_ae_add32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_add32_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32_encode_fns[] = { + Opcode_ae_sub32_Slot_inst_encode, 0, 0, Opcode_ae_sub32_Slot_ae_slot3_encode, Opcode_ae_sub32_Slot_ae_slot2_encode, 0, Opcode_ae_sub32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32_Slot_ae_slot3_encode, Opcode_ae_addsub32_Slot_ae_slot2_encode, 0, Opcode_ae_addsub32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addsub32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32_Slot_ae_slot3_encode, Opcode_ae_subadd32_Slot_ae_slot2_encode, 0, Opcode_ae_subadd32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subadd32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16_encode_fns[] = { + 0, 0, 0, Opcode_ae_add16_Slot_ae_slot3_encode, Opcode_ae_add16_Slot_ae_slot2_encode, 0, Opcode_ae_add16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub16_Slot_ae_slot3_encode, Opcode_ae_sub16_Slot_ae_slot2_encode, 0, Opcode_ae_sub16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32_hl_lh_Slot_ae_slot2_encode, 0, Opcode_ae_add32_hl_lh_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add32_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg32_Slot_ae_slot3_encode, Opcode_ae_neg32_Slot_ae_slot2_encode, 0, Opcode_ae_neg32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs32_Slot_ae_slot3_encode, Opcode_ae_abs32_Slot_ae_slot2_encode, 0, Opcode_ae_abs32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add24s_encode_fns[] = { + Opcode_ae_add24s_Slot_inst_encode, 0, 0, Opcode_ae_add24s_Slot_ae_slot3_encode, Opcode_ae_add24s_Slot_ae_slot2_encode, 0, Opcode_ae_add24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub24s_Slot_ae_slot3_encode, Opcode_ae_sub24s_Slot_ae_slot2_encode, 0, Opcode_ae_sub24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_encode_fns[] = { + Opcode_ae_add32s_Slot_inst_encode, 0, 0, Opcode_ae_add32s_Slot_ae_slot3_encode, Opcode_ae_add32s_Slot_ae_slot2_encode, 0, Opcode_ae_add32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_add32s_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub32s_encode_fns[] = { + Opcode_ae_sub32s_Slot_inst_encode, 0, 0, Opcode_ae_sub32s_Slot_ae_slot3_encode, Opcode_ae_sub32s_Slot_ae_slot2_encode, 0, Opcode_ae_sub32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsub32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsub32s_Slot_ae_slot3_encode, Opcode_ae_addsub32s_Slot_ae_slot2_encode, 0, Opcode_ae_addsub32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addsub32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subadd32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subadd32s_Slot_ae_slot3_encode, Opcode_ae_subadd32s_Slot_ae_slot2_encode, 0, Opcode_ae_subadd32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subadd32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add16s_encode_fns[] = { + Opcode_ae_add16s_Slot_inst_encode, 0, 0, Opcode_ae_add16s_Slot_ae_slot3_encode, Opcode_ae_add16s_Slot_ae_slot2_encode, 0, Opcode_ae_add16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub16s_encode_fns[] = { + Opcode_ae_sub16s_Slot_inst_encode, 0, 0, Opcode_ae_sub16s_Slot_ae_slot3_encode, Opcode_ae_sub16s_Slot_ae_slot2_encode, 0, Opcode_ae_sub16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add32s_hl_lh_encode_fns[] = { + 0, 0, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot3_encode, Opcode_ae_add32s_hl_lh_Slot_ae_slot2_encode, 0, Opcode_ae_add32s_hl_lh_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add32s_hl_lh_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg24s_Slot_ae_slot3_encode, Opcode_ae_neg24s_Slot_ae_slot2_encode, 0, Opcode_ae_neg24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs24s_encode_fns[] = { + Opcode_ae_abs24s_Slot_inst_encode, 0, 0, Opcode_ae_abs24s_Slot_ae_slot3_encode, Opcode_ae_abs24s_Slot_ae_slot2_encode, 0, Opcode_ae_abs24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg32s_encode_fns[] = { + Opcode_ae_neg32s_Slot_inst_encode, 0, 0, Opcode_ae_neg32s_Slot_ae_slot3_encode, Opcode_ae_neg32s_Slot_ae_slot2_encode, 0, Opcode_ae_neg32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs32s_encode_fns[] = { + Opcode_ae_abs32s_Slot_inst_encode, 0, 0, Opcode_ae_abs32s_Slot_ae_slot3_encode, Opcode_ae_abs32s_Slot_ae_slot2_encode, 0, Opcode_ae_abs32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg16s_encode_fns[] = { + Opcode_ae_neg16s_Slot_inst_encode, 0, 0, Opcode_ae_neg16s_Slot_ae_slot3_encode, Opcode_ae_neg16s_Slot_ae_slot2_encode, 0, Opcode_ae_neg16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs16s_encode_fns[] = { + Opcode_ae_abs16s_Slot_inst_encode, 0, 0, Opcode_ae_abs16s_Slot_ae_slot3_encode, Opcode_ae_abs16s_Slot_ae_slot2_encode, 0, Opcode_ae_abs16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_lt16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_lt16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_le16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_le16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_eq16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_eq16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt32_encode_fns[] = { + Opcode_ae_lt32_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_lt32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_lt32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_le32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_le32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq32_encode_fns[] = { + Opcode_ae_eq32_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_eq32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_eq32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min32_encode_fns[] = { + Opcode_ae_min32_Slot_inst_encode, 0, 0, Opcode_ae_min32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_min32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_min32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max32_encode_fns[] = { + Opcode_ae_max32_Slot_inst_encode, 0, 0, Opcode_ae_max32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_max32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_max32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64_encode_fns[] = { + Opcode_ae_add64_Slot_inst_encode, 0, 0, Opcode_ae_add64_Slot_ae_slot3_encode, Opcode_ae_add64_Slot_ae_slot2_encode, 0, Opcode_ae_add64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64_encode_fns[] = { + Opcode_ae_sub64_Slot_inst_encode, 0, 0, Opcode_ae_sub64_Slot_ae_slot3_encode, Opcode_ae_sub64_Slot_ae_slot2_encode, 0, Opcode_ae_sub64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64_encode_fns[] = { + Opcode_ae_neg64_Slot_inst_encode, 0, 0, Opcode_ae_neg64_Slot_ae_slot3_encode, Opcode_ae_neg64_Slot_ae_slot2_encode, 0, Opcode_ae_neg64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64_encode_fns[] = { + Opcode_ae_abs64_Slot_inst_encode, 0, 0, Opcode_ae_abs64_Slot_ae_slot3_encode, Opcode_ae_abs64_Slot_ae_slot2_encode, 0, Opcode_ae_abs64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot3_encode, Opcode_ae_addsq56s_Slot_ae_slot2_encode, 0, Opcode_ae_addsq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_addsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot3_encode, Opcode_ae_subsq56s_Slot_ae_slot2_encode, 0, Opcode_ae_subsq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_subsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_add64s_Slot_ae_slot3_encode, Opcode_ae_add64s_Slot_ae_slot2_encode, 0, Opcode_ae_add64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_add64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sub64s_Slot_ae_slot3_encode, Opcode_ae_sub64s_Slot_ae_slot2_encode, 0, Opcode_ae_sub64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sub64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot3_encode, Opcode_ae_negsq56s_Slot_ae_slot2_encode, 0, Opcode_ae_negsq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_negsq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot3_encode, Opcode_ae_abssq56s_Slot_ae_slot2_encode, 0, Opcode_ae_abssq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abssq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_neg64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_neg64s_Slot_ae_slot3_encode, Opcode_ae_neg64s_Slot_ae_slot2_encode, 0, Opcode_ae_neg64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_neg64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_abs64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_abs64s_Slot_ae_slot3_encode, Opcode_ae_abs64s_Slot_ae_slot2_encode, 0, Opcode_ae_abs64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_abs64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_and_encode_fns[] = { + Opcode_ae_and_Slot_inst_encode, 0, 0, Opcode_ae_and_Slot_ae_slot3_encode, 0, 0, Opcode_ae_and_Slot_ae_slot0_encode, 0, 0, Opcode_ae_and_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nand_encode_fns[] = { + 0, 0, 0, Opcode_ae_nand_Slot_ae_slot3_encode, 0, 0, Opcode_ae_nand_Slot_ae_slot0_encode, 0, 0, Opcode_ae_nand_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_or_encode_fns[] = { + Opcode_ae_or_Slot_inst_encode, 0, 0, Opcode_ae_or_Slot_ae_slot3_encode, 0, 0, Opcode_ae_or_Slot_ae_slot0_encode, 0, 0, Opcode_ae_or_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_xor_encode_fns[] = { + Opcode_ae_xor_Slot_inst_encode, 0, 0, Opcode_ae_xor_Slot_ae_slot3_encode, 0, 0, Opcode_ae_xor_Slot_ae_slot0_encode, 0, 0, Opcode_ae_xor_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24_encode_fns[] = { + Opcode_ae_slai24_Slot_inst_encode, 0, 0, Opcode_ae_slai24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srli24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai24_encode_fns[] = { + Opcode_ae_srai24_Slot_inst_encode, 0, 0, Opcode_ae_srai24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24_encode_fns[] = { + Opcode_ae_slas24_Slot_inst_encode, 0, 0, Opcode_ae_slas24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls24_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srls24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras24_encode_fns[] = { + Opcode_ae_sras24_Slot_inst_encode, 0, 0, Opcode_ae_sras24_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sras24_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras24_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai16_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai16r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai16r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai16r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai16r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32_encode_fns[] = { + Opcode_ae_slai32_Slot_inst_encode, 0, 0, Opcode_ae_slai32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli32_encode_fns[] = { + Opcode_ae_srli32_Slot_inst_encode, 0, 0, Opcode_ae_srli32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srli32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32_encode_fns[] = { + Opcode_ae_srai32_Slot_inst_encode, 0, 0, Opcode_ae_srai32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai32r_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai32r_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai32r_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai32r_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls32_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srls32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras32_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras32_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sras32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32_encode_fns[] = { + Opcode_ae_slaa32_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaa32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_srla32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srla32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32_encode_fns[] = { + Opcode_ae_sraa32_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sraa32_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa32_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai16s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai16s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa16s_encode_fns[] = { + Opcode_ae_slaa16s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaa16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sraa16s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa16s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa16rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sraa16rs_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa16rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai24s_encode_fns[] = { + Opcode_ae_slai24s_Slot_inst_encode, 0, 0, Opcode_ae_slai24s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas24s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas24s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas24s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas24s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai32s_encode_fns[] = { + Opcode_ae_slai32s_Slot_inst_encode, 0, 0, Opcode_ae_slai32s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas32s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas32s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa32s_encode_fns[] = { + Opcode_ae_slaa32s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaa32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32s_encode_fns[] = { + Opcode_ae_sraa32s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sraa32s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa32s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa32rs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_sraa32rs_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa32rs_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slasq56_encode_fns[] = { + Opcode_ae_slasq56_Slot_inst_encode, 0, 0, Opcode_ae_slasq56_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { + 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srlsq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { + Opcode_ae_srasq56_Slot_inst_encode, 0, 0, Opcode_ae_srasq56_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srasq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaaq56_encode_fns[] = { + Opcode_ae_slaaq56_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaaq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { + Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srlaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { + Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraaq56_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64_encode_fns[] = { + Opcode_ae_slai64_Slot_inst_encode, 0, 0, Opcode_ae_slai64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srli64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srli64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srli64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srli64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai64_encode_fns[] = { + Opcode_ae_srai64_Slot_inst_encode, 0, 0, Opcode_ae_srai64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srai64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srai64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64_encode_fns[] = { + 0, 0, 0, Opcode_ae_slas64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srls64_encode_fns[] = { + 0, 0, 0, Opcode_ae_srls64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_srls64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srls64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sras64_encode_fns[] = { + 0, 0, 0, Opcode_ae_sras64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_sras64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sras64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64_encode_fns[] = { + Opcode_ae_slaa64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaa64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srla64_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_srla64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_srla64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sraa64_encode_fns[] = { + Opcode_ae_sraa64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_sraa64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_sraa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaisq56s_encode_fns[] = { + Opcode_ae_slaisq56s_Slot_inst_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaisq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slassq56s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slassq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slassq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { + Opcode_ae_slaasq56s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaasq56s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai64s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slai64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slai64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slas64s_encode_fns[] = { + Opcode_ae_slas64s_Slot_inst_encode, 0, 0, Opcode_ae_slas64s_Slot_ae_slot3_encode, 0, 0, Opcode_ae_slas64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slas64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slaa64s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_slaa64s_Slot_ae_slot0_encode, 0, 0, Opcode_ae_slaa64s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lt64_encode_fns[] = { + Opcode_ae_lt64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_lt64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_lt64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_le64_encode_fns[] = { + Opcode_ae_le64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_le64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_le64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_eq64_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ae_eq64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_eq64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_max64_encode_fns[] = { + 0, 0, 0, Opcode_ae_max64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_max64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_max64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_min64_encode_fns[] = { + 0, 0, 0, Opcode_ae_min64_Slot_ae_slot3_encode, 0, 0, Opcode_ae_min64_Slot_ae_slot0_encode, 0, 0, Opcode_ae_min64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsa64_encode_fns[] = { + Opcode_ae_nsa64_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_nsa64_Slot_ae_slot0_encode, 0, Opcode_ae_nsa64_Slot_ae2_slot1_encode, Opcode_ae_nsa64_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz16_0_encode_fns[] = { + Opcode_ae_nsaz16_0_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_nsaz16_0_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_nsaz32_l_encode_fns[] = { + Opcode_ae_nsaz32_l_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_nsaz32_l_Slot_ae_slot0_encode, 0, Opcode_ae_nsaz32_l_Slot_ae2_slot1_encode, Opcode_ae_nsaz32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32f48p16s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32ra_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32r_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32f48p16s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32ra_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32r_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32f48p16s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32f48p16s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32ra_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32ra_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32r_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32r_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas32f48p16s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32ra_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32r_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas32f48p16s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32ra_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32r_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulas32f48p16s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulas32f48p16s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32ra_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32ra_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32r_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32r_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss32f48p16s_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32ra_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32ra_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32r_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss32f48p16s_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32ra_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32ra_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32r_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32s_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulss32f48p16s_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulss32f48p16s_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32r_hh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32ra_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32ra_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32ra_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32r_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32r_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32u_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32u_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32u_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32u_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32u_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_33_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_33_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_33_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_33_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_22_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_32_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_32_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_32_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_21_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_21_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_21_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_21_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_31_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_31_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_31_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_31_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_30_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_30_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_30_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_30_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_10_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_10_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_10_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_10_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_20_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_20_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_20_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_20_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_11_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_11_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_11_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_11_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16ss_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf16ss_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_33_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_33_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_33_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_33_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_22_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_32_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_32_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_32_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_21_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_21_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_21_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_21_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_31_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_31_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_31_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_31_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_30_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_30_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_30_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_30_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_10_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_10_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_10_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_10_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_20_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_20_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_20_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_20_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_11_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_11_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_11_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_11_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16ss_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf16ss_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_33_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_33_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_33_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_33_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_22_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_32_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_32_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_32_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_21_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_21_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_21_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_21_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_31_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_31_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_31_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_31_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_30_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_30_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_30_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_30_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_10_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_10_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_10_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_10_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_20_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_20_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_20_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_20_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_11_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_11_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_11_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_11_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf16ss_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16ss_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf16ss_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_33_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd16ss_33_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_13_02_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd16ss_13_02_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd16ss_11_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd16ss_11_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_33_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd16ss_33_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_13_02_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd16ss_13_02_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd16ss_11_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd16ss_11_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_33_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd16ss_33_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_13_02_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd16ss_13_02_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd16ss_11_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd16ss_11_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_33_22_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_33_22_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd16ss_33_22_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_13_02_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_13_02_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd16ss_13_02_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_11_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd16ss_11_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd16ss_11_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf48q32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf48q32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf48q32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulq32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf48q32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf48q32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf48q32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaq32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf48q32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf48q32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf48q32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsq32sp16u_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2r_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2ra_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24x2ra_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp24x2r_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp24x2r_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2r_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2ra_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24x2ra_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp24x2r_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp24x2r_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2r_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp24x2r_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2ra_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24x2ra_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24x2r_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp24x2r_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasd32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasd32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsad32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasd32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasd32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsad32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsad32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hh_ll_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32s_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32ra_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssd32_hl_lh_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32s_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32s_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32ra_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32ra_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulf32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaf32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_h0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_h1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_h2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_muls32x16_h3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsf32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32x16_h3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32x16_h3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasfd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasfd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulasd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulasd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsad32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsad32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsad32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsafd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsafd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsad32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsad32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssfd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssfd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasfd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasfd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzasd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzasd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsad32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzsad32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsafd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsafd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzsad32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzsad32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h3_l2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h3_l2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32x16_h3_l2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h1_l0_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssfd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssfd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32x16_h1_l0_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32x16_h1_l0_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h2_l3_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h0_l1_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h2_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32x16_h2_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaafd32x16_h0_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaafd32x16_h0_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h2_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32x16_h2_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaafd32x16_h0_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaafd32x16_h0_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h2_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32x16_h2_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32x16_h0_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32x16_h0_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h2_l3_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32x16_h2_l3_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32x16_h0_l1_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32x16_h0_l1_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2s_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp32x16x2_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2rs_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2ras_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x16x2_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp32x16x2_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2rs_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2rs_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x16x2ras_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x16x2ras_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2s_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap32x16x2_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2rs_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2ras_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulap32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x16x2_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap32x16x2_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2rs_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2rs_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x16x2ras_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x16x2ras_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2s_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp32x16x2_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_h_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_h_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsp32x16x2_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2s_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2s_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x16x2_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp32x16x2_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2rs_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2rs_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x16x2ras_l_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x16x2ras_l_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulp32x2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulp32x2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2rs_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x2rs_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp32x2ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulfp32x2ras_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulap32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulap32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2rs_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulap32x2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulap32x2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2rs_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x2rs_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafp32x2ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulafp32x2ras_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsp32x2_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsp32x2_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2rs_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2rs_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsfp32x2ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsp32x2_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsp32x2_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2rs_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x2rs_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsfp32x2ras_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulsfp32x2ras_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4s_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp16x4s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfp16x4ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfp16x4ras_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulc32_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc24ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae5_slot2_encode, 0, 0, 0, Opcode_ae_mulfc32ras_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, 0, Opcode_ae_mulfc32x16ras_l_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulc32x16_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulc32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, 0, Opcode_ae_mulfc32x16ras_h_Slot_ae6_slot2_encode, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulac32_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc24ra_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafc24ra_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc24ra_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32ras_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafc32ras_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32ras_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_l_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_l_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulac32x16_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulac32x16_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafc32x16ras_h_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafc32x16ras_h_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulf16x4ss_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaf16x4ss_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulsf16x4ss_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulsf16x4ss_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mula16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls16x4_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_muls16x4_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2s_fir_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x2ra_fir_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulfd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulfd32x16x2_fir_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_h_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2s_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2s_fir_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x2ra_fir_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x2ra_fir_l_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_hl_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_hl_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_lh_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_lh_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulafd32x16x2_fir_ll_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulafd32x16x2_fir_ll_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_Slot_ae7_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaafq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_Slot_ae7_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaafq32x16_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaafq32x16_s2_Slot_ae7_slot3_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaafq32x16_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaafq32x16_s2_Slot_ae7_slot3_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_Slot_ae7_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq32x16_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_Slot_ae7_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq32x16_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq32x16_s2_Slot_ae7_slot3_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq32x16_s2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq32x16_s2_Slot_ae7_slot3_encode, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mul16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mul16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16_00_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mula16_00_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mula16_00_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul16_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul16_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula16_00_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula16_00_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulzaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq16_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae_slot2_encode, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_ae_mulaaaaq16_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaaaaq16_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaaaaq16_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaaaaq16_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaaaaq16_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_h_encode_fns[] = { + 0, 0, 0, Opcode_ae_div64d32_h_Slot_ae_slot3_encode, 0, 0, Opcode_ae_div64d32_h_Slot_ae_slot0_encode, 0, 0, Opcode_ae_div64d32_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_div64d32_l_encode_fns[] = { + Opcode_ae_div64d32_l_Slot_inst_encode, 0, 0, Opcode_ae_div64d32_l_Slot_ae_slot3_encode, 0, 0, Opcode_ae_div64d32_l_Slot_ae_slot0_encode, 0, 0, Opcode_ae_div64d32_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { + Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { + Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { + Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16t_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { + Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ip_encode_fns[] = { + Opcode_ae_vldl16c_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic_encode_fns[] = { + Opcode_ae_vldl16c_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldl16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { + Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vldsht_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { + Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_lb_Slot_ae_slot1_encode, Opcode_ae_lb_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lb_Slot_ae3_slot1_encode, Opcode_ae_lb_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { + Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0, Opcode_ae_lbi_Slot_ae_slot1_encode, Opcode_ae_lbi_Slot_ae_slot0_encode, 0, 0, 0, Opcode_ae_lbi_Slot_ae3_slot1_encode, Opcode_ae_lbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { + Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_lbk_Slot_ae3_slot1_encode, Opcode_ae_lbk_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { + Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbs_encode_fns[] = { + Opcode_ae_lbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_lbsi_encode_fns[] = { + Opcode_ae_lbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { + Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_db_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_db_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { + Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ae_dbi_Slot_ae_slot0_encode, 0, 0, 0, 0, Opcode_ae_dbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic_encode_fns[] = { + Opcode_ae_db_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic_encode_fns[] = { + Opcode_ae_dbi_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ic1_encode_fns[] = { + Opcode_ae_db_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ic1_encode_fns[] = { + Opcode_ae_dbi_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_db_ip_encode_fns[] = { + Opcode_ae_db_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_dbi_ip_encode_fns[] = { + Opcode_ae_dbi_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { + Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { + Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { + Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sb_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { + Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_sbi_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { + Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { + Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic_encode_fns[] = { + Opcode_ae_sb_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic_encode_fns[] = { + Opcode_ae_sbi_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic_encode_fns[] = { + Opcode_ae_vles16c_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic_encode_fns[] = { + Opcode_ae_sbf_ic_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ic1_encode_fns[] = { + Opcode_ae_sb_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ic1_encode_fns[] = { + Opcode_ae_sbi_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ic1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_vles16c_ic1_Slot_ae5_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ic1_encode_fns[] = { + Opcode_ae_sbf_ic1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sb_ip_encode_fns[] = { + Opcode_ae_sb_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbi_ip_encode_fns[] = { + Opcode_ae_sbi_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_vles16c_ip_encode_fns[] = { + Opcode_ae_vles16c_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sbf_ip_encode_fns[] = { + Opcode_ae_sbf_ip_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext32_encode_fns[] = { + Opcode_ae_sext32_Slot_inst_encode, 0, 0, Opcode_ae_sext32_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movae_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movae_Slot_ae3_slot1_encode, Opcode_ae_movae_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movea_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ae_movea_Slot_ae3_slot1_encode, Opcode_ae_movea_Slot_ae3_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_moveep_encode_fns[] = { + 0, 0, 0, Opcode_ae_moveep_Slot_ae_slot3_encode, Opcode_ae_moveep_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sext72_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sext72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_add72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sub72_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_add72x64_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_add72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sub72x64_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_sub72x64_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32ep_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32ep_hh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32ep_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mul32ep_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32ep_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32ep_hh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32ep_hh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_muls32ep_hh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32ep_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mula32ep_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_muls32ep_hh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_muls32ep_hh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32ep_hh_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzssd32ep_hh_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32ep_hh_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32ep_hh_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulssd32ep_hh_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32ep_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32ep_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzssd32ep_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzssd32ep_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32ep_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32ep_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulssd32ep_hh_ll_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulssd32ep_hh_ll_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulaad32usep_hl_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulaad32usep_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulaad32usep_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32usep_hl_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mulzaad32usep_hl_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mulzaad32usep_hl_lh_s2_encode_fns[] = { + 0, 0, 0, Opcode_ae_mulzaad32usep_hl_lh_s2_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_lh_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32usep_lh_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mul32usep_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mul32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_mula32usep_ll_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_mula32usep_ll_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_srai72_encode_fns[] = { + 0, 0, 0, Opcode_ae_srai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_slai72_encode_fns[] = { + 0, 0, 0, Opcode_ae_slai72_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_sat64s_encode_fns[] = { + 0, 0, 0, Opcode_ae_sat64s_Slot_ae_slot3_encode, Opcode_ae_sat64s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16si_n_encode_fns[] = { + 0, 0, Opcode_ae_l16si_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_l16ui_n_encode_fns[] = { + 0, 0, Opcode_ae_l16ui_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_s16i_n_encode_fns[] = { + 0, 0, Opcode_ae_s16i_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movfcrfsrv_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_movfcrfsrv_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ae_movvfcrfsr_encode_fns[] = { + 0, 0, 0, 0, Opcode_ae_movvfcrfsr_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { + Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { + Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { + Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movt_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { + Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movf_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { + Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_moveqz_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { + Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movnez_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { + Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movgez_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { + Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_movltz_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_trunc_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_utrunc_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_sx2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_sx2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ficeil_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ficeil_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fifloor_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fifloor_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firound_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firound_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_fitrunc_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_fitrunc_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_firint_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_firint_s_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtsf16_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtsf16_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_l_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_l_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtf16s_h_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cvtf16s_h_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { + Opcode_abs_s_Slot_inst_encode, 0, 0, 0, Opcode_abs_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { + Opcode_mul_s_Slot_inst_encode, 0, 0, Opcode_mul_s_Slot_ae_slot3_encode, Opcode_mul_s_Slot_ae_slot2_encode, 0, 0, Opcode_mul_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_mul_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { + Opcode_madd_s_Slot_inst_encode, 0, 0, Opcode_madd_s_Slot_ae_slot3_encode, Opcode_madd_s_Slot_ae_slot2_encode, 0, 0, Opcode_madd_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_madd_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { + Opcode_msub_s_Slot_inst_encode, 0, 0, Opcode_msub_s_Slot_ae_slot3_encode, Opcode_msub_s_Slot_ae_slot2_encode, 0, 0, Opcode_msub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_msub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msubn_s_encode_fns[] = { + 0, 0, 0, Opcode_msubn_s_Slot_ae_slot3_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = { + Opcode_maddn_s_Slot_inst_encode, 0, 0, 0, Opcode_maddn_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { + Opcode_add_s_Slot_inst_encode, 0, 0, Opcode_add_s_Slot_ae_slot3_encode, Opcode_add_s_Slot_ae_slot2_encode, 0, 0, Opcode_add_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_add_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { + Opcode_sub_s_Slot_inst_encode, 0, 0, Opcode_sub_s_Slot_ae_slot3_encode, Opcode_sub_s_Slot_ae_slot2_encode, 0, 0, Opcode_sub_s_Slot_ae2_slot2_encode, 0, 0, 0, 0, 0, 0, Opcode_sub_s_Slot_ae5_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { + Opcode_neg_s_Slot_inst_encode, 0, 0, Opcode_neg_s_Slot_ae_slot3_encode, Opcode_neg_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_float_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { + 0, 0, 0, 0, 0, 0, Opcode_ufloat_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_sx2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_sx2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_sx2_Slot_ae2_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { + Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_ole_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { + Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_olt_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { + Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, Opcode_oeq_s_Slot_ae_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { + Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { + Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { + Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { + Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = { + Opcode_const_s_Slot_inst_encode, 0, 0, 0, Opcode_const_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_nexp01_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_mksadj_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_mkdadj_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_div0_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_sqrt0_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_recip0_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_rsqrt0_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = { + Opcode_divn_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_addexp_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_addexpm_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_min_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_max_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mulmux_s_encode_fns[] = { + 0, 0, 0, Opcode_mulmux_s_Slot_ae_slot3_encode, Opcode_mulmux_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddmux_s_encode_fns[] = { + 0, 0, 0, Opcode_maddmux_s_Slot_ae_slot3_encode, Opcode_maddmux_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_conjc_s_encode_fns[] = { + 0, 0, 0, 0, Opcode_conjc_s_Slot_ae_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sigmoid_q15_encode_fns[] = { + Opcode_sigmoid_q15_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sigmoid_fp32_encode_fns[] = { + Opcode_sigmoid_fp32_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +int num_bypass_groups() { + return 0; +} + +int num_bypass_group_chunks() { + return 0; +} + +uint32 *bypass_entry(int i) { + return 0; +} + + +/* Opcode table. */ + +static xtensa_funcUnit_use Opcode_l32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16si_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32r_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l8ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s16i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32nb_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s8i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hl_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hl_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_lh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_lh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_ll_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_ll_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hl_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hl_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_lh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_lh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_ll_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_ll_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_licw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sicw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ai_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32c1i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l8x4f_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x2m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2f24_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2rng_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16x4_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16m_l_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32f24_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32_l_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16_0_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s64_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_iu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32m_xu_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_lalign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_salign64_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la64_pp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4pos_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4neg_pc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64pos_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa64neg_fp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_la24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa16x4_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa32x2f24_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24_l_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ic1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_rip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sa24x2_ric1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_x_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24ra64s_xc1_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s32x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s24x2ra64s_ip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32f48p16s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32ra_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32r_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulas32f48p16s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32ra_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32r_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulss32f48p16s_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32ra_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32r_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32u_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32u_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32u_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_33_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_33_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_32_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_21_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_21_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_31_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_31_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_30_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_30_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_10_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_10_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_20_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_20_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_11_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_11_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16ss_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_33_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_33_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_32_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_21_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_21_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_31_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_31_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_30_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_30_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_10_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_10_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_20_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_20_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_11_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_11_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16ss_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_33_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_33_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_32_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_21_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_21_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_31_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_31_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_30_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_30_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_10_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_10_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_20_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_20_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_11_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_11_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16ss_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_33_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_33_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_13_02_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_13_02_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_11_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd16ss_11_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_33_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_33_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_13_02_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_13_02_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_11_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd16ss_11_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_33_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_33_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_13_02_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_13_02_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_11_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd16ss_11_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_33_22_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_33_22_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_13_02_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_13_02_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_11_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd16ss_11_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf48q32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf48q32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf48q32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf48q32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulq32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulq32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulq32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulq32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf48q32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf48q32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf48q32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf48q32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaq32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaq32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaq32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaq32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf48q32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf48q32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf48q32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf48q32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsq32sp16s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsq32sp16s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsq32sp16u_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsq32sp16u_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp24x2ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp24x2r_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp24x2ra_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp24x2r_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp24x2ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp24x2r_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp24x2ra_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp24x2r_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp24x2ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp24x2r_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp24x2ra_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp24x2r_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32s_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32ra_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32s_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32ra_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32s_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32ra_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32s_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32ra_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32x16_h3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasfd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulasd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsafd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsad32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssfd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasfd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzasd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsafd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzsad32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32x16_h3_l2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32x16_h3_l2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32x16_h1_l0_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssfd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32x16_h1_l0_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h2_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h0_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h2_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h0_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h2_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h0_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h2_l3_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h0_l1_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h2_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaafd32x16_h0_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h2_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaafd32x16_h0_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h2_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32x16_h0_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h2_l3_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32x16_h0_l1_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x16x2_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2rs_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2s_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2s_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x16x2_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2rs_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2ras_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x16x2_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2rs_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x16x2_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2rs_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x16x2ras_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x16x2_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2rs_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2s_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2s_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x16x2_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2rs_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2ras_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x16x2_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2rs_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x16x2_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2rs_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x16x2ras_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x16x2_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2rs_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2s_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2s_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x16x2_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2rs_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2ras_h_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x16x2_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2rs_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2s_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2s_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x16x2_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2rs_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x16x2ras_l_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x2rs_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x2ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulp32x2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x2rs_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp32x2ras_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x2rs_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x2ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulap32x2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x2rs_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafp32x2ras_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x2rs_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x2ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsp32x2_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x2rs_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsfp32x2ras_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp16x4s_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfp16x4ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulc32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfc24ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfc32ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulc32x16_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfc32x16ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulc32x16_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfc32x16ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulac32_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafc24ra_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafc32ras_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulac32x16_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafc32x16ras_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulac32x16_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafc32x16ras_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulf16x4ss_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaf16x4ss_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulsf16x4ss_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul16x4_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula16x4_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls16x4_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x2s_fir_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x2ra_fir_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x2s_fir_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x2ra_fir_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x16x2_fir_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x16x2_fir_hl_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x16x2_fir_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulfd32x16x2_fir_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x2s_fir_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x2ra_fir_h_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x2s_fir_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x2ra_fir_l_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x16x2_fir_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x16x2_fir_hl_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x16x2_fir_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulafd32x16x2_fir_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 }, + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaafq32x16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaafq32x16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaafq32x16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaafq32x16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaaq32x16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaaq32x16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaaq32x16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaaq32x16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul16_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula16_00_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul16_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula16_00_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaaq16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaaq16_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaaaaq16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaaaaq16_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldl16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_shift32x5, 4 }, + { FUNCUNIT_ae_add32x27, 4 } +}; + +static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbs_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_lbsi_funcUnit_uses[] = { + { FUNCUNIT_ae_leftshift32x5, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_db_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_dbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ic1_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sb_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbi_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_vles16c_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_sbf_ip_funcUnit_uses[] = { + { FUNCUNIT_ae_shift32x4, 3 }, + { FUNCUNIT_ae_leftshift32x5, 3 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32ep_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32ep_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32ep_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32ep_hh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32ep_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_muls32ep_hh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32ep_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32ep_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32ep_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32ep_hh_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32ep_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzssd32ep_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32ep_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulssd32ep_hh_ll_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32usep_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulaad32usep_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32usep_hl_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mulzaad32usep_hl_lh_s2_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_2, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32usep_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32usep_lh_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mul32usep_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_mula32usep_ll_funcUnit_uses[] = { + { FUNCUNIT_ae_mulpp_32x32x2_1, 3 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16si_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_l16ui_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ae_s16i_n_funcUnit_uses[] = { + { FUNCUNIT_ae_add32x27, 4 }, + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 1, Opcode_l32e_funcUnit_uses }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 1, Opcode_s32e_funcUnit_uses }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 1, Opcode_l32i_n_funcUnit_uses }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 1, Opcode_s32i_n_funcUnit_uses }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 1, Opcode_l16ui_funcUnit_uses }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 1, Opcode_l16si_funcUnit_uses }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 1, Opcode_l32i_funcUnit_uses }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 1, Opcode_l32r_funcUnit_uses }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 1, Opcode_l8ui_funcUnit_uses }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 1, Opcode_s16i_funcUnit_uses }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 1, Opcode_s32i_funcUnit_uses }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 1, Opcode_s32nb_funcUnit_uses }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 1, Opcode_s8i_funcUnit_uses }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "mulsh", ICLASS_xt_mul32h, + 0, + Opcode_mulsh_encode_fns, 0, 0 }, + { "muluh", ICLASS_xt_mul32h, + 0, + Opcode_muluh_encode_fns, 0, 0 }, + { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.da.hh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.da.hl", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.ll", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 1, Opcode_mula_da_hh_lddec_funcUnit_uses }, + { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 1, Opcode_mula_da_hh_ldinc_funcUnit_uses }, + { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 1, Opcode_mula_da_hl_lddec_funcUnit_uses }, + { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 1, Opcode_mula_da_hl_ldinc_funcUnit_uses }, + { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 1, Opcode_mula_da_lh_lddec_funcUnit_uses }, + { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 1, Opcode_mula_da_lh_ldinc_funcUnit_uses }, + { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 1, Opcode_mula_da_ll_lddec_funcUnit_uses }, + { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 1, Opcode_mula_da_ll_ldinc_funcUnit_uses }, + { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 1, Opcode_mula_dd_hh_lddec_funcUnit_uses }, + { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 1, Opcode_mula_dd_hh_ldinc_funcUnit_uses }, + { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 1, Opcode_mula_dd_hl_lddec_funcUnit_uses }, + { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 1, Opcode_mula_dd_hl_ldinc_funcUnit_uses }, + { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 1, Opcode_mula_dd_lh_lddec_funcUnit_uses }, + { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 1, Opcode_mula_dd_lh_ldinc_funcUnit_uses }, + { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 1, Opcode_mula_dd_ll_lddec_funcUnit_uses }, + { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 1, Opcode_mula_dd_ll_ldinc_funcUnit_uses }, + { "lddec", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_lddec_encode_fns, 1, Opcode_lddec_funcUnit_uses }, + { "ldinc", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_ldinc_encode_fns, 1, Opcode_ldinc_funcUnit_uses }, + { "rsr.m0", ICLASS_xt_iclass_rsr_m0, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", ICLASS_xt_iclass_wsr_m0, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", ICLASS_xt_iclass_xsr_m0, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", ICLASS_xt_iclass_rsr_m1, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", ICLASS_xt_iclass_wsr_m1, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", ICLASS_xt_iclass_xsr_m1, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", ICLASS_xt_iclass_rsr_m2, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", ICLASS_xt_iclass_wsr_m2, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", ICLASS_xt_iclass_xsr_m2, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", ICLASS_xt_iclass_rsr_m3, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", ICLASS_xt_iclass_wsr_m3, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", ICLASS_xt_iclass_xsr_m3, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 1, Opcode_lddr32_p_funcUnit_uses }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 1, Opcode_sddr32_p_funcUnit_uses }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 1, Opcode_lict_funcUnit_uses }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 1, Opcode_licw_funcUnit_uses }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 1, Opcode_sict_funcUnit_uses }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 1, Opcode_sicw_funcUnit_uses }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, + 0, + Opcode_diwbui_p_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfm.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfm_b_encode_fns, 0, 0 }, + { "dpfm.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfm_bf_encode_fns, 0, 0 }, + { "dpfr.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfr_b_encode_fns, 0, 0 }, + { "dpfr.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfr_bf_encode_fns, 0, 0 }, + { "dpfw.b", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfw_b_encode_fns, 0, 0 }, + { "dpfw.bf", ICLASS_xt_iclass_dpfb, + 0, + Opcode_dpfw_bf_encode_fns, 0, 0 }, + { "pfnxt.f", ICLASS_xt_iclass_bpfnxt, + 0, + Opcode_pfnxt_f_encode_fns, 0, 0 }, + { "dhi.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhi_b_encode_fns, 0, 0 }, + { "dhwbi.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhwbi_b_encode_fns, 0, 0 }, + { "dhwb.b", ICLASS_xt_iclass_dpdngrd, + 0, + Opcode_dhwb_b_encode_fns, 0, 0 }, + { "pfend.a", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfend_a_encode_fns, 0, 0 }, + { "pfend.o", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfend_o_encode_fns, 0, 0 }, + { "pfwait.a", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfwait_a_encode_fns, 0, 0 }, + { "pfwait.r", ICLASS_xt_iclass_bpfctl, + 0, + Opcode_pfwait_r_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 1, Opcode_sdct_funcUnit_uses }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 1, Opcode_ldct_funcUnit_uses }, + { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, + 0, + Opcode_rsr_prefctl_encode_fns, 0, 0 }, + { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, + 0, + Opcode_wsr_prefctl_encode_fns, 0, 0 }, + { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, + 0, + Opcode_xsr_prefctl_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 1, Opcode_l32ai_funcUnit_uses }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 1, Opcode_s32ri_funcUnit_uses }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 1, Opcode_s32c1i_funcUnit_uses }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "beqz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_w15_encode_fns, 0, 0 }, + { "bgez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_w15_encode_fns, 0, 0 }, + { "bltz.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_w15_encode_fns, 0, 0 }, + { "bnez.w15", ICLASS_xt_iclass_wb15_0, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_w15_encode_fns, 0, 0 }, + { "beqi.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_w15_encode_fns, 0, 0 }, + { "bgei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_w15_encode_fns, 0, 0 }, + { "blti.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_w15_encode_fns, 0, 0 }, + { "bnei.w15", ICLASS_xt_iclass_wb15_1, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_w15_encode_fns, 0, 0 }, + { "bgeui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_w15_encode_fns, 0, 0 }, + { "bltui.w15", ICLASS_xt_iclass_wb15_2, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_w15_encode_fns, 0, 0 }, + { "bbci.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_w15_encode_fns, 0, 0 }, + { "bbsi.w15", ICLASS_xt_iclass_wb15_3, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_w15_encode_fns, 0, 0 }, + { "ball.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_w15_encode_fns, 0, 0 }, + { "bany.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_w15_encode_fns, 0, 0 }, + { "bbc.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_w15_encode_fns, 0, 0 }, + { "bbs.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_w15_encode_fns, 0, 0 }, + { "beq.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_w15_encode_fns, 0, 0 }, + { "bgeu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_w15_encode_fns, 0, 0 }, + { "bge.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_w15_encode_fns, 0, 0 }, + { "bltu.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_w15_encode_fns, 0, 0 }, + { "blt.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_w15_encode_fns, 0, 0 }, + { "bnall.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_w15_encode_fns, 0, 0 }, + { "bne.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_w15_encode_fns, 0, 0 }, + { "bnone.w15", ICLASS_xt_iclass_wb15_4, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_w15_encode_fns, 0, 0 }, + { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, + 0, + Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, + { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, + 0, + Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, + { "rur.ae_bithead", ICLASS_rur_ae_bithead, + 0, + Opcode_rur_ae_bithead_encode_fns, 0, 0 }, + { "wur.ae_bithead", ICLASS_wur_ae_bithead, + 0, + Opcode_wur_ae_bithead_encode_fns, 0, 0 }, + { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, + 0, + Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, + 0, + Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, + { "rur.ae_cw_sd_no", ICLASS_rur_ae_cw_sd_no, + 0, + Opcode_rur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "wur.ae_cw_sd_no", ICLASS_wur_ae_cw_sd_no, + 0, + Opcode_wur_ae_cw_sd_no_encode_fns, 0, 0 }, + { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, + 0, + Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, + { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, + 0, + Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, + { "rur.ae_cend0", ICLASS_rur_ae_cend0, + 0, + Opcode_rur_ae_cend0_encode_fns, 0, 0 }, + { "wur.ae_cend0", ICLASS_wur_ae_cend0, + 0, + Opcode_wur_ae_cend0_encode_fns, 0, 0 }, + { "rur.ae_cbegin1", ICLASS_rur_ae_cbegin1, + 0, + Opcode_rur_ae_cbegin1_encode_fns, 0, 0 }, + { "wur.ae_cbegin1", ICLASS_wur_ae_cbegin1, + 0, + Opcode_wur_ae_cbegin1_encode_fns, 0, 0 }, + { "rur.ae_cend1", ICLASS_rur_ae_cend1, + 0, + Opcode_rur_ae_cend1_encode_fns, 0, 0 }, + { "wur.ae_cend1", ICLASS_wur_ae_cend1, + 0, + Opcode_wur_ae_cend1_encode_fns, 0, 0 }, + { "ae_sext16", ICLASS_ic_sext16, + 0, + Opcode_ae_sext16_encode_fns, 0, 0 }, + { "ae_zext16", ICLASS_ic_zext16, + 0, + Opcode_ae_zext16_encode_fns, 0, 0 }, + { "ae_clamps16", ICLASS_ic_clamps16, + 0, + Opcode_ae_clamps16_encode_fns, 0, 0 }, + { "rur.fcr", ICLASS_rur_fcr, + 0, + Opcode_rur_fcr_encode_fns, 0, 0 }, + { "wur.fcr", ICLASS_wur_fcr, + 0, + Opcode_wur_fcr_encode_fns, 0, 0 }, + { "rur.fsr", ICLASS_rur_fsr, + 0, + Opcode_rur_fsr_encode_fns, 0, 0 }, + { "wur.fsr", ICLASS_wur_fsr, + 0, + Opcode_wur_fsr_encode_fns, 0, 0 }, + { "f64iter", ICLASS_iclass_F64ITER, + 0, + Opcode_f64iter_encode_fns, 0, 0 }, + { "f64rnd", ICLASS_iclass_F64RND, + 0, + Opcode_f64rnd_encode_fns, 0, 0 }, + { "f64addc", ICLASS_iclass_F64ADDC_F64SUBC, + 0, + Opcode_f64addc_encode_fns, 0, 0 }, + { "f64subc", ICLASS_iclass_F64ADDC_F64SUBC, + 0, + Opcode_f64subc_encode_fns, 0, 0 }, + { "f64sig", ICLASS_iclass_F64SIG, + 0, + Opcode_f64sig_encode_fns, 0, 0 }, + { "f64cmpl", ICLASS_iclass_F64CMPL, + 0, + Opcode_f64cmpl_encode_fns, 0, 0 }, + { "f64cmph", ICLASS_iclass_F64CMPH, + 0, + Opcode_f64cmph_encode_fns, 0, 0 }, + { "f64norm", ICLASS_iclass_F64NORM, + 0, + Opcode_f64norm_encode_fns, 0, 0 }, + { "f64sexp", ICLASS_iclass_F64SEXP, + 0, + Opcode_f64sexp_encode_fns, 0, 0 }, + { "rf64r", ICLASS_iclass_RF64R, + 0, + Opcode_rf64r_encode_fns, 0, 0 }, + { "wf64r", ICLASS_iclass_WF64R, + 0, + Opcode_wf64r_encode_fns, 0, 0 }, + { "rur.f64r_lo", ICLASS_rur_f64r_lo, + 0, + Opcode_rur_f64r_lo_encode_fns, 0, 0 }, + { "wur.f64r_lo", ICLASS_wur_f64r_lo, + 0, + Opcode_wur_f64r_lo_encode_fns, 0, 0 }, + { "rur.f64r_hi", ICLASS_rur_f64r_hi, + 0, + Opcode_rur_f64r_hi_encode_fns, 0, 0 }, + { "wur.f64r_hi", ICLASS_wur_f64r_hi, + 0, + Opcode_wur_f64r_hi_encode_fns, 0, 0 }, + { "rur.f64s", ICLASS_rur_f64s, + 0, + Opcode_rur_f64s_encode_fns, 0, 0 }, + { "wur.f64s", ICLASS_wur_f64s, + 0, + Opcode_wur_f64s_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 }, + { "rur.ae_overflow", ICLASS_RUR_AE_OVERFLOW, + 0, + Opcode_rur_ae_overflow_encode_fns, 0, 0 }, + { "wur.ae_overflow", ICLASS_WUR_AE_OVERFLOW, + 0, + Opcode_wur_ae_overflow_encode_fns, 0, 0 }, + { "rur.ae_sar", ICLASS_RUR_AE_SAR, + 0, + Opcode_rur_ae_sar_encode_fns, 0, 0 }, + { "wur.ae_sar", ICLASS_WUR_AE_SAR, + 0, + Opcode_wur_ae_sar_encode_fns, 0, 0 }, + { "rur.ae_bitptr", ICLASS_RUR_AE_BITPTR, + 0, + Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, + { "wur.ae_bitptr", ICLASS_WUR_AE_BITPTR, + 0, + Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, + { "rur.ae_bitsused", ICLASS_RUR_AE_BITSUSED, + 0, + Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, + { "wur.ae_bitsused", ICLASS_WUR_AE_BITSUSED, + 0, + Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, + { "rur.ae_tablesize", ICLASS_RUR_AE_TABLESIZE, + 0, + Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, + { "wur.ae_tablesize", ICLASS_WUR_AE_TABLESIZE, + 0, + Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, + { "rur.ae_first_ts", ICLASS_RUR_AE_FIRST_TS, + 0, + Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, + { "wur.ae_first_ts", ICLASS_WUR_AE_FIRST_TS, + 0, + Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, + { "rur.ae_nextoffset", ICLASS_RUR_AE_NEXTOFFSET, + 0, + Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, + { "wur.ae_nextoffset", ICLASS_WUR_AE_NEXTOFFSET, + 0, + Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, + { "rur.ae_searchdone", ICLASS_RUR_AE_SEARCHDONE, + 0, + Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, + { "wur.ae_searchdone", ICLASS_WUR_AE_SEARCHDONE, + 0, + Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, + { "rur.ae_cwrap", ICLASS_RUR_AE_CWRAP, + 0, + Opcode_rur_ae_cwrap_encode_fns, 0, 0 }, + { "wur.ae_cwrap", ICLASS_WUR_AE_CWRAP, + 0, + Opcode_wur_ae_cwrap_encode_fns, 0, 0 }, + { "ae_l8x4f.i", ICLASS_AE_L8X4F_I, + 0, + Opcode_ae_l8x4f_i_encode_fns, 1, Opcode_ae_l8x4f_i_funcUnit_uses }, + { "ae_l8x4f.ip", ICLASS_AE_L8X4F_IP, + 0, + Opcode_ae_l8x4f_ip_encode_fns, 1, Opcode_ae_l8x4f_ip_funcUnit_uses }, + { "ae_l16m.xc", ICLASS_AE_L16M_XC, + 0, + Opcode_ae_l16m_xc_encode_fns, 1, Opcode_ae_l16m_xc_funcUnit_uses }, + { "ae_l16m.xc1", ICLASS_AE_L16M_XC1, + 0, + Opcode_ae_l16m_xc1_encode_fns, 1, Opcode_ae_l16m_xc1_funcUnit_uses }, + { "ae_l16m.i", ICLASS_AE_L16M_I, + 0, + Opcode_ae_l16m_i_encode_fns, 1, Opcode_ae_l16m_i_funcUnit_uses }, + { "ae_l16m.iu", ICLASS_AE_L16M_IU, + 0, + Opcode_ae_l16m_iu_encode_fns, 1, Opcode_ae_l16m_iu_funcUnit_uses }, + { "ae_l16m.x", ICLASS_AE_L16M_X, + 0, + Opcode_ae_l16m_x_encode_fns, 1, Opcode_ae_l16m_x_funcUnit_uses }, + { "ae_l16m.xu", ICLASS_AE_L16M_XU, + 0, + Opcode_ae_l16m_xu_encode_fns, 1, Opcode_ae_l16m_xu_funcUnit_uses }, + { "ae_l16.xc", ICLASS_AE_L16_XC, + 0, + Opcode_ae_l16_xc_encode_fns, 1, Opcode_ae_l16_xc_funcUnit_uses }, + { "ae_l16.xc1", ICLASS_AE_L16_XC1, + 0, + Opcode_ae_l16_xc1_encode_fns, 1, Opcode_ae_l16_xc1_funcUnit_uses }, + { "ae_l16.i", ICLASS_AE_L16_I, + 0, + Opcode_ae_l16_i_encode_fns, 1, Opcode_ae_l16_i_funcUnit_uses }, + { "ae_l16.ip", ICLASS_AE_L16_IP, + 0, + Opcode_ae_l16_ip_encode_fns, 1, Opcode_ae_l16_ip_funcUnit_uses }, + { "ae_l16.x", ICLASS_AE_L16_X, + 0, + Opcode_ae_l16_x_encode_fns, 1, Opcode_ae_l16_x_funcUnit_uses }, + { "ae_l16.xp", ICLASS_AE_L16_XP, + 0, + Opcode_ae_l16_xp_encode_fns, 1, Opcode_ae_l16_xp_funcUnit_uses }, + { "ae_l32f24.xc", ICLASS_AE_L32F24_XC, + 0, + Opcode_ae_l32f24_xc_encode_fns, 1, Opcode_ae_l32f24_xc_funcUnit_uses }, + { "ae_l32f24.xc1", ICLASS_AE_L32F24_XC1, + 0, + Opcode_ae_l32f24_xc1_encode_fns, 1, Opcode_ae_l32f24_xc1_funcUnit_uses }, + { "ae_l32f24.i", ICLASS_AE_L32F24_I, + 0, + Opcode_ae_l32f24_i_encode_fns, 1, Opcode_ae_l32f24_i_funcUnit_uses }, + { "ae_l32f24.ip", ICLASS_AE_L32F24_IP, + 0, + Opcode_ae_l32f24_ip_encode_fns, 1, Opcode_ae_l32f24_ip_funcUnit_uses }, + { "ae_l32f24.x", ICLASS_AE_L32F24_X, + 0, + Opcode_ae_l32f24_x_encode_fns, 1, Opcode_ae_l32f24_x_funcUnit_uses }, + { "ae_l32f24.xp", ICLASS_AE_L32F24_XP, + 0, + Opcode_ae_l32f24_xp_encode_fns, 1, Opcode_ae_l32f24_xp_funcUnit_uses }, + { "ae_l32.xc", ICLASS_AE_L32_XC, + 0, + Opcode_ae_l32_xc_encode_fns, 1, Opcode_ae_l32_xc_funcUnit_uses }, + { "ae_l32.xc1", ICLASS_AE_L32_XC1, + 0, + Opcode_ae_l32_xc1_encode_fns, 1, Opcode_ae_l32_xc1_funcUnit_uses }, + { "ae_l32.i", ICLASS_AE_L32_I, + 0, + Opcode_ae_l32_i_encode_fns, 1, Opcode_ae_l32_i_funcUnit_uses }, + { "ae_l32.ip", ICLASS_AE_L32_IP, + 0, + Opcode_ae_l32_ip_encode_fns, 1, Opcode_ae_l32_ip_funcUnit_uses }, + { "ae_l32.x", ICLASS_AE_L32_X, + 0, + Opcode_ae_l32_x_encode_fns, 1, Opcode_ae_l32_x_funcUnit_uses }, + { "ae_l32.xp", ICLASS_AE_L32_XP, + 0, + Opcode_ae_l32_xp_encode_fns, 1, Opcode_ae_l32_xp_funcUnit_uses }, + { "ae_l32m.xc", ICLASS_AE_L32M_XC, + 0, + Opcode_ae_l32m_xc_encode_fns, 1, Opcode_ae_l32m_xc_funcUnit_uses }, + { "ae_l32m.i", ICLASS_AE_L32M_I, + 0, + Opcode_ae_l32m_i_encode_fns, 1, Opcode_ae_l32m_i_funcUnit_uses }, + { "ae_l32m.iu", ICLASS_AE_L32M_IU, + 0, + Opcode_ae_l32m_iu_encode_fns, 1, Opcode_ae_l32m_iu_funcUnit_uses }, + { "ae_l32m.x", ICLASS_AE_L32M_X, + 0, + Opcode_ae_l32m_x_encode_fns, 1, Opcode_ae_l32m_x_funcUnit_uses }, + { "ae_l32m.xu", ICLASS_AE_L32M_XU, + 0, + Opcode_ae_l32m_xu_encode_fns, 1, Opcode_ae_l32m_xu_funcUnit_uses }, + { "ae_l16x2m.xc", ICLASS_AE_L16X2M_XC, + 0, + Opcode_ae_l16x2m_xc_encode_fns, 1, Opcode_ae_l16x2m_xc_funcUnit_uses }, + { "ae_l16x2m.xc1", ICLASS_AE_L16X2M_XC1, + 0, + Opcode_ae_l16x2m_xc1_encode_fns, 1, Opcode_ae_l16x2m_xc1_funcUnit_uses }, + { "ae_l16x2m.i", ICLASS_AE_L16X2M_I, + 0, + Opcode_ae_l16x2m_i_encode_fns, 1, Opcode_ae_l16x2m_i_funcUnit_uses }, + { "ae_l16x2m.iu", ICLASS_AE_L16X2M_IU, + 0, + Opcode_ae_l16x2m_iu_encode_fns, 1, Opcode_ae_l16x2m_iu_funcUnit_uses }, + { "ae_l16x2m.x", ICLASS_AE_L16X2M_X, + 0, + Opcode_ae_l16x2m_x_encode_fns, 1, Opcode_ae_l16x2m_x_funcUnit_uses }, + { "ae_l16x2m.xu", ICLASS_AE_L16X2M_XU, + 0, + Opcode_ae_l16x2m_xu_encode_fns, 1, Opcode_ae_l16x2m_xu_funcUnit_uses }, + { "ae_l32x2f24.xc", ICLASS_AE_L32X2F24_XC, + 0, + Opcode_ae_l32x2f24_xc_encode_fns, 1, Opcode_ae_l32x2f24_xc_funcUnit_uses }, + { "ae_l32x2f24.xc1", ICLASS_AE_L32X2F24_XC1, + 0, + Opcode_ae_l32x2f24_xc1_encode_fns, 1, Opcode_ae_l32x2f24_xc1_funcUnit_uses }, + { "ae_l32x2f24.i", ICLASS_AE_L32X2F24_I, + 0, + Opcode_ae_l32x2f24_i_encode_fns, 1, Opcode_ae_l32x2f24_i_funcUnit_uses }, + { "ae_l32x2f24.ip", ICLASS_AE_L32X2F24_IP, + 0, + Opcode_ae_l32x2f24_ip_encode_fns, 1, Opcode_ae_l32x2f24_ip_funcUnit_uses }, + { "ae_l32x2f24.rip", ICLASS_AE_L32X2F24_RIP, + 0, + Opcode_ae_l32x2f24_rip_encode_fns, 1, Opcode_ae_l32x2f24_rip_funcUnit_uses }, + { "ae_l32x2f24.ri", ICLASS_AE_L32X2F24_RI, + 0, + Opcode_ae_l32x2f24_ri_encode_fns, 1, Opcode_ae_l32x2f24_ri_funcUnit_uses }, + { "ae_l32x2f24.ric", ICLASS_AE_L32X2F24_RIC, + 0, + Opcode_ae_l32x2f24_ric_encode_fns, 1, Opcode_ae_l32x2f24_ric_funcUnit_uses }, + { "ae_l32x2f24.ric1", ICLASS_AE_L32X2F24_RIC1, + 0, + Opcode_ae_l32x2f24_ric1_encode_fns, 1, Opcode_ae_l32x2f24_ric1_funcUnit_uses }, + { "ae_l32x2f24.x", ICLASS_AE_L32X2F24_X, + 0, + Opcode_ae_l32x2f24_x_encode_fns, 1, Opcode_ae_l32x2f24_x_funcUnit_uses }, + { "ae_l32x2f24.xp", ICLASS_AE_L32X2F24_XP, + 0, + Opcode_ae_l32x2f24_xp_encode_fns, 1, Opcode_ae_l32x2f24_xp_funcUnit_uses }, + { "ae_l32x2.xc", ICLASS_AE_L32X2_XC, + 0, + Opcode_ae_l32x2_xc_encode_fns, 1, Opcode_ae_l32x2_xc_funcUnit_uses }, + { "ae_l32x2.xc1", ICLASS_AE_L32X2_XC1, + 0, + Opcode_ae_l32x2_xc1_encode_fns, 1, Opcode_ae_l32x2_xc1_funcUnit_uses }, + { "ae_l32x2.i", ICLASS_AE_L32X2_I, + 0, + Opcode_ae_l32x2_i_encode_fns, 1, Opcode_ae_l32x2_i_funcUnit_uses }, + { "ae_l32x2.ip", ICLASS_AE_L32X2_IP, + 0, + Opcode_ae_l32x2_ip_encode_fns, 1, Opcode_ae_l32x2_ip_funcUnit_uses }, + { "ae_l32x2.ric", ICLASS_AE_L32X2_RIC, + 0, + Opcode_ae_l32x2_ric_encode_fns, 1, Opcode_ae_l32x2_ric_funcUnit_uses }, + { "ae_l32x2.ric1", ICLASS_AE_L32X2_RIC1, + 0, + Opcode_ae_l32x2_ric1_encode_fns, 1, Opcode_ae_l32x2_ric1_funcUnit_uses }, + { "ae_l32x2.x", ICLASS_AE_L32X2_X, + 0, + Opcode_ae_l32x2_x_encode_fns, 1, Opcode_ae_l32x2_x_funcUnit_uses }, + { "ae_l32x2.xp", ICLASS_AE_L32X2_XP, + 0, + Opcode_ae_l32x2_xp_encode_fns, 1, Opcode_ae_l32x2_xp_funcUnit_uses }, + { "ae_l16x4.xc", ICLASS_AE_L16X4_XC, + 0, + Opcode_ae_l16x4_xc_encode_fns, 1, Opcode_ae_l16x4_xc_funcUnit_uses }, + { "ae_l16x4.xc1", ICLASS_AE_L16X4_XC1, + 0, + Opcode_ae_l16x4_xc1_encode_fns, 1, Opcode_ae_l16x4_xc1_funcUnit_uses }, + { "ae_l16x4.i", ICLASS_AE_L16X4_I, + 0, + Opcode_ae_l16x4_i_encode_fns, 1, Opcode_ae_l16x4_i_funcUnit_uses }, + { "ae_l16x4.ip", ICLASS_AE_L16X4_IP, + 0, + Opcode_ae_l16x4_ip_encode_fns, 1, Opcode_ae_l16x4_ip_funcUnit_uses }, + { "ae_l16x4.x", ICLASS_AE_L16X4_X, + 0, + Opcode_ae_l16x4_x_encode_fns, 1, Opcode_ae_l16x4_x_funcUnit_uses }, + { "ae_l16x4.xp", ICLASS_AE_L16X4_XP, + 0, + Opcode_ae_l16x4_xp_encode_fns, 1, Opcode_ae_l16x4_xp_funcUnit_uses }, + { "ae_l64.xc", ICLASS_AE_L64_XC, + 0, + Opcode_ae_l64_xc_encode_fns, 1, Opcode_ae_l64_xc_funcUnit_uses }, + { "ae_l64.xc1", ICLASS_AE_L64_XC1, + 0, + Opcode_ae_l64_xc1_encode_fns, 1, Opcode_ae_l64_xc1_funcUnit_uses }, + { "ae_l64.i", ICLASS_AE_L64_I, + 0, + Opcode_ae_l64_i_encode_fns, 1, Opcode_ae_l64_i_funcUnit_uses }, + { "ae_l64.ip", ICLASS_AE_L64_IP, + 0, + Opcode_ae_l64_ip_encode_fns, 1, Opcode_ae_l64_ip_funcUnit_uses }, + { "ae_l64.x", ICLASS_AE_L64_X, + 0, + Opcode_ae_l64_x_encode_fns, 1, Opcode_ae_l64_x_funcUnit_uses }, + { "ae_l64.xp", ICLASS_AE_L64_XP, + 0, + Opcode_ae_l64_xp_encode_fns, 1, Opcode_ae_l64_xp_funcUnit_uses }, + { "ae_s16x2m.xc", ICLASS_AE_S16X2M_XC, + 0, + Opcode_ae_s16x2m_xc_encode_fns, 1, Opcode_ae_s16x2m_xc_funcUnit_uses }, + { "ae_s16x2m.xc1", ICLASS_AE_S16X2M_XC1, + 0, + Opcode_ae_s16x2m_xc1_encode_fns, 1, Opcode_ae_s16x2m_xc1_funcUnit_uses }, + { "ae_s16x2m.i", ICLASS_AE_S16X2M_I, + 0, + Opcode_ae_s16x2m_i_encode_fns, 1, Opcode_ae_s16x2m_i_funcUnit_uses }, + { "ae_s16x2m.iu", ICLASS_AE_S16X2M_IU, + 0, + Opcode_ae_s16x2m_iu_encode_fns, 1, Opcode_ae_s16x2m_iu_funcUnit_uses }, + { "ae_s16x2m.x", ICLASS_AE_S16X2M_X, + 0, + Opcode_ae_s16x2m_x_encode_fns, 1, Opcode_ae_s16x2m_x_funcUnit_uses }, + { "ae_s16x2m.xu", ICLASS_AE_S16X2M_XU, + 0, + Opcode_ae_s16x2m_xu_encode_fns, 1, Opcode_ae_s16x2m_xu_funcUnit_uses }, + { "ae_s32x2f24.xc", ICLASS_AE_S32X2F24_XC, + 0, + Opcode_ae_s32x2f24_xc_encode_fns, 1, Opcode_ae_s32x2f24_xc_funcUnit_uses }, + { "ae_s32x2f24.xc1", ICLASS_AE_S32X2F24_XC1, + 0, + Opcode_ae_s32x2f24_xc1_encode_fns, 1, Opcode_ae_s32x2f24_xc1_funcUnit_uses }, + { "ae_s32x2f24.i", ICLASS_AE_S32X2F24_I, + 0, + Opcode_ae_s32x2f24_i_encode_fns, 1, Opcode_ae_s32x2f24_i_funcUnit_uses }, + { "ae_s32x2f24.ip", ICLASS_AE_S32X2F24_IP, + 0, + Opcode_ae_s32x2f24_ip_encode_fns, 1, Opcode_ae_s32x2f24_ip_funcUnit_uses }, + { "ae_s32x2f24.rip", ICLASS_AE_S32X2F24_RIP, + 0, + Opcode_ae_s32x2f24_rip_encode_fns, 1, Opcode_ae_s32x2f24_rip_funcUnit_uses }, + { "ae_s32x2f24.ric", ICLASS_AE_S32X2F24_RIC, + 0, + Opcode_ae_s32x2f24_ric_encode_fns, 1, Opcode_ae_s32x2f24_ric_funcUnit_uses }, + { "ae_s32x2f24.ric1", ICLASS_AE_S32X2F24_RIC1, + 0, + Opcode_ae_s32x2f24_ric1_encode_fns, 1, Opcode_ae_s32x2f24_ric1_funcUnit_uses }, + { "ae_s32x2f24.x", ICLASS_AE_S32X2F24_X, + 0, + Opcode_ae_s32x2f24_x_encode_fns, 1, Opcode_ae_s32x2f24_x_funcUnit_uses }, + { "ae_s32x2f24.xp", ICLASS_AE_S32X2F24_XP, + 0, + Opcode_ae_s32x2f24_xp_encode_fns, 1, Opcode_ae_s32x2f24_xp_funcUnit_uses }, + { "ae_s32x2.xc", ICLASS_AE_S32X2_XC, + 0, + Opcode_ae_s32x2_xc_encode_fns, 1, Opcode_ae_s32x2_xc_funcUnit_uses }, + { "ae_s32x2.xc1", ICLASS_AE_S32X2_XC1, + 0, + Opcode_ae_s32x2_xc1_encode_fns, 1, Opcode_ae_s32x2_xc1_funcUnit_uses }, + { "ae_s32x2.i", ICLASS_AE_S32X2_I, + 0, + Opcode_ae_s32x2_i_encode_fns, 1, Opcode_ae_s32x2_i_funcUnit_uses }, + { "ae_s32x2.ip", ICLASS_AE_S32X2_IP, + 0, + Opcode_ae_s32x2_ip_encode_fns, 1, Opcode_ae_s32x2_ip_funcUnit_uses }, + { "ae_s32x2.ric", ICLASS_AE_S32X2_RIC, + 0, + Opcode_ae_s32x2_ric_encode_fns, 1, Opcode_ae_s32x2_ric_funcUnit_uses }, + { "ae_s32x2.ric1", ICLASS_AE_S32X2_RIC1, + 0, + Opcode_ae_s32x2_ric1_encode_fns, 1, Opcode_ae_s32x2_ric1_funcUnit_uses }, + { "ae_s32x2.x", ICLASS_AE_S32X2_X, + 0, + Opcode_ae_s32x2_x_encode_fns, 1, Opcode_ae_s32x2_x_funcUnit_uses }, + { "ae_s32x2.xp", ICLASS_AE_S32X2_XP, + 0, + Opcode_ae_s32x2_xp_encode_fns, 1, Opcode_ae_s32x2_xp_funcUnit_uses }, + { "ae_s32x2rng.i", ICLASS_AE_S32X2RNG_I, + 0, + Opcode_ae_s32x2rng_i_encode_fns, 1, Opcode_ae_s32x2rng_i_funcUnit_uses }, + { "ae_s32x2rng.ip", ICLASS_AE_S32X2RNG_IP, + 0, + Opcode_ae_s32x2rng_ip_encode_fns, 1, Opcode_ae_s32x2rng_ip_funcUnit_uses }, + { "ae_s32x2rng.x", ICLASS_AE_S32X2RNG_X, + 0, + Opcode_ae_s32x2rng_x_encode_fns, 1, Opcode_ae_s32x2rng_x_funcUnit_uses }, + { "ae_s32x2rng.xp", ICLASS_AE_S32X2RNG_XP, + 0, + Opcode_ae_s32x2rng_xp_encode_fns, 1, Opcode_ae_s32x2rng_xp_funcUnit_uses }, + { "ae_s16x4.xc", ICLASS_AE_S16X4_XC, + 0, + Opcode_ae_s16x4_xc_encode_fns, 1, Opcode_ae_s16x4_xc_funcUnit_uses }, + { "ae_s16x4.xc1", ICLASS_AE_S16X4_XC1, + 0, + Opcode_ae_s16x4_xc1_encode_fns, 1, Opcode_ae_s16x4_xc1_funcUnit_uses }, + { "ae_s16x4.i", ICLASS_AE_S16X4_I, + 0, + Opcode_ae_s16x4_i_encode_fns, 1, Opcode_ae_s16x4_i_funcUnit_uses }, + { "ae_s16x4.ip", ICLASS_AE_S16X4_IP, + 0, + Opcode_ae_s16x4_ip_encode_fns, 1, Opcode_ae_s16x4_ip_funcUnit_uses }, + { "ae_s16x4.x", ICLASS_AE_S16X4_X, + 0, + Opcode_ae_s16x4_x_encode_fns, 1, Opcode_ae_s16x4_x_funcUnit_uses }, + { "ae_s16x4.xp", ICLASS_AE_S16X4_XP, + 0, + Opcode_ae_s16x4_xp_encode_fns, 1, Opcode_ae_s16x4_xp_funcUnit_uses }, + { "ae_s16m.l.xc", ICLASS_AE_S16M_L_XC, + 0, + Opcode_ae_s16m_l_xc_encode_fns, 1, Opcode_ae_s16m_l_xc_funcUnit_uses }, + { "ae_s16m.l.xc1", ICLASS_AE_S16M_L_XC1, + 0, + Opcode_ae_s16m_l_xc1_encode_fns, 1, Opcode_ae_s16m_l_xc1_funcUnit_uses }, + { "ae_s16m.l.i", ICLASS_AE_S16M_L_I, + 0, + Opcode_ae_s16m_l_i_encode_fns, 1, Opcode_ae_s16m_l_i_funcUnit_uses }, + { "ae_s16m.l.iu", ICLASS_AE_S16M_L_IU, + 0, + Opcode_ae_s16m_l_iu_encode_fns, 1, Opcode_ae_s16m_l_iu_funcUnit_uses }, + { "ae_s16m.l.x", ICLASS_AE_S16M_L_X, + 0, + Opcode_ae_s16m_l_x_encode_fns, 1, Opcode_ae_s16m_l_x_funcUnit_uses }, + { "ae_s16m.l.xu", ICLASS_AE_S16M_L_XU, + 0, + Opcode_ae_s16m_l_xu_encode_fns, 1, Opcode_ae_s16m_l_xu_funcUnit_uses }, + { "ae_s32f24.l.xc", ICLASS_AE_S32F24_L_XC, + 0, + Opcode_ae_s32f24_l_xc_encode_fns, 1, Opcode_ae_s32f24_l_xc_funcUnit_uses }, + { "ae_s32f24.l.xc1", ICLASS_AE_S32F24_L_XC1, + 0, + Opcode_ae_s32f24_l_xc1_encode_fns, 1, Opcode_ae_s32f24_l_xc1_funcUnit_uses }, + { "ae_s32f24.l.i", ICLASS_AE_S32F24_L_I, + 0, + Opcode_ae_s32f24_l_i_encode_fns, 1, Opcode_ae_s32f24_l_i_funcUnit_uses }, + { "ae_s32f24.l.ip", ICLASS_AE_S32F24_L_IP, + 0, + Opcode_ae_s32f24_l_ip_encode_fns, 1, Opcode_ae_s32f24_l_ip_funcUnit_uses }, + { "ae_s32f24.l.x", ICLASS_AE_S32F24_L_X, + 0, + Opcode_ae_s32f24_l_x_encode_fns, 1, Opcode_ae_s32f24_l_x_funcUnit_uses }, + { "ae_s32f24.l.xp", ICLASS_AE_S32F24_L_XP, + 0, + Opcode_ae_s32f24_l_xp_encode_fns, 1, Opcode_ae_s32f24_l_xp_funcUnit_uses }, + { "ae_s32.l.xc", ICLASS_AE_S32_L_XC, + 0, + Opcode_ae_s32_l_xc_encode_fns, 1, Opcode_ae_s32_l_xc_funcUnit_uses }, + { "ae_s32.l.xc1", ICLASS_AE_S32_L_XC1, + 0, + Opcode_ae_s32_l_xc1_encode_fns, 1, Opcode_ae_s32_l_xc1_funcUnit_uses }, + { "ae_s32.l.i", ICLASS_AE_S32_L_I, + 0, + Opcode_ae_s32_l_i_encode_fns, 1, Opcode_ae_s32_l_i_funcUnit_uses }, + { "ae_s32.l.ip", ICLASS_AE_S32_L_IP, + 0, + Opcode_ae_s32_l_ip_encode_fns, 1, Opcode_ae_s32_l_ip_funcUnit_uses }, + { "ae_s32.l.x", ICLASS_AE_S32_L_X, + 0, + Opcode_ae_s32_l_x_encode_fns, 1, Opcode_ae_s32_l_x_funcUnit_uses }, + { "ae_s32.l.xp", ICLASS_AE_S32_L_XP, + 0, + Opcode_ae_s32_l_xp_encode_fns, 1, Opcode_ae_s32_l_xp_funcUnit_uses }, + { "ae_s16.0.xc", ICLASS_AE_S16_0_XC, + 0, + Opcode_ae_s16_0_xc_encode_fns, 1, Opcode_ae_s16_0_xc_funcUnit_uses }, + { "ae_s16.0.xc1", ICLASS_AE_S16_0_XC1, + 0, + Opcode_ae_s16_0_xc1_encode_fns, 1, Opcode_ae_s16_0_xc1_funcUnit_uses }, + { "ae_s16.0.i", ICLASS_AE_S16_0_I, + 0, + Opcode_ae_s16_0_i_encode_fns, 1, Opcode_ae_s16_0_i_funcUnit_uses }, + { "ae_s16.0.ip", ICLASS_AE_S16_0_IP, + 0, + Opcode_ae_s16_0_ip_encode_fns, 1, Opcode_ae_s16_0_ip_funcUnit_uses }, + { "ae_s16.0.x", ICLASS_AE_S16_0_X, + 0, + Opcode_ae_s16_0_x_encode_fns, 1, Opcode_ae_s16_0_x_funcUnit_uses }, + { "ae_s16.0.xp", ICLASS_AE_S16_0_XP, + 0, + Opcode_ae_s16_0_xp_encode_fns, 1, Opcode_ae_s16_0_xp_funcUnit_uses }, + { "ae_s64.xc", ICLASS_AE_S64_XC, + 0, + Opcode_ae_s64_xc_encode_fns, 1, Opcode_ae_s64_xc_funcUnit_uses }, + { "ae_s64.xc1", ICLASS_AE_S64_XC1, + 0, + Opcode_ae_s64_xc1_encode_fns, 1, Opcode_ae_s64_xc1_funcUnit_uses }, + { "ae_s64.i", ICLASS_AE_S64_I, + 0, + Opcode_ae_s64_i_encode_fns, 1, Opcode_ae_s64_i_funcUnit_uses }, + { "ae_s64.ip", ICLASS_AE_S64_IP, + 0, + Opcode_ae_s64_ip_encode_fns, 1, Opcode_ae_s64_ip_funcUnit_uses }, + { "ae_s64.x", ICLASS_AE_S64_X, + 0, + Opcode_ae_s64_x_encode_fns, 1, Opcode_ae_s64_x_funcUnit_uses }, + { "ae_s64.xp", ICLASS_AE_S64_XP, + 0, + Opcode_ae_s64_xp_encode_fns, 1, Opcode_ae_s64_xp_funcUnit_uses }, + { "ae_s32m.xc", ICLASS_AE_S32M_XC, + 0, + Opcode_ae_s32m_xc_encode_fns, 1, Opcode_ae_s32m_xc_funcUnit_uses }, + { "ae_s32m.i", ICLASS_AE_S32M_I, + 0, + Opcode_ae_s32m_i_encode_fns, 1, Opcode_ae_s32m_i_funcUnit_uses }, + { "ae_s32m.iu", ICLASS_AE_S32M_IU, + 0, + Opcode_ae_s32m_iu_encode_fns, 1, Opcode_ae_s32m_iu_funcUnit_uses }, + { "ae_s32m.x", ICLASS_AE_S32M_X, + 0, + Opcode_ae_s32m_x_encode_fns, 1, Opcode_ae_s32m_x_funcUnit_uses }, + { "ae_s32m.xu", ICLASS_AE_S32M_XU, + 0, + Opcode_ae_s32m_xu_encode_fns, 1, Opcode_ae_s32m_xu_funcUnit_uses }, + { "ae_zalign64", ICLASS_AE_ZALIGN64, + 0, + Opcode_ae_zalign64_encode_fns, 0, 0 }, + { "ae_lalign64.i", ICLASS_AE_LALIGN64_I, + 0, + Opcode_ae_lalign64_i_encode_fns, 1, Opcode_ae_lalign64_i_funcUnit_uses }, + { "ae_salign64.i", ICLASS_AE_SALIGN64_I, + 0, + Opcode_ae_salign64_i_encode_fns, 1, Opcode_ae_salign64_i_funcUnit_uses }, + { "ae_movalign", ICLASS_AE_MOVALIGN, + 0, + Opcode_ae_movalign_encode_fns, 0, 0 }, + { "ae_la64.pp", ICLASS_AE_LA64_PP, + 0, + Opcode_ae_la64_pp_encode_fns, 1, Opcode_ae_la64_pp_funcUnit_uses }, + { "ae_la24pos.pc", ICLASS_AE_LA24POS_PC, + 0, + Opcode_ae_la24pos_pc_encode_fns, 1, Opcode_ae_la24pos_pc_funcUnit_uses }, + { "ae_la24x2pos.pc", ICLASS_AE_LA24X2POS_PC, + 0, + Opcode_ae_la24x2pos_pc_encode_fns, 1, Opcode_ae_la24x2pos_pc_funcUnit_uses }, + { "ae_la32x2pos.pc", ICLASS_AE_LA32X2POS_PC, + 0, + Opcode_ae_la32x2pos_pc_encode_fns, 1, Opcode_ae_la32x2pos_pc_funcUnit_uses }, + { "ae_la16x4pos.pc", ICLASS_AE_LA16X4POS_PC, + 0, + Opcode_ae_la16x4pos_pc_encode_fns, 1, Opcode_ae_la16x4pos_pc_funcUnit_uses }, + { "ae_la24neg.pc", ICLASS_AE_LA24NEG_PC, + 0, + Opcode_ae_la24neg_pc_encode_fns, 1, Opcode_ae_la24neg_pc_funcUnit_uses }, + { "ae_la24x2neg.pc", ICLASS_AE_LA24X2NEG_PC, + 0, + Opcode_ae_la24x2neg_pc_encode_fns, 1, Opcode_ae_la24x2neg_pc_funcUnit_uses }, + { "ae_la32x2neg.pc", ICLASS_AE_LA32X2NEG_PC, + 0, + Opcode_ae_la32x2neg_pc_encode_fns, 1, Opcode_ae_la32x2neg_pc_funcUnit_uses }, + { "ae_la16x4neg.pc", ICLASS_AE_LA16X4NEG_PC, + 0, + Opcode_ae_la16x4neg_pc_encode_fns, 1, Opcode_ae_la16x4neg_pc_funcUnit_uses }, + { "ae_la24pos.pc1", ICLASS_AE_LA24POS_PC1, + 0, + Opcode_ae_la24pos_pc1_encode_fns, 1, Opcode_ae_la24pos_pc1_funcUnit_uses }, + { "ae_la24x2pos.pc1", ICLASS_AE_LA24X2POS_PC1, + 0, + Opcode_ae_la24x2pos_pc1_encode_fns, 1, Opcode_ae_la24x2pos_pc1_funcUnit_uses }, + { "ae_la32x2pos.pc1", ICLASS_AE_LA32X2POS_PC1, + 0, + Opcode_ae_la32x2pos_pc1_encode_fns, 1, Opcode_ae_la32x2pos_pc1_funcUnit_uses }, + { "ae_la16x4pos.pc1", ICLASS_AE_LA16X4POS_PC1, + 0, + Opcode_ae_la16x4pos_pc1_encode_fns, 1, Opcode_ae_la16x4pos_pc1_funcUnit_uses }, + { "ae_la24neg.pc1", ICLASS_AE_LA24NEG_PC1, + 0, + Opcode_ae_la24neg_pc1_encode_fns, 1, Opcode_ae_la24neg_pc1_funcUnit_uses }, + { "ae_la24x2neg.pc1", ICLASS_AE_LA24X2NEG_PC1, + 0, + Opcode_ae_la24x2neg_pc1_encode_fns, 1, Opcode_ae_la24x2neg_pc1_funcUnit_uses }, + { "ae_la32x2neg.pc1", ICLASS_AE_LA32X2NEG_PC1, + 0, + Opcode_ae_la32x2neg_pc1_encode_fns, 1, Opcode_ae_la32x2neg_pc1_funcUnit_uses }, + { "ae_la16x4neg.pc1", ICLASS_AE_LA16X4NEG_PC1, + 0, + Opcode_ae_la16x4neg_pc1_encode_fns, 1, Opcode_ae_la16x4neg_pc1_funcUnit_uses }, + { "ae_sa64pos.fp", ICLASS_AE_SA64POS_FP, + 0, + Opcode_ae_sa64pos_fp_encode_fns, 1, Opcode_ae_sa64pos_fp_funcUnit_uses }, + { "ae_sa64neg.fp", ICLASS_AE_SA64NEG_FP, + 0, + Opcode_ae_sa64neg_fp_encode_fns, 1, Opcode_ae_sa64neg_fp_funcUnit_uses }, + { "ae_la32x2.ic", ICLASS_AE_LA32X2_IC, + 0, + Opcode_ae_la32x2_ic_encode_fns, 1, Opcode_ae_la32x2_ic_funcUnit_uses }, + { "ae_la32x2.ic1", ICLASS_AE_LA32X2_IC1, + 0, + Opcode_ae_la32x2_ic1_encode_fns, 1, Opcode_ae_la32x2_ic1_funcUnit_uses }, + { "ae_la32x2.ip", ICLASS_AE_LA32X2_IP, + 0, + Opcode_ae_la32x2_ip_encode_fns, 1, Opcode_ae_la32x2_ip_funcUnit_uses }, + { "ae_la32x2.rip", ICLASS_AE_LA32X2_RIP, + 0, + Opcode_ae_la32x2_rip_encode_fns, 1, Opcode_ae_la32x2_rip_funcUnit_uses }, + { "ae_la32x2.ric", ICLASS_AE_LA32X2_RIC, + 0, + Opcode_ae_la32x2_ric_encode_fns, 1, Opcode_ae_la32x2_ric_funcUnit_uses }, + { "ae_la32x2.ric1", ICLASS_AE_LA32X2_RIC1, + 0, + Opcode_ae_la32x2_ric1_encode_fns, 1, Opcode_ae_la32x2_ric1_funcUnit_uses }, + { "ae_la16x4.ic", ICLASS_AE_LA16X4_IC, + 0, + Opcode_ae_la16x4_ic_encode_fns, 1, Opcode_ae_la16x4_ic_funcUnit_uses }, + { "ae_la16x4.ic1", ICLASS_AE_LA16X4_IC1, + 0, + Opcode_ae_la16x4_ic1_encode_fns, 1, Opcode_ae_la16x4_ic1_funcUnit_uses }, + { "ae_la16x4.ip", ICLASS_AE_LA16X4_IP, + 0, + Opcode_ae_la16x4_ip_encode_fns, 1, Opcode_ae_la16x4_ip_funcUnit_uses }, + { "ae_la16x4.rip", ICLASS_AE_LA16X4_RIP, + 0, + Opcode_ae_la16x4_rip_encode_fns, 1, Opcode_ae_la16x4_rip_funcUnit_uses }, + { "ae_la16x4.ric", ICLASS_AE_LA16X4_RIC, + 0, + Opcode_ae_la16x4_ric_encode_fns, 1, Opcode_ae_la16x4_ric_funcUnit_uses }, + { "ae_la16x4.ric1", ICLASS_AE_LA16X4_RIC1, + 0, + Opcode_ae_la16x4_ric1_encode_fns, 1, Opcode_ae_la16x4_ric1_funcUnit_uses }, + { "ae_la32x2f24.ic", ICLASS_AE_LA32X2F24_IC, + 0, + Opcode_ae_la32x2f24_ic_encode_fns, 1, Opcode_ae_la32x2f24_ic_funcUnit_uses }, + { "ae_la32x2f24.ic1", ICLASS_AE_LA32X2F24_IC1, + 0, + Opcode_ae_la32x2f24_ic1_encode_fns, 1, Opcode_ae_la32x2f24_ic1_funcUnit_uses }, + { "ae_la32x2f24.ip", ICLASS_AE_LA32X2F24_IP, + 0, + Opcode_ae_la32x2f24_ip_encode_fns, 1, Opcode_ae_la32x2f24_ip_funcUnit_uses }, + { "ae_la32x2f24.rip", ICLASS_AE_LA32X2F24_RIP, + 0, + Opcode_ae_la32x2f24_rip_encode_fns, 1, Opcode_ae_la32x2f24_rip_funcUnit_uses }, + { "ae_la32x2f24.ric", ICLASS_AE_LA32X2F24_RIC, + 0, + Opcode_ae_la32x2f24_ric_encode_fns, 1, Opcode_ae_la32x2f24_ric_funcUnit_uses }, + { "ae_la32x2f24.ric1", ICLASS_AE_LA32X2F24_RIC1, + 0, + Opcode_ae_la32x2f24_ric1_encode_fns, 1, Opcode_ae_la32x2f24_ric1_funcUnit_uses }, + { "ae_la24.ic", ICLASS_AE_LA24_IC, + 0, + Opcode_ae_la24_ic_encode_fns, 1, Opcode_ae_la24_ic_funcUnit_uses }, + { "ae_la24.ic1", ICLASS_AE_LA24_IC1, + 0, + Opcode_ae_la24_ic1_encode_fns, 1, Opcode_ae_la24_ic1_funcUnit_uses }, + { "ae_la24.ip", ICLASS_AE_LA24_IP, + 0, + Opcode_ae_la24_ip_encode_fns, 1, Opcode_ae_la24_ip_funcUnit_uses }, + { "ae_la24.rip", ICLASS_AE_LA24_RIP, + 0, + Opcode_ae_la24_rip_encode_fns, 1, Opcode_ae_la24_rip_funcUnit_uses }, + { "ae_la24.ric", ICLASS_AE_LA24_RIC, + 0, + Opcode_ae_la24_ric_encode_fns, 1, Opcode_ae_la24_ric_funcUnit_uses }, + { "ae_la24.ric1", ICLASS_AE_LA24_RIC1, + 0, + Opcode_ae_la24_ric1_encode_fns, 1, Opcode_ae_la24_ric1_funcUnit_uses }, + { "ae_la24x2.ic", ICLASS_AE_LA24X2_IC, + 0, + Opcode_ae_la24x2_ic_encode_fns, 1, Opcode_ae_la24x2_ic_funcUnit_uses }, + { "ae_la24x2.ic1", ICLASS_AE_LA24X2_IC1, + 0, + Opcode_ae_la24x2_ic1_encode_fns, 1, Opcode_ae_la24x2_ic1_funcUnit_uses }, + { "ae_la24x2.ip", ICLASS_AE_LA24X2_IP, + 0, + Opcode_ae_la24x2_ip_encode_fns, 1, Opcode_ae_la24x2_ip_funcUnit_uses }, + { "ae_la24x2.rip", ICLASS_AE_LA24X2_RIP, + 0, + Opcode_ae_la24x2_rip_encode_fns, 1, Opcode_ae_la24x2_rip_funcUnit_uses }, + { "ae_la24x2.ric", ICLASS_AE_LA24X2_RIC, + 0, + Opcode_ae_la24x2_ric_encode_fns, 1, Opcode_ae_la24x2_ric_funcUnit_uses }, + { "ae_la24x2.ric1", ICLASS_AE_LA24X2_RIC1, + 0, + Opcode_ae_la24x2_ric1_encode_fns, 1, Opcode_ae_la24x2_ric1_funcUnit_uses }, + { "ae_sa32x2.ic", ICLASS_AE_SA32X2_IC, + 0, + Opcode_ae_sa32x2_ic_encode_fns, 1, Opcode_ae_sa32x2_ic_funcUnit_uses }, + { "ae_sa32x2.ic1", ICLASS_AE_SA32X2_IC1, + 0, + Opcode_ae_sa32x2_ic1_encode_fns, 1, Opcode_ae_sa32x2_ic1_funcUnit_uses }, + { "ae_sa32x2.ip", ICLASS_AE_SA32X2_IP, + 0, + Opcode_ae_sa32x2_ip_encode_fns, 1, Opcode_ae_sa32x2_ip_funcUnit_uses }, + { "ae_sa32x2.rip", ICLASS_AE_SA32X2_RIP, + 0, + Opcode_ae_sa32x2_rip_encode_fns, 1, Opcode_ae_sa32x2_rip_funcUnit_uses }, + { "ae_sa32x2.ric", ICLASS_AE_SA32X2_RIC, + 0, + Opcode_ae_sa32x2_ric_encode_fns, 1, Opcode_ae_sa32x2_ric_funcUnit_uses }, + { "ae_sa32x2.ric1", ICLASS_AE_SA32X2_RIC1, + 0, + Opcode_ae_sa32x2_ric1_encode_fns, 1, Opcode_ae_sa32x2_ric1_funcUnit_uses }, + { "ae_sa16x4.ic", ICLASS_AE_SA16X4_IC, + 0, + Opcode_ae_sa16x4_ic_encode_fns, 1, Opcode_ae_sa16x4_ic_funcUnit_uses }, + { "ae_sa16x4.ic1", ICLASS_AE_SA16X4_IC1, + 0, + Opcode_ae_sa16x4_ic1_encode_fns, 1, Opcode_ae_sa16x4_ic1_funcUnit_uses }, + { "ae_sa16x4.ip", ICLASS_AE_SA16X4_IP, + 0, + Opcode_ae_sa16x4_ip_encode_fns, 1, Opcode_ae_sa16x4_ip_funcUnit_uses }, + { "ae_sa16x4.rip", ICLASS_AE_SA16X4_RIP, + 0, + Opcode_ae_sa16x4_rip_encode_fns, 1, Opcode_ae_sa16x4_rip_funcUnit_uses }, + { "ae_sa16x4.ric", ICLASS_AE_SA16X4_RIC, + 0, + Opcode_ae_sa16x4_ric_encode_fns, 1, Opcode_ae_sa16x4_ric_funcUnit_uses }, + { "ae_sa16x4.ric1", ICLASS_AE_SA16X4_RIC1, + 0, + Opcode_ae_sa16x4_ric1_encode_fns, 1, Opcode_ae_sa16x4_ric1_funcUnit_uses }, + { "ae_sa32x2f24.ic", ICLASS_AE_SA32X2F24_IC, + 0, + Opcode_ae_sa32x2f24_ic_encode_fns, 1, Opcode_ae_sa32x2f24_ic_funcUnit_uses }, + { "ae_sa32x2f24.ic1", ICLASS_AE_SA32X2F24_IC1, + 0, + Opcode_ae_sa32x2f24_ic1_encode_fns, 1, Opcode_ae_sa32x2f24_ic1_funcUnit_uses }, + { "ae_sa32x2f24.ip", ICLASS_AE_SA32X2F24_IP, + 0, + Opcode_ae_sa32x2f24_ip_encode_fns, 1, Opcode_ae_sa32x2f24_ip_funcUnit_uses }, + { "ae_sa32x2f24.rip", ICLASS_AE_SA32X2F24_RIP, + 0, + Opcode_ae_sa32x2f24_rip_encode_fns, 1, Opcode_ae_sa32x2f24_rip_funcUnit_uses }, + { "ae_sa32x2f24.ric", ICLASS_AE_SA32X2F24_RIC, + 0, + Opcode_ae_sa32x2f24_ric_encode_fns, 1, Opcode_ae_sa32x2f24_ric_funcUnit_uses }, + { "ae_sa32x2f24.ric1", ICLASS_AE_SA32X2F24_RIC1, + 0, + Opcode_ae_sa32x2f24_ric1_encode_fns, 1, Opcode_ae_sa32x2f24_ric1_funcUnit_uses }, + { "ae_sa24.l.ic", ICLASS_AE_SA24_L_IC, + 0, + Opcode_ae_sa24_l_ic_encode_fns, 1, Opcode_ae_sa24_l_ic_funcUnit_uses }, + { "ae_sa24.l.ic1", ICLASS_AE_SA24_L_IC1, + 0, + Opcode_ae_sa24_l_ic1_encode_fns, 1, Opcode_ae_sa24_l_ic1_funcUnit_uses }, + { "ae_sa24.l.ip", ICLASS_AE_SA24_L_IP, + 0, + Opcode_ae_sa24_l_ip_encode_fns, 1, Opcode_ae_sa24_l_ip_funcUnit_uses }, + { "ae_sa24.l.rip", ICLASS_AE_SA24_L_RIP, + 0, + Opcode_ae_sa24_l_rip_encode_fns, 1, Opcode_ae_sa24_l_rip_funcUnit_uses }, + { "ae_sa24.l.ric", ICLASS_AE_SA24_L_RIC, + 0, + Opcode_ae_sa24_l_ric_encode_fns, 1, Opcode_ae_sa24_l_ric_funcUnit_uses }, + { "ae_sa24.l.ric1", ICLASS_AE_SA24_L_RIC1, + 0, + Opcode_ae_sa24_l_ric1_encode_fns, 1, Opcode_ae_sa24_l_ric1_funcUnit_uses }, + { "ae_sa24x2.ic", ICLASS_AE_SA24X2_IC, + 0, + Opcode_ae_sa24x2_ic_encode_fns, 1, Opcode_ae_sa24x2_ic_funcUnit_uses }, + { "ae_sa24x2.ic1", ICLASS_AE_SA24X2_IC1, + 0, + Opcode_ae_sa24x2_ic1_encode_fns, 1, Opcode_ae_sa24x2_ic1_funcUnit_uses }, + { "ae_sa24x2.ip", ICLASS_AE_SA24X2_IP, + 0, + Opcode_ae_sa24x2_ip_encode_fns, 1, Opcode_ae_sa24x2_ip_funcUnit_uses }, + { "ae_sa24x2.rip", ICLASS_AE_SA24X2_RIP, + 0, + Opcode_ae_sa24x2_rip_encode_fns, 1, Opcode_ae_sa24x2_rip_funcUnit_uses }, + { "ae_sa24x2.ric", ICLASS_AE_SA24X2_RIC, + 0, + Opcode_ae_sa24x2_ric_encode_fns, 1, Opcode_ae_sa24x2_ric_funcUnit_uses }, + { "ae_sa24x2.ric1", ICLASS_AE_SA24X2_RIC1, + 0, + Opcode_ae_sa24x2_ric1_encode_fns, 1, Opcode_ae_sa24x2_ric1_funcUnit_uses }, + { "ae_addicirc", ICLASS_AE_ADDICIRC, + 0, + Opcode_ae_addicirc_encode_fns, 0, 0 }, + { "ae_addcirc.xc1", ICLASS_AE_ADDCIRC_XC1, + 0, + Opcode_ae_addcirc_xc1_encode_fns, 0, 0 }, + { "ae_addcirc.xc", ICLASS_AE_ADDCIRC_XC, + 0, + Opcode_ae_addcirc_xc_encode_fns, 0, 0 }, + { "ae_s32ra64s.i", ICLASS_AE_S32RA64S_I, + 0, + Opcode_ae_s32ra64s_i_encode_fns, 1, Opcode_ae_s32ra64s_i_funcUnit_uses }, + { "ae_s32ra64s.ip", ICLASS_AE_S32RA64S_IP, + 0, + Opcode_ae_s32ra64s_ip_encode_fns, 1, Opcode_ae_s32ra64s_ip_funcUnit_uses }, + { "ae_s32ra64s.x", ICLASS_AE_S32RA64S_X, + 0, + Opcode_ae_s32ra64s_x_encode_fns, 1, Opcode_ae_s32ra64s_x_funcUnit_uses }, + { "ae_s32ra64s.xp", ICLASS_AE_S32RA64S_XP, + 0, + Opcode_ae_s32ra64s_xp_encode_fns, 1, Opcode_ae_s32ra64s_xp_funcUnit_uses }, + { "ae_s32ra64s.xc", ICLASS_AE_S32RA64S_XC, + 0, + Opcode_ae_s32ra64s_xc_encode_fns, 1, Opcode_ae_s32ra64s_xc_funcUnit_uses }, + { "ae_s32ra64s.xc1", ICLASS_AE_S32RA64S_XC1, + 0, + Opcode_ae_s32ra64s_xc1_encode_fns, 1, Opcode_ae_s32ra64s_xc1_funcUnit_uses }, + { "ae_s24ra64s.i", ICLASS_AE_S24RA64S_I, + 0, + Opcode_ae_s24ra64s_i_encode_fns, 1, Opcode_ae_s24ra64s_i_funcUnit_uses }, + { "ae_s24ra64s.ip", ICLASS_AE_S24RA64S_IP, + 0, + Opcode_ae_s24ra64s_ip_encode_fns, 1, Opcode_ae_s24ra64s_ip_funcUnit_uses }, + { "ae_s24ra64s.x", ICLASS_AE_S24RA64S_X, + 0, + Opcode_ae_s24ra64s_x_encode_fns, 1, Opcode_ae_s24ra64s_x_funcUnit_uses }, + { "ae_s24ra64s.xp", ICLASS_AE_S24RA64S_XP, + 0, + Opcode_ae_s24ra64s_xp_encode_fns, 1, Opcode_ae_s24ra64s_xp_funcUnit_uses }, + { "ae_s24ra64s.xc", ICLASS_AE_S24RA64S_XC, + 0, + Opcode_ae_s24ra64s_xc_encode_fns, 1, Opcode_ae_s24ra64s_xc_funcUnit_uses }, + { "ae_s24ra64s.xc1", ICLASS_AE_S24RA64S_XC1, + 0, + Opcode_ae_s24ra64s_xc1_encode_fns, 1, Opcode_ae_s24ra64s_xc1_funcUnit_uses }, + { "ae_s32x2ra64s.ip", ICLASS_AE_S32X2RA64S_IP, + 0, + Opcode_ae_s32x2ra64s_ip_encode_fns, 1, Opcode_ae_s32x2ra64s_ip_funcUnit_uses }, + { "ae_s24x2ra64s.ip", ICLASS_AE_S24X2RA64S_IP, + 0, + Opcode_ae_s24x2ra64s_ip_encode_fns, 1, Opcode_ae_s24x2ra64s_ip_funcUnit_uses }, + { "ae_addbrba32", ICLASS_AE_ADDBRBA32, + 0, + Opcode_ae_addbrba32_encode_fns, 0, 0 }, + { "ae_bitswap", ICLASS_AE_BITSWAP, + 0, + Opcode_ae_bitswap_encode_fns, 0, 0 }, + { "ae_mul32js", ICLASS_AE_MUL32JS, + 0, + Opcode_ae_mul32js_encode_fns, 0, 0 }, + { "ae_addandsub32s", ICLASS_AE_ADDANDSUB32S, + 0, + Opcode_ae_addandsub32s_encode_fns, 0, 0 }, + { "ae_addandsubrng32", ICLASS_AE_ADDANDSUBRNG32, + 0, + Opcode_ae_addandsubrng32_encode_fns, 0, 0 }, + { "ae_addrng32", ICLASS_AE_ADDRNG32, + 0, + Opcode_ae_addrng32_encode_fns, 0, 0 }, + { "ae_subrng32", ICLASS_AE_SUBRNG32, + 0, + Opcode_ae_subrng32_encode_fns, 0, 0 }, + { "ae_calcrng3", ICLASS_AE_CALCRNG3, + 0, + Opcode_ae_calcrng3_encode_fns, 0, 0 }, + { "ae_calcrng2", ICLASS_AE_CALCRNG2, + 0, + Opcode_ae_calcrng2_encode_fns, 0, 0 }, + { "ae_calcrng1", ICLASS_AE_CALCRNG1, + 0, + Opcode_ae_calcrng1_encode_fns, 0, 0 }, + { "ae_rng32x2", ICLASS_AE_RNG32X2, + 0, + Opcode_ae_rng32x2_encode_fns, 0, 0 }, + { "ae_sel16i", ICLASS_AE_SEL16I, + 0, + Opcode_ae_sel16i_encode_fns, 0, 0 }, + { "ae_sel16i.n", ICLASS_AE_SEL16I_N, + 0, + Opcode_ae_sel16i_n_encode_fns, 0, 0 }, + { "ae_shortswap", ICLASS_AE_SHORTSWAP, + 0, + Opcode_ae_shortswap_encode_fns, 0, 0 }, + { "ae_movab4", ICLASS_AE_MOVAB4, + 0, + Opcode_ae_movab4_encode_fns, 0, 0 }, + { "ae_movab2", ICLASS_AE_MOVAB2, + 0, + Opcode_ae_movab2_encode_fns, 0, 0 }, + { "ae_movab", ICLASS_AE_MOVAB, + 0, + Opcode_ae_movab_encode_fns, 0, 0 }, + { "ae_movba", ICLASS_AE_MOVBA, + 0, + Opcode_ae_movba_encode_fns, 0, 0 }, + { "ae_movba1x2", ICLASS_AE_MOVBA1X2, + 0, + Opcode_ae_movba1x2_encode_fns, 0, 0 }, + { "ae_movba4", ICLASS_AE_MOVBA4, + 0, + Opcode_ae_movba4_encode_fns, 0, 0 }, + { "ae_movba2", ICLASS_AE_MOVBA2, + 0, + Opcode_ae_movba2_encode_fns, 0, 0 }, + { "ae_movb2", ICLASS_AE_MOVB2, + 0, + Opcode_ae_movb2_encode_fns, 0, 0 }, + { "ae_movb4", ICLASS_AE_MOVB4, + 0, + Opcode_ae_movb4_encode_fns, 0, 0 }, + { "ae_movt16x4", ICLASS_AE_MOVT16X4, + 0, + Opcode_ae_movt16x4_encode_fns, 0, 0 }, + { "ae_movf16x4", ICLASS_AE_MOVF16X4, + 0, + Opcode_ae_movf16x4_encode_fns, 0, 0 }, + { "ae_movt32x2", ICLASS_AE_MOVT32X2, + 0, + Opcode_ae_movt32x2_encode_fns, 0, 0 }, + { "ae_movf32x2", ICLASS_AE_MOVF32X2, + 0, + Opcode_ae_movf32x2_encode_fns, 0, 0 }, + { "ae_movsara7x2", ICLASS_AE_MOVSARA7X2, + 0, + Opcode_ae_movsara7x2_encode_fns, 0, 0 }, + { "ae_movsard7", ICLASS_AE_MOVSARD7, + 0, + Opcode_ae_movsard7_encode_fns, 0, 0 }, + { "ae_movasar", ICLASS_AE_MOVASAR, + 0, + Opcode_ae_movasar_encode_fns, 0, 0 }, + { "ae_movda32x2", ICLASS_AE_MOVDA32X2, + 0, + Opcode_ae_movda32x2_encode_fns, 0, 0 }, + { "ae_movda32", ICLASS_AE_MOVDA32, + 0, + Opcode_ae_movda32_encode_fns, 0, 0 }, + { "ae_movda16x2", ICLASS_AE_MOVDA16X2, + 0, + Opcode_ae_movda16x2_encode_fns, 0, 0 }, + { "ae_movda16", ICLASS_AE_MOVDA16, + 0, + Opcode_ae_movda16_encode_fns, 0, 0 }, + { "ae_movi", ICLASS_AE_MOVI, + 0, + Opcode_ae_movi_encode_fns, 0, 0 }, + { "ae_truncp24a32x2", ICLASS_AE_TRUNCP24A32X2, + 0, + Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, + { "ae_sat16x4", ICLASS_AE_SAT16X4, + 0, + Opcode_ae_sat16x4_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.32", ICLASS_AE_CVT32X2F16_32, + 0, + Opcode_ae_cvt32x2f16_32_encode_fns, 0, 0 }, + { "ae_cvt32x2f16.10", ICLASS_AE_CVT32X2F16_10, + 0, + Opcode_ae_cvt32x2f16_10_encode_fns, 0, 0 }, + { "ae_sext32x2d16.32", ICLASS_AE_SEXT32X2D16_32, + 0, + Opcode_ae_sext32x2d16_32_encode_fns, 0, 0 }, + { "ae_sext32x2d16.10", ICLASS_AE_SEXT32X2D16_10, + 0, + Opcode_ae_sext32x2d16_10_encode_fns, 0, 0 }, + { "ae_cvta32f24s.l", ICLASS_AE_CVTA32F24S_L, + 0, + Opcode_ae_cvta32f24s_l_encode_fns, 0, 0 }, + { "ae_cvta32f24s.h", ICLASS_AE_CVTA32F24S_H, + 0, + Opcode_ae_cvta32f24s_h_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.ll", ICLASS_AE_CVTP24A16X2_LL, + 0, + Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.lh", ICLASS_AE_CVTP24A16X2_LH, + 0, + Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hl", ICLASS_AE_CVTP24A16X2_HL, + 0, + Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, + { "ae_cvtp24a16x2.hh", ICLASS_AE_CVTP24A16X2_HH, + 0, + Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, + { "ae_truncp24q48x2", ICLASS_AE_TRUNCP24Q48X2, + 0, + Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, + { "ae_trunca32x2f64s", ICLASS_AE_TRUNCA32X2F64S, + 0, + Opcode_ae_trunca32x2f64s_encode_fns, 0, 0 }, + { "ae_trunci32x2f64s", ICLASS_AE_TRUNCI32X2F64S, + 0, + Opcode_ae_trunci32x2f64s_encode_fns, 0, 0 }, + { "ae_trunca32f64s.l", ICLASS_AE_TRUNCA32F64S_L, + 0, + Opcode_ae_trunca32f64s_l_encode_fns, 0, 0 }, + { "ae_trunci32f64s.l", ICLASS_AE_TRUNCI32F64S_L, + 0, + Opcode_ae_trunci32f64s_l_encode_fns, 0, 0 }, + { "ae_truncp16", ICLASS_AE_TRUNCP16, + 0, + Opcode_ae_truncp16_encode_fns, 0, 0 }, + { "ae_round32x2f64ssym", ICLASS_AE_ROUND32X2F64SSYM, + 0, + Opcode_ae_round32x2f64ssym_encode_fns, 0, 0 }, + { "ae_round32x2f64sasym", ICLASS_AE_ROUND32X2F64SASYM, + 0, + Opcode_ae_round32x2f64sasym_encode_fns, 0, 0 }, + { "ae_round32x2f48ssym", ICLASS_AE_ROUND32X2F48SSYM, + 0, + Opcode_ae_round32x2f48ssym_encode_fns, 0, 0 }, + { "ae_round32x2f48sasym", ICLASS_AE_ROUND32X2F48SASYM, + 0, + Opcode_ae_round32x2f48sasym_encode_fns, 0, 0 }, + { "ae_round16x4f32ssym", ICLASS_AE_ROUND16X4F32SSYM, + 0, + Opcode_ae_round16x4f32ssym_encode_fns, 0, 0 }, + { "ae_round16x4f32sasym", ICLASS_AE_ROUND16X4F32SASYM, + 0, + Opcode_ae_round16x4f32sasym_encode_fns, 0, 0 }, + { "ae_round24x2f48ssym", ICLASS_AE_ROUND24X2F48SSYM, + 0, + Opcode_ae_round24x2f48ssym_encode_fns, 0, 0 }, + { "ae_round24x2f48sasym", ICLASS_AE_ROUND24X2F48SASYM, + 0, + Opcode_ae_round24x2f48sasym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2sym", ICLASS_AE_ROUNDSP16Q48X2SYM, + 0, + Opcode_ae_roundsp16q48x2sym_encode_fns, 0, 0 }, + { "ae_roundsp16q48x2asym", ICLASS_AE_ROUNDSP16Q48X2ASYM, + 0, + Opcode_ae_roundsp16q48x2asym_encode_fns, 0, 0 }, + { "ae_minabs32s", ICLASS_AE_MINABS32S, + 0, + Opcode_ae_minabs32s_encode_fns, 0, 0 }, + { "ae_maxabs32s", ICLASS_AE_MAXABS32S, + 0, + Opcode_ae_maxabs32s_encode_fns, 0, 0 }, + { "ae_roundsp16f24sym", ICLASS_AE_ROUNDSP16F24SYM, + 0, + Opcode_ae_roundsp16f24sym_encode_fns, 0, 0 }, + { "ae_roundsp16f24asym", ICLASS_AE_ROUNDSP16F24ASYM, + 0, + Opcode_ae_roundsp16f24asym_encode_fns, 0, 0 }, + { "ae_mov", ICLASS_AE_MOV, + 0, + Opcode_ae_mov_encode_fns, 0, 0 }, + { "ae_movt64", ICLASS_AE_MOVT64, + 0, + Opcode_ae_movt64_encode_fns, 0, 0 }, + { "ae_movf64", ICLASS_AE_MOVF64, + 0, + Opcode_ae_movf64_encode_fns, 0, 0 }, + { "ae_cvtq56a32s", ICLASS_AE_CVTQ56A32S, + 0, + Opcode_ae_cvtq56a32s_encode_fns, 0, 0 }, + { "ae_cvt48a32", ICLASS_AE_CVT48A32, + 0, + Opcode_ae_cvt48a32_encode_fns, 0, 0 }, + { "ae_cvt64a32", ICLASS_AE_CVT64A32, + 0, + Opcode_ae_cvt64a32_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.l", ICLASS_AE_CVTQ56P32S_L, + 0, + Opcode_ae_cvtq56p32s_l_encode_fns, 0, 0 }, + { "ae_cvtq56p32s.h", ICLASS_AE_CVTQ56P32S_H, + 0, + Opcode_ae_cvtq56p32s_h_encode_fns, 0, 0 }, + { "ae_cvt64f32.h", ICLASS_AE_CVT64F32_H, + 0, + Opcode_ae_cvt64f32_h_encode_fns, 0, 0 }, + { "ae_cvt48f32.l", ICLASS_AE_CVT48F32_L, + 0, + Opcode_ae_cvt48f32_l_encode_fns, 0, 0 }, + { "ae_cvt48f32.h", ICLASS_AE_CVT48F32_H, + 0, + Opcode_ae_cvt48f32_h_encode_fns, 0, 0 }, + { "ae_sat48s", ICLASS_AE_SAT48S, + 0, + Opcode_ae_sat48s_encode_fns, 0, 0 }, + { "ae_satq56s", ICLASS_AE_SATQ56S, + 0, + Opcode_ae_satq56s_encode_fns, 0, 0 }, + { "ae_sat24s", ICLASS_AE_SAT24S, + 0, + Opcode_ae_sat24s_encode_fns, 0, 0 }, + { "ae_truncq32", ICLASS_AE_TRUNCQ32, + 0, + Opcode_ae_truncq32_encode_fns, 0, 0 }, + { "ae_minabs64s", ICLASS_AE_MINABS64S, + 0, + Opcode_ae_minabs64s_encode_fns, 0, 0 }, + { "ae_maxabs64s", ICLASS_AE_MAXABS64S, + 0, + Opcode_ae_maxabs64s_encode_fns, 0, 0 }, + { "ae_roundsq32f48sym", ICLASS_AE_ROUNDSQ32F48SYM, + 0, + Opcode_ae_roundsq32f48sym_encode_fns, 0, 0 }, + { "ae_roundsq32f48asym", ICLASS_AE_ROUNDSQ32F48ASYM, + 0, + Opcode_ae_roundsq32f48asym_encode_fns, 0, 0 }, + { "ae_trunca32q48", ICLASS_AE_TRUNCA32Q48, + 0, + Opcode_ae_trunca32q48_encode_fns, 0, 0 }, + { "ae_movad32.l", ICLASS_AE_MOVAD32_L, + 0, + Opcode_ae_movad32_l_encode_fns, 0, 0 }, + { "ae_movad32.h", ICLASS_AE_MOVAD32_H, + 0, + Opcode_ae_movad32_h_encode_fns, 0, 0 }, + { "ae_movad16.3", ICLASS_AE_MOVAD16_3, + 0, + Opcode_ae_movad16_3_encode_fns, 0, 0 }, + { "ae_movad16.2", ICLASS_AE_MOVAD16_2, + 0, + Opcode_ae_movad16_2_encode_fns, 0, 0 }, + { "ae_movad16.1", ICLASS_AE_MOVAD16_1, + 0, + Opcode_ae_movad16_1_encode_fns, 0, 0 }, + { "ae_movad16.0", ICLASS_AE_MOVAD16_0, + 0, + Opcode_ae_movad16_0_encode_fns, 0, 0 }, + { "ae_sra64_32", ICLASS_AE_SRA64_32, + 0, + Opcode_ae_sra64_32_encode_fns, 0, 0 }, + { "ae_pksr32", ICLASS_AE_PKSR32, + 0, + Opcode_ae_pksr32_encode_fns, 0, 0 }, + { "ae_pksr24", ICLASS_AE_PKSR24, + 0, + Opcode_ae_pksr24_encode_fns, 0, 0 }, + { "ae_pksrf32", ICLASS_AE_PKSRF32, + 0, + Opcode_ae_pksrf32_encode_fns, 0, 0 }, + { "ae_trunca16p24s.l", ICLASS_AE_TRUNCA16P24S_L, + 0, + Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, + { "ae_trunca16p24s.h", ICLASS_AE_TRUNCA16P24S_H, + 0, + Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, + { "ae_add32", ICLASS_AE_ADD32, + 0, + Opcode_ae_add32_encode_fns, 0, 0 }, + { "ae_sub32", ICLASS_AE_SUB32, + 0, + Opcode_ae_sub32_encode_fns, 0, 0 }, + { "ae_addsub32", ICLASS_AE_ADDSUB32, + 0, + Opcode_ae_addsub32_encode_fns, 0, 0 }, + { "ae_subadd32", ICLASS_AE_SUBADD32, + 0, + Opcode_ae_subadd32_encode_fns, 0, 0 }, + { "ae_add16", ICLASS_AE_ADD16, + 0, + Opcode_ae_add16_encode_fns, 0, 0 }, + { "ae_sub16", ICLASS_AE_SUB16, + 0, + Opcode_ae_sub16_encode_fns, 0, 0 }, + { "ae_add32_hl_lh", ICLASS_AE_ADD32_HL_LH, + 0, + Opcode_ae_add32_hl_lh_encode_fns, 0, 0 }, + { "ae_neg32", ICLASS_AE_NEG32, + 0, + Opcode_ae_neg32_encode_fns, 0, 0 }, + { "ae_abs32", ICLASS_AE_ABS32, + 0, + Opcode_ae_abs32_encode_fns, 0, 0 }, + { "ae_add24s", ICLASS_AE_ADD24S, + 0, + Opcode_ae_add24s_encode_fns, 0, 0 }, + { "ae_sub24s", ICLASS_AE_SUB24S, + 0, + Opcode_ae_sub24s_encode_fns, 0, 0 }, + { "ae_add32s", ICLASS_AE_ADD32S, + 0, + Opcode_ae_add32s_encode_fns, 0, 0 }, + { "ae_sub32s", ICLASS_AE_SUB32S, + 0, + Opcode_ae_sub32s_encode_fns, 0, 0 }, + { "ae_addsub32s", ICLASS_AE_ADDSUB32S, + 0, + Opcode_ae_addsub32s_encode_fns, 0, 0 }, + { "ae_subadd32s", ICLASS_AE_SUBADD32S, + 0, + Opcode_ae_subadd32s_encode_fns, 0, 0 }, + { "ae_add16s", ICLASS_AE_ADD16S, + 0, + Opcode_ae_add16s_encode_fns, 0, 0 }, + { "ae_sub16s", ICLASS_AE_SUB16S, + 0, + Opcode_ae_sub16s_encode_fns, 0, 0 }, + { "ae_add32s_hl_lh", ICLASS_AE_ADD32S_HL_LH, + 0, + Opcode_ae_add32s_hl_lh_encode_fns, 0, 0 }, + { "ae_neg24s", ICLASS_AE_NEG24S, + 0, + Opcode_ae_neg24s_encode_fns, 0, 0 }, + { "ae_abs24s", ICLASS_AE_ABS24S, + 0, + Opcode_ae_abs24s_encode_fns, 0, 0 }, + { "ae_neg32s", ICLASS_AE_NEG32S, + 0, + Opcode_ae_neg32s_encode_fns, 0, 0 }, + { "ae_abs32s", ICLASS_AE_ABS32S, + 0, + Opcode_ae_abs32s_encode_fns, 0, 0 }, + { "ae_neg16s", ICLASS_AE_NEG16S, + 0, + Opcode_ae_neg16s_encode_fns, 0, 0 }, + { "ae_abs16s", ICLASS_AE_ABS16S, + 0, + Opcode_ae_abs16s_encode_fns, 0, 0 }, + { "ae_lt16", ICLASS_AE_LT16, + 0, + Opcode_ae_lt16_encode_fns, 0, 0 }, + { "ae_le16", ICLASS_AE_LE16, + 0, + Opcode_ae_le16_encode_fns, 0, 0 }, + { "ae_eq16", ICLASS_AE_EQ16, + 0, + Opcode_ae_eq16_encode_fns, 0, 0 }, + { "ae_lt32", ICLASS_AE_LT32, + 0, + Opcode_ae_lt32_encode_fns, 0, 0 }, + { "ae_le32", ICLASS_AE_LE32, + 0, + Opcode_ae_le32_encode_fns, 0, 0 }, + { "ae_eq32", ICLASS_AE_EQ32, + 0, + Opcode_ae_eq32_encode_fns, 0, 0 }, + { "ae_min32", ICLASS_AE_MIN32, + 0, + Opcode_ae_min32_encode_fns, 0, 0 }, + { "ae_max32", ICLASS_AE_MAX32, + 0, + Opcode_ae_max32_encode_fns, 0, 0 }, + { "ae_add64", ICLASS_AE_ADD64, + 0, + Opcode_ae_add64_encode_fns, 0, 0 }, + { "ae_sub64", ICLASS_AE_SUB64, + 0, + Opcode_ae_sub64_encode_fns, 0, 0 }, + { "ae_neg64", ICLASS_AE_NEG64, + 0, + Opcode_ae_neg64_encode_fns, 0, 0 }, + { "ae_abs64", ICLASS_AE_ABS64, + 0, + Opcode_ae_abs64_encode_fns, 0, 0 }, + { "ae_addsq56s", ICLASS_AE_ADDSQ56S, + 0, + Opcode_ae_addsq56s_encode_fns, 0, 0 }, + { "ae_subsq56s", ICLASS_AE_SUBSQ56S, + 0, + Opcode_ae_subsq56s_encode_fns, 0, 0 }, + { "ae_add64s", ICLASS_AE_ADD64S, + 0, + Opcode_ae_add64s_encode_fns, 0, 0 }, + { "ae_sub64s", ICLASS_AE_SUB64S, + 0, + Opcode_ae_sub64s_encode_fns, 0, 0 }, + { "ae_negsq56s", ICLASS_AE_NEGSQ56S, + 0, + Opcode_ae_negsq56s_encode_fns, 0, 0 }, + { "ae_abssq56s", ICLASS_AE_ABSSQ56S, + 0, + Opcode_ae_abssq56s_encode_fns, 0, 0 }, + { "ae_neg64s", ICLASS_AE_NEG64S, + 0, + Opcode_ae_neg64s_encode_fns, 0, 0 }, + { "ae_abs64s", ICLASS_AE_ABS64S, + 0, + Opcode_ae_abs64s_encode_fns, 0, 0 }, + { "ae_and", ICLASS_AE_AND, + 0, + Opcode_ae_and_encode_fns, 0, 0 }, + { "ae_nand", ICLASS_AE_NAND, + 0, + Opcode_ae_nand_encode_fns, 0, 0 }, + { "ae_or", ICLASS_AE_OR, + 0, + Opcode_ae_or_encode_fns, 0, 0 }, + { "ae_xor", ICLASS_AE_XOR, + 0, + Opcode_ae_xor_encode_fns, 0, 0 }, + { "ae_slai24", ICLASS_AE_SLAI24, + 0, + Opcode_ae_slai24_encode_fns, 0, 0 }, + { "ae_srli24", ICLASS_AE_SRLI24, + 0, + Opcode_ae_srli24_encode_fns, 0, 0 }, + { "ae_srai24", ICLASS_AE_SRAI24, + 0, + Opcode_ae_srai24_encode_fns, 0, 0 }, + { "ae_slas24", ICLASS_AE_SLAS24, + 0, + Opcode_ae_slas24_encode_fns, 0, 0 }, + { "ae_srls24", ICLASS_AE_SRLS24, + 0, + Opcode_ae_srls24_encode_fns, 0, 0 }, + { "ae_sras24", ICLASS_AE_SRAS24, + 0, + Opcode_ae_sras24_encode_fns, 0, 0 }, + { "ae_srai16", ICLASS_AE_SRAI16, + 0, + Opcode_ae_srai16_encode_fns, 0, 0 }, + { "ae_srai16r", ICLASS_AE_SRAI16R, + 0, + Opcode_ae_srai16r_encode_fns, 0, 0 }, + { "ae_slai32", ICLASS_AE_SLAI32, + 0, + Opcode_ae_slai32_encode_fns, 0, 0 }, + { "ae_srli32", ICLASS_AE_SRLI32, + 0, + Opcode_ae_srli32_encode_fns, 0, 0 }, + { "ae_srai32", ICLASS_AE_SRAI32, + 0, + Opcode_ae_srai32_encode_fns, 0, 0 }, + { "ae_srai32r", ICLASS_AE_SRAI32R, + 0, + Opcode_ae_srai32r_encode_fns, 0, 0 }, + { "ae_slas32", ICLASS_AE_SLAS32, + 0, + Opcode_ae_slas32_encode_fns, 0, 0 }, + { "ae_srls32", ICLASS_AE_SRLS32, + 0, + Opcode_ae_srls32_encode_fns, 0, 0 }, + { "ae_sras32", ICLASS_AE_SRAS32, + 0, + Opcode_ae_sras32_encode_fns, 0, 0 }, + { "ae_slaa32", ICLASS_AE_SLAA32, + 0, + Opcode_ae_slaa32_encode_fns, 0, 0 }, + { "ae_srla32", ICLASS_AE_SRLA32, + 0, + Opcode_ae_srla32_encode_fns, 0, 0 }, + { "ae_sraa32", ICLASS_AE_SRAA32, + 0, + Opcode_ae_sraa32_encode_fns, 0, 0 }, + { "ae_slai16s", ICLASS_AE_SLAI16S, + 0, + Opcode_ae_slai16s_encode_fns, 0, 0 }, + { "ae_slaa16s", ICLASS_AE_SLAA16S, + 0, + Opcode_ae_slaa16s_encode_fns, 0, 0 }, + { "ae_sraa16s", ICLASS_AE_SRAA16S, + 0, + Opcode_ae_sraa16s_encode_fns, 0, 0 }, + { "ae_sraa16rs", ICLASS_AE_SRAA16RS, + 0, + Opcode_ae_sraa16rs_encode_fns, 0, 0 }, + { "ae_slai24s", ICLASS_AE_SLAI24S, + 0, + Opcode_ae_slai24s_encode_fns, 0, 0 }, + { "ae_slas24s", ICLASS_AE_SLAS24S, + 0, + Opcode_ae_slas24s_encode_fns, 0, 0 }, + { "ae_slai32s", ICLASS_AE_SLAI32S, + 0, + Opcode_ae_slai32s_encode_fns, 0, 0 }, + { "ae_slas32s", ICLASS_AE_SLAS32S, + 0, + Opcode_ae_slas32s_encode_fns, 0, 0 }, + { "ae_slaa32s", ICLASS_AE_SLAA32S, + 0, + Opcode_ae_slaa32s_encode_fns, 0, 0 }, + { "ae_sraa32s", ICLASS_AE_SRAA32S, + 0, + Opcode_ae_sraa32s_encode_fns, 0, 0 }, + { "ae_sraa32rs", ICLASS_AE_SRAA32RS, + 0, + Opcode_ae_sraa32rs_encode_fns, 0, 0 }, + { "ae_slasq56", ICLASS_AE_SLASQ56, + 0, + Opcode_ae_slasq56_encode_fns, 0, 0 }, + { "ae_srlsq56", ICLASS_AE_SRLSQ56, + 0, + Opcode_ae_srlsq56_encode_fns, 0, 0 }, + { "ae_srasq56", ICLASS_AE_SRASQ56, + 0, + Opcode_ae_srasq56_encode_fns, 0, 0 }, + { "ae_slaaq56", ICLASS_AE_SLAAQ56, + 0, + Opcode_ae_slaaq56_encode_fns, 0, 0 }, + { "ae_srlaq56", ICLASS_AE_SRLAQ56, + 0, + Opcode_ae_srlaq56_encode_fns, 0, 0 }, + { "ae_sraaq56", ICLASS_AE_SRAAQ56, + 0, + Opcode_ae_sraaq56_encode_fns, 0, 0 }, + { "ae_slai64", ICLASS_AE_SLAI64, + 0, + Opcode_ae_slai64_encode_fns, 0, 0 }, + { "ae_srli64", ICLASS_AE_SRLI64, + 0, + Opcode_ae_srli64_encode_fns, 0, 0 }, + { "ae_srai64", ICLASS_AE_SRAI64, + 0, + Opcode_ae_srai64_encode_fns, 0, 0 }, + { "ae_slas64", ICLASS_AE_SLAS64, + 0, + Opcode_ae_slas64_encode_fns, 0, 0 }, + { "ae_srls64", ICLASS_AE_SRLS64, + 0, + Opcode_ae_srls64_encode_fns, 0, 0 }, + { "ae_sras64", ICLASS_AE_SRAS64, + 0, + Opcode_ae_sras64_encode_fns, 0, 0 }, + { "ae_slaa64", ICLASS_AE_SLAA64, + 0, + Opcode_ae_slaa64_encode_fns, 0, 0 }, + { "ae_srla64", ICLASS_AE_SRLA64, + 0, + Opcode_ae_srla64_encode_fns, 0, 0 }, + { "ae_sraa64", ICLASS_AE_SRAA64, + 0, + Opcode_ae_sraa64_encode_fns, 0, 0 }, + { "ae_slaisq56s", ICLASS_AE_SLAISQ56S, + 0, + Opcode_ae_slaisq56s_encode_fns, 0, 0 }, + { "ae_slassq56s", ICLASS_AE_SLASSQ56S, + 0, + Opcode_ae_slassq56s_encode_fns, 0, 0 }, + { "ae_slaasq56s", ICLASS_AE_SLAASQ56S, + 0, + Opcode_ae_slaasq56s_encode_fns, 0, 0 }, + { "ae_slai64s", ICLASS_AE_SLAI64S, + 0, + Opcode_ae_slai64s_encode_fns, 0, 0 }, + { "ae_slas64s", ICLASS_AE_SLAS64S, + 0, + Opcode_ae_slas64s_encode_fns, 0, 0 }, + { "ae_slaa64s", ICLASS_AE_SLAA64S, + 0, + Opcode_ae_slaa64s_encode_fns, 0, 0 }, + { "ae_lt64", ICLASS_AE_LT64, + 0, + Opcode_ae_lt64_encode_fns, 0, 0 }, + { "ae_le64", ICLASS_AE_LE64, + 0, + Opcode_ae_le64_encode_fns, 0, 0 }, + { "ae_eq64", ICLASS_AE_EQ64, + 0, + Opcode_ae_eq64_encode_fns, 0, 0 }, + { "ae_max64", ICLASS_AE_MAX64, + 0, + Opcode_ae_max64_encode_fns, 0, 0 }, + { "ae_min64", ICLASS_AE_MIN64, + 0, + Opcode_ae_min64_encode_fns, 0, 0 }, + { "ae_nsa64", ICLASS_AE_NSA64, + 0, + Opcode_ae_nsa64_encode_fns, 0, 0 }, + { "ae_nsaz16.0", ICLASS_AE_NSAZ16_0, + 0, + Opcode_ae_nsaz16_0_encode_fns, 0, 0 }, + { "ae_nsaz32.l", ICLASS_AE_NSAZ32_L, + 0, + Opcode_ae_nsaz32_l_encode_fns, 0, 0 }, + { "ae_muls32f48p16s.ll", ICLASS_AE_MULS32F48P16S_LL, + 0, + Opcode_ae_muls32f48p16s_ll_encode_fns, 1, Opcode_ae_muls32f48p16s_ll_funcUnit_uses }, + { "ae_mulf32s.ll", ICLASS_AE_MULF32S_LL, + 0, + Opcode_ae_mulf32s_ll_encode_fns, 1, Opcode_ae_mulf32s_ll_funcUnit_uses }, + { "ae_mul32.ll", ICLASS_AE_MUL32_LL, + 0, + Opcode_ae_mul32_ll_encode_fns, 1, Opcode_ae_mul32_ll_funcUnit_uses }, + { "ae_mulf32s.ll_s2", ICLASS_AE_MULF32S_LL_S2, + 0, + Opcode_ae_mulf32s_ll_s2_encode_fns, 1, Opcode_ae_mulf32s_ll_s2_funcUnit_uses }, + { "ae_mul32.ll_s2", ICLASS_AE_MUL32_LL_S2, + 0, + Opcode_ae_mul32_ll_s2_encode_fns, 1, Opcode_ae_mul32_ll_s2_funcUnit_uses }, + { "ae_muls32f48p16s.ll_s2", ICLASS_AE_MULS32F48P16S_LL_S2, + 0, + Opcode_ae_muls32f48p16s_ll_s2_encode_fns, 1, Opcode_ae_muls32f48p16s_ll_s2_funcUnit_uses }, + { "ae_mulf32r.ll", ICLASS_AE_MULF32R_LL, + 0, + Opcode_ae_mulf32r_ll_encode_fns, 1, Opcode_ae_mulf32r_ll_funcUnit_uses }, + { "ae_mulf32ra.ll", ICLASS_AE_MULF32RA_LL, + 0, + Opcode_ae_mulf32ra_ll_encode_fns, 1, Opcode_ae_mulf32ra_ll_funcUnit_uses }, + { "ae_mulf32ra.ll_s2", ICLASS_AE_MULF32RA_LL_S2, + 0, + Opcode_ae_mulf32ra_ll_s2_encode_fns, 1, Opcode_ae_mulf32ra_ll_s2_funcUnit_uses }, + { "ae_mulf32r.ll_s2", ICLASS_AE_MULF32R_LL_S2, + 0, + Opcode_ae_mulf32r_ll_s2_encode_fns, 1, Opcode_ae_mulf32r_ll_s2_funcUnit_uses }, + { "ae_muls32f48p16s.lh", ICLASS_AE_MULS32F48P16S_LH, + 0, + Opcode_ae_muls32f48p16s_lh_encode_fns, 1, Opcode_ae_muls32f48p16s_lh_funcUnit_uses }, + { "ae_mulf32s.lh", ICLASS_AE_MULF32S_LH, + 0, + Opcode_ae_mulf32s_lh_encode_fns, 1, Opcode_ae_mulf32s_lh_funcUnit_uses }, + { "ae_mul32.lh", ICLASS_AE_MUL32_LH, + 0, + Opcode_ae_mul32_lh_encode_fns, 1, Opcode_ae_mul32_lh_funcUnit_uses }, + { "ae_mulf32s.lh_s2", ICLASS_AE_MULF32S_LH_S2, + 0, + Opcode_ae_mulf32s_lh_s2_encode_fns, 1, Opcode_ae_mulf32s_lh_s2_funcUnit_uses }, + { "ae_mul32.lh_s2", ICLASS_AE_MUL32_LH_S2, + 0, + Opcode_ae_mul32_lh_s2_encode_fns, 1, Opcode_ae_mul32_lh_s2_funcUnit_uses }, + { "ae_muls32f48p16s.lh_s2", ICLASS_AE_MULS32F48P16S_LH_S2, + 0, + Opcode_ae_muls32f48p16s_lh_s2_encode_fns, 1, Opcode_ae_muls32f48p16s_lh_s2_funcUnit_uses }, + { "ae_mulf32r.lh", ICLASS_AE_MULF32R_LH, + 0, + Opcode_ae_mulf32r_lh_encode_fns, 1, Opcode_ae_mulf32r_lh_funcUnit_uses }, + { "ae_mulf32ra.lh", ICLASS_AE_MULF32RA_LH, + 0, + Opcode_ae_mulf32ra_lh_encode_fns, 1, Opcode_ae_mulf32ra_lh_funcUnit_uses }, + { "ae_mulf32ra.lh_s2", ICLASS_AE_MULF32RA_LH_S2, + 0, + Opcode_ae_mulf32ra_lh_s2_encode_fns, 1, Opcode_ae_mulf32ra_lh_s2_funcUnit_uses }, + { "ae_mulf32r.lh_s2", ICLASS_AE_MULF32R_LH_S2, + 0, + Opcode_ae_mulf32r_lh_s2_encode_fns, 1, Opcode_ae_mulf32r_lh_s2_funcUnit_uses }, + { "ae_muls32f48p16s.hh", ICLASS_AE_MULS32F48P16S_HH, + 0, + Opcode_ae_muls32f48p16s_hh_encode_fns, 1, Opcode_ae_muls32f48p16s_hh_funcUnit_uses }, + { "ae_mulf32s.hh", ICLASS_AE_MULF32S_HH, + 0, + Opcode_ae_mulf32s_hh_encode_fns, 1, Opcode_ae_mulf32s_hh_funcUnit_uses }, + { "ae_mul32.hh", ICLASS_AE_MUL32_HH, + 0, + Opcode_ae_mul32_hh_encode_fns, 1, Opcode_ae_mul32_hh_funcUnit_uses }, + { "ae_mulf32s.hh_s2", ICLASS_AE_MULF32S_HH_S2, + 0, + Opcode_ae_mulf32s_hh_s2_encode_fns, 1, Opcode_ae_mulf32s_hh_s2_funcUnit_uses }, + { "ae_mul32.hh_s2", ICLASS_AE_MUL32_HH_S2, + 0, + Opcode_ae_mul32_hh_s2_encode_fns, 1, Opcode_ae_mul32_hh_s2_funcUnit_uses }, + { "ae_muls32f48p16s.hh_s2", ICLASS_AE_MULS32F48P16S_HH_S2, + 0, + Opcode_ae_muls32f48p16s_hh_s2_encode_fns, 1, Opcode_ae_muls32f48p16s_hh_s2_funcUnit_uses }, + { "ae_mulf32r.hh", ICLASS_AE_MULF32R_HH, + 0, + Opcode_ae_mulf32r_hh_encode_fns, 1, Opcode_ae_mulf32r_hh_funcUnit_uses }, + { "ae_mulf32ra.hh", ICLASS_AE_MULF32RA_HH, + 0, + Opcode_ae_mulf32ra_hh_encode_fns, 1, Opcode_ae_mulf32ra_hh_funcUnit_uses }, + { "ae_mulf32ra.hh_s2", ICLASS_AE_MULF32RA_HH_S2, + 0, + Opcode_ae_mulf32ra_hh_s2_encode_fns, 1, Opcode_ae_mulf32ra_hh_s2_funcUnit_uses }, + { "ae_mulf32r.hh_s2", ICLASS_AE_MULF32R_HH_S2, + 0, + Opcode_ae_mulf32r_hh_s2_encode_fns, 1, Opcode_ae_mulf32r_hh_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.ll", ICLASS_AE_MULAS32F48P16S_LL, + 0, + Opcode_ae_mulas32f48p16s_ll_encode_fns, 1, Opcode_ae_mulas32f48p16s_ll_funcUnit_uses }, + { "ae_mulaf32s.ll", ICLASS_AE_MULAF32S_LL, + 0, + Opcode_ae_mulaf32s_ll_encode_fns, 1, Opcode_ae_mulaf32s_ll_funcUnit_uses }, + { "ae_mula32.ll", ICLASS_AE_MULA32_LL, + 0, + Opcode_ae_mula32_ll_encode_fns, 1, Opcode_ae_mula32_ll_funcUnit_uses }, + { "ae_mulaf32s.ll_s2", ICLASS_AE_MULAF32S_LL_S2, + 0, + Opcode_ae_mulaf32s_ll_s2_encode_fns, 1, Opcode_ae_mulaf32s_ll_s2_funcUnit_uses }, + { "ae_mula32.ll_s2", ICLASS_AE_MULA32_LL_S2, + 0, + Opcode_ae_mula32_ll_s2_encode_fns, 1, Opcode_ae_mula32_ll_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.ll_s2", ICLASS_AE_MULAS32F48P16S_LL_S2, + 0, + Opcode_ae_mulas32f48p16s_ll_s2_encode_fns, 1, Opcode_ae_mulas32f48p16s_ll_s2_funcUnit_uses }, + { "ae_mulaf32r.ll", ICLASS_AE_MULAF32R_LL, + 0, + Opcode_ae_mulaf32r_ll_encode_fns, 1, Opcode_ae_mulaf32r_ll_funcUnit_uses }, + { "ae_mulaf32ra.ll", ICLASS_AE_MULAF32RA_LL, + 0, + Opcode_ae_mulaf32ra_ll_encode_fns, 1, Opcode_ae_mulaf32ra_ll_funcUnit_uses }, + { "ae_mulaf32ra.ll_s2", ICLASS_AE_MULAF32RA_LL_S2, + 0, + Opcode_ae_mulaf32ra_ll_s2_encode_fns, 1, Opcode_ae_mulaf32ra_ll_s2_funcUnit_uses }, + { "ae_mulaf32r.ll_s2", ICLASS_AE_MULAF32R_LL_S2, + 0, + Opcode_ae_mulaf32r_ll_s2_encode_fns, 1, Opcode_ae_mulaf32r_ll_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.lh", ICLASS_AE_MULAS32F48P16S_LH, + 0, + Opcode_ae_mulas32f48p16s_lh_encode_fns, 1, Opcode_ae_mulas32f48p16s_lh_funcUnit_uses }, + { "ae_mulaf32s.lh", ICLASS_AE_MULAF32S_LH, + 0, + Opcode_ae_mulaf32s_lh_encode_fns, 1, Opcode_ae_mulaf32s_lh_funcUnit_uses }, + { "ae_mula32.lh", ICLASS_AE_MULA32_LH, + 0, + Opcode_ae_mula32_lh_encode_fns, 1, Opcode_ae_mula32_lh_funcUnit_uses }, + { "ae_mulaf32s.lh_s2", ICLASS_AE_MULAF32S_LH_S2, + 0, + Opcode_ae_mulaf32s_lh_s2_encode_fns, 1, Opcode_ae_mulaf32s_lh_s2_funcUnit_uses }, + { "ae_mula32.lh_s2", ICLASS_AE_MULA32_LH_S2, + 0, + Opcode_ae_mula32_lh_s2_encode_fns, 1, Opcode_ae_mula32_lh_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.lh_s2", ICLASS_AE_MULAS32F48P16S_LH_S2, + 0, + Opcode_ae_mulas32f48p16s_lh_s2_encode_fns, 1, Opcode_ae_mulas32f48p16s_lh_s2_funcUnit_uses }, + { "ae_mulaf32r.lh", ICLASS_AE_MULAF32R_LH, + 0, + Opcode_ae_mulaf32r_lh_encode_fns, 1, Opcode_ae_mulaf32r_lh_funcUnit_uses }, + { "ae_mulaf32ra.lh", ICLASS_AE_MULAF32RA_LH, + 0, + Opcode_ae_mulaf32ra_lh_encode_fns, 1, Opcode_ae_mulaf32ra_lh_funcUnit_uses }, + { "ae_mulaf32ra.lh_s2", ICLASS_AE_MULAF32RA_LH_S2, + 0, + Opcode_ae_mulaf32ra_lh_s2_encode_fns, 1, Opcode_ae_mulaf32ra_lh_s2_funcUnit_uses }, + { "ae_mulaf32r.lh_s2", ICLASS_AE_MULAF32R_LH_S2, + 0, + Opcode_ae_mulaf32r_lh_s2_encode_fns, 1, Opcode_ae_mulaf32r_lh_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.hh", ICLASS_AE_MULAS32F48P16S_HH, + 0, + Opcode_ae_mulas32f48p16s_hh_encode_fns, 1, Opcode_ae_mulas32f48p16s_hh_funcUnit_uses }, + { "ae_mulaf32s.hh", ICLASS_AE_MULAF32S_HH, + 0, + Opcode_ae_mulaf32s_hh_encode_fns, 1, Opcode_ae_mulaf32s_hh_funcUnit_uses }, + { "ae_mula32.hh", ICLASS_AE_MULA32_HH, + 0, + Opcode_ae_mula32_hh_encode_fns, 1, Opcode_ae_mula32_hh_funcUnit_uses }, + { "ae_mulaf32s.hh_s2", ICLASS_AE_MULAF32S_HH_S2, + 0, + Opcode_ae_mulaf32s_hh_s2_encode_fns, 1, Opcode_ae_mulaf32s_hh_s2_funcUnit_uses }, + { "ae_mula32.hh_s2", ICLASS_AE_MULA32_HH_S2, + 0, + Opcode_ae_mula32_hh_s2_encode_fns, 1, Opcode_ae_mula32_hh_s2_funcUnit_uses }, + { "ae_mulas32f48p16s.hh_s2", ICLASS_AE_MULAS32F48P16S_HH_S2, + 0, + Opcode_ae_mulas32f48p16s_hh_s2_encode_fns, 1, Opcode_ae_mulas32f48p16s_hh_s2_funcUnit_uses }, + { "ae_mulaf32r.hh", ICLASS_AE_MULAF32R_HH, + 0, + Opcode_ae_mulaf32r_hh_encode_fns, 1, Opcode_ae_mulaf32r_hh_funcUnit_uses }, + { "ae_mulaf32ra.hh", ICLASS_AE_MULAF32RA_HH, + 0, + Opcode_ae_mulaf32ra_hh_encode_fns, 1, Opcode_ae_mulaf32ra_hh_funcUnit_uses }, + { "ae_mulaf32ra.hh_s2", ICLASS_AE_MULAF32RA_HH_S2, + 0, + Opcode_ae_mulaf32ra_hh_s2_encode_fns, 1, Opcode_ae_mulaf32ra_hh_s2_funcUnit_uses }, + { "ae_mulaf32r.hh_s2", ICLASS_AE_MULAF32R_HH_S2, + 0, + Opcode_ae_mulaf32r_hh_s2_encode_fns, 1, Opcode_ae_mulaf32r_hh_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.ll", ICLASS_AE_MULSS32F48P16S_LL, + 0, + Opcode_ae_mulss32f48p16s_ll_encode_fns, 1, Opcode_ae_mulss32f48p16s_ll_funcUnit_uses }, + { "ae_mulsf32s.ll", ICLASS_AE_MULSF32S_LL, + 0, + Opcode_ae_mulsf32s_ll_encode_fns, 1, Opcode_ae_mulsf32s_ll_funcUnit_uses }, + { "ae_muls32.ll", ICLASS_AE_MULS32_LL, + 0, + Opcode_ae_muls32_ll_encode_fns, 1, Opcode_ae_muls32_ll_funcUnit_uses }, + { "ae_mulsf32s.ll_s2", ICLASS_AE_MULSF32S_LL_S2, + 0, + Opcode_ae_mulsf32s_ll_s2_encode_fns, 1, Opcode_ae_mulsf32s_ll_s2_funcUnit_uses }, + { "ae_muls32.ll_s2", ICLASS_AE_MULS32_LL_S2, + 0, + Opcode_ae_muls32_ll_s2_encode_fns, 1, Opcode_ae_muls32_ll_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.ll_s2", ICLASS_AE_MULSS32F48P16S_LL_S2, + 0, + Opcode_ae_mulss32f48p16s_ll_s2_encode_fns, 1, Opcode_ae_mulss32f48p16s_ll_s2_funcUnit_uses }, + { "ae_mulsf32r.ll", ICLASS_AE_MULSF32R_LL, + 0, + Opcode_ae_mulsf32r_ll_encode_fns, 1, Opcode_ae_mulsf32r_ll_funcUnit_uses }, + { "ae_mulsf32ra.ll", ICLASS_AE_MULSF32RA_LL, + 0, + Opcode_ae_mulsf32ra_ll_encode_fns, 1, Opcode_ae_mulsf32ra_ll_funcUnit_uses }, + { "ae_mulsf32ra.ll_s2", ICLASS_AE_MULSF32RA_LL_S2, + 0, + Opcode_ae_mulsf32ra_ll_s2_encode_fns, 1, Opcode_ae_mulsf32ra_ll_s2_funcUnit_uses }, + { "ae_mulsf32r.ll_s2", ICLASS_AE_MULSF32R_LL_S2, + 0, + Opcode_ae_mulsf32r_ll_s2_encode_fns, 1, Opcode_ae_mulsf32r_ll_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.lh", ICLASS_AE_MULSS32F48P16S_LH, + 0, + Opcode_ae_mulss32f48p16s_lh_encode_fns, 1, Opcode_ae_mulss32f48p16s_lh_funcUnit_uses }, + { "ae_mulsf32s.lh", ICLASS_AE_MULSF32S_LH, + 0, + Opcode_ae_mulsf32s_lh_encode_fns, 1, Opcode_ae_mulsf32s_lh_funcUnit_uses }, + { "ae_muls32.lh", ICLASS_AE_MULS32_LH, + 0, + Opcode_ae_muls32_lh_encode_fns, 1, Opcode_ae_muls32_lh_funcUnit_uses }, + { "ae_mulsf32s.lh_s2", ICLASS_AE_MULSF32S_LH_S2, + 0, + Opcode_ae_mulsf32s_lh_s2_encode_fns, 1, Opcode_ae_mulsf32s_lh_s2_funcUnit_uses }, + { "ae_muls32.lh_s2", ICLASS_AE_MULS32_LH_S2, + 0, + Opcode_ae_muls32_lh_s2_encode_fns, 1, Opcode_ae_muls32_lh_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.lh_s2", ICLASS_AE_MULSS32F48P16S_LH_S2, + 0, + Opcode_ae_mulss32f48p16s_lh_s2_encode_fns, 1, Opcode_ae_mulss32f48p16s_lh_s2_funcUnit_uses }, + { "ae_mulsf32r.lh", ICLASS_AE_MULSF32R_LH, + 0, + Opcode_ae_mulsf32r_lh_encode_fns, 1, Opcode_ae_mulsf32r_lh_funcUnit_uses }, + { "ae_mulsf32ra.lh", ICLASS_AE_MULSF32RA_LH, + 0, + Opcode_ae_mulsf32ra_lh_encode_fns, 1, Opcode_ae_mulsf32ra_lh_funcUnit_uses }, + { "ae_mulsf32ra.lh_s2", ICLASS_AE_MULSF32RA_LH_S2, + 0, + Opcode_ae_mulsf32ra_lh_s2_encode_fns, 1, Opcode_ae_mulsf32ra_lh_s2_funcUnit_uses }, + { "ae_mulsf32r.lh_s2", ICLASS_AE_MULSF32R_LH_S2, + 0, + Opcode_ae_mulsf32r_lh_s2_encode_fns, 1, Opcode_ae_mulsf32r_lh_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.hh", ICLASS_AE_MULSS32F48P16S_HH, + 0, + Opcode_ae_mulss32f48p16s_hh_encode_fns, 1, Opcode_ae_mulss32f48p16s_hh_funcUnit_uses }, + { "ae_mulsf32s.hh", ICLASS_AE_MULSF32S_HH, + 0, + Opcode_ae_mulsf32s_hh_encode_fns, 1, Opcode_ae_mulsf32s_hh_funcUnit_uses }, + { "ae_muls32.hh", ICLASS_AE_MULS32_HH, + 0, + Opcode_ae_muls32_hh_encode_fns, 1, Opcode_ae_muls32_hh_funcUnit_uses }, + { "ae_mulsf32s.hh_s2", ICLASS_AE_MULSF32S_HH_S2, + 0, + Opcode_ae_mulsf32s_hh_s2_encode_fns, 1, Opcode_ae_mulsf32s_hh_s2_funcUnit_uses }, + { "ae_muls32.hh_s2", ICLASS_AE_MULS32_HH_S2, + 0, + Opcode_ae_muls32_hh_s2_encode_fns, 1, Opcode_ae_muls32_hh_s2_funcUnit_uses }, + { "ae_mulss32f48p16s.hh_s2", ICLASS_AE_MULSS32F48P16S_HH_S2, + 0, + Opcode_ae_mulss32f48p16s_hh_s2_encode_fns, 1, Opcode_ae_mulss32f48p16s_hh_s2_funcUnit_uses }, + { "ae_mulsf32r.hh", ICLASS_AE_MULSF32R_HH, + 0, + Opcode_ae_mulsf32r_hh_encode_fns, 1, Opcode_ae_mulsf32r_hh_funcUnit_uses }, + { "ae_mulsf32ra.hh", ICLASS_AE_MULSF32RA_HH, + 0, + Opcode_ae_mulsf32ra_hh_encode_fns, 1, Opcode_ae_mulsf32ra_hh_funcUnit_uses }, + { "ae_mulsf32ra.hh_s2", ICLASS_AE_MULSF32RA_HH_S2, + 0, + Opcode_ae_mulsf32ra_hh_s2_encode_fns, 1, Opcode_ae_mulsf32ra_hh_s2_funcUnit_uses }, + { "ae_mulsf32r.hh_s2", ICLASS_AE_MULSF32R_HH_S2, + 0, + Opcode_ae_mulsf32r_hh_s2_encode_fns, 1, Opcode_ae_mulsf32r_hh_s2_funcUnit_uses }, + { "ae_mul32u.ll", ICLASS_AE_MUL32U_LL, + 0, + Opcode_ae_mul32u_ll_encode_fns, 1, Opcode_ae_mul32u_ll_funcUnit_uses }, + { "ae_mula32u.ll", ICLASS_AE_MULA32U_LL, + 0, + Opcode_ae_mula32u_ll_encode_fns, 1, Opcode_ae_mula32u_ll_funcUnit_uses }, + { "ae_muls32u.ll", ICLASS_AE_MULS32U_LL, + 0, + Opcode_ae_muls32u_ll_encode_fns, 1, Opcode_ae_muls32u_ll_funcUnit_uses }, + { "ae_mulf16ss.33", ICLASS_AE_MULF16SS_33, + 0, + Opcode_ae_mulf16ss_33_encode_fns, 1, Opcode_ae_mulf16ss_33_funcUnit_uses }, + { "ae_mulf16ss.33_s2", ICLASS_AE_MULF16SS_33_S2, + 0, + Opcode_ae_mulf16ss_33_s2_encode_fns, 1, Opcode_ae_mulf16ss_33_s2_funcUnit_uses }, + { "ae_mulf16ss.22", ICLASS_AE_MULF16SS_22, + 0, + Opcode_ae_mulf16ss_22_encode_fns, 1, Opcode_ae_mulf16ss_22_funcUnit_uses }, + { "ae_mulf16ss.22_s2", ICLASS_AE_MULF16SS_22_S2, + 0, + Opcode_ae_mulf16ss_22_s2_encode_fns, 1, Opcode_ae_mulf16ss_22_s2_funcUnit_uses }, + { "ae_mulf16ss.32", ICLASS_AE_MULF16SS_32, + 0, + Opcode_ae_mulf16ss_32_encode_fns, 1, Opcode_ae_mulf16ss_32_funcUnit_uses }, + { "ae_mulf16ss.32_s2", ICLASS_AE_MULF16SS_32_S2, + 0, + Opcode_ae_mulf16ss_32_s2_encode_fns, 1, Opcode_ae_mulf16ss_32_s2_funcUnit_uses }, + { "ae_mulf16ss.21", ICLASS_AE_MULF16SS_21, + 0, + Opcode_ae_mulf16ss_21_encode_fns, 1, Opcode_ae_mulf16ss_21_funcUnit_uses }, + { "ae_mulf16ss.21_s2", ICLASS_AE_MULF16SS_21_S2, + 0, + Opcode_ae_mulf16ss_21_s2_encode_fns, 1, Opcode_ae_mulf16ss_21_s2_funcUnit_uses }, + { "ae_mulf16ss.31", ICLASS_AE_MULF16SS_31, + 0, + Opcode_ae_mulf16ss_31_encode_fns, 1, Opcode_ae_mulf16ss_31_funcUnit_uses }, + { "ae_mulf16ss.31_s2", ICLASS_AE_MULF16SS_31_S2, + 0, + Opcode_ae_mulf16ss_31_s2_encode_fns, 1, Opcode_ae_mulf16ss_31_s2_funcUnit_uses }, + { "ae_mulf16ss.30", ICLASS_AE_MULF16SS_30, + 0, + Opcode_ae_mulf16ss_30_encode_fns, 1, Opcode_ae_mulf16ss_30_funcUnit_uses }, + { "ae_mulf16ss.30_s2", ICLASS_AE_MULF16SS_30_S2, + 0, + Opcode_ae_mulf16ss_30_s2_encode_fns, 1, Opcode_ae_mulf16ss_30_s2_funcUnit_uses }, + { "ae_mulf16ss.10", ICLASS_AE_MULF16SS_10, + 0, + Opcode_ae_mulf16ss_10_encode_fns, 1, Opcode_ae_mulf16ss_10_funcUnit_uses }, + { "ae_mulf16ss.10_s2", ICLASS_AE_MULF16SS_10_S2, + 0, + Opcode_ae_mulf16ss_10_s2_encode_fns, 1, Opcode_ae_mulf16ss_10_s2_funcUnit_uses }, + { "ae_mulf16ss.20", ICLASS_AE_MULF16SS_20, + 0, + Opcode_ae_mulf16ss_20_encode_fns, 1, Opcode_ae_mulf16ss_20_funcUnit_uses }, + { "ae_mulf16ss.20_s2", ICLASS_AE_MULF16SS_20_S2, + 0, + Opcode_ae_mulf16ss_20_s2_encode_fns, 1, Opcode_ae_mulf16ss_20_s2_funcUnit_uses }, + { "ae_mulf16ss.11", ICLASS_AE_MULF16SS_11, + 0, + Opcode_ae_mulf16ss_11_encode_fns, 1, Opcode_ae_mulf16ss_11_funcUnit_uses }, + { "ae_mulf16ss.11_s2", ICLASS_AE_MULF16SS_11_S2, + 0, + Opcode_ae_mulf16ss_11_s2_encode_fns, 1, Opcode_ae_mulf16ss_11_s2_funcUnit_uses }, + { "ae_mulf16ss.00", ICLASS_AE_MULF16SS_00, + 0, + Opcode_ae_mulf16ss_00_encode_fns, 1, Opcode_ae_mulf16ss_00_funcUnit_uses }, + { "ae_mulf16ss.00_s2", ICLASS_AE_MULF16SS_00_S2, + 0, + Opcode_ae_mulf16ss_00_s2_encode_fns, 1, Opcode_ae_mulf16ss_00_s2_funcUnit_uses }, + { "ae_mulsf16ss.33", ICLASS_AE_MULSF16SS_33, + 0, + Opcode_ae_mulsf16ss_33_encode_fns, 1, Opcode_ae_mulsf16ss_33_funcUnit_uses }, + { "ae_mulsf16ss.33_s2", ICLASS_AE_MULSF16SS_33_S2, + 0, + Opcode_ae_mulsf16ss_33_s2_encode_fns, 1, Opcode_ae_mulsf16ss_33_s2_funcUnit_uses }, + { "ae_mulsf16ss.22", ICLASS_AE_MULSF16SS_22, + 0, + Opcode_ae_mulsf16ss_22_encode_fns, 1, Opcode_ae_mulsf16ss_22_funcUnit_uses }, + { "ae_mulsf16ss.22_s2", ICLASS_AE_MULSF16SS_22_S2, + 0, + Opcode_ae_mulsf16ss_22_s2_encode_fns, 1, Opcode_ae_mulsf16ss_22_s2_funcUnit_uses }, + { "ae_mulsf16ss.32", ICLASS_AE_MULSF16SS_32, + 0, + Opcode_ae_mulsf16ss_32_encode_fns, 1, Opcode_ae_mulsf16ss_32_funcUnit_uses }, + { "ae_mulsf16ss.32_s2", ICLASS_AE_MULSF16SS_32_S2, + 0, + Opcode_ae_mulsf16ss_32_s2_encode_fns, 1, Opcode_ae_mulsf16ss_32_s2_funcUnit_uses }, + { "ae_mulsf16ss.21", ICLASS_AE_MULSF16SS_21, + 0, + Opcode_ae_mulsf16ss_21_encode_fns, 1, Opcode_ae_mulsf16ss_21_funcUnit_uses }, + { "ae_mulsf16ss.21_s2", ICLASS_AE_MULSF16SS_21_S2, + 0, + Opcode_ae_mulsf16ss_21_s2_encode_fns, 1, Opcode_ae_mulsf16ss_21_s2_funcUnit_uses }, + { "ae_mulsf16ss.31", ICLASS_AE_MULSF16SS_31, + 0, + Opcode_ae_mulsf16ss_31_encode_fns, 1, Opcode_ae_mulsf16ss_31_funcUnit_uses }, + { "ae_mulsf16ss.31_s2", ICLASS_AE_MULSF16SS_31_S2, + 0, + Opcode_ae_mulsf16ss_31_s2_encode_fns, 1, Opcode_ae_mulsf16ss_31_s2_funcUnit_uses }, + { "ae_mulsf16ss.30", ICLASS_AE_MULSF16SS_30, + 0, + Opcode_ae_mulsf16ss_30_encode_fns, 1, Opcode_ae_mulsf16ss_30_funcUnit_uses }, + { "ae_mulsf16ss.30_s2", ICLASS_AE_MULSF16SS_30_S2, + 0, + Opcode_ae_mulsf16ss_30_s2_encode_fns, 1, Opcode_ae_mulsf16ss_30_s2_funcUnit_uses }, + { "ae_mulsf16ss.10", ICLASS_AE_MULSF16SS_10, + 0, + Opcode_ae_mulsf16ss_10_encode_fns, 1, Opcode_ae_mulsf16ss_10_funcUnit_uses }, + { "ae_mulsf16ss.10_s2", ICLASS_AE_MULSF16SS_10_S2, + 0, + Opcode_ae_mulsf16ss_10_s2_encode_fns, 1, Opcode_ae_mulsf16ss_10_s2_funcUnit_uses }, + { "ae_mulsf16ss.20", ICLASS_AE_MULSF16SS_20, + 0, + Opcode_ae_mulsf16ss_20_encode_fns, 1, Opcode_ae_mulsf16ss_20_funcUnit_uses }, + { "ae_mulsf16ss.20_s2", ICLASS_AE_MULSF16SS_20_S2, + 0, + Opcode_ae_mulsf16ss_20_s2_encode_fns, 1, Opcode_ae_mulsf16ss_20_s2_funcUnit_uses }, + { "ae_mulsf16ss.11", ICLASS_AE_MULSF16SS_11, + 0, + Opcode_ae_mulsf16ss_11_encode_fns, 1, Opcode_ae_mulsf16ss_11_funcUnit_uses }, + { "ae_mulsf16ss.11_s2", ICLASS_AE_MULSF16SS_11_S2, + 0, + Opcode_ae_mulsf16ss_11_s2_encode_fns, 1, Opcode_ae_mulsf16ss_11_s2_funcUnit_uses }, + { "ae_mulsf16ss.00", ICLASS_AE_MULSF16SS_00, + 0, + Opcode_ae_mulsf16ss_00_encode_fns, 1, Opcode_ae_mulsf16ss_00_funcUnit_uses }, + { "ae_mulsf16ss.00_s2", ICLASS_AE_MULSF16SS_00_S2, + 0, + Opcode_ae_mulsf16ss_00_s2_encode_fns, 1, Opcode_ae_mulsf16ss_00_s2_funcUnit_uses }, + { "ae_mulaf16ss.33", ICLASS_AE_MULAF16SS_33, + 0, + Opcode_ae_mulaf16ss_33_encode_fns, 1, Opcode_ae_mulaf16ss_33_funcUnit_uses }, + { "ae_mulaf16ss.33_s2", ICLASS_AE_MULAF16SS_33_S2, + 0, + Opcode_ae_mulaf16ss_33_s2_encode_fns, 1, Opcode_ae_mulaf16ss_33_s2_funcUnit_uses }, + { "ae_mulaf16ss.22", ICLASS_AE_MULAF16SS_22, + 0, + Opcode_ae_mulaf16ss_22_encode_fns, 1, Opcode_ae_mulaf16ss_22_funcUnit_uses }, + { "ae_mulaf16ss.22_s2", ICLASS_AE_MULAF16SS_22_S2, + 0, + Opcode_ae_mulaf16ss_22_s2_encode_fns, 1, Opcode_ae_mulaf16ss_22_s2_funcUnit_uses }, + { "ae_mulaf16ss.32", ICLASS_AE_MULAF16SS_32, + 0, + Opcode_ae_mulaf16ss_32_encode_fns, 1, Opcode_ae_mulaf16ss_32_funcUnit_uses }, + { "ae_mulaf16ss.32_s2", ICLASS_AE_MULAF16SS_32_S2, + 0, + Opcode_ae_mulaf16ss_32_s2_encode_fns, 1, Opcode_ae_mulaf16ss_32_s2_funcUnit_uses }, + { "ae_mulaf16ss.21", ICLASS_AE_MULAF16SS_21, + 0, + Opcode_ae_mulaf16ss_21_encode_fns, 1, Opcode_ae_mulaf16ss_21_funcUnit_uses }, + { "ae_mulaf16ss.21_s2", ICLASS_AE_MULAF16SS_21_S2, + 0, + Opcode_ae_mulaf16ss_21_s2_encode_fns, 1, Opcode_ae_mulaf16ss_21_s2_funcUnit_uses }, + { "ae_mulaf16ss.31", ICLASS_AE_MULAF16SS_31, + 0, + Opcode_ae_mulaf16ss_31_encode_fns, 1, Opcode_ae_mulaf16ss_31_funcUnit_uses }, + { "ae_mulaf16ss.31_s2", ICLASS_AE_MULAF16SS_31_S2, + 0, + Opcode_ae_mulaf16ss_31_s2_encode_fns, 1, Opcode_ae_mulaf16ss_31_s2_funcUnit_uses }, + { "ae_mulaf16ss.30", ICLASS_AE_MULAF16SS_30, + 0, + Opcode_ae_mulaf16ss_30_encode_fns, 1, Opcode_ae_mulaf16ss_30_funcUnit_uses }, + { "ae_mulaf16ss.30_s2", ICLASS_AE_MULAF16SS_30_S2, + 0, + Opcode_ae_mulaf16ss_30_s2_encode_fns, 1, Opcode_ae_mulaf16ss_30_s2_funcUnit_uses }, + { "ae_mulaf16ss.10", ICLASS_AE_MULAF16SS_10, + 0, + Opcode_ae_mulaf16ss_10_encode_fns, 1, Opcode_ae_mulaf16ss_10_funcUnit_uses }, + { "ae_mulaf16ss.10_s2", ICLASS_AE_MULAF16SS_10_S2, + 0, + Opcode_ae_mulaf16ss_10_s2_encode_fns, 1, Opcode_ae_mulaf16ss_10_s2_funcUnit_uses }, + { "ae_mulaf16ss.20", ICLASS_AE_MULAF16SS_20, + 0, + Opcode_ae_mulaf16ss_20_encode_fns, 1, Opcode_ae_mulaf16ss_20_funcUnit_uses }, + { "ae_mulaf16ss.20_s2", ICLASS_AE_MULAF16SS_20_S2, + 0, + Opcode_ae_mulaf16ss_20_s2_encode_fns, 1, Opcode_ae_mulaf16ss_20_s2_funcUnit_uses }, + { "ae_mulaf16ss.11", ICLASS_AE_MULAF16SS_11, + 0, + Opcode_ae_mulaf16ss_11_encode_fns, 1, Opcode_ae_mulaf16ss_11_funcUnit_uses }, + { "ae_mulaf16ss.11_s2", ICLASS_AE_MULAF16SS_11_S2, + 0, + Opcode_ae_mulaf16ss_11_s2_encode_fns, 1, Opcode_ae_mulaf16ss_11_s2_funcUnit_uses }, + { "ae_mulaf16ss.00", ICLASS_AE_MULAF16SS_00, + 0, + Opcode_ae_mulaf16ss_00_encode_fns, 1, Opcode_ae_mulaf16ss_00_funcUnit_uses }, + { "ae_mulaf16ss.00_s2", ICLASS_AE_MULAF16SS_00_S2, + 0, + Opcode_ae_mulaf16ss_00_s2_encode_fns, 1, Opcode_ae_mulaf16ss_00_s2_funcUnit_uses }, + { "ae_mulaafd16ss.33_22", ICLASS_AE_MULAAFD16SS_33_22, + 0, + Opcode_ae_mulaafd16ss_33_22_encode_fns, 1, Opcode_ae_mulaafd16ss_33_22_funcUnit_uses }, + { "ae_mulaafd16ss.33_22_s2", ICLASS_AE_MULAAFD16SS_33_22_S2, + 0, + Opcode_ae_mulaafd16ss_33_22_s2_encode_fns, 1, Opcode_ae_mulaafd16ss_33_22_s2_funcUnit_uses }, + { "ae_mulaafd16ss.13_02", ICLASS_AE_MULAAFD16SS_13_02, + 0, + Opcode_ae_mulaafd16ss_13_02_encode_fns, 1, Opcode_ae_mulaafd16ss_13_02_funcUnit_uses }, + { "ae_mulaafd16ss.13_02_s2", ICLASS_AE_MULAAFD16SS_13_02_S2, + 0, + Opcode_ae_mulaafd16ss_13_02_s2_encode_fns, 1, Opcode_ae_mulaafd16ss_13_02_s2_funcUnit_uses }, + { "ae_mulaafd16ss.11_00", ICLASS_AE_MULAAFD16SS_11_00, + 0, + Opcode_ae_mulaafd16ss_11_00_encode_fns, 1, Opcode_ae_mulaafd16ss_11_00_funcUnit_uses }, + { "ae_mulaafd16ss.11_00_s2", ICLASS_AE_MULAAFD16SS_11_00_S2, + 0, + Opcode_ae_mulaafd16ss_11_00_s2_encode_fns, 1, Opcode_ae_mulaafd16ss_11_00_s2_funcUnit_uses }, + { "ae_mulssfd16ss.33_22", ICLASS_AE_MULSSFD16SS_33_22, + 0, + Opcode_ae_mulssfd16ss_33_22_encode_fns, 1, Opcode_ae_mulssfd16ss_33_22_funcUnit_uses }, + { "ae_mulssfd16ss.33_22_s2", ICLASS_AE_MULSSFD16SS_33_22_S2, + 0, + Opcode_ae_mulssfd16ss_33_22_s2_encode_fns, 1, Opcode_ae_mulssfd16ss_33_22_s2_funcUnit_uses }, + { "ae_mulssfd16ss.13_02", ICLASS_AE_MULSSFD16SS_13_02, + 0, + Opcode_ae_mulssfd16ss_13_02_encode_fns, 1, Opcode_ae_mulssfd16ss_13_02_funcUnit_uses }, + { "ae_mulssfd16ss.13_02_s2", ICLASS_AE_MULSSFD16SS_13_02_S2, + 0, + Opcode_ae_mulssfd16ss_13_02_s2_encode_fns, 1, Opcode_ae_mulssfd16ss_13_02_s2_funcUnit_uses }, + { "ae_mulssfd16ss.11_00", ICLASS_AE_MULSSFD16SS_11_00, + 0, + Opcode_ae_mulssfd16ss_11_00_encode_fns, 1, Opcode_ae_mulssfd16ss_11_00_funcUnit_uses }, + { "ae_mulssfd16ss.11_00_s2", ICLASS_AE_MULSSFD16SS_11_00_S2, + 0, + Opcode_ae_mulssfd16ss_11_00_s2_encode_fns, 1, Opcode_ae_mulssfd16ss_11_00_s2_funcUnit_uses }, + { "ae_mulzaafd16ss.33_22", ICLASS_AE_MULZAAFD16SS_33_22, + 0, + Opcode_ae_mulzaafd16ss_33_22_encode_fns, 1, Opcode_ae_mulzaafd16ss_33_22_funcUnit_uses }, + { "ae_mulzaafd16ss.33_22_s2", ICLASS_AE_MULZAAFD16SS_33_22_S2, + 0, + Opcode_ae_mulzaafd16ss_33_22_s2_encode_fns, 1, Opcode_ae_mulzaafd16ss_33_22_s2_funcUnit_uses }, + { "ae_mulzaafd16ss.13_02", ICLASS_AE_MULZAAFD16SS_13_02, + 0, + Opcode_ae_mulzaafd16ss_13_02_encode_fns, 1, Opcode_ae_mulzaafd16ss_13_02_funcUnit_uses }, + { "ae_mulzaafd16ss.13_02_s2", ICLASS_AE_MULZAAFD16SS_13_02_S2, + 0, + Opcode_ae_mulzaafd16ss_13_02_s2_encode_fns, 1, Opcode_ae_mulzaafd16ss_13_02_s2_funcUnit_uses }, + { "ae_mulzaafd16ss.11_00", ICLASS_AE_MULZAAFD16SS_11_00, + 0, + Opcode_ae_mulzaafd16ss_11_00_encode_fns, 1, Opcode_ae_mulzaafd16ss_11_00_funcUnit_uses }, + { "ae_mulzaafd16ss.11_00_s2", ICLASS_AE_MULZAAFD16SS_11_00_S2, + 0, + Opcode_ae_mulzaafd16ss_11_00_s2_encode_fns, 1, Opcode_ae_mulzaafd16ss_11_00_s2_funcUnit_uses }, + { "ae_mulzssfd16ss.33_22", ICLASS_AE_MULZSSFD16SS_33_22, + 0, + Opcode_ae_mulzssfd16ss_33_22_encode_fns, 1, Opcode_ae_mulzssfd16ss_33_22_funcUnit_uses }, + { "ae_mulzssfd16ss.33_22_s2", ICLASS_AE_MULZSSFD16SS_33_22_S2, + 0, + Opcode_ae_mulzssfd16ss_33_22_s2_encode_fns, 1, Opcode_ae_mulzssfd16ss_33_22_s2_funcUnit_uses }, + { "ae_mulzssfd16ss.13_02", ICLASS_AE_MULZSSFD16SS_13_02, + 0, + Opcode_ae_mulzssfd16ss_13_02_encode_fns, 1, Opcode_ae_mulzssfd16ss_13_02_funcUnit_uses }, + { "ae_mulzssfd16ss.13_02_s2", ICLASS_AE_MULZSSFD16SS_13_02_S2, + 0, + Opcode_ae_mulzssfd16ss_13_02_s2_encode_fns, 1, Opcode_ae_mulzssfd16ss_13_02_s2_funcUnit_uses }, + { "ae_mulzssfd16ss.11_00", ICLASS_AE_MULZSSFD16SS_11_00, + 0, + Opcode_ae_mulzssfd16ss_11_00_encode_fns, 1, Opcode_ae_mulzssfd16ss_11_00_funcUnit_uses }, + { "ae_mulzssfd16ss.11_00_s2", ICLASS_AE_MULZSSFD16SS_11_00_S2, + 0, + Opcode_ae_mulzssfd16ss_11_00_s2_encode_fns, 1, Opcode_ae_mulzssfd16ss_11_00_s2_funcUnit_uses }, + { "ae_mulf48q32sp16s.l", ICLASS_AE_MULF48Q32SP16S_L, + 0, + Opcode_ae_mulf48q32sp16s_l_encode_fns, 1, Opcode_ae_mulf48q32sp16s_l_funcUnit_uses }, + { "ae_mulf48q32sp16s.l_s2", ICLASS_AE_MULF48Q32SP16S_L_S2, + 0, + Opcode_ae_mulf48q32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulf48q32sp16s_l_s2_funcUnit_uses }, + { "ae_mulf48q32sp16u.l", ICLASS_AE_MULF48Q32SP16U_L, + 0, + Opcode_ae_mulf48q32sp16u_l_encode_fns, 1, Opcode_ae_mulf48q32sp16u_l_funcUnit_uses }, + { "ae_mulf48q32sp16u.l_s2", ICLASS_AE_MULF48Q32SP16U_L_S2, + 0, + Opcode_ae_mulf48q32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulf48q32sp16u_l_s2_funcUnit_uses }, + { "ae_mulq32sp16s.l", ICLASS_AE_MULQ32SP16S_L, + 0, + Opcode_ae_mulq32sp16s_l_encode_fns, 1, Opcode_ae_mulq32sp16s_l_funcUnit_uses }, + { "ae_mulq32sp16s.l_s2", ICLASS_AE_MULQ32SP16S_L_S2, + 0, + Opcode_ae_mulq32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulq32sp16s_l_s2_funcUnit_uses }, + { "ae_mulq32sp16u.l", ICLASS_AE_MULQ32SP16U_L, + 0, + Opcode_ae_mulq32sp16u_l_encode_fns, 1, Opcode_ae_mulq32sp16u_l_funcUnit_uses }, + { "ae_mulq32sp16u.l_s2", ICLASS_AE_MULQ32SP16U_L_S2, + 0, + Opcode_ae_mulq32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulq32sp16u_l_s2_funcUnit_uses }, + { "ae_mulaf48q32sp16s.l", ICLASS_AE_MULAF48Q32SP16S_L, + 0, + Opcode_ae_mulaf48q32sp16s_l_encode_fns, 1, Opcode_ae_mulaf48q32sp16s_l_funcUnit_uses }, + { "ae_mulaf48q32sp16s.l_s2", ICLASS_AE_MULAF48Q32SP16S_L_S2, + 0, + Opcode_ae_mulaf48q32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulaf48q32sp16s_l_s2_funcUnit_uses }, + { "ae_mulaf48q32sp16u.l", ICLASS_AE_MULAF48Q32SP16U_L, + 0, + Opcode_ae_mulaf48q32sp16u_l_encode_fns, 1, Opcode_ae_mulaf48q32sp16u_l_funcUnit_uses }, + { "ae_mulaf48q32sp16u.l_s2", ICLASS_AE_MULAF48Q32SP16U_L_S2, + 0, + Opcode_ae_mulaf48q32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulaf48q32sp16u_l_s2_funcUnit_uses }, + { "ae_mulaq32sp16s.l", ICLASS_AE_MULAQ32SP16S_L, + 0, + Opcode_ae_mulaq32sp16s_l_encode_fns, 1, Opcode_ae_mulaq32sp16s_l_funcUnit_uses }, + { "ae_mulaq32sp16s.l_s2", ICLASS_AE_MULAQ32SP16S_L_S2, + 0, + Opcode_ae_mulaq32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulaq32sp16s_l_s2_funcUnit_uses }, + { "ae_mulaq32sp16u.l", ICLASS_AE_MULAQ32SP16U_L, + 0, + Opcode_ae_mulaq32sp16u_l_encode_fns, 1, Opcode_ae_mulaq32sp16u_l_funcUnit_uses }, + { "ae_mulaq32sp16u.l_s2", ICLASS_AE_MULAQ32SP16U_L_S2, + 0, + Opcode_ae_mulaq32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulaq32sp16u_l_s2_funcUnit_uses }, + { "ae_mulsf48q32sp16s.l", ICLASS_AE_MULSF48Q32SP16S_L, + 0, + Opcode_ae_mulsf48q32sp16s_l_encode_fns, 1, Opcode_ae_mulsf48q32sp16s_l_funcUnit_uses }, + { "ae_mulsf48q32sp16s.l_s2", ICLASS_AE_MULSF48Q32SP16S_L_S2, + 0, + Opcode_ae_mulsf48q32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulsf48q32sp16s_l_s2_funcUnit_uses }, + { "ae_mulsf48q32sp16u.l", ICLASS_AE_MULSF48Q32SP16U_L, + 0, + Opcode_ae_mulsf48q32sp16u_l_encode_fns, 1, Opcode_ae_mulsf48q32sp16u_l_funcUnit_uses }, + { "ae_mulsf48q32sp16u.l_s2", ICLASS_AE_MULSF48Q32SP16U_L_S2, + 0, + Opcode_ae_mulsf48q32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulsf48q32sp16u_l_s2_funcUnit_uses }, + { "ae_mulsq32sp16s.l", ICLASS_AE_MULSQ32SP16S_L, + 0, + Opcode_ae_mulsq32sp16s_l_encode_fns, 1, Opcode_ae_mulsq32sp16s_l_funcUnit_uses }, + { "ae_mulsq32sp16s.l_s2", ICLASS_AE_MULSQ32SP16S_L_S2, + 0, + Opcode_ae_mulsq32sp16s_l_s2_encode_fns, 1, Opcode_ae_mulsq32sp16s_l_s2_funcUnit_uses }, + { "ae_mulsq32sp16u.l", ICLASS_AE_MULSQ32SP16U_L, + 0, + Opcode_ae_mulsq32sp16u_l_encode_fns, 1, Opcode_ae_mulsq32sp16u_l_funcUnit_uses }, + { "ae_mulsq32sp16u.l_s2", ICLASS_AE_MULSQ32SP16U_L_S2, + 0, + Opcode_ae_mulsq32sp16u_l_s2_encode_fns, 1, Opcode_ae_mulsq32sp16u_l_s2_funcUnit_uses }, + { "ae_mulfp24x2ra", ICLASS_AE_MULFP24X2RA, + 0, + Opcode_ae_mulfp24x2ra_encode_fns, 1, Opcode_ae_mulfp24x2ra_funcUnit_uses }, + { "ae_mulfp24x2r", ICLASS_AE_MULFP24X2R, + 0, + Opcode_ae_mulfp24x2r_encode_fns, 1, Opcode_ae_mulfp24x2r_funcUnit_uses }, + { "ae_mulfp24x2ra_s2", ICLASS_AE_MULFP24X2RA_S2, + 0, + Opcode_ae_mulfp24x2ra_s2_encode_fns, 1, Opcode_ae_mulfp24x2ra_s2_funcUnit_uses }, + { "ae_mulfp24x2r_s2", ICLASS_AE_MULFP24X2R_S2, + 0, + Opcode_ae_mulfp24x2r_s2_encode_fns, 1, Opcode_ae_mulfp24x2r_s2_funcUnit_uses }, + { "ae_mulafp24x2ra", ICLASS_AE_MULAFP24X2RA, + 0, + Opcode_ae_mulafp24x2ra_encode_fns, 1, Opcode_ae_mulafp24x2ra_funcUnit_uses }, + { "ae_mulafp24x2r", ICLASS_AE_MULAFP24X2R, + 0, + Opcode_ae_mulafp24x2r_encode_fns, 1, Opcode_ae_mulafp24x2r_funcUnit_uses }, + { "ae_mulafp24x2ra_s2", ICLASS_AE_MULAFP24X2RA_S2, + 0, + Opcode_ae_mulafp24x2ra_s2_encode_fns, 1, Opcode_ae_mulafp24x2ra_s2_funcUnit_uses }, + { "ae_mulafp24x2r_s2", ICLASS_AE_MULAFP24X2R_S2, + 0, + Opcode_ae_mulafp24x2r_s2_encode_fns, 1, Opcode_ae_mulafp24x2r_s2_funcUnit_uses }, + { "ae_mulsfp24x2ra", ICLASS_AE_MULSFP24X2RA, + 0, + Opcode_ae_mulsfp24x2ra_encode_fns, 1, Opcode_ae_mulsfp24x2ra_funcUnit_uses }, + { "ae_mulsfp24x2r", ICLASS_AE_MULSFP24X2R, + 0, + Opcode_ae_mulsfp24x2r_encode_fns, 1, Opcode_ae_mulsfp24x2r_funcUnit_uses }, + { "ae_mulsfp24x2ra_s2", ICLASS_AE_MULSFP24X2RA_S2, + 0, + Opcode_ae_mulsfp24x2ra_s2_encode_fns, 1, Opcode_ae_mulsfp24x2ra_s2_funcUnit_uses }, + { "ae_mulsfp24x2r_s2", ICLASS_AE_MULSFP24X2R_S2, + 0, + Opcode_ae_mulsfp24x2r_s2_encode_fns, 1, Opcode_ae_mulsfp24x2r_s2_funcUnit_uses }, + { "ae_mulzaafd32s.hh.ll", ICLASS_AE_MULZAAFD32S_HH_LL, + 0, + Opcode_ae_mulzaafd32s_hh_ll_encode_fns, 1, Opcode_ae_mulzaafd32s_hh_ll_funcUnit_uses }, + { "ae_mulzaafd32ra.hh.ll", ICLASS_AE_MULZAAFD32RA_HH_LL, + 0, + Opcode_ae_mulzaafd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulzaafd32ra_hh_ll_funcUnit_uses }, + { "ae_mulzaad32.hh.ll", ICLASS_AE_MULZAAD32_HH_LL, + 0, + Opcode_ae_mulzaad32_hh_ll_encode_fns, 1, Opcode_ae_mulzaad32_hh_ll_funcUnit_uses }, + { "ae_mulzaafd32s.hh.ll_s2", ICLASS_AE_MULZAAFD32S_HH_LL_S2, + 0, + Opcode_ae_mulzaafd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzaafd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulzaafd32ra.hh.ll_s2", ICLASS_AE_MULZAAFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulzaafd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzaafd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulzaad32.hh.ll_s2", ICLASS_AE_MULZAAD32_HH_LL_S2, + 0, + Opcode_ae_mulzaad32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzaad32_hh_ll_s2_funcUnit_uses }, + { "ae_mulzaafd32s.hl.lh", ICLASS_AE_MULZAAFD32S_HL_LH, + 0, + Opcode_ae_mulzaafd32s_hl_lh_encode_fns, 1, Opcode_ae_mulzaafd32s_hl_lh_funcUnit_uses }, + { "ae_mulzaafd32ra.hl.lh", ICLASS_AE_MULZAAFD32RA_HL_LH, + 0, + Opcode_ae_mulzaafd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulzaafd32ra_hl_lh_funcUnit_uses }, + { "ae_mulzaad32.hl.lh", ICLASS_AE_MULZAAD32_HL_LH, + 0, + Opcode_ae_mulzaad32_hl_lh_encode_fns, 1, Opcode_ae_mulzaad32_hl_lh_funcUnit_uses }, + { "ae_mulzaafd32s.hl.lh_s2", ICLASS_AE_MULZAAFD32S_HL_LH_S2, + 0, + Opcode_ae_mulzaafd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzaafd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulzaafd32ra.hl.lh_s2", ICLASS_AE_MULZAAFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulzaafd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzaafd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulzaad32.hl.lh_s2", ICLASS_AE_MULZAAD32_HL_LH_S2, + 0, + Opcode_ae_mulzaad32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzaad32_hl_lh_s2_funcUnit_uses }, + { "ae_mulzasfd32s.hh.ll", ICLASS_AE_MULZASFD32S_HH_LL, + 0, + Opcode_ae_mulzasfd32s_hh_ll_encode_fns, 1, Opcode_ae_mulzasfd32s_hh_ll_funcUnit_uses }, + { "ae_mulzasfd32ra.hh.ll", ICLASS_AE_MULZASFD32RA_HH_LL, + 0, + Opcode_ae_mulzasfd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulzasfd32ra_hh_ll_funcUnit_uses }, + { "ae_mulzasd32.hh.ll", ICLASS_AE_MULZASD32_HH_LL, + 0, + Opcode_ae_mulzasd32_hh_ll_encode_fns, 1, Opcode_ae_mulzasd32_hh_ll_funcUnit_uses }, + { "ae_mulzasfd32s.hh.ll_s2", ICLASS_AE_MULZASFD32S_HH_LL_S2, + 0, + Opcode_ae_mulzasfd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzasfd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulzasfd32ra.hh.ll_s2", ICLASS_AE_MULZASFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulzasfd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzasfd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulzasd32.hh.ll_s2", ICLASS_AE_MULZASD32_HH_LL_S2, + 0, + Opcode_ae_mulzasd32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzasd32_hh_ll_s2_funcUnit_uses }, + { "ae_mulzasfd32s.hl.lh", ICLASS_AE_MULZASFD32S_HL_LH, + 0, + Opcode_ae_mulzasfd32s_hl_lh_encode_fns, 1, Opcode_ae_mulzasfd32s_hl_lh_funcUnit_uses }, + { "ae_mulzasfd32ra.hl.lh", ICLASS_AE_MULZASFD32RA_HL_LH, + 0, + Opcode_ae_mulzasfd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulzasfd32ra_hl_lh_funcUnit_uses }, + { "ae_mulzasd32.hl.lh", ICLASS_AE_MULZASD32_HL_LH, + 0, + Opcode_ae_mulzasd32_hl_lh_encode_fns, 1, Opcode_ae_mulzasd32_hl_lh_funcUnit_uses }, + { "ae_mulzasfd32s.hl.lh_s2", ICLASS_AE_MULZASFD32S_HL_LH_S2, + 0, + Opcode_ae_mulzasfd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzasfd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulzasfd32ra.hl.lh_s2", ICLASS_AE_MULZASFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulzasfd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzasfd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulzasd32.hl.lh_s2", ICLASS_AE_MULZASD32_HL_LH_S2, + 0, + Opcode_ae_mulzasd32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzasd32_hl_lh_s2_funcUnit_uses }, + { "ae_mulzsafd32s.hh.ll", ICLASS_AE_MULZSAFD32S_HH_LL, + 0, + Opcode_ae_mulzsafd32s_hh_ll_encode_fns, 1, Opcode_ae_mulzsafd32s_hh_ll_funcUnit_uses }, + { "ae_mulzsafd32ra.hh.ll", ICLASS_AE_MULZSAFD32RA_HH_LL, + 0, + Opcode_ae_mulzsafd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulzsafd32ra_hh_ll_funcUnit_uses }, + { "ae_mulzsad32.hh.ll", ICLASS_AE_MULZSAD32_HH_LL, + 0, + Opcode_ae_mulzsad32_hh_ll_encode_fns, 1, Opcode_ae_mulzsad32_hh_ll_funcUnit_uses }, + { "ae_mulzsafd32s.hh.ll_s2", ICLASS_AE_MULZSAFD32S_HH_LL_S2, + 0, + Opcode_ae_mulzsafd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzsafd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulzsafd32ra.hh.ll_s2", ICLASS_AE_MULZSAFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulzsafd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzsafd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulzsad32.hh.ll_s2", ICLASS_AE_MULZSAD32_HH_LL_S2, + 0, + Opcode_ae_mulzsad32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzsad32_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssfd32s.hh.ll", ICLASS_AE_MULZSSFD32S_HH_LL, + 0, + Opcode_ae_mulzssfd32s_hh_ll_encode_fns, 1, Opcode_ae_mulzssfd32s_hh_ll_funcUnit_uses }, + { "ae_mulzssfd32ra.hh.ll", ICLASS_AE_MULZSSFD32RA_HH_LL, + 0, + Opcode_ae_mulzssfd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulzssfd32ra_hh_ll_funcUnit_uses }, + { "ae_mulzssd32.hh.ll", ICLASS_AE_MULZSSD32_HH_LL, + 0, + Opcode_ae_mulzssd32_hh_ll_encode_fns, 1, Opcode_ae_mulzssd32_hh_ll_funcUnit_uses }, + { "ae_mulzssfd32s.hh.ll_s2", ICLASS_AE_MULZSSFD32S_HH_LL_S2, + 0, + Opcode_ae_mulzssfd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzssfd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssfd32ra.hh.ll_s2", ICLASS_AE_MULZSSFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulzssfd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzssfd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssd32.hh.ll_s2", ICLASS_AE_MULZSSD32_HH_LL_S2, + 0, + Opcode_ae_mulzssd32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzssd32_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssfd32s.hl.lh", ICLASS_AE_MULZSSFD32S_HL_LH, + 0, + Opcode_ae_mulzssfd32s_hl_lh_encode_fns, 1, Opcode_ae_mulzssfd32s_hl_lh_funcUnit_uses }, + { "ae_mulzssfd32ra.hl.lh", ICLASS_AE_MULZSSFD32RA_HL_LH, + 0, + Opcode_ae_mulzssfd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulzssfd32ra_hl_lh_funcUnit_uses }, + { "ae_mulzssd32.hl.lh", ICLASS_AE_MULZSSD32_HL_LH, + 0, + Opcode_ae_mulzssd32_hl_lh_encode_fns, 1, Opcode_ae_mulzssd32_hl_lh_funcUnit_uses }, + { "ae_mulzssfd32s.hl.lh_s2", ICLASS_AE_MULZSSFD32S_HL_LH_S2, + 0, + Opcode_ae_mulzssfd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzssfd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulzssfd32ra.hl.lh_s2", ICLASS_AE_MULZSSFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulzssfd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzssfd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulzssd32.hl.lh_s2", ICLASS_AE_MULZSSD32_HL_LH_S2, + 0, + Opcode_ae_mulzssd32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzssd32_hl_lh_s2_funcUnit_uses }, + { "ae_mulaafd32s.hh.ll", ICLASS_AE_MULAAFD32S_HH_LL, + 0, + Opcode_ae_mulaafd32s_hh_ll_encode_fns, 1, Opcode_ae_mulaafd32s_hh_ll_funcUnit_uses }, + { "ae_mulaafd32ra.hh.ll", ICLASS_AE_MULAAFD32RA_HH_LL, + 0, + Opcode_ae_mulaafd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulaafd32ra_hh_ll_funcUnit_uses }, + { "ae_mulaad32.hh.ll", ICLASS_AE_MULAAD32_HH_LL, + 0, + Opcode_ae_mulaad32_hh_ll_encode_fns, 1, Opcode_ae_mulaad32_hh_ll_funcUnit_uses }, + { "ae_mulaafd32s.hh.ll_s2", ICLASS_AE_MULAAFD32S_HH_LL_S2, + 0, + Opcode_ae_mulaafd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulaafd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulaafd32ra.hh.ll_s2", ICLASS_AE_MULAAFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulaafd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulaafd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulaad32.hh.ll_s2", ICLASS_AE_MULAAD32_HH_LL_S2, + 0, + Opcode_ae_mulaad32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulaad32_hh_ll_s2_funcUnit_uses }, + { "ae_mulaafd32s.hl.lh", ICLASS_AE_MULAAFD32S_HL_LH, + 0, + Opcode_ae_mulaafd32s_hl_lh_encode_fns, 1, Opcode_ae_mulaafd32s_hl_lh_funcUnit_uses }, + { "ae_mulaafd32ra.hl.lh", ICLASS_AE_MULAAFD32RA_HL_LH, + 0, + Opcode_ae_mulaafd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulaafd32ra_hl_lh_funcUnit_uses }, + { "ae_mulaad32.hl.lh", ICLASS_AE_MULAAD32_HL_LH, + 0, + Opcode_ae_mulaad32_hl_lh_encode_fns, 1, Opcode_ae_mulaad32_hl_lh_funcUnit_uses }, + { "ae_mulaafd32s.hl.lh_s2", ICLASS_AE_MULAAFD32S_HL_LH_S2, + 0, + Opcode_ae_mulaafd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulaafd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulaafd32ra.hl.lh_s2", ICLASS_AE_MULAAFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulaafd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulaafd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulaad32.hl.lh_s2", ICLASS_AE_MULAAD32_HL_LH_S2, + 0, + Opcode_ae_mulaad32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulaad32_hl_lh_s2_funcUnit_uses }, + { "ae_mulasfd32s.hh.ll", ICLASS_AE_MULASFD32S_HH_LL, + 0, + Opcode_ae_mulasfd32s_hh_ll_encode_fns, 1, Opcode_ae_mulasfd32s_hh_ll_funcUnit_uses }, + { "ae_mulasfd32ra.hh.ll", ICLASS_AE_MULASFD32RA_HH_LL, + 0, + Opcode_ae_mulasfd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulasfd32ra_hh_ll_funcUnit_uses }, + { "ae_mulasd32.hh.ll", ICLASS_AE_MULASD32_HH_LL, + 0, + Opcode_ae_mulasd32_hh_ll_encode_fns, 1, Opcode_ae_mulasd32_hh_ll_funcUnit_uses }, + { "ae_mulasfd32s.hh.ll_s2", ICLASS_AE_MULASFD32S_HH_LL_S2, + 0, + Opcode_ae_mulasfd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulasfd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulasfd32ra.hh.ll_s2", ICLASS_AE_MULASFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulasfd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulasfd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulasd32.hh.ll_s2", ICLASS_AE_MULASD32_HH_LL_S2, + 0, + Opcode_ae_mulasd32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulasd32_hh_ll_s2_funcUnit_uses }, + { "ae_mulasfd32s.hl.lh", ICLASS_AE_MULASFD32S_HL_LH, + 0, + Opcode_ae_mulasfd32s_hl_lh_encode_fns, 1, Opcode_ae_mulasfd32s_hl_lh_funcUnit_uses }, + { "ae_mulasfd32ra.hl.lh", ICLASS_AE_MULASFD32RA_HL_LH, + 0, + Opcode_ae_mulasfd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulasfd32ra_hl_lh_funcUnit_uses }, + { "ae_mulasd32.hl.lh", ICLASS_AE_MULASD32_HL_LH, + 0, + Opcode_ae_mulasd32_hl_lh_encode_fns, 1, Opcode_ae_mulasd32_hl_lh_funcUnit_uses }, + { "ae_mulasfd32s.hl.lh_s2", ICLASS_AE_MULASFD32S_HL_LH_S2, + 0, + Opcode_ae_mulasfd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulasfd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulasfd32ra.hl.lh_s2", ICLASS_AE_MULASFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulasfd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulasfd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulasd32.hl.lh_s2", ICLASS_AE_MULASD32_HL_LH_S2, + 0, + Opcode_ae_mulasd32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulasd32_hl_lh_s2_funcUnit_uses }, + { "ae_mulsafd32s.hh.ll", ICLASS_AE_MULSAFD32S_HH_LL, + 0, + Opcode_ae_mulsafd32s_hh_ll_encode_fns, 1, Opcode_ae_mulsafd32s_hh_ll_funcUnit_uses }, + { "ae_mulsafd32ra.hh.ll", ICLASS_AE_MULSAFD32RA_HH_LL, + 0, + Opcode_ae_mulsafd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulsafd32ra_hh_ll_funcUnit_uses }, + { "ae_mulsad32.hh.ll", ICLASS_AE_MULSAD32_HH_LL, + 0, + Opcode_ae_mulsad32_hh_ll_encode_fns, 1, Opcode_ae_mulsad32_hh_ll_funcUnit_uses }, + { "ae_mulsafd32s.hh.ll_s2", ICLASS_AE_MULSAFD32S_HH_LL_S2, + 0, + Opcode_ae_mulsafd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulsafd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulsafd32ra.hh.ll_s2", ICLASS_AE_MULSAFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulsafd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulsafd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulsad32.hh.ll_s2", ICLASS_AE_MULSAD32_HH_LL_S2, + 0, + Opcode_ae_mulsad32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulsad32_hh_ll_s2_funcUnit_uses }, + { "ae_mulssfd32s.hh.ll", ICLASS_AE_MULSSFD32S_HH_LL, + 0, + Opcode_ae_mulssfd32s_hh_ll_encode_fns, 1, Opcode_ae_mulssfd32s_hh_ll_funcUnit_uses }, + { "ae_mulssfd32ra.hh.ll", ICLASS_AE_MULSSFD32RA_HH_LL, + 0, + Opcode_ae_mulssfd32ra_hh_ll_encode_fns, 1, Opcode_ae_mulssfd32ra_hh_ll_funcUnit_uses }, + { "ae_mulssd32.hh.ll", ICLASS_AE_MULSSD32_HH_LL, + 0, + Opcode_ae_mulssd32_hh_ll_encode_fns, 1, Opcode_ae_mulssd32_hh_ll_funcUnit_uses }, + { "ae_mulssfd32s.hh.ll_s2", ICLASS_AE_MULSSFD32S_HH_LL_S2, + 0, + Opcode_ae_mulssfd32s_hh_ll_s2_encode_fns, 1, Opcode_ae_mulssfd32s_hh_ll_s2_funcUnit_uses }, + { "ae_mulssfd32ra.hh.ll_s2", ICLASS_AE_MULSSFD32RA_HH_LL_S2, + 0, + Opcode_ae_mulssfd32ra_hh_ll_s2_encode_fns, 1, Opcode_ae_mulssfd32ra_hh_ll_s2_funcUnit_uses }, + { "ae_mulssd32.hh.ll_s2", ICLASS_AE_MULSSD32_HH_LL_S2, + 0, + Opcode_ae_mulssd32_hh_ll_s2_encode_fns, 1, Opcode_ae_mulssd32_hh_ll_s2_funcUnit_uses }, + { "ae_mulssfd32s.hl.lh", ICLASS_AE_MULSSFD32S_HL_LH, + 0, + Opcode_ae_mulssfd32s_hl_lh_encode_fns, 1, Opcode_ae_mulssfd32s_hl_lh_funcUnit_uses }, + { "ae_mulssfd32ra.hl.lh", ICLASS_AE_MULSSFD32RA_HL_LH, + 0, + Opcode_ae_mulssfd32ra_hl_lh_encode_fns, 1, Opcode_ae_mulssfd32ra_hl_lh_funcUnit_uses }, + { "ae_mulssd32.hl.lh", ICLASS_AE_MULSSD32_HL_LH, + 0, + Opcode_ae_mulssd32_hl_lh_encode_fns, 1, Opcode_ae_mulssd32_hl_lh_funcUnit_uses }, + { "ae_mulssfd32s.hl.lh_s2", ICLASS_AE_MULSSFD32S_HL_LH_S2, + 0, + Opcode_ae_mulssfd32s_hl_lh_s2_encode_fns, 1, Opcode_ae_mulssfd32s_hl_lh_s2_funcUnit_uses }, + { "ae_mulssfd32ra.hl.lh_s2", ICLASS_AE_MULSSFD32RA_HL_LH_S2, + 0, + Opcode_ae_mulssfd32ra_hl_lh_s2_encode_fns, 1, Opcode_ae_mulssfd32ra_hl_lh_s2_funcUnit_uses }, + { "ae_mulssd32.hl.lh_s2", ICLASS_AE_MULSSD32_HL_LH_S2, + 0, + Opcode_ae_mulssd32_hl_lh_s2_encode_fns, 1, Opcode_ae_mulssd32_hl_lh_s2_funcUnit_uses }, + { "ae_mulf32x16.l0", ICLASS_AE_MULF32X16_L0, + 0, + Opcode_ae_mulf32x16_l0_encode_fns, 1, Opcode_ae_mulf32x16_l0_funcUnit_uses }, + { "ae_mul32x16.l0", ICLASS_AE_MUL32X16_L0, + 0, + Opcode_ae_mul32x16_l0_encode_fns, 1, Opcode_ae_mul32x16_l0_funcUnit_uses }, + { "ae_mulf32x16.l0_s2", ICLASS_AE_MULF32X16_L0_S2, + 0, + Opcode_ae_mulf32x16_l0_s2_encode_fns, 1, Opcode_ae_mulf32x16_l0_s2_funcUnit_uses }, + { "ae_mul32x16.l0_s2", ICLASS_AE_MUL32X16_L0_S2, + 0, + Opcode_ae_mul32x16_l0_s2_encode_fns, 1, Opcode_ae_mul32x16_l0_s2_funcUnit_uses }, + { "ae_mulf32x16.l1", ICLASS_AE_MULF32X16_L1, + 0, + Opcode_ae_mulf32x16_l1_encode_fns, 1, Opcode_ae_mulf32x16_l1_funcUnit_uses }, + { "ae_mul32x16.l1", ICLASS_AE_MUL32X16_L1, + 0, + Opcode_ae_mul32x16_l1_encode_fns, 1, Opcode_ae_mul32x16_l1_funcUnit_uses }, + { "ae_mulf32x16.l1_s2", ICLASS_AE_MULF32X16_L1_S2, + 0, + Opcode_ae_mulf32x16_l1_s2_encode_fns, 1, Opcode_ae_mulf32x16_l1_s2_funcUnit_uses }, + { "ae_mul32x16.l1_s2", ICLASS_AE_MUL32X16_L1_S2, + 0, + Opcode_ae_mul32x16_l1_s2_encode_fns, 1, Opcode_ae_mul32x16_l1_s2_funcUnit_uses }, + { "ae_mulf32x16.l2", ICLASS_AE_MULF32X16_L2, + 0, + Opcode_ae_mulf32x16_l2_encode_fns, 1, Opcode_ae_mulf32x16_l2_funcUnit_uses }, + { "ae_mul32x16.l2", ICLASS_AE_MUL32X16_L2, + 0, + Opcode_ae_mul32x16_l2_encode_fns, 1, Opcode_ae_mul32x16_l2_funcUnit_uses }, + { "ae_mulf32x16.l2_s2", ICLASS_AE_MULF32X16_L2_S2, + 0, + Opcode_ae_mulf32x16_l2_s2_encode_fns, 1, Opcode_ae_mulf32x16_l2_s2_funcUnit_uses }, + { "ae_mul32x16.l2_s2", ICLASS_AE_MUL32X16_L2_S2, + 0, + Opcode_ae_mul32x16_l2_s2_encode_fns, 1, Opcode_ae_mul32x16_l2_s2_funcUnit_uses }, + { "ae_mulf32x16.l3", ICLASS_AE_MULF32X16_L3, + 0, + Opcode_ae_mulf32x16_l3_encode_fns, 1, Opcode_ae_mulf32x16_l3_funcUnit_uses }, + { "ae_mul32x16.l3", ICLASS_AE_MUL32X16_L3, + 0, + Opcode_ae_mul32x16_l3_encode_fns, 1, Opcode_ae_mul32x16_l3_funcUnit_uses }, + { "ae_mulf32x16.l3_s2", ICLASS_AE_MULF32X16_L3_S2, + 0, + Opcode_ae_mulf32x16_l3_s2_encode_fns, 1, Opcode_ae_mulf32x16_l3_s2_funcUnit_uses }, + { "ae_mul32x16.l3_s2", ICLASS_AE_MUL32X16_L3_S2, + 0, + Opcode_ae_mul32x16_l3_s2_encode_fns, 1, Opcode_ae_mul32x16_l3_s2_funcUnit_uses }, + { "ae_mulf32x16.h0", ICLASS_AE_MULF32X16_H0, + 0, + Opcode_ae_mulf32x16_h0_encode_fns, 1, Opcode_ae_mulf32x16_h0_funcUnit_uses }, + { "ae_mul32x16.h0", ICLASS_AE_MUL32X16_H0, + 0, + Opcode_ae_mul32x16_h0_encode_fns, 1, Opcode_ae_mul32x16_h0_funcUnit_uses }, + { "ae_mulf32x16.h0_s2", ICLASS_AE_MULF32X16_H0_S2, + 0, + Opcode_ae_mulf32x16_h0_s2_encode_fns, 1, Opcode_ae_mulf32x16_h0_s2_funcUnit_uses }, + { "ae_mul32x16.h0_s2", ICLASS_AE_MUL32X16_H0_S2, + 0, + Opcode_ae_mul32x16_h0_s2_encode_fns, 1, Opcode_ae_mul32x16_h0_s2_funcUnit_uses }, + { "ae_mulf32x16.h1", ICLASS_AE_MULF32X16_H1, + 0, + Opcode_ae_mulf32x16_h1_encode_fns, 1, Opcode_ae_mulf32x16_h1_funcUnit_uses }, + { "ae_mul32x16.h1", ICLASS_AE_MUL32X16_H1, + 0, + Opcode_ae_mul32x16_h1_encode_fns, 1, Opcode_ae_mul32x16_h1_funcUnit_uses }, + { "ae_mulf32x16.h1_s2", ICLASS_AE_MULF32X16_H1_S2, + 0, + Opcode_ae_mulf32x16_h1_s2_encode_fns, 1, Opcode_ae_mulf32x16_h1_s2_funcUnit_uses }, + { "ae_mul32x16.h1_s2", ICLASS_AE_MUL32X16_H1_S2, + 0, + Opcode_ae_mul32x16_h1_s2_encode_fns, 1, Opcode_ae_mul32x16_h1_s2_funcUnit_uses }, + { "ae_mulf32x16.h2", ICLASS_AE_MULF32X16_H2, + 0, + Opcode_ae_mulf32x16_h2_encode_fns, 1, Opcode_ae_mulf32x16_h2_funcUnit_uses }, + { "ae_mul32x16.h2", ICLASS_AE_MUL32X16_H2, + 0, + Opcode_ae_mul32x16_h2_encode_fns, 1, Opcode_ae_mul32x16_h2_funcUnit_uses }, + { "ae_mulf32x16.h2_s2", ICLASS_AE_MULF32X16_H2_S2, + 0, + Opcode_ae_mulf32x16_h2_s2_encode_fns, 1, Opcode_ae_mulf32x16_h2_s2_funcUnit_uses }, + { "ae_mul32x16.h2_s2", ICLASS_AE_MUL32X16_H2_S2, + 0, + Opcode_ae_mul32x16_h2_s2_encode_fns, 1, Opcode_ae_mul32x16_h2_s2_funcUnit_uses }, + { "ae_mulf32x16.h3", ICLASS_AE_MULF32X16_H3, + 0, + Opcode_ae_mulf32x16_h3_encode_fns, 1, Opcode_ae_mulf32x16_h3_funcUnit_uses }, + { "ae_mul32x16.h3", ICLASS_AE_MUL32X16_H3, + 0, + Opcode_ae_mul32x16_h3_encode_fns, 1, Opcode_ae_mul32x16_h3_funcUnit_uses }, + { "ae_mulf32x16.h3_s2", ICLASS_AE_MULF32X16_H3_S2, + 0, + Opcode_ae_mulf32x16_h3_s2_encode_fns, 1, Opcode_ae_mulf32x16_h3_s2_funcUnit_uses }, + { "ae_mul32x16.h3_s2", ICLASS_AE_MUL32X16_H3_S2, + 0, + Opcode_ae_mul32x16_h3_s2_encode_fns, 1, Opcode_ae_mul32x16_h3_s2_funcUnit_uses }, + { "ae_mulaf32x16.l0", ICLASS_AE_MULAF32X16_L0, + 0, + Opcode_ae_mulaf32x16_l0_encode_fns, 1, Opcode_ae_mulaf32x16_l0_funcUnit_uses }, + { "ae_mula32x16.l0", ICLASS_AE_MULA32X16_L0, + 0, + Opcode_ae_mula32x16_l0_encode_fns, 1, Opcode_ae_mula32x16_l0_funcUnit_uses }, + { "ae_mulaf32x16.l0_s2", ICLASS_AE_MULAF32X16_L0_S2, + 0, + Opcode_ae_mulaf32x16_l0_s2_encode_fns, 1, Opcode_ae_mulaf32x16_l0_s2_funcUnit_uses }, + { "ae_mula32x16.l0_s2", ICLASS_AE_MULA32X16_L0_S2, + 0, + Opcode_ae_mula32x16_l0_s2_encode_fns, 1, Opcode_ae_mula32x16_l0_s2_funcUnit_uses }, + { "ae_mulaf32x16.l1", ICLASS_AE_MULAF32X16_L1, + 0, + Opcode_ae_mulaf32x16_l1_encode_fns, 1, Opcode_ae_mulaf32x16_l1_funcUnit_uses }, + { "ae_mula32x16.l1", ICLASS_AE_MULA32X16_L1, + 0, + Opcode_ae_mula32x16_l1_encode_fns, 1, Opcode_ae_mula32x16_l1_funcUnit_uses }, + { "ae_mulaf32x16.l1_s2", ICLASS_AE_MULAF32X16_L1_S2, + 0, + Opcode_ae_mulaf32x16_l1_s2_encode_fns, 1, Opcode_ae_mulaf32x16_l1_s2_funcUnit_uses }, + { "ae_mula32x16.l1_s2", ICLASS_AE_MULA32X16_L1_S2, + 0, + Opcode_ae_mula32x16_l1_s2_encode_fns, 1, Opcode_ae_mula32x16_l1_s2_funcUnit_uses }, + { "ae_mulaf32x16.l2", ICLASS_AE_MULAF32X16_L2, + 0, + Opcode_ae_mulaf32x16_l2_encode_fns, 1, Opcode_ae_mulaf32x16_l2_funcUnit_uses }, + { "ae_mula32x16.l2", ICLASS_AE_MULA32X16_L2, + 0, + Opcode_ae_mula32x16_l2_encode_fns, 1, Opcode_ae_mula32x16_l2_funcUnit_uses }, + { "ae_mulaf32x16.l2_s2", ICLASS_AE_MULAF32X16_L2_S2, + 0, + Opcode_ae_mulaf32x16_l2_s2_encode_fns, 1, Opcode_ae_mulaf32x16_l2_s2_funcUnit_uses }, + { "ae_mula32x16.l2_s2", ICLASS_AE_MULA32X16_L2_S2, + 0, + Opcode_ae_mula32x16_l2_s2_encode_fns, 1, Opcode_ae_mula32x16_l2_s2_funcUnit_uses }, + { "ae_mulaf32x16.l3", ICLASS_AE_MULAF32X16_L3, + 0, + Opcode_ae_mulaf32x16_l3_encode_fns, 1, Opcode_ae_mulaf32x16_l3_funcUnit_uses }, + { "ae_mula32x16.l3", ICLASS_AE_MULA32X16_L3, + 0, + Opcode_ae_mula32x16_l3_encode_fns, 1, Opcode_ae_mula32x16_l3_funcUnit_uses }, + { "ae_mulaf32x16.l3_s2", ICLASS_AE_MULAF32X16_L3_S2, + 0, + Opcode_ae_mulaf32x16_l3_s2_encode_fns, 1, Opcode_ae_mulaf32x16_l3_s2_funcUnit_uses }, + { "ae_mula32x16.l3_s2", ICLASS_AE_MULA32X16_L3_S2, + 0, + Opcode_ae_mula32x16_l3_s2_encode_fns, 1, Opcode_ae_mula32x16_l3_s2_funcUnit_uses }, + { "ae_mulaf32x16.h0", ICLASS_AE_MULAF32X16_H0, + 0, + Opcode_ae_mulaf32x16_h0_encode_fns, 1, Opcode_ae_mulaf32x16_h0_funcUnit_uses }, + { "ae_mula32x16.h0", ICLASS_AE_MULA32X16_H0, + 0, + Opcode_ae_mula32x16_h0_encode_fns, 1, Opcode_ae_mula32x16_h0_funcUnit_uses }, + { "ae_mulaf32x16.h0_s2", ICLASS_AE_MULAF32X16_H0_S2, + 0, + Opcode_ae_mulaf32x16_h0_s2_encode_fns, 1, Opcode_ae_mulaf32x16_h0_s2_funcUnit_uses }, + { "ae_mula32x16.h0_s2", ICLASS_AE_MULA32X16_H0_S2, + 0, + Opcode_ae_mula32x16_h0_s2_encode_fns, 1, Opcode_ae_mula32x16_h0_s2_funcUnit_uses }, + { "ae_mulaf32x16.h1", ICLASS_AE_MULAF32X16_H1, + 0, + Opcode_ae_mulaf32x16_h1_encode_fns, 1, Opcode_ae_mulaf32x16_h1_funcUnit_uses }, + { "ae_mula32x16.h1", ICLASS_AE_MULA32X16_H1, + 0, + Opcode_ae_mula32x16_h1_encode_fns, 1, Opcode_ae_mula32x16_h1_funcUnit_uses }, + { "ae_mulaf32x16.h1_s2", ICLASS_AE_MULAF32X16_H1_S2, + 0, + Opcode_ae_mulaf32x16_h1_s2_encode_fns, 1, Opcode_ae_mulaf32x16_h1_s2_funcUnit_uses }, + { "ae_mula32x16.h1_s2", ICLASS_AE_MULA32X16_H1_S2, + 0, + Opcode_ae_mula32x16_h1_s2_encode_fns, 1, Opcode_ae_mula32x16_h1_s2_funcUnit_uses }, + { "ae_mulaf32x16.h2", ICLASS_AE_MULAF32X16_H2, + 0, + Opcode_ae_mulaf32x16_h2_encode_fns, 1, Opcode_ae_mulaf32x16_h2_funcUnit_uses }, + { "ae_mula32x16.h2", ICLASS_AE_MULA32X16_H2, + 0, + Opcode_ae_mula32x16_h2_encode_fns, 1, Opcode_ae_mula32x16_h2_funcUnit_uses }, + { "ae_mulaf32x16.h2_s2", ICLASS_AE_MULAF32X16_H2_S2, + 0, + Opcode_ae_mulaf32x16_h2_s2_encode_fns, 1, Opcode_ae_mulaf32x16_h2_s2_funcUnit_uses }, + { "ae_mula32x16.h2_s2", ICLASS_AE_MULA32X16_H2_S2, + 0, + Opcode_ae_mula32x16_h2_s2_encode_fns, 1, Opcode_ae_mula32x16_h2_s2_funcUnit_uses }, + { "ae_mulaf32x16.h3", ICLASS_AE_MULAF32X16_H3, + 0, + Opcode_ae_mulaf32x16_h3_encode_fns, 1, Opcode_ae_mulaf32x16_h3_funcUnit_uses }, + { "ae_mula32x16.h3", ICLASS_AE_MULA32X16_H3, + 0, + Opcode_ae_mula32x16_h3_encode_fns, 1, Opcode_ae_mula32x16_h3_funcUnit_uses }, + { "ae_mulaf32x16.h3_s2", ICLASS_AE_MULAF32X16_H3_S2, + 0, + Opcode_ae_mulaf32x16_h3_s2_encode_fns, 1, Opcode_ae_mulaf32x16_h3_s2_funcUnit_uses }, + { "ae_mula32x16.h3_s2", ICLASS_AE_MULA32X16_H3_S2, + 0, + Opcode_ae_mula32x16_h3_s2_encode_fns, 1, Opcode_ae_mula32x16_h3_s2_funcUnit_uses }, + { "ae_mulsf32x16.l0", ICLASS_AE_MULSF32X16_L0, + 0, + Opcode_ae_mulsf32x16_l0_encode_fns, 1, Opcode_ae_mulsf32x16_l0_funcUnit_uses }, + { "ae_muls32x16.l0", ICLASS_AE_MULS32X16_L0, + 0, + Opcode_ae_muls32x16_l0_encode_fns, 1, Opcode_ae_muls32x16_l0_funcUnit_uses }, + { "ae_mulsf32x16.l0_s2", ICLASS_AE_MULSF32X16_L0_S2, + 0, + Opcode_ae_mulsf32x16_l0_s2_encode_fns, 1, Opcode_ae_mulsf32x16_l0_s2_funcUnit_uses }, + { "ae_muls32x16.l0_s2", ICLASS_AE_MULS32X16_L0_S2, + 0, + Opcode_ae_muls32x16_l0_s2_encode_fns, 1, Opcode_ae_muls32x16_l0_s2_funcUnit_uses }, + { "ae_mulsf32x16.l1", ICLASS_AE_MULSF32X16_L1, + 0, + Opcode_ae_mulsf32x16_l1_encode_fns, 1, Opcode_ae_mulsf32x16_l1_funcUnit_uses }, + { "ae_muls32x16.l1", ICLASS_AE_MULS32X16_L1, + 0, + Opcode_ae_muls32x16_l1_encode_fns, 1, Opcode_ae_muls32x16_l1_funcUnit_uses }, + { "ae_mulsf32x16.l1_s2", ICLASS_AE_MULSF32X16_L1_S2, + 0, + Opcode_ae_mulsf32x16_l1_s2_encode_fns, 1, Opcode_ae_mulsf32x16_l1_s2_funcUnit_uses }, + { "ae_muls32x16.l1_s2", ICLASS_AE_MULS32X16_L1_S2, + 0, + Opcode_ae_muls32x16_l1_s2_encode_fns, 1, Opcode_ae_muls32x16_l1_s2_funcUnit_uses }, + { "ae_mulsf32x16.l2", ICLASS_AE_MULSF32X16_L2, + 0, + Opcode_ae_mulsf32x16_l2_encode_fns, 1, Opcode_ae_mulsf32x16_l2_funcUnit_uses }, + { "ae_muls32x16.l2", ICLASS_AE_MULS32X16_L2, + 0, + Opcode_ae_muls32x16_l2_encode_fns, 1, Opcode_ae_muls32x16_l2_funcUnit_uses }, + { "ae_mulsf32x16.l2_s2", ICLASS_AE_MULSF32X16_L2_S2, + 0, + Opcode_ae_mulsf32x16_l2_s2_encode_fns, 1, Opcode_ae_mulsf32x16_l2_s2_funcUnit_uses }, + { "ae_muls32x16.l2_s2", ICLASS_AE_MULS32X16_L2_S2, + 0, + Opcode_ae_muls32x16_l2_s2_encode_fns, 1, Opcode_ae_muls32x16_l2_s2_funcUnit_uses }, + { "ae_mulsf32x16.l3", ICLASS_AE_MULSF32X16_L3, + 0, + Opcode_ae_mulsf32x16_l3_encode_fns, 1, Opcode_ae_mulsf32x16_l3_funcUnit_uses }, + { "ae_muls32x16.l3", ICLASS_AE_MULS32X16_L3, + 0, + Opcode_ae_muls32x16_l3_encode_fns, 1, Opcode_ae_muls32x16_l3_funcUnit_uses }, + { "ae_mulsf32x16.l3_s2", ICLASS_AE_MULSF32X16_L3_S2, + 0, + Opcode_ae_mulsf32x16_l3_s2_encode_fns, 1, Opcode_ae_mulsf32x16_l3_s2_funcUnit_uses }, + { "ae_muls32x16.l3_s2", ICLASS_AE_MULS32X16_L3_S2, + 0, + Opcode_ae_muls32x16_l3_s2_encode_fns, 1, Opcode_ae_muls32x16_l3_s2_funcUnit_uses }, + { "ae_mulsf32x16.h0", ICLASS_AE_MULSF32X16_H0, + 0, + Opcode_ae_mulsf32x16_h0_encode_fns, 1, Opcode_ae_mulsf32x16_h0_funcUnit_uses }, + { "ae_muls32x16.h0", ICLASS_AE_MULS32X16_H0, + 0, + Opcode_ae_muls32x16_h0_encode_fns, 1, Opcode_ae_muls32x16_h0_funcUnit_uses }, + { "ae_mulsf32x16.h0_s2", ICLASS_AE_MULSF32X16_H0_S2, + 0, + Opcode_ae_mulsf32x16_h0_s2_encode_fns, 1, Opcode_ae_mulsf32x16_h0_s2_funcUnit_uses }, + { "ae_muls32x16.h0_s2", ICLASS_AE_MULS32X16_H0_S2, + 0, + Opcode_ae_muls32x16_h0_s2_encode_fns, 1, Opcode_ae_muls32x16_h0_s2_funcUnit_uses }, + { "ae_mulsf32x16.h1", ICLASS_AE_MULSF32X16_H1, + 0, + Opcode_ae_mulsf32x16_h1_encode_fns, 1, Opcode_ae_mulsf32x16_h1_funcUnit_uses }, + { "ae_muls32x16.h1", ICLASS_AE_MULS32X16_H1, + 0, + Opcode_ae_muls32x16_h1_encode_fns, 1, Opcode_ae_muls32x16_h1_funcUnit_uses }, + { "ae_mulsf32x16.h1_s2", ICLASS_AE_MULSF32X16_H1_S2, + 0, + Opcode_ae_mulsf32x16_h1_s2_encode_fns, 1, Opcode_ae_mulsf32x16_h1_s2_funcUnit_uses }, + { "ae_muls32x16.h1_s2", ICLASS_AE_MULS32X16_H1_S2, + 0, + Opcode_ae_muls32x16_h1_s2_encode_fns, 1, Opcode_ae_muls32x16_h1_s2_funcUnit_uses }, + { "ae_mulsf32x16.h2", ICLASS_AE_MULSF32X16_H2, + 0, + Opcode_ae_mulsf32x16_h2_encode_fns, 1, Opcode_ae_mulsf32x16_h2_funcUnit_uses }, + { "ae_muls32x16.h2", ICLASS_AE_MULS32X16_H2, + 0, + Opcode_ae_muls32x16_h2_encode_fns, 1, Opcode_ae_muls32x16_h2_funcUnit_uses }, + { "ae_mulsf32x16.h2_s2", ICLASS_AE_MULSF32X16_H2_S2, + 0, + Opcode_ae_mulsf32x16_h2_s2_encode_fns, 1, Opcode_ae_mulsf32x16_h2_s2_funcUnit_uses }, + { "ae_muls32x16.h2_s2", ICLASS_AE_MULS32X16_H2_S2, + 0, + Opcode_ae_muls32x16_h2_s2_encode_fns, 1, Opcode_ae_muls32x16_h2_s2_funcUnit_uses }, + { "ae_mulsf32x16.h3", ICLASS_AE_MULSF32X16_H3, + 0, + Opcode_ae_mulsf32x16_h3_encode_fns, 1, Opcode_ae_mulsf32x16_h3_funcUnit_uses }, + { "ae_muls32x16.h3", ICLASS_AE_MULS32X16_H3, + 0, + Opcode_ae_muls32x16_h3_encode_fns, 1, Opcode_ae_muls32x16_h3_funcUnit_uses }, + { "ae_mulsf32x16.h3_s2", ICLASS_AE_MULSF32X16_H3_S2, + 0, + Opcode_ae_mulsf32x16_h3_s2_encode_fns, 1, Opcode_ae_mulsf32x16_h3_s2_funcUnit_uses }, + { "ae_muls32x16.h3_s2", ICLASS_AE_MULS32X16_H3_S2, + 0, + Opcode_ae_muls32x16_h3_s2_encode_fns, 1, Opcode_ae_muls32x16_h3_s2_funcUnit_uses }, + { "ae_mulaafd32x16.h3.l2", ICLASS_AE_MULAAFD32X16_H3_L2, + 0, + Opcode_ae_mulaafd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulaafd32x16_h3_l2_funcUnit_uses }, + { "ae_mulaad32x16.h3.l2", ICLASS_AE_MULAAD32X16_H3_L2, + 0, + Opcode_ae_mulaad32x16_h3_l2_encode_fns, 1, Opcode_ae_mulaad32x16_h3_l2_funcUnit_uses }, + { "ae_mulaafd32x16.h3.l2_s2", ICLASS_AE_MULAAFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulaafd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulaafd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulaad32x16.h3.l2_s2", ICLASS_AE_MULAAD32X16_H3_L2_S2, + 0, + Opcode_ae_mulaad32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulaad32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulaafd32x16.h1.l0", ICLASS_AE_MULAAFD32X16_H1_L0, + 0, + Opcode_ae_mulaafd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulaafd32x16_h1_l0_funcUnit_uses }, + { "ae_mulaad32x16.h1.l0", ICLASS_AE_MULAAD32X16_H1_L0, + 0, + Opcode_ae_mulaad32x16_h1_l0_encode_fns, 1, Opcode_ae_mulaad32x16_h1_l0_funcUnit_uses }, + { "ae_mulaafd32x16.h1.l0_s2", ICLASS_AE_MULAAFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulaafd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulaafd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulaad32x16.h1.l0_s2", ICLASS_AE_MULAAD32X16_H1_L0_S2, + 0, + Opcode_ae_mulaad32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulaad32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulasfd32x16.h3.l2", ICLASS_AE_MULASFD32X16_H3_L2, + 0, + Opcode_ae_mulasfd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulasfd32x16_h3_l2_funcUnit_uses }, + { "ae_mulasd32x16.h3.l2", ICLASS_AE_MULASD32X16_H3_L2, + 0, + Opcode_ae_mulasd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulasd32x16_h3_l2_funcUnit_uses }, + { "ae_mulasfd32x16.h3.l2_s2", ICLASS_AE_MULASFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulasfd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulasfd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulasd32x16.h3.l2_s2", ICLASS_AE_MULASD32X16_H3_L2_S2, + 0, + Opcode_ae_mulasd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulasd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulasfd32x16.h1.l0", ICLASS_AE_MULASFD32X16_H1_L0, + 0, + Opcode_ae_mulasfd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulasfd32x16_h1_l0_funcUnit_uses }, + { "ae_mulasd32x16.h1.l0", ICLASS_AE_MULASD32X16_H1_L0, + 0, + Opcode_ae_mulasd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulasd32x16_h1_l0_funcUnit_uses }, + { "ae_mulasfd32x16.h1.l0_s2", ICLASS_AE_MULASFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulasfd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulasfd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulasd32x16.h1.l0_s2", ICLASS_AE_MULASD32X16_H1_L0_S2, + 0, + Opcode_ae_mulasd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulasd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulsafd32x16.h3.l2", ICLASS_AE_MULSAFD32X16_H3_L2, + 0, + Opcode_ae_mulsafd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulsafd32x16_h3_l2_funcUnit_uses }, + { "ae_mulsad32x16.h3.l2", ICLASS_AE_MULSAD32X16_H3_L2, + 0, + Opcode_ae_mulsad32x16_h3_l2_encode_fns, 1, Opcode_ae_mulsad32x16_h3_l2_funcUnit_uses }, + { "ae_mulsafd32x16.h3.l2_s2", ICLASS_AE_MULSAFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulsafd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulsafd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulsad32x16.h3.l2_s2", ICLASS_AE_MULSAD32X16_H3_L2_S2, + 0, + Opcode_ae_mulsad32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulsad32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulsafd32x16.h1.l0", ICLASS_AE_MULSAFD32X16_H1_L0, + 0, + Opcode_ae_mulsafd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulsafd32x16_h1_l0_funcUnit_uses }, + { "ae_mulsad32x16.h1.l0", ICLASS_AE_MULSAD32X16_H1_L0, + 0, + Opcode_ae_mulsad32x16_h1_l0_encode_fns, 1, Opcode_ae_mulsad32x16_h1_l0_funcUnit_uses }, + { "ae_mulsafd32x16.h1.l0_s2", ICLASS_AE_MULSAFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulsafd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulsafd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulsad32x16.h1.l0_s2", ICLASS_AE_MULSAD32X16_H1_L0_S2, + 0, + Opcode_ae_mulsad32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulsad32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulssfd32x16.h3.l2", ICLASS_AE_MULSSFD32X16_H3_L2, + 0, + Opcode_ae_mulssfd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulssfd32x16_h3_l2_funcUnit_uses }, + { "ae_mulssd32x16.h3.l2", ICLASS_AE_MULSSD32X16_H3_L2, + 0, + Opcode_ae_mulssd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulssd32x16_h3_l2_funcUnit_uses }, + { "ae_mulssfd32x16.h3.l2_s2", ICLASS_AE_MULSSFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulssfd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulssfd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulssd32x16.h3.l2_s2", ICLASS_AE_MULSSD32X16_H3_L2_S2, + 0, + Opcode_ae_mulssd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulssd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulssfd32x16.h1.l0", ICLASS_AE_MULSSFD32X16_H1_L0, + 0, + Opcode_ae_mulssfd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulssfd32x16_h1_l0_funcUnit_uses }, + { "ae_mulssd32x16.h1.l0", ICLASS_AE_MULSSD32X16_H1_L0, + 0, + Opcode_ae_mulssd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulssd32x16_h1_l0_funcUnit_uses }, + { "ae_mulssfd32x16.h1.l0_s2", ICLASS_AE_MULSSFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulssfd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulssfd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulssd32x16.h1.l0_s2", ICLASS_AE_MULSSD32X16_H1_L0_S2, + 0, + Opcode_ae_mulssd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulssd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzaafd32x16.h3.l2", ICLASS_AE_MULZAAFD32X16_H3_L2, + 0, + Opcode_ae_mulzaafd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzaad32x16.h3.l2", ICLASS_AE_MULZAAD32X16_H3_L2, + 0, + Opcode_ae_mulzaad32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzaad32x16_h3_l2_funcUnit_uses }, + { "ae_mulzaafd32x16.h3.l2_s2", ICLASS_AE_MULZAAFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzaafd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzaad32x16.h3.l2_s2", ICLASS_AE_MULZAAD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzaad32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzaad32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzaafd32x16.h1.l0", ICLASS_AE_MULZAAFD32X16_H1_L0, + 0, + Opcode_ae_mulzaafd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzaafd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzaad32x16.h1.l0", ICLASS_AE_MULZAAD32X16_H1_L0, + 0, + Opcode_ae_mulzaad32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzaad32x16_h1_l0_funcUnit_uses }, + { "ae_mulzaafd32x16.h1.l0_s2", ICLASS_AE_MULZAAFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzaafd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzaad32x16.h1.l0_s2", ICLASS_AE_MULZAAD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzaad32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzaad32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzasfd32x16.h3.l2", ICLASS_AE_MULZASFD32X16_H3_L2, + 0, + Opcode_ae_mulzasfd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzasfd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzasd32x16.h3.l2", ICLASS_AE_MULZASD32X16_H3_L2, + 0, + Opcode_ae_mulzasd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzasd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzasfd32x16.h3.l2_s2", ICLASS_AE_MULZASFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzasfd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzasfd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzasd32x16.h3.l2_s2", ICLASS_AE_MULZASD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzasd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzasd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzasfd32x16.h1.l0", ICLASS_AE_MULZASFD32X16_H1_L0, + 0, + Opcode_ae_mulzasfd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzasfd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzasd32x16.h1.l0", ICLASS_AE_MULZASD32X16_H1_L0, + 0, + Opcode_ae_mulzasd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzasd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzasfd32x16.h1.l0_s2", ICLASS_AE_MULZASFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzasfd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzasfd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzasd32x16.h1.l0_s2", ICLASS_AE_MULZASD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzasd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzasd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzsafd32x16.h3.l2", ICLASS_AE_MULZSAFD32X16_H3_L2, + 0, + Opcode_ae_mulzsafd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzsafd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzsad32x16.h3.l2", ICLASS_AE_MULZSAD32X16_H3_L2, + 0, + Opcode_ae_mulzsad32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzsad32x16_h3_l2_funcUnit_uses }, + { "ae_mulzsafd32x16.h3.l2_s2", ICLASS_AE_MULZSAFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzsafd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzsafd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzsad32x16.h3.l2_s2", ICLASS_AE_MULZSAD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzsad32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzsad32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzsafd32x16.h1.l0", ICLASS_AE_MULZSAFD32X16_H1_L0, + 0, + Opcode_ae_mulzsafd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzsafd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzsad32x16.h1.l0", ICLASS_AE_MULZSAD32X16_H1_L0, + 0, + Opcode_ae_mulzsad32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzsad32x16_h1_l0_funcUnit_uses }, + { "ae_mulzsafd32x16.h1.l0_s2", ICLASS_AE_MULZSAFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzsafd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzsafd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzsad32x16.h1.l0_s2", ICLASS_AE_MULZSAD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzsad32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzsad32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzssfd32x16.h3.l2", ICLASS_AE_MULZSSFD32X16_H3_L2, + 0, + Opcode_ae_mulzssfd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzssfd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzssd32x16.h3.l2", ICLASS_AE_MULZSSD32X16_H3_L2, + 0, + Opcode_ae_mulzssd32x16_h3_l2_encode_fns, 1, Opcode_ae_mulzssd32x16_h3_l2_funcUnit_uses }, + { "ae_mulzssfd32x16.h3.l2_s2", ICLASS_AE_MULZSSFD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzssfd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzssfd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzssd32x16.h3.l2_s2", ICLASS_AE_MULZSSD32X16_H3_L2_S2, + 0, + Opcode_ae_mulzssd32x16_h3_l2_s2_encode_fns, 1, Opcode_ae_mulzssd32x16_h3_l2_s2_funcUnit_uses }, + { "ae_mulzssfd32x16.h1.l0", ICLASS_AE_MULZSSFD32X16_H1_L0, + 0, + Opcode_ae_mulzssfd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzssfd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzssd32x16.h1.l0", ICLASS_AE_MULZSSD32X16_H1_L0, + 0, + Opcode_ae_mulzssd32x16_h1_l0_encode_fns, 1, Opcode_ae_mulzssd32x16_h1_l0_funcUnit_uses }, + { "ae_mulzssfd32x16.h1.l0_s2", ICLASS_AE_MULZSSFD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzssfd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzssfd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzssd32x16.h1.l0_s2", ICLASS_AE_MULZSSD32X16_H1_L0_S2, + 0, + Opcode_ae_mulzssd32x16_h1_l0_s2_encode_fns, 1, Opcode_ae_mulzssd32x16_h1_l0_s2_funcUnit_uses }, + { "ae_mulzaafd32x16.h2.l3", ICLASS_AE_MULZAAFD32X16_H2_L3, + 0, + Opcode_ae_mulzaafd32x16_h2_l3_encode_fns, 1, Opcode_ae_mulzaafd32x16_h2_l3_funcUnit_uses }, + { "ae_mulzaafd32x16.h0.l1", ICLASS_AE_MULZAAFD32X16_H0_L1, + 0, + Opcode_ae_mulzaafd32x16_h0_l1_encode_fns, 1, Opcode_ae_mulzaafd32x16_h0_l1_funcUnit_uses }, + { "ae_mulaafd32x16.h2.l3", ICLASS_AE_MULAAFD32X16_H2_L3, + 0, + Opcode_ae_mulaafd32x16_h2_l3_encode_fns, 1, Opcode_ae_mulaafd32x16_h2_l3_funcUnit_uses }, + { "ae_mulaafd32x16.h0.l1", ICLASS_AE_MULAAFD32X16_H0_L1, + 0, + Opcode_ae_mulaafd32x16_h0_l1_encode_fns, 1, Opcode_ae_mulaafd32x16_h0_l1_funcUnit_uses }, + { "ae_mulzaad32x16.h2.l3", ICLASS_AE_MULZAAD32X16_H2_L3, + 0, + Opcode_ae_mulzaad32x16_h2_l3_encode_fns, 1, Opcode_ae_mulzaad32x16_h2_l3_funcUnit_uses }, + { "ae_mulzaad32x16.h0.l1", ICLASS_AE_MULZAAD32X16_H0_L1, + 0, + Opcode_ae_mulzaad32x16_h0_l1_encode_fns, 1, Opcode_ae_mulzaad32x16_h0_l1_funcUnit_uses }, + { "ae_mulaad32x16.h2.l3", ICLASS_AE_MULAAD32X16_H2_L3, + 0, + Opcode_ae_mulaad32x16_h2_l3_encode_fns, 1, Opcode_ae_mulaad32x16_h2_l3_funcUnit_uses }, + { "ae_mulaad32x16.h0.l1", ICLASS_AE_MULAAD32X16_H0_L1, + 0, + Opcode_ae_mulaad32x16_h0_l1_encode_fns, 1, Opcode_ae_mulaad32x16_h0_l1_funcUnit_uses }, + { "ae_mulzaafd32x16.h2.l3_s2", ICLASS_AE_MULZAAFD32X16_H2_L3_S2, + 0, + Opcode_ae_mulzaafd32x16_h2_l3_s2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h2_l3_s2_funcUnit_uses }, + { "ae_mulzaafd32x16.h0.l1_s2", ICLASS_AE_MULZAAFD32X16_H0_L1_S2, + 0, + Opcode_ae_mulzaafd32x16_h0_l1_s2_encode_fns, 1, Opcode_ae_mulzaafd32x16_h0_l1_s2_funcUnit_uses }, + { "ae_mulaafd32x16.h2.l3_s2", ICLASS_AE_MULAAFD32X16_H2_L3_S2, + 0, + Opcode_ae_mulaafd32x16_h2_l3_s2_encode_fns, 1, Opcode_ae_mulaafd32x16_h2_l3_s2_funcUnit_uses }, + { "ae_mulaafd32x16.h0.l1_s2", ICLASS_AE_MULAAFD32X16_H0_L1_S2, + 0, + Opcode_ae_mulaafd32x16_h0_l1_s2_encode_fns, 1, Opcode_ae_mulaafd32x16_h0_l1_s2_funcUnit_uses }, + { "ae_mulzaad32x16.h2.l3_s2", ICLASS_AE_MULZAAD32X16_H2_L3_S2, + 0, + Opcode_ae_mulzaad32x16_h2_l3_s2_encode_fns, 1, Opcode_ae_mulzaad32x16_h2_l3_s2_funcUnit_uses }, + { "ae_mulzaad32x16.h0.l1_s2", ICLASS_AE_MULZAAD32X16_H0_L1_S2, + 0, + Opcode_ae_mulzaad32x16_h0_l1_s2_encode_fns, 1, Opcode_ae_mulzaad32x16_h0_l1_s2_funcUnit_uses }, + { "ae_mulaad32x16.h2.l3_s2", ICLASS_AE_MULAAD32X16_H2_L3_S2, + 0, + Opcode_ae_mulaad32x16_h2_l3_s2_encode_fns, 1, Opcode_ae_mulaad32x16_h2_l3_s2_funcUnit_uses }, + { "ae_mulaad32x16.h0.l1_s2", ICLASS_AE_MULAAD32X16_H0_L1_S2, + 0, + Opcode_ae_mulaad32x16_h0_l1_s2_encode_fns, 1, Opcode_ae_mulaad32x16_h0_l1_s2_funcUnit_uses }, + { "ae_mulp32x16x2.h", ICLASS_AE_MULP32X16X2_H, + 0, + Opcode_ae_mulp32x16x2_h_encode_fns, 1, Opcode_ae_mulp32x16x2_h_funcUnit_uses }, + { "ae_mulfp32x16x2rs.h", ICLASS_AE_MULFP32X16X2RS_H, + 0, + Opcode_ae_mulfp32x16x2rs_h_encode_fns, 1, Opcode_ae_mulfp32x16x2rs_h_funcUnit_uses }, + { "ae_mulfp32x16x2ras.h", ICLASS_AE_MULFP32X16X2RAS_H, + 0, + Opcode_ae_mulfp32x16x2ras_h_encode_fns, 1, Opcode_ae_mulfp32x16x2ras_h_funcUnit_uses }, + { "ae_mulfp32x16x2s.h", ICLASS_AE_MULFP32X16X2S_H, + 0, + Opcode_ae_mulfp32x16x2s_h_encode_fns, 1, Opcode_ae_mulfp32x16x2s_h_funcUnit_uses }, + { "ae_mulfp32x16x2s.h_s2", ICLASS_AE_MULFP32X16X2S_H_S2, + 0, + Opcode_ae_mulfp32x16x2s_h_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2s_h_s2_funcUnit_uses }, + { "ae_mulp32x16x2.h_s2", ICLASS_AE_MULP32X16X2_H_S2, + 0, + Opcode_ae_mulp32x16x2_h_s2_encode_fns, 1, Opcode_ae_mulp32x16x2_h_s2_funcUnit_uses }, + { "ae_mulfp32x16x2rs.h_s2", ICLASS_AE_MULFP32X16X2RS_H_S2, + 0, + Opcode_ae_mulfp32x16x2rs_h_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2rs_h_s2_funcUnit_uses }, + { "ae_mulfp32x16x2ras.h_s2", ICLASS_AE_MULFP32X16X2RAS_H_S2, + 0, + Opcode_ae_mulfp32x16x2ras_h_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2ras_h_s2_funcUnit_uses }, + { "ae_mulp32x16x2.l", ICLASS_AE_MULP32X16X2_L, + 0, + Opcode_ae_mulp32x16x2_l_encode_fns, 1, Opcode_ae_mulp32x16x2_l_funcUnit_uses }, + { "ae_mulfp32x16x2rs.l", ICLASS_AE_MULFP32X16X2RS_L, + 0, + Opcode_ae_mulfp32x16x2rs_l_encode_fns, 1, Opcode_ae_mulfp32x16x2rs_l_funcUnit_uses }, + { "ae_mulfp32x16x2ras.l", ICLASS_AE_MULFP32X16X2RAS_L, + 0, + Opcode_ae_mulfp32x16x2ras_l_encode_fns, 1, Opcode_ae_mulfp32x16x2ras_l_funcUnit_uses }, + { "ae_mulfp32x16x2s.l", ICLASS_AE_MULFP32X16X2S_L, + 0, + Opcode_ae_mulfp32x16x2s_l_encode_fns, 1, Opcode_ae_mulfp32x16x2s_l_funcUnit_uses }, + { "ae_mulfp32x16x2s.l_s2", ICLASS_AE_MULFP32X16X2S_L_S2, + 0, + Opcode_ae_mulfp32x16x2s_l_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2s_l_s2_funcUnit_uses }, + { "ae_mulp32x16x2.l_s2", ICLASS_AE_MULP32X16X2_L_S2, + 0, + Opcode_ae_mulp32x16x2_l_s2_encode_fns, 1, Opcode_ae_mulp32x16x2_l_s2_funcUnit_uses }, + { "ae_mulfp32x16x2rs.l_s2", ICLASS_AE_MULFP32X16X2RS_L_S2, + 0, + Opcode_ae_mulfp32x16x2rs_l_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2rs_l_s2_funcUnit_uses }, + { "ae_mulfp32x16x2ras.l_s2", ICLASS_AE_MULFP32X16X2RAS_L_S2, + 0, + Opcode_ae_mulfp32x16x2ras_l_s2_encode_fns, 1, Opcode_ae_mulfp32x16x2ras_l_s2_funcUnit_uses }, + { "ae_mulap32x16x2.h", ICLASS_AE_MULAP32X16X2_H, + 0, + Opcode_ae_mulap32x16x2_h_encode_fns, 1, Opcode_ae_mulap32x16x2_h_funcUnit_uses }, + { "ae_mulafp32x16x2rs.h", ICLASS_AE_MULAFP32X16X2RS_H, + 0, + Opcode_ae_mulafp32x16x2rs_h_encode_fns, 1, Opcode_ae_mulafp32x16x2rs_h_funcUnit_uses }, + { "ae_mulafp32x16x2ras.h", ICLASS_AE_MULAFP32X16X2RAS_H, + 0, + Opcode_ae_mulafp32x16x2ras_h_encode_fns, 1, Opcode_ae_mulafp32x16x2ras_h_funcUnit_uses }, + { "ae_mulafp32x16x2s.h", ICLASS_AE_MULAFP32X16X2S_H, + 0, + Opcode_ae_mulafp32x16x2s_h_encode_fns, 1, Opcode_ae_mulafp32x16x2s_h_funcUnit_uses }, + { "ae_mulafp32x16x2s.h_s2", ICLASS_AE_MULAFP32X16X2S_H_S2, + 0, + Opcode_ae_mulafp32x16x2s_h_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2s_h_s2_funcUnit_uses }, + { "ae_mulap32x16x2.h_s2", ICLASS_AE_MULAP32X16X2_H_S2, + 0, + Opcode_ae_mulap32x16x2_h_s2_encode_fns, 1, Opcode_ae_mulap32x16x2_h_s2_funcUnit_uses }, + { "ae_mulafp32x16x2rs.h_s2", ICLASS_AE_MULAFP32X16X2RS_H_S2, + 0, + Opcode_ae_mulafp32x16x2rs_h_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2rs_h_s2_funcUnit_uses }, + { "ae_mulafp32x16x2ras.h_s2", ICLASS_AE_MULAFP32X16X2RAS_H_S2, + 0, + Opcode_ae_mulafp32x16x2ras_h_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2ras_h_s2_funcUnit_uses }, + { "ae_mulap32x16x2.l", ICLASS_AE_MULAP32X16X2_L, + 0, + Opcode_ae_mulap32x16x2_l_encode_fns, 1, Opcode_ae_mulap32x16x2_l_funcUnit_uses }, + { "ae_mulafp32x16x2rs.l", ICLASS_AE_MULAFP32X16X2RS_L, + 0, + Opcode_ae_mulafp32x16x2rs_l_encode_fns, 1, Opcode_ae_mulafp32x16x2rs_l_funcUnit_uses }, + { "ae_mulafp32x16x2ras.l", ICLASS_AE_MULAFP32X16X2RAS_L, + 0, + Opcode_ae_mulafp32x16x2ras_l_encode_fns, 1, Opcode_ae_mulafp32x16x2ras_l_funcUnit_uses }, + { "ae_mulafp32x16x2s.l", ICLASS_AE_MULAFP32X16X2S_L, + 0, + Opcode_ae_mulafp32x16x2s_l_encode_fns, 1, Opcode_ae_mulafp32x16x2s_l_funcUnit_uses }, + { "ae_mulafp32x16x2s.l_s2", ICLASS_AE_MULAFP32X16X2S_L_S2, + 0, + Opcode_ae_mulafp32x16x2s_l_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2s_l_s2_funcUnit_uses }, + { "ae_mulap32x16x2.l_s2", ICLASS_AE_MULAP32X16X2_L_S2, + 0, + Opcode_ae_mulap32x16x2_l_s2_encode_fns, 1, Opcode_ae_mulap32x16x2_l_s2_funcUnit_uses }, + { "ae_mulafp32x16x2rs.l_s2", ICLASS_AE_MULAFP32X16X2RS_L_S2, + 0, + Opcode_ae_mulafp32x16x2rs_l_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2rs_l_s2_funcUnit_uses }, + { "ae_mulafp32x16x2ras.l_s2", ICLASS_AE_MULAFP32X16X2RAS_L_S2, + 0, + Opcode_ae_mulafp32x16x2ras_l_s2_encode_fns, 1, Opcode_ae_mulafp32x16x2ras_l_s2_funcUnit_uses }, + { "ae_mulsp32x16x2.h", ICLASS_AE_MULSP32X16X2_H, + 0, + Opcode_ae_mulsp32x16x2_h_encode_fns, 1, Opcode_ae_mulsp32x16x2_h_funcUnit_uses }, + { "ae_mulsfp32x16x2rs.h", ICLASS_AE_MULSFP32X16X2RS_H, + 0, + Opcode_ae_mulsfp32x16x2rs_h_encode_fns, 1, Opcode_ae_mulsfp32x16x2rs_h_funcUnit_uses }, + { "ae_mulsfp32x16x2ras.h", ICLASS_AE_MULSFP32X16X2RAS_H, + 0, + Opcode_ae_mulsfp32x16x2ras_h_encode_fns, 1, Opcode_ae_mulsfp32x16x2ras_h_funcUnit_uses }, + { "ae_mulsfp32x16x2s.h", ICLASS_AE_MULSFP32X16X2S_H, + 0, + Opcode_ae_mulsfp32x16x2s_h_encode_fns, 1, Opcode_ae_mulsfp32x16x2s_h_funcUnit_uses }, + { "ae_mulsfp32x16x2s.h_s2", ICLASS_AE_MULSFP32X16X2S_H_S2, + 0, + Opcode_ae_mulsfp32x16x2s_h_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2s_h_s2_funcUnit_uses }, + { "ae_mulsp32x16x2.h_s2", ICLASS_AE_MULSP32X16X2_H_S2, + 0, + Opcode_ae_mulsp32x16x2_h_s2_encode_fns, 1, Opcode_ae_mulsp32x16x2_h_s2_funcUnit_uses }, + { "ae_mulsfp32x16x2rs.h_s2", ICLASS_AE_MULSFP32X16X2RS_H_S2, + 0, + Opcode_ae_mulsfp32x16x2rs_h_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2rs_h_s2_funcUnit_uses }, + { "ae_mulsfp32x16x2ras.h_s2", ICLASS_AE_MULSFP32X16X2RAS_H_S2, + 0, + Opcode_ae_mulsfp32x16x2ras_h_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2ras_h_s2_funcUnit_uses }, + { "ae_mulsp32x16x2.l", ICLASS_AE_MULSP32X16X2_L, + 0, + Opcode_ae_mulsp32x16x2_l_encode_fns, 1, Opcode_ae_mulsp32x16x2_l_funcUnit_uses }, + { "ae_mulsfp32x16x2rs.l", ICLASS_AE_MULSFP32X16X2RS_L, + 0, + Opcode_ae_mulsfp32x16x2rs_l_encode_fns, 1, Opcode_ae_mulsfp32x16x2rs_l_funcUnit_uses }, + { "ae_mulsfp32x16x2ras.l", ICLASS_AE_MULSFP32X16X2RAS_L, + 0, + Opcode_ae_mulsfp32x16x2ras_l_encode_fns, 1, Opcode_ae_mulsfp32x16x2ras_l_funcUnit_uses }, + { "ae_mulsfp32x16x2s.l", ICLASS_AE_MULSFP32X16X2S_L, + 0, + Opcode_ae_mulsfp32x16x2s_l_encode_fns, 1, Opcode_ae_mulsfp32x16x2s_l_funcUnit_uses }, + { "ae_mulsfp32x16x2s.l_s2", ICLASS_AE_MULSFP32X16X2S_L_S2, + 0, + Opcode_ae_mulsfp32x16x2s_l_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2s_l_s2_funcUnit_uses }, + { "ae_mulsp32x16x2.l_s2", ICLASS_AE_MULSP32X16X2_L_S2, + 0, + Opcode_ae_mulsp32x16x2_l_s2_encode_fns, 1, Opcode_ae_mulsp32x16x2_l_s2_funcUnit_uses }, + { "ae_mulsfp32x16x2rs.l_s2", ICLASS_AE_MULSFP32X16X2RS_L_S2, + 0, + Opcode_ae_mulsfp32x16x2rs_l_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2rs_l_s2_funcUnit_uses }, + { "ae_mulsfp32x16x2ras.l_s2", ICLASS_AE_MULSFP32X16X2RAS_L_S2, + 0, + Opcode_ae_mulsfp32x16x2ras_l_s2_encode_fns, 1, Opcode_ae_mulsfp32x16x2ras_l_s2_funcUnit_uses }, + { "ae_mulp32x2", ICLASS_AE_MULP32X2, + 0, + Opcode_ae_mulp32x2_encode_fns, 1, Opcode_ae_mulp32x2_funcUnit_uses }, + { "ae_mulfp32x2rs", ICLASS_AE_MULFP32X2RS, + 0, + Opcode_ae_mulfp32x2rs_encode_fns, 1, Opcode_ae_mulfp32x2rs_funcUnit_uses }, + { "ae_mulfp32x2ras", ICLASS_AE_MULFP32X2RAS, + 0, + Opcode_ae_mulfp32x2ras_encode_fns, 1, Opcode_ae_mulfp32x2ras_funcUnit_uses }, + { "ae_mulp32x2_s2", ICLASS_AE_MULP32X2_S2, + 0, + Opcode_ae_mulp32x2_s2_encode_fns, 1, Opcode_ae_mulp32x2_s2_funcUnit_uses }, + { "ae_mulfp32x2rs_s2", ICLASS_AE_MULFP32X2RS_S2, + 0, + Opcode_ae_mulfp32x2rs_s2_encode_fns, 1, Opcode_ae_mulfp32x2rs_s2_funcUnit_uses }, + { "ae_mulfp32x2ras_s2", ICLASS_AE_MULFP32X2RAS_S2, + 0, + Opcode_ae_mulfp32x2ras_s2_encode_fns, 1, Opcode_ae_mulfp32x2ras_s2_funcUnit_uses }, + { "ae_mulap32x2", ICLASS_AE_MULAP32X2, + 0, + Opcode_ae_mulap32x2_encode_fns, 1, Opcode_ae_mulap32x2_funcUnit_uses }, + { "ae_mulafp32x2rs", ICLASS_AE_MULAFP32X2RS, + 0, + Opcode_ae_mulafp32x2rs_encode_fns, 1, Opcode_ae_mulafp32x2rs_funcUnit_uses }, + { "ae_mulafp32x2ras", ICLASS_AE_MULAFP32X2RAS, + 0, + Opcode_ae_mulafp32x2ras_encode_fns, 1, Opcode_ae_mulafp32x2ras_funcUnit_uses }, + { "ae_mulap32x2_s2", ICLASS_AE_MULAP32X2_S2, + 0, + Opcode_ae_mulap32x2_s2_encode_fns, 1, Opcode_ae_mulap32x2_s2_funcUnit_uses }, + { "ae_mulafp32x2rs_s2", ICLASS_AE_MULAFP32X2RS_S2, + 0, + Opcode_ae_mulafp32x2rs_s2_encode_fns, 1, Opcode_ae_mulafp32x2rs_s2_funcUnit_uses }, + { "ae_mulafp32x2ras_s2", ICLASS_AE_MULAFP32X2RAS_S2, + 0, + Opcode_ae_mulafp32x2ras_s2_encode_fns, 1, Opcode_ae_mulafp32x2ras_s2_funcUnit_uses }, + { "ae_mulsp32x2", ICLASS_AE_MULSP32X2, + 0, + Opcode_ae_mulsp32x2_encode_fns, 1, Opcode_ae_mulsp32x2_funcUnit_uses }, + { "ae_mulsfp32x2rs", ICLASS_AE_MULSFP32X2RS, + 0, + Opcode_ae_mulsfp32x2rs_encode_fns, 1, Opcode_ae_mulsfp32x2rs_funcUnit_uses }, + { "ae_mulsfp32x2ras", ICLASS_AE_MULSFP32X2RAS, + 0, + Opcode_ae_mulsfp32x2ras_encode_fns, 1, Opcode_ae_mulsfp32x2ras_funcUnit_uses }, + { "ae_mulsp32x2_s2", ICLASS_AE_MULSP32X2_S2, + 0, + Opcode_ae_mulsp32x2_s2_encode_fns, 1, Opcode_ae_mulsp32x2_s2_funcUnit_uses }, + { "ae_mulsfp32x2rs_s2", ICLASS_AE_MULSFP32X2RS_S2, + 0, + Opcode_ae_mulsfp32x2rs_s2_encode_fns, 1, Opcode_ae_mulsfp32x2rs_s2_funcUnit_uses }, + { "ae_mulsfp32x2ras_s2", ICLASS_AE_MULSFP32X2RAS_S2, + 0, + Opcode_ae_mulsfp32x2ras_s2_encode_fns, 1, Opcode_ae_mulsfp32x2ras_s2_funcUnit_uses }, + { "ae_mulfp16x4s", ICLASS_AE_MULFP16X4S, + 0, + Opcode_ae_mulfp16x4s_encode_fns, 2, Opcode_ae_mulfp16x4s_funcUnit_uses }, + { "ae_mulfp16x4ras", ICLASS_AE_MULFP16X4RAS, + 0, + Opcode_ae_mulfp16x4ras_encode_fns, 2, Opcode_ae_mulfp16x4ras_funcUnit_uses }, + { "ae_mulc32", ICLASS_AE_MULC32, + 0, + Opcode_ae_mulc32_encode_fns, 2, Opcode_ae_mulc32_funcUnit_uses }, + { "ae_mulfc24ra", ICLASS_AE_MULFC24RA, + 0, + Opcode_ae_mulfc24ra_encode_fns, 2, Opcode_ae_mulfc24ra_funcUnit_uses }, + { "ae_mulfc32ras", ICLASS_AE_MULFC32RAS, + 0, + Opcode_ae_mulfc32ras_encode_fns, 2, Opcode_ae_mulfc32ras_funcUnit_uses }, + { "ae_mulc32x16.l", ICLASS_AE_MULC32X16_L, + 0, + Opcode_ae_mulc32x16_l_encode_fns, 2, Opcode_ae_mulc32x16_l_funcUnit_uses }, + { "ae_mulfc32x16ras.l", ICLASS_AE_MULFC32X16RAS_L, + 0, + Opcode_ae_mulfc32x16ras_l_encode_fns, 2, Opcode_ae_mulfc32x16ras_l_funcUnit_uses }, + { "ae_mulc32x16.h", ICLASS_AE_MULC32X16_H, + 0, + Opcode_ae_mulc32x16_h_encode_fns, 2, Opcode_ae_mulc32x16_h_funcUnit_uses }, + { "ae_mulfc32x16ras.h", ICLASS_AE_MULFC32X16RAS_H, + 0, + Opcode_ae_mulfc32x16ras_h_encode_fns, 2, Opcode_ae_mulfc32x16ras_h_funcUnit_uses }, + { "ae_mulac32", ICLASS_AE_MULAC32, + 0, + Opcode_ae_mulac32_encode_fns, 2, Opcode_ae_mulac32_funcUnit_uses }, + { "ae_mulafc24ra", ICLASS_AE_MULAFC24RA, + 0, + Opcode_ae_mulafc24ra_encode_fns, 2, Opcode_ae_mulafc24ra_funcUnit_uses }, + { "ae_mulafc32ras", ICLASS_AE_MULAFC32RAS, + 0, + Opcode_ae_mulafc32ras_encode_fns, 2, Opcode_ae_mulafc32ras_funcUnit_uses }, + { "ae_mulac32x16.l", ICLASS_AE_MULAC32X16_L, + 0, + Opcode_ae_mulac32x16_l_encode_fns, 2, Opcode_ae_mulac32x16_l_funcUnit_uses }, + { "ae_mulafc32x16ras.l", ICLASS_AE_MULAFC32X16RAS_L, + 0, + Opcode_ae_mulafc32x16ras_l_encode_fns, 2, Opcode_ae_mulafc32x16ras_l_funcUnit_uses }, + { "ae_mulac32x16.h", ICLASS_AE_MULAC32X16_H, + 0, + Opcode_ae_mulac32x16_h_encode_fns, 2, Opcode_ae_mulac32x16_h_funcUnit_uses }, + { "ae_mulafc32x16ras.h", ICLASS_AE_MULAFC32X16RAS_H, + 0, + Opcode_ae_mulafc32x16ras_h_encode_fns, 2, Opcode_ae_mulafc32x16ras_h_funcUnit_uses }, + { "ae_mulf16x4ss", ICLASS_AE_MULF16X4SS, + 0, + Opcode_ae_mulf16x4ss_encode_fns, 2, Opcode_ae_mulf16x4ss_funcUnit_uses }, + { "ae_mulaf16x4ss", ICLASS_AE_MULAF16X4SS, + 0, + Opcode_ae_mulaf16x4ss_encode_fns, 2, Opcode_ae_mulaf16x4ss_funcUnit_uses }, + { "ae_mulsf16x4ss", ICLASS_AE_MULSF16X4SS, + 0, + Opcode_ae_mulsf16x4ss_encode_fns, 2, Opcode_ae_mulsf16x4ss_funcUnit_uses }, + { "ae_mul16x4", ICLASS_AE_MUL16X4, + 0, + Opcode_ae_mul16x4_encode_fns, 2, Opcode_ae_mul16x4_funcUnit_uses }, + { "ae_mula16x4", ICLASS_AE_MULA16X4, + 0, + Opcode_ae_mula16x4_encode_fns, 2, Opcode_ae_mula16x4_funcUnit_uses }, + { "ae_muls16x4", ICLASS_AE_MULS16X4, + 0, + Opcode_ae_muls16x4_encode_fns, 2, Opcode_ae_muls16x4_funcUnit_uses }, + { "ae_mulfd32x2s.fir.h", ICLASS_AE_MULFD32X2S_FIR_H, + 0, + Opcode_ae_mulfd32x2s_fir_h_encode_fns, 2, Opcode_ae_mulfd32x2s_fir_h_funcUnit_uses }, + { "ae_mulfd32x2ra.fir.h", ICLASS_AE_MULFD32X2RA_FIR_H, + 0, + Opcode_ae_mulfd32x2ra_fir_h_encode_fns, 2, Opcode_ae_mulfd32x2ra_fir_h_funcUnit_uses }, + { "ae_mulfd32x2s.fir.l", ICLASS_AE_MULFD32X2S_FIR_L, + 0, + Opcode_ae_mulfd32x2s_fir_l_encode_fns, 2, Opcode_ae_mulfd32x2s_fir_l_funcUnit_uses }, + { "ae_mulfd32x2ra.fir.l", ICLASS_AE_MULFD32X2RA_FIR_L, + 0, + Opcode_ae_mulfd32x2ra_fir_l_encode_fns, 2, Opcode_ae_mulfd32x2ra_fir_l_funcUnit_uses }, + { "ae_mulfd32x16x2.fir.hh", ICLASS_AE_MULFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulfd32x16x2_fir_hh_encode_fns, 2, Opcode_ae_mulfd32x16x2_fir_hh_funcUnit_uses }, + { "ae_mulfd32x16x2.fir.hl", ICLASS_AE_MULFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulfd32x16x2_fir_hl_encode_fns, 2, Opcode_ae_mulfd32x16x2_fir_hl_funcUnit_uses }, + { "ae_mulfd32x16x2.fir.lh", ICLASS_AE_MULFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulfd32x16x2_fir_lh_encode_fns, 2, Opcode_ae_mulfd32x16x2_fir_lh_funcUnit_uses }, + { "ae_mulfd32x16x2.fir.ll", ICLASS_AE_MULFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulfd32x16x2_fir_ll_encode_fns, 2, Opcode_ae_mulfd32x16x2_fir_ll_funcUnit_uses }, + { "ae_mulafd32x2s.fir.h", ICLASS_AE_MULAFD32X2S_FIR_H, + 0, + Opcode_ae_mulafd32x2s_fir_h_encode_fns, 2, Opcode_ae_mulafd32x2s_fir_h_funcUnit_uses }, + { "ae_mulafd32x2ra.fir.h", ICLASS_AE_MULAFD32X2RA_FIR_H, + 0, + Opcode_ae_mulafd32x2ra_fir_h_encode_fns, 2, Opcode_ae_mulafd32x2ra_fir_h_funcUnit_uses }, + { "ae_mulafd32x2s.fir.l", ICLASS_AE_MULAFD32X2S_FIR_L, + 0, + Opcode_ae_mulafd32x2s_fir_l_encode_fns, 2, Opcode_ae_mulafd32x2s_fir_l_funcUnit_uses }, + { "ae_mulafd32x2ra.fir.l", ICLASS_AE_MULAFD32X2RA_FIR_L, + 0, + Opcode_ae_mulafd32x2ra_fir_l_encode_fns, 2, Opcode_ae_mulafd32x2ra_fir_l_funcUnit_uses }, + { "ae_mulafd32x16x2.fir.hh", ICLASS_AE_MULAFD32X16X2_FIR_HH, + 0, + Opcode_ae_mulafd32x16x2_fir_hh_encode_fns, 2, Opcode_ae_mulafd32x16x2_fir_hh_funcUnit_uses }, + { "ae_mulafd32x16x2.fir.hl", ICLASS_AE_MULAFD32X16X2_FIR_HL, + 0, + Opcode_ae_mulafd32x16x2_fir_hl_encode_fns, 2, Opcode_ae_mulafd32x16x2_fir_hl_funcUnit_uses }, + { "ae_mulafd32x16x2.fir.lh", ICLASS_AE_MULAFD32X16X2_FIR_LH, + 0, + Opcode_ae_mulafd32x16x2_fir_lh_encode_fns, 2, Opcode_ae_mulafd32x16x2_fir_lh_funcUnit_uses }, + { "ae_mulafd32x16x2.fir.ll", ICLASS_AE_MULAFD32X16X2_FIR_LL, + 0, + Opcode_ae_mulafd32x16x2_fir_ll_encode_fns, 2, Opcode_ae_mulafd32x16x2_fir_ll_funcUnit_uses }, + { "ae_mulzaaaafq32x16", ICLASS_AE_MULZAAAAFQ32X16, + 0, + Opcode_ae_mulzaaaafq32x16_encode_fns, 1, Opcode_ae_mulzaaaafq32x16_funcUnit_uses }, + { "ae_mulaaaafq32x16", ICLASS_AE_MULAAAAFQ32X16, + 0, + Opcode_ae_mulaaaafq32x16_encode_fns, 1, Opcode_ae_mulaaaafq32x16_funcUnit_uses }, + { "ae_mulzaaaafq32x16_s2", ICLASS_AE_MULZAAAAFQ32X16_S2, + 0, + Opcode_ae_mulzaaaafq32x16_s2_encode_fns, 1, Opcode_ae_mulzaaaafq32x16_s2_funcUnit_uses }, + { "ae_mulaaaafq32x16_s2", ICLASS_AE_MULAAAAFQ32X16_S2, + 0, + Opcode_ae_mulaaaafq32x16_s2_encode_fns, 1, Opcode_ae_mulaaaafq32x16_s2_funcUnit_uses }, + { "ae_mulzaaaaq32x16", ICLASS_AE_MULZAAAAQ32X16, + 0, + Opcode_ae_mulzaaaaq32x16_encode_fns, 1, Opcode_ae_mulzaaaaq32x16_funcUnit_uses }, + { "ae_mulaaaaq32x16", ICLASS_AE_MULAAAAQ32X16, + 0, + Opcode_ae_mulaaaaq32x16_encode_fns, 1, Opcode_ae_mulaaaaq32x16_funcUnit_uses }, + { "ae_mulzaaaaq32x16_s2", ICLASS_AE_MULZAAAAQ32X16_S2, + 0, + Opcode_ae_mulzaaaaq32x16_s2_encode_fns, 1, Opcode_ae_mulzaaaaq32x16_s2_funcUnit_uses }, + { "ae_mulaaaaq32x16_s2", ICLASS_AE_MULAAAAQ32X16_S2, + 0, + Opcode_ae_mulaaaaq32x16_s2_encode_fns, 1, Opcode_ae_mulaaaaq32x16_s2_funcUnit_uses }, + { "ae_mul16.00", ICLASS_AE_MUL16_00, + 0, + Opcode_ae_mul16_00_encode_fns, 1, Opcode_ae_mul16_00_funcUnit_uses }, + { "ae_mula16.00", ICLASS_AE_MULA16_00, + 0, + Opcode_ae_mula16_00_encode_fns, 1, Opcode_ae_mula16_00_funcUnit_uses }, + { "ae_mul16.00_s2", ICLASS_AE_MUL16_00_S2, + 0, + Opcode_ae_mul16_00_s2_encode_fns, 1, Opcode_ae_mul16_00_s2_funcUnit_uses }, + { "ae_mula16.00_s2", ICLASS_AE_MULA16_00_S2, + 0, + Opcode_ae_mula16_00_s2_encode_fns, 1, Opcode_ae_mula16_00_s2_funcUnit_uses }, + { "ae_mulzaaaaq16", ICLASS_AE_MULZAAAAQ16, + 0, + Opcode_ae_mulzaaaaq16_encode_fns, 1, Opcode_ae_mulzaaaaq16_funcUnit_uses }, + { "ae_mulaaaaq16", ICLASS_AE_MULAAAAQ16, + 0, + Opcode_ae_mulaaaaq16_encode_fns, 1, Opcode_ae_mulaaaaq16_funcUnit_uses }, + { "ae_mulzaaaaq16_s2", ICLASS_AE_MULZAAAAQ16_S2, + 0, + Opcode_ae_mulzaaaaq16_s2_encode_fns, 1, Opcode_ae_mulzaaaaq16_s2_funcUnit_uses }, + { "ae_mulaaaaq16_s2", ICLASS_AE_MULAAAAQ16_S2, + 0, + Opcode_ae_mulaaaaq16_s2_encode_fns, 1, Opcode_ae_mulaaaaq16_s2_funcUnit_uses }, + { "ae_div64d32.h", ICLASS_AE_DIV64D32_H, + 0, + Opcode_ae_div64d32_h_encode_fns, 0, 0 }, + { "ae_div64d32.l", ICLASS_AE_DIV64D32_L, + 0, + Opcode_ae_div64d32_l_encode_fns, 0, 0 }, + { "ae_sha32", ICLASS_AE_SHA32, + 0, + Opcode_ae_sha32_encode_fns, 0, 0 }, + { "ae_vldl32t", ICLASS_AE_VLDL32T, + 0, + Opcode_ae_vldl32t_encode_fns, 2, Opcode_ae_vldl32t_funcUnit_uses }, + { "ae_vldl16t", ICLASS_AE_VLDL16T, + 0, + Opcode_ae_vldl16t_encode_fns, 2, Opcode_ae_vldl16t_funcUnit_uses }, + { "ae_vldl16c", ICLASS_AE_VLDL16C, + 0, + Opcode_ae_vldl16c_encode_fns, 4, Opcode_ae_vldl16c_funcUnit_uses }, + { "ae_vldl16c.ip", ICLASS_AE_VLDL16C_IP, + 0, + Opcode_ae_vldl16c_ip_encode_fns, 4, Opcode_ae_vldl16c_ip_funcUnit_uses }, + { "ae_vldl16c.ic", ICLASS_AE_VLDL16C_IC, + 0, + Opcode_ae_vldl16c_ic_encode_fns, 4, Opcode_ae_vldl16c_ic_funcUnit_uses }, + { "ae_vldl16c.ic1", ICLASS_AE_VLDL16C_IC1, + 0, + Opcode_ae_vldl16c_ic1_encode_fns, 4, Opcode_ae_vldl16c_ic1_funcUnit_uses }, + { "ae_vldsht", ICLASS_AE_VLDSHT, + 0, + Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, + { "ae_lb", ICLASS_AE_LB, + 0, + Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, + { "ae_lbi", ICLASS_AE_LBI, + 0, + Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, + { "ae_lbk", ICLASS_AE_LBK, + 0, + Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, + { "ae_lbki", ICLASS_AE_LBKI, + 0, + Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, + { "ae_lbs", ICLASS_AE_LBS, + 0, + Opcode_ae_lbs_encode_fns, 1, Opcode_ae_lbs_funcUnit_uses }, + { "ae_lbsi", ICLASS_AE_LBSI, + 0, + Opcode_ae_lbsi_encode_fns, 1, Opcode_ae_lbsi_funcUnit_uses }, + { "ae_db", ICLASS_AE_DB, + 0, + Opcode_ae_db_encode_fns, 3, Opcode_ae_db_funcUnit_uses }, + { "ae_dbi", ICLASS_AE_DBI, + 0, + Opcode_ae_dbi_encode_fns, 3, Opcode_ae_dbi_funcUnit_uses }, + { "ae_db.ic", ICLASS_AE_DB_IC, + 0, + Opcode_ae_db_ic_encode_fns, 3, Opcode_ae_db_ic_funcUnit_uses }, + { "ae_dbi.ic", ICLASS_AE_DBI_IC, + 0, + Opcode_ae_dbi_ic_encode_fns, 3, Opcode_ae_dbi_ic_funcUnit_uses }, + { "ae_db.ic1", ICLASS_AE_DB_IC1, + 0, + Opcode_ae_db_ic1_encode_fns, 3, Opcode_ae_db_ic1_funcUnit_uses }, + { "ae_dbi.ic1", ICLASS_AE_DBI_IC1, + 0, + Opcode_ae_dbi_ic1_encode_fns, 3, Opcode_ae_dbi_ic1_funcUnit_uses }, + { "ae_db.ip", ICLASS_AE_DB_IP, + 0, + Opcode_ae_db_ip_encode_fns, 3, Opcode_ae_db_ip_funcUnit_uses }, + { "ae_dbi.ip", ICLASS_AE_DBI_IP, + 0, + Opcode_ae_dbi_ip_encode_fns, 3, Opcode_ae_dbi_ip_funcUnit_uses }, + { "ae_vlel32t", ICLASS_AE_VLEL32T, + 0, + Opcode_ae_vlel32t_encode_fns, 2, Opcode_ae_vlel32t_funcUnit_uses }, + { "ae_vlel16t", ICLASS_AE_VLEL16T, + 0, + Opcode_ae_vlel16t_encode_fns, 2, Opcode_ae_vlel16t_funcUnit_uses }, + { "ae_sb", ICLASS_AE_SB, + 0, + Opcode_ae_sb_encode_fns, 3, Opcode_ae_sb_funcUnit_uses }, + { "ae_sbi", ICLASS_AE_SBI, + 0, + Opcode_ae_sbi_encode_fns, 3, Opcode_ae_sbi_funcUnit_uses }, + { "ae_vles16c", ICLASS_AE_VLES16C, + 0, + Opcode_ae_vles16c_encode_fns, 3, Opcode_ae_vles16c_funcUnit_uses }, + { "ae_sbf", ICLASS_AE_SBF, + 0, + Opcode_ae_sbf_encode_fns, 3, Opcode_ae_sbf_funcUnit_uses }, + { "ae_sb.ic", ICLASS_AE_SB_IC, + 0, + Opcode_ae_sb_ic_encode_fns, 3, Opcode_ae_sb_ic_funcUnit_uses }, + { "ae_sbi.ic", ICLASS_AE_SBI_IC, + 0, + Opcode_ae_sbi_ic_encode_fns, 3, Opcode_ae_sbi_ic_funcUnit_uses }, + { "ae_vles16c.ic", ICLASS_AE_VLES16C_IC, + 0, + Opcode_ae_vles16c_ic_encode_fns, 3, Opcode_ae_vles16c_ic_funcUnit_uses }, + { "ae_sbf.ic", ICLASS_AE_SBF_IC, + 0, + Opcode_ae_sbf_ic_encode_fns, 3, Opcode_ae_sbf_ic_funcUnit_uses }, + { "ae_sb.ic1", ICLASS_AE_SB_IC1, + 0, + Opcode_ae_sb_ic1_encode_fns, 3, Opcode_ae_sb_ic1_funcUnit_uses }, + { "ae_sbi.ic1", ICLASS_AE_SBI_IC1, + 0, + Opcode_ae_sbi_ic1_encode_fns, 3, Opcode_ae_sbi_ic1_funcUnit_uses }, + { "ae_vles16c.ic1", ICLASS_AE_VLES16C_IC1, + 0, + Opcode_ae_vles16c_ic1_encode_fns, 3, Opcode_ae_vles16c_ic1_funcUnit_uses }, + { "ae_sbf.ic1", ICLASS_AE_SBF_IC1, + 0, + Opcode_ae_sbf_ic1_encode_fns, 3, Opcode_ae_sbf_ic1_funcUnit_uses }, + { "ae_sb.ip", ICLASS_AE_SB_IP, + 0, + Opcode_ae_sb_ip_encode_fns, 3, Opcode_ae_sb_ip_funcUnit_uses }, + { "ae_sbi.ip", ICLASS_AE_SBI_IP, + 0, + Opcode_ae_sbi_ip_encode_fns, 3, Opcode_ae_sbi_ip_funcUnit_uses }, + { "ae_vles16c.ip", ICLASS_AE_VLES16C_IP, + 0, + Opcode_ae_vles16c_ip_encode_fns, 3, Opcode_ae_vles16c_ip_funcUnit_uses }, + { "ae_sbf.ip", ICLASS_AE_SBF_IP, + 0, + Opcode_ae_sbf_ip_encode_fns, 3, Opcode_ae_sbf_ip_funcUnit_uses }, + { "ae_sext32", ICLASS_AE_SEXT32, + 0, + Opcode_ae_sext32_encode_fns, 0, 0 }, + { "ae_movae", ICLASS_AE_MOVAE, + 0, + Opcode_ae_movae_encode_fns, 0, 0 }, + { "ae_movea", ICLASS_AE_MOVEA, + 0, + Opcode_ae_movea_encode_fns, 0, 0 }, + { "ae_moveep", ICLASS_AE_MOVEEP, + 0, + Opcode_ae_moveep_encode_fns, 0, 0 }, + { "ae_sext72", ICLASS_AE_SEXT72, + 0, + Opcode_ae_sext72_encode_fns, 0, 0 }, + { "ae_add72", ICLASS_AE_ADD72, + 0, + Opcode_ae_add72_encode_fns, 0, 0 }, + { "ae_sub72", ICLASS_AE_SUB72, + 0, + Opcode_ae_sub72_encode_fns, 0, 0 }, + { "ae_add72x64", ICLASS_AE_ADD72X64, + 0, + Opcode_ae_add72x64_encode_fns, 0, 0 }, + { "ae_sub72x64", ICLASS_AE_SUB72X64, + 0, + Opcode_ae_sub72x64_encode_fns, 0, 0 }, + { "ae_mul32ep.hh", ICLASS_AE_MUL32EP_HH, + 0, + Opcode_ae_mul32ep_hh_encode_fns, 1, Opcode_ae_mul32ep_hh_funcUnit_uses }, + { "ae_mul32ep.hh_s2", ICLASS_AE_MUL32EP_HH_S2, + 0, + Opcode_ae_mul32ep_hh_s2_encode_fns, 1, Opcode_ae_mul32ep_hh_s2_funcUnit_uses }, + { "ae_mula32ep.hh", ICLASS_AE_MULA32EP_HH, + 0, + Opcode_ae_mula32ep_hh_encode_fns, 1, Opcode_ae_mula32ep_hh_funcUnit_uses }, + { "ae_muls32ep.hh", ICLASS_AE_MULS32EP_HH, + 0, + Opcode_ae_muls32ep_hh_encode_fns, 1, Opcode_ae_muls32ep_hh_funcUnit_uses }, + { "ae_mula32ep.hh_s2", ICLASS_AE_MULA32EP_HH_S2, + 0, + Opcode_ae_mula32ep_hh_s2_encode_fns, 1, Opcode_ae_mula32ep_hh_s2_funcUnit_uses }, + { "ae_muls32ep.hh_s2", ICLASS_AE_MULS32EP_HH_S2, + 0, + Opcode_ae_muls32ep_hh_s2_encode_fns, 1, Opcode_ae_muls32ep_hh_s2_funcUnit_uses }, + { "ae_mulzaad32ep.hh.ll", ICLASS_AE_MULZAAD32EP_HH_LL, + 0, + Opcode_ae_mulzaad32ep_hh_ll_encode_fns, 1, Opcode_ae_mulzaad32ep_hh_ll_funcUnit_uses }, + { "ae_mulzssd32ep.hh.ll", ICLASS_AE_MULZSSD32EP_HH_LL, + 0, + Opcode_ae_mulzssd32ep_hh_ll_encode_fns, 1, Opcode_ae_mulzssd32ep_hh_ll_funcUnit_uses }, + { "ae_mulaad32ep.hh.ll", ICLASS_AE_MULAAD32EP_HH_LL, + 0, + Opcode_ae_mulaad32ep_hh_ll_encode_fns, 1, Opcode_ae_mulaad32ep_hh_ll_funcUnit_uses }, + { "ae_mulssd32ep.hh.ll", ICLASS_AE_MULSSD32EP_HH_LL, + 0, + Opcode_ae_mulssd32ep_hh_ll_encode_fns, 1, Opcode_ae_mulssd32ep_hh_ll_funcUnit_uses }, + { "ae_mulzaad32ep.hh.ll_s2", ICLASS_AE_MULZAAD32EP_HH_LL_S2, + 0, + Opcode_ae_mulzaad32ep_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzaad32ep_hh_ll_s2_funcUnit_uses }, + { "ae_mulzssd32ep.hh.ll_s2", ICLASS_AE_MULZSSD32EP_HH_LL_S2, + 0, + Opcode_ae_mulzssd32ep_hh_ll_s2_encode_fns, 1, Opcode_ae_mulzssd32ep_hh_ll_s2_funcUnit_uses }, + { "ae_mulaad32ep.hh.ll_s2", ICLASS_AE_MULAAD32EP_HH_LL_S2, + 0, + Opcode_ae_mulaad32ep_hh_ll_s2_encode_fns, 1, Opcode_ae_mulaad32ep_hh_ll_s2_funcUnit_uses }, + { "ae_mulssd32ep.hh.ll_s2", ICLASS_AE_MULSSD32EP_HH_LL_S2, + 0, + Opcode_ae_mulssd32ep_hh_ll_s2_encode_fns, 1, Opcode_ae_mulssd32ep_hh_ll_s2_funcUnit_uses }, + { "ae_mulaad32usep.hl.lh", ICLASS_AE_MULAAD32USEP_HL_LH, + 0, + Opcode_ae_mulaad32usep_hl_lh_encode_fns, 1, Opcode_ae_mulaad32usep_hl_lh_funcUnit_uses }, + { "ae_mulaad32usep.hl.lh_s2", ICLASS_AE_MULAAD32USEP_HL_LH_S2, + 0, + Opcode_ae_mulaad32usep_hl_lh_s2_encode_fns, 1, Opcode_ae_mulaad32usep_hl_lh_s2_funcUnit_uses }, + { "ae_mulzaad32usep.hl.lh", ICLASS_AE_MULZAAD32USEP_HL_LH, + 0, + Opcode_ae_mulzaad32usep_hl_lh_encode_fns, 1, Opcode_ae_mulzaad32usep_hl_lh_funcUnit_uses }, + { "ae_mulzaad32usep.hl.lh_s2", ICLASS_AE_MULZAAD32USEP_HL_LH_S2, + 0, + Opcode_ae_mulzaad32usep_hl_lh_s2_encode_fns, 1, Opcode_ae_mulzaad32usep_hl_lh_s2_funcUnit_uses }, + { "ae_mul32usep.lh", ICLASS_AE_MUL32USEP_LH, + 0, + Opcode_ae_mul32usep_lh_encode_fns, 1, Opcode_ae_mul32usep_lh_funcUnit_uses }, + { "ae_mula32usep.lh", ICLASS_AE_MULA32USEP_LH, + 0, + Opcode_ae_mula32usep_lh_encode_fns, 1, Opcode_ae_mula32usep_lh_funcUnit_uses }, + { "ae_mul32usep.ll", ICLASS_AE_MUL32USEP_LL, + 0, + Opcode_ae_mul32usep_ll_encode_fns, 1, Opcode_ae_mul32usep_ll_funcUnit_uses }, + { "ae_mula32usep.ll", ICLASS_AE_MULA32USEP_LL, + 0, + Opcode_ae_mula32usep_ll_encode_fns, 1, Opcode_ae_mula32usep_ll_funcUnit_uses }, + { "ae_srai72", ICLASS_AE_SRAI72, + 0, + Opcode_ae_srai72_encode_fns, 0, 0 }, + { "ae_slai72", ICLASS_AE_SLAI72, + 0, + Opcode_ae_slai72_encode_fns, 0, 0 }, + { "ae_sat64s", ICLASS_AE_SAT64S, + 0, + Opcode_ae_sat64s_encode_fns, 0, 0 }, + { "ae_l16si.n", ICLASS_AE_L16SI_N, + 0, + Opcode_ae_l16si_n_encode_fns, 2, Opcode_ae_l16si_n_funcUnit_uses }, + { "ae_l16ui.n", ICLASS_AE_L16UI_N, + 0, + Opcode_ae_l16ui_n_encode_fns, 2, Opcode_ae_l16ui_n_funcUnit_uses }, + { "ae_s16i.n", ICLASS_AE_S16I_N, + 0, + Opcode_ae_s16i_n_encode_fns, 2, Opcode_ae_s16i_n_funcUnit_uses }, + { "ae_movfcrfsrv", ICLASS_AE_MOVFCRFSRV, + 0, + Opcode_ae_movfcrfsrv_encode_fns, 0, 0 }, + { "ae_movvfcrfsr", ICLASS_AE_MOVVFCRFSR, + 0, + Opcode_ae_movvfcrfsr_encode_fns, 0, 0 }, + { "rfr", ICLASS_RFR, + 0, + Opcode_rfr_encode_fns, 0, 0 }, + { "wfr", ICLASS_WFR, + 0, + Opcode_wfr_encode_fns, 0, 0 }, + { "movt.s", ICLASS_MOVT_S, + 0, + Opcode_movt_s_encode_fns, 0, 0 }, + { "movf.s", ICLASS_MOVF_S, + 0, + Opcode_movf_s_encode_fns, 0, 0 }, + { "moveqz.s", ICLASS_MOVEQZ_S, + 0, + Opcode_moveqz_s_encode_fns, 0, 0 }, + { "movnez.s", ICLASS_MOVNEZ_S, + 0, + Opcode_movnez_s_encode_fns, 0, 0 }, + { "movgez.s", ICLASS_MOVGEZ_S, + 0, + Opcode_movgez_s_encode_fns, 0, 0 }, + { "movltz.s", ICLASS_MOVLTZ_S, + 0, + Opcode_movltz_s_encode_fns, 0, 0 }, + { "trunc.s", ICLASS_TRUNC_S, + 0, + Opcode_trunc_s_encode_fns, 0, 0 }, + { "utrunc.s", ICLASS_UTRUNC_S, + 0, + Opcode_utrunc_s_encode_fns, 0, 0 }, + { "trunc.sx2", ICLASS_TRUNC_SX2, + 0, + Opcode_trunc_sx2_encode_fns, 0, 0 }, + { "utrunc.sx2", ICLASS_UTRUNC_SX2, + 0, + Opcode_utrunc_sx2_encode_fns, 0, 0 }, + { "ficeil.s", ICLASS_FICEIL_S, + 0, + Opcode_ficeil_s_encode_fns, 0, 0 }, + { "fifloor.s", ICLASS_FIFLOOR_S, + 0, + Opcode_fifloor_s_encode_fns, 0, 0 }, + { "firound.s", ICLASS_FIROUND_S, + 0, + Opcode_firound_s_encode_fns, 0, 0 }, + { "fitrunc.s", ICLASS_FITRUNC_S, + 0, + Opcode_fitrunc_s_encode_fns, 0, 0 }, + { "firint.s", ICLASS_FIRINT_S, + 0, + Opcode_firint_s_encode_fns, 0, 0 }, + { "cvtsf16.l", ICLASS_CVTSF16_L, + 0, + Opcode_cvtsf16_l_encode_fns, 0, 0 }, + { "cvtsf16.h", ICLASS_CVTSF16_H, + 0, + Opcode_cvtsf16_h_encode_fns, 0, 0 }, + { "cvtf16s.l", ICLASS_CVTF16S_L, + 0, + Opcode_cvtf16s_l_encode_fns, 0, 0 }, + { "cvtf16s.h", ICLASS_CVTF16S_H, + 0, + Opcode_cvtf16s_h_encode_fns, 0, 0 }, + { "abs.s", ICLASS_ABS_S, + 0, + Opcode_abs_s_encode_fns, 0, 0 }, + { "mul.s", ICLASS_MUL_S, + 0, + Opcode_mul_s_encode_fns, 0, 0 }, + { "madd.s", ICLASS_MADD_S, + 0, + Opcode_madd_s_encode_fns, 0, 0 }, + { "msub.s", ICLASS_MSUB_S, + 0, + Opcode_msub_s_encode_fns, 0, 0 }, + { "msubn.s", ICLASS_MSUBN_S, + 0, + Opcode_msubn_s_encode_fns, 0, 0 }, + { "maddn.s", ICLASS_MADDN_S, + 0, + Opcode_maddn_s_encode_fns, 0, 0 }, + { "add.s", ICLASS_ADD_S, + 0, + Opcode_add_s_encode_fns, 0, 0 }, + { "sub.s", ICLASS_SUB_S, + 0, + Opcode_sub_s_encode_fns, 0, 0 }, + { "neg.s", ICLASS_NEG_S, + 0, + Opcode_neg_s_encode_fns, 0, 0 }, + { "float.s", ICLASS_FLOAT_S, + 0, + Opcode_float_s_encode_fns, 0, 0 }, + { "ufloat.s", ICLASS_UFLOAT_S, + 0, + Opcode_ufloat_s_encode_fns, 0, 0 }, + { "float.sx2", ICLASS_FLOAT_SX2, + 0, + Opcode_float_sx2_encode_fns, 0, 0 }, + { "ufloat.sx2", ICLASS_UFLOAT_SX2, + 0, + Opcode_ufloat_sx2_encode_fns, 0, 0 }, + { "ole.s", ICLASS_OLE_S, + 0, + Opcode_ole_s_encode_fns, 0, 0 }, + { "olt.s", ICLASS_OLT_S, + 0, + Opcode_olt_s_encode_fns, 0, 0 }, + { "oeq.s", ICLASS_OEQ_S, + 0, + Opcode_oeq_s_encode_fns, 0, 0 }, + { "un.s", ICLASS_UN_S, + 0, + Opcode_un_s_encode_fns, 0, 0 }, + { "ule.s", ICLASS_ULE_S, + 0, + Opcode_ule_s_encode_fns, 0, 0 }, + { "ult.s", ICLASS_ULT_S, + 0, + Opcode_ult_s_encode_fns, 0, 0 }, + { "ueq.s", ICLASS_UEQ_S, + 0, + Opcode_ueq_s_encode_fns, 0, 0 }, + { "const.s", ICLASS_CONST_S, + 0, + Opcode_const_s_encode_fns, 0, 0 }, + { "nexp01.s", ICLASS_NEXP01_S, + 0, + Opcode_nexp01_s_encode_fns, 0, 0 }, + { "mksadj.s", ICLASS_MKSADJ_S, + 0, + Opcode_mksadj_s_encode_fns, 0, 0 }, + { "mkdadj.s", ICLASS_MKDADJ_S, + 0, + Opcode_mkdadj_s_encode_fns, 0, 0 }, + { "div0.s", ICLASS_DIV0_S, + 0, + Opcode_div0_s_encode_fns, 0, 0 }, + { "sqrt0.s", ICLASS_SQRT0_S, + 0, + Opcode_sqrt0_s_encode_fns, 0, 0 }, + { "recip0.s", ICLASS_RECIP0_S, + 0, + Opcode_recip0_s_encode_fns, 0, 0 }, + { "rsqrt0.s", ICLASS_RSQRT0_S, + 0, + Opcode_rsqrt0_s_encode_fns, 0, 0 }, + { "divn.s", ICLASS_DIVN_S, + 0, + Opcode_divn_s_encode_fns, 0, 0 }, + { "addexp.s", ICLASS_ADDEXP_S, + 0, + Opcode_addexp_s_encode_fns, 0, 0 }, + { "addexpm.s", ICLASS_ADDEXPM_S, + 0, + Opcode_addexpm_s_encode_fns, 0, 0 }, + { "min.s", ICLASS_MIN_S, + 0, + Opcode_min_s_encode_fns, 0, 0 }, + { "max.s", ICLASS_MAX_S, + 0, + Opcode_max_s_encode_fns, 0, 0 }, + { "mulmux.s", ICLASS_MULMUX_S, + 0, + Opcode_mulmux_s_encode_fns, 0, 0 }, + { "maddmux.s", ICLASS_MADDMUX_S, + 0, + Opcode_maddmux_s_encode_fns, 0, 0 }, + { "conjc.s", ICLASS_CONJC_S, + 0, + Opcode_conjc_s_encode_fns, 0, 0 }, + { "sigmoid_q15", ICLASS_SIGMOID_Q15, + 0, + Opcode_sigmoid_q15_encode_fns, 0, 0 }, + { "sigmoid_fp32", ICLASS_SIGMOID_FP32, + 0, + Opcode_sigmoid_fp32_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUB, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BNEI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BALL, + OPCODE_BANY, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQ, + OPCODE_BGE, + OPCODE_BGEU, + OPCODE_BLT, + OPCODE_BLTU, + OPCODE_BNALL, + OPCODE_BNE, + OPCODE_BNONE, + OPCODE_BEQZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_BNEZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPGTZ, + OPCODE_LOOPNEZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVGEZ, + OPCODE_MOVLTZ, + OPCODE_MOVNEZ, + OPCODE_ABS, + OPCODE_NEG, + OPCODE_NOP, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSA8B, + OPCODE_SSA8L, + OPCODE_SSL, + OPCODE_SSR, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRA, + OPCODE_SRL, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_DSYNC, + OPCODE_ESYNC, + OPCODE_RSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_MUL16S, + OPCODE_MUL16U, + OPCODE_MULL, + OPCODE_MULSH, + OPCODE_MULUH, + OPCODE_MUL_AA_HH, + OPCODE_MUL_AA_HL, + OPCODE_MUL_AA_LH, + OPCODE_MUL_AA_LL, + OPCODE_UMUL_AA_HH, + OPCODE_UMUL_AA_HL, + OPCODE_UMUL_AA_LH, + OPCODE_UMUL_AA_LL, + OPCODE_MUL_AD_HH, + OPCODE_MUL_AD_HL, + OPCODE_MUL_AD_LH, + OPCODE_MUL_AD_LL, + OPCODE_MUL_DA_HH, + OPCODE_MUL_DA_HL, + OPCODE_MUL_DA_LH, + OPCODE_MUL_DA_LL, + OPCODE_MUL_DD_HH, + OPCODE_MUL_DD_HL, + OPCODE_MUL_DD_LH, + OPCODE_MUL_DD_LL, + OPCODE_MULA_AA_HH, + OPCODE_MULA_AA_HL, + OPCODE_MULA_AA_LH, + OPCODE_MULA_AA_LL, + OPCODE_MULS_AA_HH, + OPCODE_MULS_AA_HL, + OPCODE_MULS_AA_LH, + OPCODE_MULS_AA_LL, + OPCODE_MULA_AD_HH, + OPCODE_MULA_AD_HL, + OPCODE_MULA_AD_LH, + OPCODE_MULA_AD_LL, + OPCODE_MULS_AD_HH, + OPCODE_MULS_AD_HL, + OPCODE_MULS_AD_LH, + OPCODE_MULS_AD_LL, + OPCODE_MULA_DA_HH, + OPCODE_MULA_DA_HL, + OPCODE_MULA_DA_LH, + OPCODE_MULA_DA_LL, + OPCODE_MULS_DA_HH, + OPCODE_MULS_DA_HL, + OPCODE_MULS_DA_LH, + OPCODE_MULS_DA_LL, + OPCODE_MULA_DD_HH, + OPCODE_MULA_DD_HL, + OPCODE_MULA_DD_LH, + OPCODE_MULA_DD_LL, + OPCODE_MULS_DD_HH, + OPCODE_MULS_DD_HL, + OPCODE_MULS_DD_LH, + OPCODE_MULS_DD_LL, + OPCODE_MULA_DA_HH_LDDEC, + OPCODE_MULA_DA_HH_LDINC, + OPCODE_MULA_DA_HL_LDDEC, + OPCODE_MULA_DA_HL_LDINC, + OPCODE_MULA_DA_LH_LDDEC, + OPCODE_MULA_DA_LH_LDINC, + OPCODE_MULA_DA_LL_LDDEC, + OPCODE_MULA_DA_LL_LDINC, + OPCODE_MULA_DD_HH_LDDEC, + OPCODE_MULA_DD_HH_LDINC, + OPCODE_MULA_DD_HL_LDDEC, + OPCODE_MULA_DD_HL_LDINC, + OPCODE_MULA_DD_LH_LDDEC, + OPCODE_MULA_DD_LH_LDINC, + OPCODE_MULA_DD_LL_LDDEC, + OPCODE_MULA_DD_LL_LDINC, + OPCODE_LDDEC, + OPCODE_LDINC, + OPCODE_RSR_M0, + OPCODE_WSR_M0, + OPCODE_XSR_M0, + OPCODE_RSR_M1, + OPCODE_WSR_M1, + OPCODE_XSR_M1, + OPCODE_RSR_M2, + OPCODE_WSR_M2, + OPCODE_XSR_M2, + OPCODE_RSR_M3, + OPCODE_WSR_M3, + OPCODE_XSR_M3, + OPCODE_RSR_ACCLO, + OPCODE_WSR_ACCLO, + OPCODE_XSR_ACCLO, + OPCODE_RSR_ACCHI, + OPCODE_WSR_ACCHI, + OPCODE_XSR_ACCHI, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ALL4, + OPCODE_ANY4, + OPCODE_ALL8, + OPCODE_ANY8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_IHI, + OPCODE_IPF, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_IPFL, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWBUI_P, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFRO, + OPCODE_DPFW, + OPCODE_DPFWO, + OPCODE_DPFM_B, + OPCODE_DPFM_BF, + OPCODE_DPFR_B, + OPCODE_DPFR_BF, + OPCODE_DPFW_B, + OPCODE_DPFW_BF, + OPCODE_PFNXT_F, + OPCODE_DHI_B, + OPCODE_DHWBI_B, + OPCODE_DHWB_B, + OPCODE_PFEND_A, + OPCODE_PFEND_O, + OPCODE_PFWAIT_A, + OPCODE_PFWAIT_R, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_DPFL, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_RSR_PREFCTL, + OPCODE_WSR_PREFCTL, + OPCODE_XSR_PREFCTL, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MAX, + OPCODE_MAXU, + OPCODE_MIN, + OPCODE_MINU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOS, + OPCODE_QUOU, + OPCODE_REMS, + OPCODE_REMU, + OPCODE_RER, + OPCODE_WER, + OPCODE_BEQZ_W15, + OPCODE_BGEZ_W15, + OPCODE_BLTZ_W15, + OPCODE_BNEZ_W15, + OPCODE_BEQI_W15, + OPCODE_BGEI_W15, + OPCODE_BLTI_W15, + OPCODE_BNEI_W15, + OPCODE_BGEUI_W15, + OPCODE_BLTUI_W15, + OPCODE_BBCI_W15, + OPCODE_BBSI_W15, + OPCODE_BALL_W15, + OPCODE_BANY_W15, + OPCODE_BBC_W15, + OPCODE_BBS_W15, + OPCODE_BEQ_W15, + OPCODE_BGEU_W15, + OPCODE_BGE_W15, + OPCODE_BLTU_W15, + OPCODE_BLT_W15, + OPCODE_BNALL_W15, + OPCODE_BNE_W15, + OPCODE_BNONE_W15, + OPCODE_RUR_AE_OVF_SAR, + OPCODE_WUR_AE_OVF_SAR, + OPCODE_RUR_AE_BITHEAD, + OPCODE_WUR_AE_BITHEAD, + OPCODE_RUR_AE_TS_FTS_BU_BP, + OPCODE_WUR_AE_TS_FTS_BU_BP, + OPCODE_RUR_AE_CW_SD_NO, + OPCODE_WUR_AE_CW_SD_NO, + OPCODE_RUR_AE_CBEGIN0, + OPCODE_WUR_AE_CBEGIN0, + OPCODE_RUR_AE_CEND0, + OPCODE_WUR_AE_CEND0, + OPCODE_RUR_AE_CBEGIN1, + OPCODE_WUR_AE_CBEGIN1, + OPCODE_RUR_AE_CEND1, + OPCODE_WUR_AE_CEND1, + OPCODE_AE_SEXT16, + OPCODE_AE_ZEXT16, + OPCODE_AE_CLAMPS16, + OPCODE_RUR_FCR, + OPCODE_WUR_FCR, + OPCODE_RUR_FSR, + OPCODE_WUR_FSR, + OPCODE_F64ITER, + OPCODE_F64RND, + OPCODE_F64ADDC, + OPCODE_F64SUBC, + OPCODE_F64SIG, + OPCODE_F64CMPL, + OPCODE_F64CMPH, + OPCODE_F64NORM, + OPCODE_F64SEXP, + OPCODE_RF64R, + OPCODE_WF64R, + OPCODE_RUR_F64R_LO, + OPCODE_WUR_F64R_LO, + OPCODE_RUR_F64R_HI, + OPCODE_WUR_F64R_HI, + OPCODE_RUR_F64S, + OPCODE_WUR_F64S, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE, + OPCODE_RUR_AE_OVERFLOW, + OPCODE_WUR_AE_OVERFLOW, + OPCODE_RUR_AE_SAR, + OPCODE_WUR_AE_SAR, + OPCODE_RUR_AE_BITPTR, + OPCODE_WUR_AE_BITPTR, + OPCODE_RUR_AE_BITSUSED, + OPCODE_WUR_AE_BITSUSED, + OPCODE_RUR_AE_TABLESIZE, + OPCODE_WUR_AE_TABLESIZE, + OPCODE_RUR_AE_FIRST_TS, + OPCODE_WUR_AE_FIRST_TS, + OPCODE_RUR_AE_NEXTOFFSET, + OPCODE_WUR_AE_NEXTOFFSET, + OPCODE_RUR_AE_SEARCHDONE, + OPCODE_WUR_AE_SEARCHDONE, + OPCODE_RUR_AE_CWRAP, + OPCODE_WUR_AE_CWRAP, + OPCODE_AE_L8X4F_I, + OPCODE_AE_L8X4F_IP, + OPCODE_AE_L16M_XC, + OPCODE_AE_L16M_XC1, + OPCODE_AE_L16M_I, + OPCODE_AE_L16M_IU, + OPCODE_AE_L16M_X, + OPCODE_AE_L16M_XU, + OPCODE_AE_L16_XC, + OPCODE_AE_L16_XC1, + OPCODE_AE_L16_I, + OPCODE_AE_L16_IP, + OPCODE_AE_L16_X, + OPCODE_AE_L16_XP, + OPCODE_AE_L32F24_XC, + OPCODE_AE_L32F24_XC1, + OPCODE_AE_L32F24_I, + OPCODE_AE_L32F24_IP, + OPCODE_AE_L32F24_X, + OPCODE_AE_L32F24_XP, + OPCODE_AE_L32_XC, + OPCODE_AE_L32_XC1, + OPCODE_AE_L32_I, + OPCODE_AE_L32_IP, + OPCODE_AE_L32_X, + OPCODE_AE_L32_XP, + OPCODE_AE_L32M_XC, + OPCODE_AE_L32M_I, + OPCODE_AE_L32M_IU, + OPCODE_AE_L32M_X, + OPCODE_AE_L32M_XU, + OPCODE_AE_L16X2M_XC, + OPCODE_AE_L16X2M_XC1, + OPCODE_AE_L16X2M_I, + OPCODE_AE_L16X2M_IU, + OPCODE_AE_L16X2M_X, + OPCODE_AE_L16X2M_XU, + OPCODE_AE_L32X2F24_XC, + OPCODE_AE_L32X2F24_XC1, + OPCODE_AE_L32X2F24_I, + OPCODE_AE_L32X2F24_IP, + OPCODE_AE_L32X2F24_RIP, + OPCODE_AE_L32X2F24_RI, + OPCODE_AE_L32X2F24_RIC, + OPCODE_AE_L32X2F24_RIC1, + OPCODE_AE_L32X2F24_X, + OPCODE_AE_L32X2F24_XP, + OPCODE_AE_L32X2_XC, + OPCODE_AE_L32X2_XC1, + OPCODE_AE_L32X2_I, + OPCODE_AE_L32X2_IP, + OPCODE_AE_L32X2_RIC, + OPCODE_AE_L32X2_RIC1, + OPCODE_AE_L32X2_X, + OPCODE_AE_L32X2_XP, + OPCODE_AE_L16X4_XC, + OPCODE_AE_L16X4_XC1, + OPCODE_AE_L16X4_I, + OPCODE_AE_L16X4_IP, + OPCODE_AE_L16X4_X, + OPCODE_AE_L16X4_XP, + OPCODE_AE_L64_XC, + OPCODE_AE_L64_XC1, + OPCODE_AE_L64_I, + OPCODE_AE_L64_IP, + OPCODE_AE_L64_X, + OPCODE_AE_L64_XP, + OPCODE_AE_S16X2M_XC, + OPCODE_AE_S16X2M_XC1, + OPCODE_AE_S16X2M_I, + OPCODE_AE_S16X2M_IU, + OPCODE_AE_S16X2M_X, + OPCODE_AE_S16X2M_XU, + OPCODE_AE_S32X2F24_XC, + OPCODE_AE_S32X2F24_XC1, + OPCODE_AE_S32X2F24_I, + OPCODE_AE_S32X2F24_IP, + OPCODE_AE_S32X2F24_RIP, + OPCODE_AE_S32X2F24_RIC, + OPCODE_AE_S32X2F24_RIC1, + OPCODE_AE_S32X2F24_X, + OPCODE_AE_S32X2F24_XP, + OPCODE_AE_S32X2_XC, + OPCODE_AE_S32X2_XC1, + OPCODE_AE_S32X2_I, + OPCODE_AE_S32X2_IP, + OPCODE_AE_S32X2_RIC, + OPCODE_AE_S32X2_RIC1, + OPCODE_AE_S32X2_X, + OPCODE_AE_S32X2_XP, + OPCODE_AE_S32X2RNG_I, + OPCODE_AE_S32X2RNG_IP, + OPCODE_AE_S32X2RNG_X, + OPCODE_AE_S32X2RNG_XP, + OPCODE_AE_S16X4_XC, + OPCODE_AE_S16X4_XC1, + OPCODE_AE_S16X4_I, + OPCODE_AE_S16X4_IP, + OPCODE_AE_S16X4_X, + OPCODE_AE_S16X4_XP, + OPCODE_AE_S16M_L_XC, + OPCODE_AE_S16M_L_XC1, + OPCODE_AE_S16M_L_I, + OPCODE_AE_S16M_L_IU, + OPCODE_AE_S16M_L_X, + OPCODE_AE_S16M_L_XU, + OPCODE_AE_S32F24_L_XC, + OPCODE_AE_S32F24_L_XC1, + OPCODE_AE_S32F24_L_I, + OPCODE_AE_S32F24_L_IP, + OPCODE_AE_S32F24_L_X, + OPCODE_AE_S32F24_L_XP, + OPCODE_AE_S32_L_XC, + OPCODE_AE_S32_L_XC1, + OPCODE_AE_S32_L_I, + OPCODE_AE_S32_L_IP, + OPCODE_AE_S32_L_X, + OPCODE_AE_S32_L_XP, + OPCODE_AE_S16_0_XC, + OPCODE_AE_S16_0_XC1, + OPCODE_AE_S16_0_I, + OPCODE_AE_S16_0_IP, + OPCODE_AE_S16_0_X, + OPCODE_AE_S16_0_XP, + OPCODE_AE_S64_XC, + OPCODE_AE_S64_XC1, + OPCODE_AE_S64_I, + OPCODE_AE_S64_IP, + OPCODE_AE_S64_X, + OPCODE_AE_S64_XP, + OPCODE_AE_S32M_XC, + OPCODE_AE_S32M_I, + OPCODE_AE_S32M_IU, + OPCODE_AE_S32M_X, + OPCODE_AE_S32M_XU, + OPCODE_AE_ZALIGN64, + OPCODE_AE_LALIGN64_I, + OPCODE_AE_SALIGN64_I, + OPCODE_AE_MOVALIGN, + OPCODE_AE_LA64_PP, + OPCODE_AE_LA24POS_PC, + OPCODE_AE_LA24X2POS_PC, + OPCODE_AE_LA32X2POS_PC, + OPCODE_AE_LA16X4POS_PC, + OPCODE_AE_LA24NEG_PC, + OPCODE_AE_LA24X2NEG_PC, + OPCODE_AE_LA32X2NEG_PC, + OPCODE_AE_LA16X4NEG_PC, + OPCODE_AE_LA24POS_PC1, + OPCODE_AE_LA24X2POS_PC1, + OPCODE_AE_LA32X2POS_PC1, + OPCODE_AE_LA16X4POS_PC1, + OPCODE_AE_LA24NEG_PC1, + OPCODE_AE_LA24X2NEG_PC1, + OPCODE_AE_LA32X2NEG_PC1, + OPCODE_AE_LA16X4NEG_PC1, + OPCODE_AE_SA64POS_FP, + OPCODE_AE_SA64NEG_FP, + OPCODE_AE_LA32X2_IC, + OPCODE_AE_LA32X2_IC1, + OPCODE_AE_LA32X2_IP, + OPCODE_AE_LA32X2_RIP, + OPCODE_AE_LA32X2_RIC, + OPCODE_AE_LA32X2_RIC1, + OPCODE_AE_LA16X4_IC, + OPCODE_AE_LA16X4_IC1, + OPCODE_AE_LA16X4_IP, + OPCODE_AE_LA16X4_RIP, + OPCODE_AE_LA16X4_RIC, + OPCODE_AE_LA16X4_RIC1, + OPCODE_AE_LA32X2F24_IC, + OPCODE_AE_LA32X2F24_IC1, + OPCODE_AE_LA32X2F24_IP, + OPCODE_AE_LA32X2F24_RIP, + OPCODE_AE_LA32X2F24_RIC, + OPCODE_AE_LA32X2F24_RIC1, + OPCODE_AE_LA24_IC, + OPCODE_AE_LA24_IC1, + OPCODE_AE_LA24_IP, + OPCODE_AE_LA24_RIP, + OPCODE_AE_LA24_RIC, + OPCODE_AE_LA24_RIC1, + OPCODE_AE_LA24X2_IC, + OPCODE_AE_LA24X2_IC1, + OPCODE_AE_LA24X2_IP, + OPCODE_AE_LA24X2_RIP, + OPCODE_AE_LA24X2_RIC, + OPCODE_AE_LA24X2_RIC1, + OPCODE_AE_SA32X2_IC, + OPCODE_AE_SA32X2_IC1, + OPCODE_AE_SA32X2_IP, + OPCODE_AE_SA32X2_RIP, + OPCODE_AE_SA32X2_RIC, + OPCODE_AE_SA32X2_RIC1, + OPCODE_AE_SA16X4_IC, + OPCODE_AE_SA16X4_IC1, + OPCODE_AE_SA16X4_IP, + OPCODE_AE_SA16X4_RIP, + OPCODE_AE_SA16X4_RIC, + OPCODE_AE_SA16X4_RIC1, + OPCODE_AE_SA32X2F24_IC, + OPCODE_AE_SA32X2F24_IC1, + OPCODE_AE_SA32X2F24_IP, + OPCODE_AE_SA32X2F24_RIP, + OPCODE_AE_SA32X2F24_RIC, + OPCODE_AE_SA32X2F24_RIC1, + OPCODE_AE_SA24_L_IC, + OPCODE_AE_SA24_L_IC1, + OPCODE_AE_SA24_L_IP, + OPCODE_AE_SA24_L_RIP, + OPCODE_AE_SA24_L_RIC, + OPCODE_AE_SA24_L_RIC1, + OPCODE_AE_SA24X2_IC, + OPCODE_AE_SA24X2_IC1, + OPCODE_AE_SA24X2_IP, + OPCODE_AE_SA24X2_RIP, + OPCODE_AE_SA24X2_RIC, + OPCODE_AE_SA24X2_RIC1, + OPCODE_AE_ADDICIRC, + OPCODE_AE_ADDCIRC_XC1, + OPCODE_AE_ADDCIRC_XC, + OPCODE_AE_S32RA64S_I, + OPCODE_AE_S32RA64S_IP, + OPCODE_AE_S32RA64S_X, + OPCODE_AE_S32RA64S_XP, + OPCODE_AE_S32RA64S_XC, + OPCODE_AE_S32RA64S_XC1, + OPCODE_AE_S24RA64S_I, + OPCODE_AE_S24RA64S_IP, + OPCODE_AE_S24RA64S_X, + OPCODE_AE_S24RA64S_XP, + OPCODE_AE_S24RA64S_XC, + OPCODE_AE_S24RA64S_XC1, + OPCODE_AE_S32X2RA64S_IP, + OPCODE_AE_S24X2RA64S_IP, + OPCODE_AE_ADDBRBA32, + OPCODE_AE_BITSWAP, + OPCODE_AE_MUL32JS, + OPCODE_AE_ADDANDSUB32S, + OPCODE_AE_ADDANDSUBRNG32, + OPCODE_AE_ADDRNG32, + OPCODE_AE_SUBRNG32, + OPCODE_AE_CALCRNG3, + OPCODE_AE_CALCRNG2, + OPCODE_AE_CALCRNG1, + OPCODE_AE_RNG32X2, + OPCODE_AE_SEL16I, + OPCODE_AE_SEL16I_N, + OPCODE_AE_SHORTSWAP, + OPCODE_AE_MOVAB4, + OPCODE_AE_MOVAB2, + OPCODE_AE_MOVAB, + OPCODE_AE_MOVBA, + OPCODE_AE_MOVBA1X2, + OPCODE_AE_MOVBA4, + OPCODE_AE_MOVBA2, + OPCODE_AE_MOVB2, + OPCODE_AE_MOVB4, + OPCODE_AE_MOVT16X4, + OPCODE_AE_MOVF16X4, + OPCODE_AE_MOVT32X2, + OPCODE_AE_MOVF32X2, + OPCODE_AE_MOVSARA7X2, + OPCODE_AE_MOVSARD7, + OPCODE_AE_MOVASAR, + OPCODE_AE_MOVDA32X2, + OPCODE_AE_MOVDA32, + OPCODE_AE_MOVDA16X2, + OPCODE_AE_MOVDA16, + OPCODE_AE_MOVI, + OPCODE_AE_TRUNCP24A32X2, + OPCODE_AE_SAT16X4, + OPCODE_AE_CVT32X2F16_32, + OPCODE_AE_CVT32X2F16_10, + OPCODE_AE_SEXT32X2D16_32, + OPCODE_AE_SEXT32X2D16_10, + OPCODE_AE_CVTA32F24S_L, + OPCODE_AE_CVTA32F24S_H, + OPCODE_AE_CVTP24A16X2_LL, + OPCODE_AE_CVTP24A16X2_LH, + OPCODE_AE_CVTP24A16X2_HL, + OPCODE_AE_CVTP24A16X2_HH, + OPCODE_AE_TRUNCP24Q48X2, + OPCODE_AE_TRUNCA32X2F64S, + OPCODE_AE_TRUNCI32X2F64S, + OPCODE_AE_TRUNCA32F64S_L, + OPCODE_AE_TRUNCI32F64S_L, + OPCODE_AE_TRUNCP16, + OPCODE_AE_ROUND32X2F64SSYM, + OPCODE_AE_ROUND32X2F64SASYM, + OPCODE_AE_ROUND32X2F48SSYM, + OPCODE_AE_ROUND32X2F48SASYM, + OPCODE_AE_ROUND16X4F32SSYM, + OPCODE_AE_ROUND16X4F32SASYM, + OPCODE_AE_ROUND24X2F48SSYM, + OPCODE_AE_ROUND24X2F48SASYM, + OPCODE_AE_ROUNDSP16Q48X2SYM, + OPCODE_AE_ROUNDSP16Q48X2ASYM, + OPCODE_AE_MINABS32S, + OPCODE_AE_MAXABS32S, + OPCODE_AE_ROUNDSP16F24SYM, + OPCODE_AE_ROUNDSP16F24ASYM, + OPCODE_AE_MOV, + OPCODE_AE_MOVT64, + OPCODE_AE_MOVF64, + OPCODE_AE_CVTQ56A32S, + OPCODE_AE_CVT48A32, + OPCODE_AE_CVT64A32, + OPCODE_AE_CVTQ56P32S_L, + OPCODE_AE_CVTQ56P32S_H, + OPCODE_AE_CVT64F32_H, + OPCODE_AE_CVT48F32_L, + OPCODE_AE_CVT48F32_H, + OPCODE_AE_SAT48S, + OPCODE_AE_SATQ56S, + OPCODE_AE_SAT24S, + OPCODE_AE_TRUNCQ32, + OPCODE_AE_MINABS64S, + OPCODE_AE_MAXABS64S, + OPCODE_AE_ROUNDSQ32F48SYM, + OPCODE_AE_ROUNDSQ32F48ASYM, + OPCODE_AE_TRUNCA32Q48, + OPCODE_AE_MOVAD32_L, + OPCODE_AE_MOVAD32_H, + OPCODE_AE_MOVAD16_3, + OPCODE_AE_MOVAD16_2, + OPCODE_AE_MOVAD16_1, + OPCODE_AE_MOVAD16_0, + OPCODE_AE_SRA64_32, + OPCODE_AE_PKSR32, + OPCODE_AE_PKSR24, + OPCODE_AE_PKSRF32, + OPCODE_AE_TRUNCA16P24S_L, + OPCODE_AE_TRUNCA16P24S_H, + OPCODE_AE_ADD32, + OPCODE_AE_SUB32, + OPCODE_AE_ADDSUB32, + OPCODE_AE_SUBADD32, + OPCODE_AE_ADD16, + OPCODE_AE_SUB16, + OPCODE_AE_ADD32_HL_LH, + OPCODE_AE_NEG32, + OPCODE_AE_ABS32, + OPCODE_AE_ADD24S, + OPCODE_AE_SUB24S, + OPCODE_AE_ADD32S, + OPCODE_AE_SUB32S, + OPCODE_AE_ADDSUB32S, + OPCODE_AE_SUBADD32S, + OPCODE_AE_ADD16S, + OPCODE_AE_SUB16S, + OPCODE_AE_ADD32S_HL_LH, + OPCODE_AE_NEG24S, + OPCODE_AE_ABS24S, + OPCODE_AE_NEG32S, + OPCODE_AE_ABS32S, + OPCODE_AE_NEG16S, + OPCODE_AE_ABS16S, + OPCODE_AE_LT16, + OPCODE_AE_LE16, + OPCODE_AE_EQ16, + OPCODE_AE_LT32, + OPCODE_AE_LE32, + OPCODE_AE_EQ32, + OPCODE_AE_MIN32, + OPCODE_AE_MAX32, + OPCODE_AE_ADD64, + OPCODE_AE_SUB64, + OPCODE_AE_NEG64, + OPCODE_AE_ABS64, + OPCODE_AE_ADDSQ56S, + OPCODE_AE_SUBSQ56S, + OPCODE_AE_ADD64S, + OPCODE_AE_SUB64S, + OPCODE_AE_NEGSQ56S, + OPCODE_AE_ABSSQ56S, + OPCODE_AE_NEG64S, + OPCODE_AE_ABS64S, + OPCODE_AE_AND, + OPCODE_AE_NAND, + OPCODE_AE_OR, + OPCODE_AE_XOR, + OPCODE_AE_SLAI24, + OPCODE_AE_SRLI24, + OPCODE_AE_SRAI24, + OPCODE_AE_SLAS24, + OPCODE_AE_SRLS24, + OPCODE_AE_SRAS24, + OPCODE_AE_SRAI16, + OPCODE_AE_SRAI16R, + OPCODE_AE_SLAI32, + OPCODE_AE_SRLI32, + OPCODE_AE_SRAI32, + OPCODE_AE_SRAI32R, + OPCODE_AE_SLAS32, + OPCODE_AE_SRLS32, + OPCODE_AE_SRAS32, + OPCODE_AE_SLAA32, + OPCODE_AE_SRLA32, + OPCODE_AE_SRAA32, + OPCODE_AE_SLAI16S, + OPCODE_AE_SLAA16S, + OPCODE_AE_SRAA16S, + OPCODE_AE_SRAA16RS, + OPCODE_AE_SLAI24S, + OPCODE_AE_SLAS24S, + OPCODE_AE_SLAI32S, + OPCODE_AE_SLAS32S, + OPCODE_AE_SLAA32S, + OPCODE_AE_SRAA32S, + OPCODE_AE_SRAA32RS, + OPCODE_AE_SLASQ56, + OPCODE_AE_SRLSQ56, + OPCODE_AE_SRASQ56, + OPCODE_AE_SLAAQ56, + OPCODE_AE_SRLAQ56, + OPCODE_AE_SRAAQ56, + OPCODE_AE_SLAI64, + OPCODE_AE_SRLI64, + OPCODE_AE_SRAI64, + OPCODE_AE_SLAS64, + OPCODE_AE_SRLS64, + OPCODE_AE_SRAS64, + OPCODE_AE_SLAA64, + OPCODE_AE_SRLA64, + OPCODE_AE_SRAA64, + OPCODE_AE_SLAISQ56S, + OPCODE_AE_SLASSQ56S, + OPCODE_AE_SLAASQ56S, + OPCODE_AE_SLAI64S, + OPCODE_AE_SLAS64S, + OPCODE_AE_SLAA64S, + OPCODE_AE_LT64, + OPCODE_AE_LE64, + OPCODE_AE_EQ64, + OPCODE_AE_MAX64, + OPCODE_AE_MIN64, + OPCODE_AE_NSA64, + OPCODE_AE_NSAZ16_0, + OPCODE_AE_NSAZ32_L, + OPCODE_AE_MULS32F48P16S_LL, + OPCODE_AE_MULF32S_LL, + OPCODE_AE_MUL32_LL, + OPCODE_AE_MULF32S_LL_S2, + OPCODE_AE_MUL32_LL_S2, + OPCODE_AE_MULS32F48P16S_LL_S2, + OPCODE_AE_MULF32R_LL, + OPCODE_AE_MULF32RA_LL, + OPCODE_AE_MULF32RA_LL_S2, + OPCODE_AE_MULF32R_LL_S2, + OPCODE_AE_MULS32F48P16S_LH, + OPCODE_AE_MULF32S_LH, + OPCODE_AE_MUL32_LH, + OPCODE_AE_MULF32S_LH_S2, + OPCODE_AE_MUL32_LH_S2, + OPCODE_AE_MULS32F48P16S_LH_S2, + OPCODE_AE_MULF32R_LH, + OPCODE_AE_MULF32RA_LH, + OPCODE_AE_MULF32RA_LH_S2, + OPCODE_AE_MULF32R_LH_S2, + OPCODE_AE_MULS32F48P16S_HH, + OPCODE_AE_MULF32S_HH, + OPCODE_AE_MUL32_HH, + OPCODE_AE_MULF32S_HH_S2, + OPCODE_AE_MUL32_HH_S2, + OPCODE_AE_MULS32F48P16S_HH_S2, + OPCODE_AE_MULF32R_HH, + OPCODE_AE_MULF32RA_HH, + OPCODE_AE_MULF32RA_HH_S2, + OPCODE_AE_MULF32R_HH_S2, + OPCODE_AE_MULAS32F48P16S_LL, + OPCODE_AE_MULAF32S_LL, + OPCODE_AE_MULA32_LL, + OPCODE_AE_MULAF32S_LL_S2, + OPCODE_AE_MULA32_LL_S2, + OPCODE_AE_MULAS32F48P16S_LL_S2, + OPCODE_AE_MULAF32R_LL, + OPCODE_AE_MULAF32RA_LL, + OPCODE_AE_MULAF32RA_LL_S2, + OPCODE_AE_MULAF32R_LL_S2, + OPCODE_AE_MULAS32F48P16S_LH, + OPCODE_AE_MULAF32S_LH, + OPCODE_AE_MULA32_LH, + OPCODE_AE_MULAF32S_LH_S2, + OPCODE_AE_MULA32_LH_S2, + OPCODE_AE_MULAS32F48P16S_LH_S2, + OPCODE_AE_MULAF32R_LH, + OPCODE_AE_MULAF32RA_LH, + OPCODE_AE_MULAF32RA_LH_S2, + OPCODE_AE_MULAF32R_LH_S2, + OPCODE_AE_MULAS32F48P16S_HH, + OPCODE_AE_MULAF32S_HH, + OPCODE_AE_MULA32_HH, + OPCODE_AE_MULAF32S_HH_S2, + OPCODE_AE_MULA32_HH_S2, + OPCODE_AE_MULAS32F48P16S_HH_S2, + OPCODE_AE_MULAF32R_HH, + OPCODE_AE_MULAF32RA_HH, + OPCODE_AE_MULAF32RA_HH_S2, + OPCODE_AE_MULAF32R_HH_S2, + OPCODE_AE_MULSS32F48P16S_LL, + OPCODE_AE_MULSF32S_LL, + OPCODE_AE_MULS32_LL, + OPCODE_AE_MULSF32S_LL_S2, + OPCODE_AE_MULS32_LL_S2, + OPCODE_AE_MULSS32F48P16S_LL_S2, + OPCODE_AE_MULSF32R_LL, + OPCODE_AE_MULSF32RA_LL, + OPCODE_AE_MULSF32RA_LL_S2, + OPCODE_AE_MULSF32R_LL_S2, + OPCODE_AE_MULSS32F48P16S_LH, + OPCODE_AE_MULSF32S_LH, + OPCODE_AE_MULS32_LH, + OPCODE_AE_MULSF32S_LH_S2, + OPCODE_AE_MULS32_LH_S2, + OPCODE_AE_MULSS32F48P16S_LH_S2, + OPCODE_AE_MULSF32R_LH, + OPCODE_AE_MULSF32RA_LH, + OPCODE_AE_MULSF32RA_LH_S2, + OPCODE_AE_MULSF32R_LH_S2, + OPCODE_AE_MULSS32F48P16S_HH, + OPCODE_AE_MULSF32S_HH, + OPCODE_AE_MULS32_HH, + OPCODE_AE_MULSF32S_HH_S2, + OPCODE_AE_MULS32_HH_S2, + OPCODE_AE_MULSS32F48P16S_HH_S2, + OPCODE_AE_MULSF32R_HH, + OPCODE_AE_MULSF32RA_HH, + OPCODE_AE_MULSF32RA_HH_S2, + OPCODE_AE_MULSF32R_HH_S2, + OPCODE_AE_MUL32U_LL, + OPCODE_AE_MULA32U_LL, + OPCODE_AE_MULS32U_LL, + OPCODE_AE_MULF16SS_33, + OPCODE_AE_MULF16SS_33_S2, + OPCODE_AE_MULF16SS_22, + OPCODE_AE_MULF16SS_22_S2, + OPCODE_AE_MULF16SS_32, + OPCODE_AE_MULF16SS_32_S2, + OPCODE_AE_MULF16SS_21, + OPCODE_AE_MULF16SS_21_S2, + OPCODE_AE_MULF16SS_31, + OPCODE_AE_MULF16SS_31_S2, + OPCODE_AE_MULF16SS_30, + OPCODE_AE_MULF16SS_30_S2, + OPCODE_AE_MULF16SS_10, + OPCODE_AE_MULF16SS_10_S2, + OPCODE_AE_MULF16SS_20, + OPCODE_AE_MULF16SS_20_S2, + OPCODE_AE_MULF16SS_11, + OPCODE_AE_MULF16SS_11_S2, + OPCODE_AE_MULF16SS_00, + OPCODE_AE_MULF16SS_00_S2, + OPCODE_AE_MULSF16SS_33, + OPCODE_AE_MULSF16SS_33_S2, + OPCODE_AE_MULSF16SS_22, + OPCODE_AE_MULSF16SS_22_S2, + OPCODE_AE_MULSF16SS_32, + OPCODE_AE_MULSF16SS_32_S2, + OPCODE_AE_MULSF16SS_21, + OPCODE_AE_MULSF16SS_21_S2, + OPCODE_AE_MULSF16SS_31, + OPCODE_AE_MULSF16SS_31_S2, + OPCODE_AE_MULSF16SS_30, + OPCODE_AE_MULSF16SS_30_S2, + OPCODE_AE_MULSF16SS_10, + OPCODE_AE_MULSF16SS_10_S2, + OPCODE_AE_MULSF16SS_20, + OPCODE_AE_MULSF16SS_20_S2, + OPCODE_AE_MULSF16SS_11, + OPCODE_AE_MULSF16SS_11_S2, + OPCODE_AE_MULSF16SS_00, + OPCODE_AE_MULSF16SS_00_S2, + OPCODE_AE_MULAF16SS_33, + OPCODE_AE_MULAF16SS_33_S2, + OPCODE_AE_MULAF16SS_22, + OPCODE_AE_MULAF16SS_22_S2, + OPCODE_AE_MULAF16SS_32, + OPCODE_AE_MULAF16SS_32_S2, + OPCODE_AE_MULAF16SS_21, + OPCODE_AE_MULAF16SS_21_S2, + OPCODE_AE_MULAF16SS_31, + OPCODE_AE_MULAF16SS_31_S2, + OPCODE_AE_MULAF16SS_30, + OPCODE_AE_MULAF16SS_30_S2, + OPCODE_AE_MULAF16SS_10, + OPCODE_AE_MULAF16SS_10_S2, + OPCODE_AE_MULAF16SS_20, + OPCODE_AE_MULAF16SS_20_S2, + OPCODE_AE_MULAF16SS_11, + OPCODE_AE_MULAF16SS_11_S2, + OPCODE_AE_MULAF16SS_00, + OPCODE_AE_MULAF16SS_00_S2, + OPCODE_AE_MULAAFD16SS_33_22, + OPCODE_AE_MULAAFD16SS_33_22_S2, + OPCODE_AE_MULAAFD16SS_13_02, + OPCODE_AE_MULAAFD16SS_13_02_S2, + OPCODE_AE_MULAAFD16SS_11_00, + OPCODE_AE_MULAAFD16SS_11_00_S2, + OPCODE_AE_MULSSFD16SS_33_22, + OPCODE_AE_MULSSFD16SS_33_22_S2, + OPCODE_AE_MULSSFD16SS_13_02, + OPCODE_AE_MULSSFD16SS_13_02_S2, + OPCODE_AE_MULSSFD16SS_11_00, + OPCODE_AE_MULSSFD16SS_11_00_S2, + OPCODE_AE_MULZAAFD16SS_33_22, + OPCODE_AE_MULZAAFD16SS_33_22_S2, + OPCODE_AE_MULZAAFD16SS_13_02, + OPCODE_AE_MULZAAFD16SS_13_02_S2, + OPCODE_AE_MULZAAFD16SS_11_00, + OPCODE_AE_MULZAAFD16SS_11_00_S2, + OPCODE_AE_MULZSSFD16SS_33_22, + OPCODE_AE_MULZSSFD16SS_33_22_S2, + OPCODE_AE_MULZSSFD16SS_13_02, + OPCODE_AE_MULZSSFD16SS_13_02_S2, + OPCODE_AE_MULZSSFD16SS_11_00, + OPCODE_AE_MULZSSFD16SS_11_00_S2, + OPCODE_AE_MULF48Q32SP16S_L, + OPCODE_AE_MULF48Q32SP16S_L_S2, + OPCODE_AE_MULF48Q32SP16U_L, + OPCODE_AE_MULF48Q32SP16U_L_S2, + OPCODE_AE_MULQ32SP16S_L, + OPCODE_AE_MULQ32SP16S_L_S2, + OPCODE_AE_MULQ32SP16U_L, + OPCODE_AE_MULQ32SP16U_L_S2, + OPCODE_AE_MULAF48Q32SP16S_L, + OPCODE_AE_MULAF48Q32SP16S_L_S2, + OPCODE_AE_MULAF48Q32SP16U_L, + OPCODE_AE_MULAF48Q32SP16U_L_S2, + OPCODE_AE_MULAQ32SP16S_L, + OPCODE_AE_MULAQ32SP16S_L_S2, + OPCODE_AE_MULAQ32SP16U_L, + OPCODE_AE_MULAQ32SP16U_L_S2, + OPCODE_AE_MULSF48Q32SP16S_L, + OPCODE_AE_MULSF48Q32SP16S_L_S2, + OPCODE_AE_MULSF48Q32SP16U_L, + OPCODE_AE_MULSF48Q32SP16U_L_S2, + OPCODE_AE_MULSQ32SP16S_L, + OPCODE_AE_MULSQ32SP16S_L_S2, + OPCODE_AE_MULSQ32SP16U_L, + OPCODE_AE_MULSQ32SP16U_L_S2, + OPCODE_AE_MULFP24X2RA, + OPCODE_AE_MULFP24X2R, + OPCODE_AE_MULFP24X2RA_S2, + OPCODE_AE_MULFP24X2R_S2, + OPCODE_AE_MULAFP24X2RA, + OPCODE_AE_MULAFP24X2R, + OPCODE_AE_MULAFP24X2RA_S2, + OPCODE_AE_MULAFP24X2R_S2, + OPCODE_AE_MULSFP24X2RA, + OPCODE_AE_MULSFP24X2R, + OPCODE_AE_MULSFP24X2RA_S2, + OPCODE_AE_MULSFP24X2R_S2, + OPCODE_AE_MULZAAFD32S_HH_LL, + OPCODE_AE_MULZAAFD32RA_HH_LL, + OPCODE_AE_MULZAAD32_HH_LL, + OPCODE_AE_MULZAAFD32S_HH_LL_S2, + OPCODE_AE_MULZAAFD32RA_HH_LL_S2, + OPCODE_AE_MULZAAD32_HH_LL_S2, + OPCODE_AE_MULZAAFD32S_HL_LH, + OPCODE_AE_MULZAAFD32RA_HL_LH, + OPCODE_AE_MULZAAD32_HL_LH, + OPCODE_AE_MULZAAFD32S_HL_LH_S2, + OPCODE_AE_MULZAAFD32RA_HL_LH_S2, + OPCODE_AE_MULZAAD32_HL_LH_S2, + OPCODE_AE_MULZASFD32S_HH_LL, + OPCODE_AE_MULZASFD32RA_HH_LL, + OPCODE_AE_MULZASD32_HH_LL, + OPCODE_AE_MULZASFD32S_HH_LL_S2, + OPCODE_AE_MULZASFD32RA_HH_LL_S2, + OPCODE_AE_MULZASD32_HH_LL_S2, + OPCODE_AE_MULZASFD32S_HL_LH, + OPCODE_AE_MULZASFD32RA_HL_LH, + OPCODE_AE_MULZASD32_HL_LH, + OPCODE_AE_MULZASFD32S_HL_LH_S2, + OPCODE_AE_MULZASFD32RA_HL_LH_S2, + OPCODE_AE_MULZASD32_HL_LH_S2, + OPCODE_AE_MULZSAFD32S_HH_LL, + OPCODE_AE_MULZSAFD32RA_HH_LL, + OPCODE_AE_MULZSAD32_HH_LL, + OPCODE_AE_MULZSAFD32S_HH_LL_S2, + OPCODE_AE_MULZSAFD32RA_HH_LL_S2, + OPCODE_AE_MULZSAD32_HH_LL_S2, + OPCODE_AE_MULZSSFD32S_HH_LL, + OPCODE_AE_MULZSSFD32RA_HH_LL, + OPCODE_AE_MULZSSD32_HH_LL, + OPCODE_AE_MULZSSFD32S_HH_LL_S2, + OPCODE_AE_MULZSSFD32RA_HH_LL_S2, + OPCODE_AE_MULZSSD32_HH_LL_S2, + OPCODE_AE_MULZSSFD32S_HL_LH, + OPCODE_AE_MULZSSFD32RA_HL_LH, + OPCODE_AE_MULZSSD32_HL_LH, + OPCODE_AE_MULZSSFD32S_HL_LH_S2, + OPCODE_AE_MULZSSFD32RA_HL_LH_S2, + OPCODE_AE_MULZSSD32_HL_LH_S2, + OPCODE_AE_MULAAFD32S_HH_LL, + OPCODE_AE_MULAAFD32RA_HH_LL, + OPCODE_AE_MULAAD32_HH_LL, + OPCODE_AE_MULAAFD32S_HH_LL_S2, + OPCODE_AE_MULAAFD32RA_HH_LL_S2, + OPCODE_AE_MULAAD32_HH_LL_S2, + OPCODE_AE_MULAAFD32S_HL_LH, + OPCODE_AE_MULAAFD32RA_HL_LH, + OPCODE_AE_MULAAD32_HL_LH, + OPCODE_AE_MULAAFD32S_HL_LH_S2, + OPCODE_AE_MULAAFD32RA_HL_LH_S2, + OPCODE_AE_MULAAD32_HL_LH_S2, + OPCODE_AE_MULASFD32S_HH_LL, + OPCODE_AE_MULASFD32RA_HH_LL, + OPCODE_AE_MULASD32_HH_LL, + OPCODE_AE_MULASFD32S_HH_LL_S2, + OPCODE_AE_MULASFD32RA_HH_LL_S2, + OPCODE_AE_MULASD32_HH_LL_S2, + OPCODE_AE_MULASFD32S_HL_LH, + OPCODE_AE_MULASFD32RA_HL_LH, + OPCODE_AE_MULASD32_HL_LH, + OPCODE_AE_MULASFD32S_HL_LH_S2, + OPCODE_AE_MULASFD32RA_HL_LH_S2, + OPCODE_AE_MULASD32_HL_LH_S2, + OPCODE_AE_MULSAFD32S_HH_LL, + OPCODE_AE_MULSAFD32RA_HH_LL, + OPCODE_AE_MULSAD32_HH_LL, + OPCODE_AE_MULSAFD32S_HH_LL_S2, + OPCODE_AE_MULSAFD32RA_HH_LL_S2, + OPCODE_AE_MULSAD32_HH_LL_S2, + OPCODE_AE_MULSSFD32S_HH_LL, + OPCODE_AE_MULSSFD32RA_HH_LL, + OPCODE_AE_MULSSD32_HH_LL, + OPCODE_AE_MULSSFD32S_HH_LL_S2, + OPCODE_AE_MULSSFD32RA_HH_LL_S2, + OPCODE_AE_MULSSD32_HH_LL_S2, + OPCODE_AE_MULSSFD32S_HL_LH, + OPCODE_AE_MULSSFD32RA_HL_LH, + OPCODE_AE_MULSSD32_HL_LH, + OPCODE_AE_MULSSFD32S_HL_LH_S2, + OPCODE_AE_MULSSFD32RA_HL_LH_S2, + OPCODE_AE_MULSSD32_HL_LH_S2, + OPCODE_AE_MULF32X16_L0, + OPCODE_AE_MUL32X16_L0, + OPCODE_AE_MULF32X16_L0_S2, + OPCODE_AE_MUL32X16_L0_S2, + OPCODE_AE_MULF32X16_L1, + OPCODE_AE_MUL32X16_L1, + OPCODE_AE_MULF32X16_L1_S2, + OPCODE_AE_MUL32X16_L1_S2, + OPCODE_AE_MULF32X16_L2, + OPCODE_AE_MUL32X16_L2, + OPCODE_AE_MULF32X16_L2_S2, + OPCODE_AE_MUL32X16_L2_S2, + OPCODE_AE_MULF32X16_L3, + OPCODE_AE_MUL32X16_L3, + OPCODE_AE_MULF32X16_L3_S2, + OPCODE_AE_MUL32X16_L3_S2, + OPCODE_AE_MULF32X16_H0, + OPCODE_AE_MUL32X16_H0, + OPCODE_AE_MULF32X16_H0_S2, + OPCODE_AE_MUL32X16_H0_S2, + OPCODE_AE_MULF32X16_H1, + OPCODE_AE_MUL32X16_H1, + OPCODE_AE_MULF32X16_H1_S2, + OPCODE_AE_MUL32X16_H1_S2, + OPCODE_AE_MULF32X16_H2, + OPCODE_AE_MUL32X16_H2, + OPCODE_AE_MULF32X16_H2_S2, + OPCODE_AE_MUL32X16_H2_S2, + OPCODE_AE_MULF32X16_H3, + OPCODE_AE_MUL32X16_H3, + OPCODE_AE_MULF32X16_H3_S2, + OPCODE_AE_MUL32X16_H3_S2, + OPCODE_AE_MULAF32X16_L0, + OPCODE_AE_MULA32X16_L0, + OPCODE_AE_MULAF32X16_L0_S2, + OPCODE_AE_MULA32X16_L0_S2, + OPCODE_AE_MULAF32X16_L1, + OPCODE_AE_MULA32X16_L1, + OPCODE_AE_MULAF32X16_L1_S2, + OPCODE_AE_MULA32X16_L1_S2, + OPCODE_AE_MULAF32X16_L2, + OPCODE_AE_MULA32X16_L2, + OPCODE_AE_MULAF32X16_L2_S2, + OPCODE_AE_MULA32X16_L2_S2, + OPCODE_AE_MULAF32X16_L3, + OPCODE_AE_MULA32X16_L3, + OPCODE_AE_MULAF32X16_L3_S2, + OPCODE_AE_MULA32X16_L3_S2, + OPCODE_AE_MULAF32X16_H0, + OPCODE_AE_MULA32X16_H0, + OPCODE_AE_MULAF32X16_H0_S2, + OPCODE_AE_MULA32X16_H0_S2, + OPCODE_AE_MULAF32X16_H1, + OPCODE_AE_MULA32X16_H1, + OPCODE_AE_MULAF32X16_H1_S2, + OPCODE_AE_MULA32X16_H1_S2, + OPCODE_AE_MULAF32X16_H2, + OPCODE_AE_MULA32X16_H2, + OPCODE_AE_MULAF32X16_H2_S2, + OPCODE_AE_MULA32X16_H2_S2, + OPCODE_AE_MULAF32X16_H3, + OPCODE_AE_MULA32X16_H3, + OPCODE_AE_MULAF32X16_H3_S2, + OPCODE_AE_MULA32X16_H3_S2, + OPCODE_AE_MULSF32X16_L0, + OPCODE_AE_MULS32X16_L0, + OPCODE_AE_MULSF32X16_L0_S2, + OPCODE_AE_MULS32X16_L0_S2, + OPCODE_AE_MULSF32X16_L1, + OPCODE_AE_MULS32X16_L1, + OPCODE_AE_MULSF32X16_L1_S2, + OPCODE_AE_MULS32X16_L1_S2, + OPCODE_AE_MULSF32X16_L2, + OPCODE_AE_MULS32X16_L2, + OPCODE_AE_MULSF32X16_L2_S2, + OPCODE_AE_MULS32X16_L2_S2, + OPCODE_AE_MULSF32X16_L3, + OPCODE_AE_MULS32X16_L3, + OPCODE_AE_MULSF32X16_L3_S2, + OPCODE_AE_MULS32X16_L3_S2, + OPCODE_AE_MULSF32X16_H0, + OPCODE_AE_MULS32X16_H0, + OPCODE_AE_MULSF32X16_H0_S2, + OPCODE_AE_MULS32X16_H0_S2, + OPCODE_AE_MULSF32X16_H1, + OPCODE_AE_MULS32X16_H1, + OPCODE_AE_MULSF32X16_H1_S2, + OPCODE_AE_MULS32X16_H1_S2, + OPCODE_AE_MULSF32X16_H2, + OPCODE_AE_MULS32X16_H2, + OPCODE_AE_MULSF32X16_H2_S2, + OPCODE_AE_MULS32X16_H2_S2, + OPCODE_AE_MULSF32X16_H3, + OPCODE_AE_MULS32X16_H3, + OPCODE_AE_MULSF32X16_H3_S2, + OPCODE_AE_MULS32X16_H3_S2, + OPCODE_AE_MULAAFD32X16_H3_L2, + OPCODE_AE_MULAAD32X16_H3_L2, + OPCODE_AE_MULAAFD32X16_H3_L2_S2, + OPCODE_AE_MULAAD32X16_H3_L2_S2, + OPCODE_AE_MULAAFD32X16_H1_L0, + OPCODE_AE_MULAAD32X16_H1_L0, + OPCODE_AE_MULAAFD32X16_H1_L0_S2, + OPCODE_AE_MULAAD32X16_H1_L0_S2, + OPCODE_AE_MULASFD32X16_H3_L2, + OPCODE_AE_MULASD32X16_H3_L2, + OPCODE_AE_MULASFD32X16_H3_L2_S2, + OPCODE_AE_MULASD32X16_H3_L2_S2, + OPCODE_AE_MULASFD32X16_H1_L0, + OPCODE_AE_MULASD32X16_H1_L0, + OPCODE_AE_MULASFD32X16_H1_L0_S2, + OPCODE_AE_MULASD32X16_H1_L0_S2, + OPCODE_AE_MULSAFD32X16_H3_L2, + OPCODE_AE_MULSAD32X16_H3_L2, + OPCODE_AE_MULSAFD32X16_H3_L2_S2, + OPCODE_AE_MULSAD32X16_H3_L2_S2, + OPCODE_AE_MULSAFD32X16_H1_L0, + OPCODE_AE_MULSAD32X16_H1_L0, + OPCODE_AE_MULSAFD32X16_H1_L0_S2, + OPCODE_AE_MULSAD32X16_H1_L0_S2, + OPCODE_AE_MULSSFD32X16_H3_L2, + OPCODE_AE_MULSSD32X16_H3_L2, + OPCODE_AE_MULSSFD32X16_H3_L2_S2, + OPCODE_AE_MULSSD32X16_H3_L2_S2, + OPCODE_AE_MULSSFD32X16_H1_L0, + OPCODE_AE_MULSSD32X16_H1_L0, + OPCODE_AE_MULSSFD32X16_H1_L0_S2, + OPCODE_AE_MULSSD32X16_H1_L0_S2, + OPCODE_AE_MULZAAFD32X16_H3_L2, + OPCODE_AE_MULZAAD32X16_H3_L2, + OPCODE_AE_MULZAAFD32X16_H3_L2_S2, + OPCODE_AE_MULZAAD32X16_H3_L2_S2, + OPCODE_AE_MULZAAFD32X16_H1_L0, + OPCODE_AE_MULZAAD32X16_H1_L0, + OPCODE_AE_MULZAAFD32X16_H1_L0_S2, + OPCODE_AE_MULZAAD32X16_H1_L0_S2, + OPCODE_AE_MULZASFD32X16_H3_L2, + OPCODE_AE_MULZASD32X16_H3_L2, + OPCODE_AE_MULZASFD32X16_H3_L2_S2, + OPCODE_AE_MULZASD32X16_H3_L2_S2, + OPCODE_AE_MULZASFD32X16_H1_L0, + OPCODE_AE_MULZASD32X16_H1_L0, + OPCODE_AE_MULZASFD32X16_H1_L0_S2, + OPCODE_AE_MULZASD32X16_H1_L0_S2, + OPCODE_AE_MULZSAFD32X16_H3_L2, + OPCODE_AE_MULZSAD32X16_H3_L2, + OPCODE_AE_MULZSAFD32X16_H3_L2_S2, + OPCODE_AE_MULZSAD32X16_H3_L2_S2, + OPCODE_AE_MULZSAFD32X16_H1_L0, + OPCODE_AE_MULZSAD32X16_H1_L0, + OPCODE_AE_MULZSAFD32X16_H1_L0_S2, + OPCODE_AE_MULZSAD32X16_H1_L0_S2, + OPCODE_AE_MULZSSFD32X16_H3_L2, + OPCODE_AE_MULZSSD32X16_H3_L2, + OPCODE_AE_MULZSSFD32X16_H3_L2_S2, + OPCODE_AE_MULZSSD32X16_H3_L2_S2, + OPCODE_AE_MULZSSFD32X16_H1_L0, + OPCODE_AE_MULZSSD32X16_H1_L0, + OPCODE_AE_MULZSSFD32X16_H1_L0_S2, + OPCODE_AE_MULZSSD32X16_H1_L0_S2, + OPCODE_AE_MULZAAFD32X16_H2_L3, + OPCODE_AE_MULZAAFD32X16_H0_L1, + OPCODE_AE_MULAAFD32X16_H2_L3, + OPCODE_AE_MULAAFD32X16_H0_L1, + OPCODE_AE_MULZAAD32X16_H2_L3, + OPCODE_AE_MULZAAD32X16_H0_L1, + OPCODE_AE_MULAAD32X16_H2_L3, + OPCODE_AE_MULAAD32X16_H0_L1, + OPCODE_AE_MULZAAFD32X16_H2_L3_S2, + OPCODE_AE_MULZAAFD32X16_H0_L1_S2, + OPCODE_AE_MULAAFD32X16_H2_L3_S2, + OPCODE_AE_MULAAFD32X16_H0_L1_S2, + OPCODE_AE_MULZAAD32X16_H2_L3_S2, + OPCODE_AE_MULZAAD32X16_H0_L1_S2, + OPCODE_AE_MULAAD32X16_H2_L3_S2, + OPCODE_AE_MULAAD32X16_H0_L1_S2, + OPCODE_AE_MULP32X16X2_H, + OPCODE_AE_MULFP32X16X2RS_H, + OPCODE_AE_MULFP32X16X2RAS_H, + OPCODE_AE_MULFP32X16X2S_H, + OPCODE_AE_MULFP32X16X2S_H_S2, + OPCODE_AE_MULP32X16X2_H_S2, + OPCODE_AE_MULFP32X16X2RS_H_S2, + OPCODE_AE_MULFP32X16X2RAS_H_S2, + OPCODE_AE_MULP32X16X2_L, + OPCODE_AE_MULFP32X16X2RS_L, + OPCODE_AE_MULFP32X16X2RAS_L, + OPCODE_AE_MULFP32X16X2S_L, + OPCODE_AE_MULFP32X16X2S_L_S2, + OPCODE_AE_MULP32X16X2_L_S2, + OPCODE_AE_MULFP32X16X2RS_L_S2, + OPCODE_AE_MULFP32X16X2RAS_L_S2, + OPCODE_AE_MULAP32X16X2_H, + OPCODE_AE_MULAFP32X16X2RS_H, + OPCODE_AE_MULAFP32X16X2RAS_H, + OPCODE_AE_MULAFP32X16X2S_H, + OPCODE_AE_MULAFP32X16X2S_H_S2, + OPCODE_AE_MULAP32X16X2_H_S2, + OPCODE_AE_MULAFP32X16X2RS_H_S2, + OPCODE_AE_MULAFP32X16X2RAS_H_S2, + OPCODE_AE_MULAP32X16X2_L, + OPCODE_AE_MULAFP32X16X2RS_L, + OPCODE_AE_MULAFP32X16X2RAS_L, + OPCODE_AE_MULAFP32X16X2S_L, + OPCODE_AE_MULAFP32X16X2S_L_S2, + OPCODE_AE_MULAP32X16X2_L_S2, + OPCODE_AE_MULAFP32X16X2RS_L_S2, + OPCODE_AE_MULAFP32X16X2RAS_L_S2, + OPCODE_AE_MULSP32X16X2_H, + OPCODE_AE_MULSFP32X16X2RS_H, + OPCODE_AE_MULSFP32X16X2RAS_H, + OPCODE_AE_MULSFP32X16X2S_H, + OPCODE_AE_MULSFP32X16X2S_H_S2, + OPCODE_AE_MULSP32X16X2_H_S2, + OPCODE_AE_MULSFP32X16X2RS_H_S2, + OPCODE_AE_MULSFP32X16X2RAS_H_S2, + OPCODE_AE_MULSP32X16X2_L, + OPCODE_AE_MULSFP32X16X2RS_L, + OPCODE_AE_MULSFP32X16X2RAS_L, + OPCODE_AE_MULSFP32X16X2S_L, + OPCODE_AE_MULSFP32X16X2S_L_S2, + OPCODE_AE_MULSP32X16X2_L_S2, + OPCODE_AE_MULSFP32X16X2RS_L_S2, + OPCODE_AE_MULSFP32X16X2RAS_L_S2, + OPCODE_AE_MULP32X2, + OPCODE_AE_MULFP32X2RS, + OPCODE_AE_MULFP32X2RAS, + OPCODE_AE_MULP32X2_S2, + OPCODE_AE_MULFP32X2RS_S2, + OPCODE_AE_MULFP32X2RAS_S2, + OPCODE_AE_MULAP32X2, + OPCODE_AE_MULAFP32X2RS, + OPCODE_AE_MULAFP32X2RAS, + OPCODE_AE_MULAP32X2_S2, + OPCODE_AE_MULAFP32X2RS_S2, + OPCODE_AE_MULAFP32X2RAS_S2, + OPCODE_AE_MULSP32X2, + OPCODE_AE_MULSFP32X2RS, + OPCODE_AE_MULSFP32X2RAS, + OPCODE_AE_MULSP32X2_S2, + OPCODE_AE_MULSFP32X2RS_S2, + OPCODE_AE_MULSFP32X2RAS_S2, + OPCODE_AE_MULFP16X4S, + OPCODE_AE_MULFP16X4RAS, + OPCODE_AE_MULC32, + OPCODE_AE_MULFC24RA, + OPCODE_AE_MULFC32RAS, + OPCODE_AE_MULC32X16_L, + OPCODE_AE_MULFC32X16RAS_L, + OPCODE_AE_MULC32X16_H, + OPCODE_AE_MULFC32X16RAS_H, + OPCODE_AE_MULAC32, + OPCODE_AE_MULAFC24RA, + OPCODE_AE_MULAFC32RAS, + OPCODE_AE_MULAC32X16_L, + OPCODE_AE_MULAFC32X16RAS_L, + OPCODE_AE_MULAC32X16_H, + OPCODE_AE_MULAFC32X16RAS_H, + OPCODE_AE_MULF16X4SS, + OPCODE_AE_MULAF16X4SS, + OPCODE_AE_MULSF16X4SS, + OPCODE_AE_MUL16X4, + OPCODE_AE_MULA16X4, + OPCODE_AE_MULS16X4, + OPCODE_AE_MULFD32X2S_FIR_H, + OPCODE_AE_MULFD32X2RA_FIR_H, + OPCODE_AE_MULFD32X2S_FIR_L, + OPCODE_AE_MULFD32X2RA_FIR_L, + OPCODE_AE_MULFD32X16X2_FIR_HH, + OPCODE_AE_MULFD32X16X2_FIR_HL, + OPCODE_AE_MULFD32X16X2_FIR_LH, + OPCODE_AE_MULFD32X16X2_FIR_LL, + OPCODE_AE_MULAFD32X2S_FIR_H, + OPCODE_AE_MULAFD32X2RA_FIR_H, + OPCODE_AE_MULAFD32X2S_FIR_L, + OPCODE_AE_MULAFD32X2RA_FIR_L, + OPCODE_AE_MULAFD32X16X2_FIR_HH, + OPCODE_AE_MULAFD32X16X2_FIR_HL, + OPCODE_AE_MULAFD32X16X2_FIR_LH, + OPCODE_AE_MULAFD32X16X2_FIR_LL, + OPCODE_AE_MULZAAAAFQ32X16, + OPCODE_AE_MULAAAAFQ32X16, + OPCODE_AE_MULZAAAAFQ32X16_S2, + OPCODE_AE_MULAAAAFQ32X16_S2, + OPCODE_AE_MULZAAAAQ32X16, + OPCODE_AE_MULAAAAQ32X16, + OPCODE_AE_MULZAAAAQ32X16_S2, + OPCODE_AE_MULAAAAQ32X16_S2, + OPCODE_AE_MUL16_00, + OPCODE_AE_MULA16_00, + OPCODE_AE_MUL16_00_S2, + OPCODE_AE_MULA16_00_S2, + OPCODE_AE_MULZAAAAQ16, + OPCODE_AE_MULAAAAQ16, + OPCODE_AE_MULZAAAAQ16_S2, + OPCODE_AE_MULAAAAQ16_S2, + OPCODE_AE_DIV64D32_H, + OPCODE_AE_DIV64D32_L, + OPCODE_AE_SHA32, + OPCODE_AE_VLDL32T, + OPCODE_AE_VLDL16T, + OPCODE_AE_VLDL16C, + OPCODE_AE_VLDL16C_IP, + OPCODE_AE_VLDL16C_IC, + OPCODE_AE_VLDL16C_IC1, + OPCODE_AE_VLDSHT, + OPCODE_AE_LB, + OPCODE_AE_LBI, + OPCODE_AE_LBK, + OPCODE_AE_LBKI, + OPCODE_AE_LBS, + OPCODE_AE_LBSI, + OPCODE_AE_DB, + OPCODE_AE_DBI, + OPCODE_AE_DB_IC, + OPCODE_AE_DBI_IC, + OPCODE_AE_DB_IC1, + OPCODE_AE_DBI_IC1, + OPCODE_AE_DB_IP, + OPCODE_AE_DBI_IP, + OPCODE_AE_VLEL32T, + OPCODE_AE_VLEL16T, + OPCODE_AE_SB, + OPCODE_AE_SBI, + OPCODE_AE_VLES16C, + OPCODE_AE_SBF, + OPCODE_AE_SB_IC, + OPCODE_AE_SBI_IC, + OPCODE_AE_VLES16C_IC, + OPCODE_AE_SBF_IC, + OPCODE_AE_SB_IC1, + OPCODE_AE_SBI_IC1, + OPCODE_AE_VLES16C_IC1, + OPCODE_AE_SBF_IC1, + OPCODE_AE_SB_IP, + OPCODE_AE_SBI_IP, + OPCODE_AE_VLES16C_IP, + OPCODE_AE_SBF_IP, + OPCODE_AE_SEXT32, + OPCODE_AE_MOVAE, + OPCODE_AE_MOVEA, + OPCODE_AE_MOVEEP, + OPCODE_AE_SEXT72, + OPCODE_AE_ADD72, + OPCODE_AE_SUB72, + OPCODE_AE_ADD72X64, + OPCODE_AE_SUB72X64, + OPCODE_AE_MUL32EP_HH, + OPCODE_AE_MUL32EP_HH_S2, + OPCODE_AE_MULA32EP_HH, + OPCODE_AE_MULS32EP_HH, + OPCODE_AE_MULA32EP_HH_S2, + OPCODE_AE_MULS32EP_HH_S2, + OPCODE_AE_MULZAAD32EP_HH_LL, + OPCODE_AE_MULZSSD32EP_HH_LL, + OPCODE_AE_MULAAD32EP_HH_LL, + OPCODE_AE_MULSSD32EP_HH_LL, + OPCODE_AE_MULZAAD32EP_HH_LL_S2, + OPCODE_AE_MULZSSD32EP_HH_LL_S2, + OPCODE_AE_MULAAD32EP_HH_LL_S2, + OPCODE_AE_MULSSD32EP_HH_LL_S2, + OPCODE_AE_MULAAD32USEP_HL_LH, + OPCODE_AE_MULAAD32USEP_HL_LH_S2, + OPCODE_AE_MULZAAD32USEP_HL_LH, + OPCODE_AE_MULZAAD32USEP_HL_LH_S2, + OPCODE_AE_MUL32USEP_LH, + OPCODE_AE_MULA32USEP_LH, + OPCODE_AE_MUL32USEP_LL, + OPCODE_AE_MULA32USEP_LL, + OPCODE_AE_SRAI72, + OPCODE_AE_SLAI72, + OPCODE_AE_SAT64S, + OPCODE_AE_L16SI_N, + OPCODE_AE_L16UI_N, + OPCODE_AE_S16I_N, + OPCODE_AE_MOVFCRFSRV, + OPCODE_AE_MOVVFCRFSR, + OPCODE_RFR, + OPCODE_WFR, + OPCODE_MOVT_S, + OPCODE_MOVF_S, + OPCODE_MOVEQZ_S, + OPCODE_MOVNEZ_S, + OPCODE_MOVGEZ_S, + OPCODE_MOVLTZ_S, + OPCODE_TRUNC_S, + OPCODE_UTRUNC_S, + OPCODE_TRUNC_SX2, + OPCODE_UTRUNC_SX2, + OPCODE_FICEIL_S, + OPCODE_FIFLOOR_S, + OPCODE_FIROUND_S, + OPCODE_FITRUNC_S, + OPCODE_FIRINT_S, + OPCODE_CVTSF16_L, + OPCODE_CVTSF16_H, + OPCODE_CVTF16S_L, + OPCODE_CVTF16S_H, + OPCODE_ABS_S, + OPCODE_MUL_S, + OPCODE_MADD_S, + OPCODE_MSUB_S, + OPCODE_MSUBN_S, + OPCODE_MADDN_S, + OPCODE_ADD_S, + OPCODE_SUB_S, + OPCODE_NEG_S, + OPCODE_FLOAT_S, + OPCODE_UFLOAT_S, + OPCODE_FLOAT_SX2, + OPCODE_UFLOAT_SX2, + OPCODE_OLE_S, + OPCODE_OLT_S, + OPCODE_OEQ_S, + OPCODE_UN_S, + OPCODE_ULE_S, + OPCODE_ULT_S, + OPCODE_UEQ_S, + OPCODE_CONST_S, + OPCODE_NEXP01_S, + OPCODE_MKSADJ_S, + OPCODE_MKDADJ_S, + OPCODE_DIV0_S, + OPCODE_SQRT0_S, + OPCODE_RECIP0_S, + OPCODE_RSQRT0_S, + OPCODE_DIVN_S, + OPCODE_ADDEXP_S, + OPCODE_ADDEXPM_S, + OPCODE_MIN_S, + OPCODE_MAX_S, + OPCODE_MULMUX_S, + OPCODE_MADDMUX_S, + OPCODE_CONJC_S, + OPCODE_SIGMOID_Q15, + OPCODE_SIGMOID_FP32 +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 6 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 1 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_SIGMOID_Q15; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 6 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 0 && + Field_fld_inst_3_0_Slot_inst_get (insn) == 0) + return OPCODE_SIGMOID_FP32; + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + } + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFNXT_F; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFEND_A; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFEND_O; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFWAIT_A; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 3) + return OPCODE_PFWAIT_R; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_RITLB0; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_PITLB; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_WITLB; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_RITLB1; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RDTLB0; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PDTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WDTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RDTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_XSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_XSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_XSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_XSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_XSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_XSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_XSR_M3; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_XSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MULUH; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MULSH; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_RSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_RSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_RSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_RSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_RSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_RSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_RSR_M3; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_RSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_WSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_WSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_WSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_WSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_WSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_WSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_WSR_M3; + if (Field_sr_Slot_inst_get (insn) == 40) + return OPCODE_WSR_PREFCTL; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 232) + return OPCODE_RUR_FCR; + if (Field_st_Slot_inst_get (insn) == 233) + return OPCODE_RUR_FSR; + if (Field_st_Slot_inst_get (insn) == 234) + return OPCODE_RUR_F64R_LO; + if (Field_st_Slot_inst_get (insn) == 235) + return OPCODE_RUR_F64R_HI; + if (Field_st_Slot_inst_get (insn) == 236) + return OPCODE_RUR_F64S; + if (Field_st_Slot_inst_get (insn) == 240) + return OPCODE_RUR_AE_OVF_SAR; + if (Field_st_Slot_inst_get (insn) == 241) + return OPCODE_RUR_AE_BITHEAD; + if (Field_st_Slot_inst_get (insn) == 242) + return OPCODE_RUR_AE_TS_FTS_BU_BP; + if (Field_st_Slot_inst_get (insn) == 243) + return OPCODE_RUR_AE_CW_SD_NO; + if (Field_st_Slot_inst_get (insn) == 246) + return OPCODE_RUR_AE_CBEGIN0; + if (Field_st_Slot_inst_get (insn) == 247) + return OPCODE_RUR_AE_CEND0; + if (Field_st_Slot_inst_get (insn) == 248) + return OPCODE_RUR_AE_CBEGIN1; + if (Field_st_Slot_inst_get (insn) == 249) + return OPCODE_RUR_AE_CEND1; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WUR_FCR; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WUR_FSR; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WUR_F64R_LO; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_WUR_F64R_HI; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WUR_F64S; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WUR_AE_OVF_SAR; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WUR_AE_BITHEAD; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WUR_AE_TS_FTS_BU_BP; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_WUR_AE_CW_SD_NO; + if (Field_sr_Slot_inst_get (insn) == 246) + return OPCODE_WUR_AE_CBEGIN0; + if (Field_sr_Slot_inst_get (insn) == 247) + return OPCODE_WUR_AE_CEND0; + if (Field_sr_Slot_inst_get (insn) == 248) + return OPCODE_WUR_AE_CBEGIN1; + if (Field_sr_Slot_inst_get (insn) == 249) + return OPCODE_WUR_AE_CEND1; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 3) + return OPCODE_DPFM_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 7) + return OPCODE_DPFM_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 1) + return OPCODE_DPFR_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 5) + return OPCODE_DPFR_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 2) + return OPCODE_DPFW_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 6) + return OPCODE_DPFW_BF; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 9) + return OPCODE_DHI_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 11) + return OPCODE_DHWBI_B; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 10) + return OPCODE_DHWB_B; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_op1_Slot_inst_get (insn) == 10) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ADD_S; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_SUB_S; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_MUL_S; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MADD_S; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MSUB_S; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MADDN_S; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_DIVN_S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_CONST_S; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_RFR; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_WFR; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_NEG_S; + } + } + if (Field_op1_Slot_inst_get (insn) == 11) + { + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_UN_S; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OEQ_S; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_UEQ_S; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_OLT_S; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_ULT_S; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_OLE_S; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_ULE_S; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ_S; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ_S; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ_S; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ_S; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF_S; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT_S; + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_dfp_fld_op1_Slot_inst_get (insn) == 11) + { + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 0) + { + if (Field_dfp_fld_r_3_1_Slot_inst_get (insn) == 7) + return OPCODE_WF64R; + if (Field_dfp_fld_s_3_1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 12) + return OPCODE_RF64R; + } + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 14) + { + return OPCODE_F64CMPL; + } + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 15) + { + if (Field_dfp_fld_r_3_Slot_inst_get (insn) == 0) + return OPCODE_F64ADDC; + if (Field_dfp_fld_r_3_Slot_inst_get (insn) == 1) + return OPCODE_F64SUBC; + } + } + if (Field_dfp_fld_op1_Slot_inst_get (insn) == 14) + { + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_F64SIG; + } + if (Field_dfp_fld_op2_Slot_inst_get (insn) == 1) + { + return OPCODE_F64SEXP; + } + if (Field_dfp_fld_op2_3_Slot_inst_get (insn) == 1) + return OPCODE_F64ITER; + if (Field_dfp_fld_op2_3_1_Slot_inst_get (insn) == 1) + return OPCODE_F64NORM; + if (Field_dfp_fld_op2_3_2_Slot_inst_get (insn) == 1) + return OPCODE_F64RND; + } + if (Field_dfp_fld_op1_Slot_inst_get (insn) == 15) + { + return OPCODE_F64CMPH; + } + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_DPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_DHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_DIU; + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_DIWBUI_P; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_S32C1I; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1860) + return OPCODE_AE_DBI_IC1; + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1918 && + Field_fld_inst_7_4_Slot_inst_get (insn) == 12) + return OPCODE_AE_SBF_IC1; + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1956) + return OPCODE_AE_SB_IC1; + if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1972) + return OPCODE_AE_DB_IC1; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 27 && + Field_fld_inst_7_7_Slot_inst_get (insn) == 0 && + Field_fld_inst_4_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 31) + return OPCODE_AE_SBI_IC1; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 36 && + Field_fld_inst_13_8_Slot_inst_get (insn) == 23) + return OPCODE_AE_MOVBA4; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 36 && + Field_fld_inst_12_8_Slot_inst_get (insn) == 7) + return OPCODE_AE_MOVBA2; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 38 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_AE_MOVAB; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 46 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_AE_MOVBA; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 47 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8 && + Field_fld_inst_5_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_MOVAB4; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 47 && + Field_fld_inst_11_8_Slot_inst_get (insn) == 8 && + Field_fld_inst_4_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_MOVAB2; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 47 && + Field_fld_inst_13_8_Slot_inst_get (insn) == 8 && + Field_fld_inst_5_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_MOVB4; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 70) + return OPCODE_AE_L64_IP; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 104 && + Field_fld_inst_12_8_Slot_inst_get (insn) == 8 && + Field_fld_inst_4_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_MOVB2; + if (Field_fld_inst_23_16_Slot_inst_get (insn) == 104 && + Field_fld_inst_9_8_Slot_inst_get (insn) == 1) + return OPCODE_AE_PKSRF32; + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_S64_I; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_S64_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_LA32X2_IC; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_6_Slot_inst_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_6_Slot_inst_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 0) + return OPCODE_AE_LA24X2_IC; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 1) + return OPCODE_AE_LA24X2_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_6_Slot_inst_get (insn) == 3) + return OPCODE_AE_SA32X2_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_S32RA64S_XP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_SRAA32; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_SLAA32S; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_SLAASQ56S; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_VLDL32T; + if (Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_VLDL16T; + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_MOVDA32X2; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_MOVDA16X2; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_TRUNCP16; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_TRUNCQ32; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_OR; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_XOR; + if (Field_op2_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_SEXT32; + if (Field_op2_Slot_inst_get (insn) == 2) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_inst_11_8_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 1 && + Field_inst_5_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_ZALIGN64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_inst_11_8_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 0) + return OPCODE_AE_MOVALIGN; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_AE_SAT48S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_TRUNCA32Q48; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVAD32_L; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 11) + return OPCODE_AE_MOVAD32_H; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 10) + return OPCODE_AE_MOVAD16_3; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 9) + return OPCODE_AE_MOVAD16_2; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 8) + return OPCODE_AE_MOVAD16_0; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_9_8_Slot_inst_get (insn) == 2) + return OPCODE_AE_PKSR32; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_inst_9_8_Slot_inst_get (insn) == 2) + return OPCODE_AE_PKSR24; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 1) + return OPCODE_AE_ABS24S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_AE_NEG32S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_AE_ABS32S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_AE_NEG16S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_AE_ABS16S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 5) + return OPCODE_AE_NEG64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_AE_ABS64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_AE_SLAS24; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 14) + return OPCODE_AE_SRAS24; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_SLAA32; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_SLAA16S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLASQ56; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 15) + return OPCODE_AE_SRASQ56; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_SLAAQ56; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_SLAA64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_11_8_Slot_inst_get (insn) == 13) + return OPCODE_AE_SLAS64S; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 13) + return OPCODE_AE_NSA64; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 14) + return OPCODE_AE_NSAZ16_0; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_4_Slot_inst_get (insn) == 15) + return OPCODE_AE_NSAZ32_L; + if (Field_op2_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_11_8_Slot_inst_get (insn) == 4) + return OPCODE_AE_DIV64D32_L; + if (Field_op2_Slot_inst_get (insn) == 3) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_LA16X4_IC; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 3) + return OPCODE_AE_LA16X4_IP; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_LA16X4_RIP; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_inst_7_6_Slot_inst_get (insn) == 3) + return OPCODE_AE_SA32X2F24_IP; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_inst_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_inst_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_MOVF32X2; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_MOVDA32; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_MOVDA16; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_inst_7_6_Slot_inst_get (insn) == 2) + return OPCODE_AE_MOVI; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_CVT48A32; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_ADD32; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_ADD24S; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_ADD16S; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_ADD64; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_inst_7_4_Slot_inst_get (insn) == 8) + return OPCODE_AE_SHA32; + if (Field_op2_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_15_12_Slot_inst_get (insn) == 1 && + Field_inst_11_8_Slot_inst_get (insn) == 0) + return OPCODE_AE_VLDSHT; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_SUB32; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_ADD32S; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_SUB32S; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_SUB16S; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_SUB64; + if (Field_op2_Slot_inst_get (insn) == 4 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_AND; + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_12_Slot_inst_get (insn) == 1) + return OPCODE_AE_LT32; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_inst_12_Slot_inst_get (insn) == 0) + return OPCODE_AE_EQ32; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_MIN32; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_MAX32; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_LT64; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_LE64; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_SBI_IC; + if (Field_op2_Slot_inst_get (insn) == 5 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_SBI_IP; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_OVERFLOW; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 13) + return OPCODE_WUR_AE_SAR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 14) + return OPCODE_RUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_11_8_Slot_inst_get (insn) == 15) + return OPCODE_WUR_AE_BITPTR; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 0) + return OPCODE_RUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 1) + return OPCODE_WUR_AE_BITSUSED; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_RUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_WUR_AE_TABLESIZE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 4) + return OPCODE_RUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 5) + return OPCODE_WUR_AE_FIRST_TS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_RUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_WUR_AE_NEXTOFFSET; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 8) + return OPCODE_RUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 9) + return OPCODE_WUR_AE_SEARCHDONE; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 10) + return OPCODE_RUR_AE_CWRAP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 15 && + Field_inst_11_8_Slot_inst_get (insn) == 11) + return OPCODE_WUR_AE_CWRAP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_inst_7_Slot_inst_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_MOVT64; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_SRLAQ56; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_inst_11_8_Slot_inst_get (insn) == 2) + return OPCODE_AE_LB; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_inst_11_8_Slot_inst_get (insn) == 3) + return OPCODE_AE_LBI; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_inst_11_8_Slot_inst_get (insn) == 6) + return OPCODE_AE_LBS; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_inst_11_8_Slot_inst_get (insn) == 7) + return OPCODE_AE_LBSI; + if (Field_op2_Slot_inst_get (insn) == 6 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_SBI; + if (Field_op2_Slot_inst_get (insn) == 7) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 2) + return OPCODE_AE_LA64_PP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 1) + return OPCODE_AE_LA32X2POS_PC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_7_6_Slot_inst_get (insn) == 3 && + Field_inst_15_12_Slot_inst_get (insn) == 3) + return OPCODE_AE_SA64POS_FP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 6) + return OPCODE_AE_VLDL16C; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 8) + return OPCODE_AE_VLDL16C_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 7) + return OPCODE_AE_VLDL16C_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 4) + return OPCODE_AE_DB; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 5) + return OPCODE_AE_DBI; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 6) + return OPCODE_AE_DB_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 7) + return OPCODE_AE_DBI_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 8) + return OPCODE_AE_DB_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 9) + return OPCODE_AE_DBI_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 10) + return OPCODE_AE_SB; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 0) + return OPCODE_AE_VLES16C; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 1) + return OPCODE_AE_SBF; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 11) + return OPCODE_AE_SB_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 2) + return OPCODE_AE_VLES16C_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 3) + return OPCODE_AE_SBF_IC; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 12) + return OPCODE_AE_SB_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 4) + return OPCODE_AE_VLES16C_IP; + if (Field_op2_Slot_inst_get (insn) == 7 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_inst_15_12_Slot_inst_get (insn) == 14 && + Field_inst_7_4_Slot_inst_get (insn) == 5) + return OPCODE_AE_SBF_IP; + if (Field_op2_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_SRAA32S; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_inst_19_18_Slot_inst_get (insn) == 2) + return OPCODE_AE_SLAI64; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_inst_19_18_Slot_inst_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_SRAA64; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_inst_19_18_Slot_inst_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_op2_Slot_inst_get (insn) == 8 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_LBK; + if (Field_op2_Slot_inst_get (insn) == 9) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_inst_7_Slot_inst_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 2) + return OPCODE_AE_SLAI24; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 6) + return OPCODE_AE_SRAI24; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 3) + return OPCODE_AE_SLAI32; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 1) + return OPCODE_AE_SRLI32; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 7) + return OPCODE_AE_SRAI32; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 4) + return OPCODE_AE_SLAI24S; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_inst_19_17_Slot_inst_get (insn) == 5) + return OPCODE_AE_SLAI32S; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_SRAAQ56; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_SEL16I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_L16M_IU; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_L16M_XU; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_L16_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_L16_IP; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_L32F24_XC; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_L32F24_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_L32F24_IP; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_L32_XC; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_L32_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_L32_IP; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_L32_X; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 8) + return OPCODE_AE_L16X2M_I; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 9) + return OPCODE_AE_L16X2M_IU; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 10) + return OPCODE_AE_L16X2M_X; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_op1_Slot_inst_get (insn) == 11) + return OPCODE_AE_L16X2M_XU; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 8) + return OPCODE_AE_L32M_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 9) + return OPCODE_AE_L32M_IU; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 10) + return OPCODE_AE_L32M_X; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 11) + return OPCODE_AE_L32M_XU; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_L32X2F24_XC; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_L32X2F24_X; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_L32X2F24_XP; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_L32X2_XC; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_L32X2_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_L32X2_X; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_L32X2_XP; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_L16X4_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_L16X4_XP; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_L64_I; + if (Field_op2_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_LBKI; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 8) + return OPCODE_AE_S16X2M_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 9) + return OPCODE_AE_S16X2M_IU; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 10) + return OPCODE_AE_S16X2M_X; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 11) + return OPCODE_AE_S16X2M_XU; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_S16X4_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_S16M_L_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_S16M_L_IU; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_S16M_L_X; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_S32F24_L_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_S32F24_L_IP; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_S16_0_I; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_S16_0_IP; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_S16_0_XP; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_S24RA64S_XP; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_VLEL32T; + if (Field_op2_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_VLEL16T; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 12) + return OPCODE_AE_S32X2F24_XC; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 13) + return OPCODE_AE_S32X2F24_I; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_AE_S32X2F24_X; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 15) + return OPCODE_AE_S32X2F24_XP; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 8) + return OPCODE_AE_S32X2_XC; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 9) + return OPCODE_AE_S32X2_I; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 10) + return OPCODE_AE_S32X2_X; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 11) + return OPCODE_AE_S32X2_XP; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_AE_S32_L_I; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 1) + return OPCODE_AE_S32_L_IP; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_AE_S32_L_X; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_AE_S32_L_XP; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_AE_S32M_I; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_AE_S32M_IU; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 6) + return OPCODE_AE_S32M_X; + if (Field_op2_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 7) + return OPCODE_AE_S32M_XU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_TRUNCA32X2F64S; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_L16SI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 2) + return OPCODE_AE_L16UI_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 3) + return OPCODE_AE_S16I_N; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_SEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 4 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 1) + return OPCODE_AE_ZEXT16; + if (Field_ae_fld_inst16b_15_13_Slot_inst16b_get (insn) == 5 && + Field_ae_fld_inst16b_12_Slot_inst16b_get (insn) == 0) + return OPCODE_AE_CLAMPS16; + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_get (insn) == 14592) + return OPCODE_NOP; + if (Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_get (insn) == 6) + return OPCODE_MOVI_N; + if (Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get (insn) == 0) + return OPCODE_ADD; + if (Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get (insn) == 1) + return OPCODE_ADDI_N; + if (Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get (insn) == 2) + return OPCODE_L32I_N; + if (Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_get (insn) == 56) + return OPCODE_MOV_N; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66116) + return OPCODE_ADD; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66117) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66118) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66119) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66120) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66121) + return OPCODE_AND; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66122) + return OPCODE_MAX; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66123) + return OPCODE_MAXU; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66124) + return OPCODE_MIN; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66125) + return OPCODE_MINU; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66126) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66127) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66320) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66321) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66322) + return OPCODE_OR; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66323) + return OPCODE_SRC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66324) + return OPCODE_SUB; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66325) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66326) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66327) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66328) + return OPCODE_XOR; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66329) + return OPCODE_MOVF; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66330) + return OPCODE_MOVT; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66331) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66332) + return OPCODE_SEXT; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66333) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66334) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66335) + return OPCODE_SRLI; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66336) + return OPCODE_ANDB; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66337) + return OPCODE_ANDBC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66338) + return OPCODE_ORB; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66339) + return OPCODE_ORBC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66340) + return OPCODE_XORB; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66341 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66341 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66341 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66341 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66342 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66342 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66342 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66342 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66343 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66343 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66343 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66343 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66344 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66344 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66344 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66345 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66345 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66345 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66346 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66346 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66346 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66347 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66347 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66347 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66348 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66348 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66348 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66349 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66350 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66350 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66350 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66350 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66351 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66351 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_CVTF16S_L; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66370 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_CVTF16S_H; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_FICEIL_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_FIFLOOR_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_FIROUND_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_FITRUNC_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_FIRINT_S; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_CVTSF16_L; + if (Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get (insn) == 66371 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_CVTSF16_H; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33056) + return OPCODE_SLLI; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33057) + return OPCODE_SRAI; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33176 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_SSAI; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33186) + return OPCODE_UFLOAT_SX2; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33187) + return OPCODE_UTRUNC_SX2; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33188) + return OPCODE_FLOAT_SX2; + if (Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get (insn) == 33189) + return OPCODE_TRUNC_SX2; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4114) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4115) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4116) + return OPCODE_ADDI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4117) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4118) + return OPCODE_L16SI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4119) + return OPCODE_L16UI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4120) + return OPCODE_L32I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4121) + return OPCODE_L8UI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4122) + return OPCODE_S16I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4123) + return OPCODE_S32I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4124) + return OPCODE_S8I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4125) + return OPCODE_MOVI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4126) + return OPCODE_AE_TRUNCI32F64S_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4127) + return OPCODE_AE_TRUNCI32X2F64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4128) + return OPCODE_AE_SEL16I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4129 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4129 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4129 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4129 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SRAI32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4130 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRLI64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRLI24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SRLI32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SLAA32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4131 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4133 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4134 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4135 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32M_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4136 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4137 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S64_XC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4138 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S64_XP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4139 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S32M_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_ADD32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_ADD16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_ADD24S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_ADD32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_ADD16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4140 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_ADD64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SUB32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SUB16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SUB24S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SUB32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SUB16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_MIN32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_MAX32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_SUB64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_ADD64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_SUB64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_MAX64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4141 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_MIN64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_MOVT64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_MOVF64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get (insn) == 61) + return OPCODE_AE_LE16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get (insn) == 29) + return OPCODE_AE_EQ16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get (insn) == 25) + return OPCODE_AE_LT32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get (insn) == 21) + return OPCODE_AE_LE32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get (insn) == 17) + return OPCODE_AE_EQ32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4142 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_AE_SRLA32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_SRLA64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4143 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_SRAA64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_LOOP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_LOOPGTZ; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_LOOPNEZ; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_AE_S64_I; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_AE_S64_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_AND; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_AE_NAND; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_AE_OR; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_AE_XOR; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_SRAI16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LT64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_AE_LE64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4144 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_AE_EQ64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 112) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 116) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 120) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 124) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 133) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 69) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 197) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 5 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 4 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_get (insn) == 166) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 162) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 160) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 164) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 163) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 34) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 32) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 161) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 111) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 109) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 110) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 108) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 107) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 41) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 39) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 37) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 38) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 36) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 35) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 33) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LT16; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 43) + return OPCODE_AE_SLAS24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 103) + return OPCODE_AE_SRLS24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 99) + return OPCODE_AE_SRAS24; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 46) + return OPCODE_AE_SLAS32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 104) + return OPCODE_AE_SRLS32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 100) + return OPCODE_AE_SRAS32; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 44) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 45) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 98) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 105) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 101) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 47) + return OPCODE_AE_SLAS64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 106) + return OPCODE_AE_SRLS64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 102) + return OPCODE_AE_SRAS64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 97) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 96) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 40) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get (insn) == 4147 && + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get (insn) == 42) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_get (insn) == 2056) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_get (insn) == 256) + return OPCODE_L32R; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BBSI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BALL_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BANY_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 9) + return OPCODE_BBC_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 13) + return OPCODE_BBS_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BEQ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BGEU_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BGE_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BLTU_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_BLT_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 7) + return OPCODE_BNALL_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 11) + return OPCODE_BNE_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 0 && + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get (insn) == 15) + return OPCODE_BNONE_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 10) + return OPCODE_BEQZ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 14) + return OPCODE_BGEZ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 74) + return OPCODE_BLTZ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get (insn) == 78) + return OPCODE_BNEZ_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_BEQI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 4) + return OPCODE_BGEI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_BLTI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 6) + return OPCODE_BNEI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 8) + return OPCODE_BGEUI_W15; + if (Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get (insn) == 1 && + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_BLTUI_W15; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16986637) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16986893) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16987149) + return OPCODE_SSL; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16987405) + return OPCODE_SSR; + if (Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get (insn) == 16990675 && + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get (insn) == 5) + return OPCODE_NOP; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061888) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061889) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061890) + return OPCODE_DPFM_B; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061891) + return OPCODE_DPFM_BF; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061892) + return OPCODE_DPFR_B; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061893) + return OPCODE_DPFR_BF; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061894) + return OPCODE_DPFW_B; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061895) + return OPCODE_DPFW_BF; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061896) + return OPCODE_MOV_N; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061897) + return OPCODE_AE_ABS16S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061898) + return OPCODE_AE_ABS24S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061899) + return OPCODE_AE_ABS32; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061900) + return OPCODE_AE_ABS32S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061901) + return OPCODE_AE_ABS64; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061902) + return OPCODE_AE_ABS64S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061903) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061904) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061905) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061906) + return OPCODE_AE_NEG16S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061907) + return OPCODE_AE_NEG24S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061908) + return OPCODE_AE_NEG32; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061909) + return OPCODE_AE_NEG32S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061910) + return OPCODE_AE_NEG64; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061911) + return OPCODE_AE_NEG64S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061912) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061913 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061913 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061913 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061913 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061914 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061914 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061914 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061914 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061915 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061915 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061915 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061915 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061916 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061916 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061916 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061916 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_get (insn) == 52) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_get (insn) == 12) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 2) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061917 && + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061918 && + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ALL4; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061918 && + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061918 && + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get (insn) == 1061918 && + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get (insn) == 2 && + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get (insn) == 1) + return OPCODE_ANY8; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_get (insn) == 939984) + return OPCODE_NOP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 148) + return OPCODE_ADD; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 149) + return OPCODE_ADDX2; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 150) + return OPCODE_ADDX4; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 151) + return OPCODE_ADDX8; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 152) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 153) + return OPCODE_AND; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 154) + return OPCODE_MAX; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 155) + return OPCODE_MAXU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 156) + return OPCODE_MIN; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 157) + return OPCODE_MINU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 158) + return OPCODE_MOVEQZ; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 159) + return OPCODE_MOVGEZ; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 160) + return OPCODE_MOVLTZ; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 161) + return OPCODE_MOVNEZ; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 162) + return OPCODE_OR; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 163) + return OPCODE_SRC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 164) + return OPCODE_SUB; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 165) + return OPCODE_SUBX2; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 166) + return OPCODE_SUBX4; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 167) + return OPCODE_SUBX8; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 168) + return OPCODE_XOR; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 169) + return OPCODE_CLAMPS; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 170) + return OPCODE_SEXT; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 171) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 172) + return OPCODE_AE_L16M_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 173) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 174) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 175) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 176) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 177) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 178) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 179) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 180) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 181) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 182) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 183) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 184) + return OPCODE_AE_L16_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 185) + return OPCODE_AE_L16_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 186) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 187) + return OPCODE_AE_L16_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 188) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 189) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 190) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 191) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 192) + return OPCODE_AE_L32M_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 193) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 194) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 195) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 196) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 197) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 198) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 199) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 200) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 201) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 202) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 203) + return OPCODE_AE_L32_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 204) + return OPCODE_AE_L32_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 205) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 206) + return OPCODE_AE_L32_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 207) + return OPCODE_AE_L64_X; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 208) + return OPCODE_AE_L64_XC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 209) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 210) + return OPCODE_AE_L64_XP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 211) + return OPCODE_AE_L16M_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 212) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 213) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 214) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 215) + return OPCODE_AE_L16_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 216) + return OPCODE_AE_L16_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 217) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 218) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 219) + return OPCODE_AE_L32M_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 220) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 221) + return OPCODE_AE_L32_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 222) + return OPCODE_AE_L32_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 223) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 224) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 225) + return OPCODE_SRLI; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 226 && + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 226 && + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 227 && + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 227 && + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 15) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 228 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 12) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 9) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 10) + return OPCODE_AE_NSA64; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 229 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 11) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get (insn) == 231 && + Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_get (insn) == 72) + return OPCODE_SLLI; + if (Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_get (insn) == 73) + return OPCODE_SRAI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get (insn) == 15 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 5) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58669) + return OPCODE_SSA8B; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58685) + return OPCODE_SSA8L; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58701) + return OPCODE_SSL; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58717) + return OPCODE_SSR; + if (Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get (insn) == 58733) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3680) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3681) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3682) + return OPCODE_MOV_N; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3683) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3684) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3685) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3686) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3687) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3688) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3689) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3690) + return OPCODE_AE_MOV; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3691) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get (insn) == 3692) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_get (insn) == 1832 && + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get (insn) == 13) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_get (insn) == 2493300) + return OPCODE_NOP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 452) + return OPCODE_ADD; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 453) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 454) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 455) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 456) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 457) + return OPCODE_AND; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 458) + return OPCODE_MAX; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 459) + return OPCODE_MAXU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 460) + return OPCODE_MIN; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 461) + return OPCODE_MINU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 462) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 463) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 464) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 465) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 466) + return OPCODE_OR; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 467) + return OPCODE_SUB; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 468) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 469) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 470) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 471) + return OPCODE_XOR; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 472) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 473) + return OPCODE_SEXT; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 474) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 475) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 476) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 477) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 478) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 479) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 480) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 481) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 482) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 483) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 484) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 485) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 486) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 487) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 488) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 489) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 490) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 491) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 492) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 493) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 494) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 495) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 496) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 497) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 498) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 499) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 500) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 501) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 502) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 503) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 504) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 505) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 506) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 507) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 508) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 509) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 510) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 511) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 512) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 513) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 514) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 515) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 516) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 517) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 518) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 519) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 520) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 521) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 522) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 523) + return OPCODE_AE_S32M_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 524) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 525) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 526) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 527) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 528) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 529) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 530) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 531) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 532) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 533) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 534) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 535) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 536) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 537) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 538) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 539) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 540) + return OPCODE_AE_S64_X; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 541) + return OPCODE_AE_S64_XC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 542) + return OPCODE_AE_S64_XP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 543) + return OPCODE_AE_SBI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 544) + return OPCODE_AE_VLDL16T; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 545) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 546) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 547) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 548) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 549) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 550) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 551) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 552) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 553) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 554) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 555) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 556) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 557) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 558) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 559) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 560) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 561) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 562) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 563) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 564) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 565) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 566) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 567) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 568) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 569) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 570) + return OPCODE_AE_S32M_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 571) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 572) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 573) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 574) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 575) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 576) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 577) + return OPCODE_SRLI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 578 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 578 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 579 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 579 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 592 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 592 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 593 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 593 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 594 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 594 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 595 && + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 595 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 596 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 596 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 596 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 597 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 597 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 597 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_SLL; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 598 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 599 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 600 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 600 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 600 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 16) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 601 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 601 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 602 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 602 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 603 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 603 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 604 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 604 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 605 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 605 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 606 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 606 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 607 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 607 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 608 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 609 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 609 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 609 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 609 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 610 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 610 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 610 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 610 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 611 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 611 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 611 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 611 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_NEG; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_SRA; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_SRL; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 15) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 13) + return OPCODE_AE_MOVAB; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 5) + return OPCODE_AE_MOVBA; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get (insn) == 31) + return OPCODE_AE_MOVB2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 1 && + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get (insn) == 31) + return OPCODE_AE_MOVB4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 14) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 11) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 10) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 9) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 7) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 616 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 6) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 617 && + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get (insn) == 617 && + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get (insn) == 0 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_get (insn) == 224) + return OPCODE_SLLI; + if (Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_get (insn) == 225) + return OPCODE_SRAI; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 145 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 145 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 145 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 145 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 146 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 146 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 146 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 146 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 147 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 147 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_S64_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 147 && + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_S64_IP; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 153 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get (insn) == 153 && + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 18) + return OPCODE_ADDI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 19) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 20) + return OPCODE_L16SI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 21) + return OPCODE_L16UI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 22) + return OPCODE_L32I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 23) + return OPCODE_L8UI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 24) + return OPCODE_S16I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 25) + return OPCODE_S32I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 26) + return OPCODE_S8I; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 27) + return OPCODE_MOVI; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 37 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 37 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 4) + return OPCODE_LOOPGTZ; + if (Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get (insn) == 37 && + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_LOOPNEZ; + if (Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_get (insn) == 8) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_get (insn) == 623309) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_get (insn) == 153857) + return OPCODE_AE_VLDL16C; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9729) + return OPCODE_AE_DB; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9731 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9731 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9731 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9731 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9733) + return OPCODE_AE_SB; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9735 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9735 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9735 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9735 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9737) + return OPCODE_MOV_N; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9739 && + Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_get (insn) == 12) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9739 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9739 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9739 && + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get (insn) == 2) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9741) + return OPCODE_AE_DBI; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9743 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 0) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9743 && + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVEA; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9874 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_VLDSHT; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9878 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_RUR_AE_BITPTR; + if (Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get (insn) == 9882 && + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get (insn) == 1) + return OPCODE_AE_MOVSARD7; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae3_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_get (insn) == 995350) + return OPCODE_NOP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 164) + return OPCODE_ADD; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 165) + return OPCODE_ADDX2; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 166) + return OPCODE_ADDX4; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 167) + return OPCODE_ADDX8; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 168) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 169) + return OPCODE_AE_LBK; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 170) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 171) + return OPCODE_AND; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 172) + return OPCODE_MAX; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 173) + return OPCODE_MAXU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 174) + return OPCODE_MIN; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 175) + return OPCODE_MINU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 176) + return OPCODE_MOVEQZ; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 177) + return OPCODE_MOVGEZ; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 178) + return OPCODE_MOVLTZ; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 179) + return OPCODE_MOVNEZ; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 180) + return OPCODE_OR; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 181) + return OPCODE_SRC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 182) + return OPCODE_SUB; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 183) + return OPCODE_SUBX2; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 184) + return OPCODE_SUBX4; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 185) + return OPCODE_SUBX8; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 186) + return OPCODE_XOR; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 187) + return OPCODE_AE_L16M_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 188) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 189) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 190) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 191) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 192) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 193) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 194) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 195) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 196) + return OPCODE_AE_L16_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 197) + return OPCODE_AE_L16_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 198) + return OPCODE_AE_L16_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 199) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 200) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 201) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 202) + return OPCODE_AE_L32M_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 203) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 204) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 205) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 206) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 207) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 208) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 209) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 210) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 211) + return OPCODE_AE_L32_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 212) + return OPCODE_AE_L32_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 213) + return OPCODE_AE_L32_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 214) + return OPCODE_AE_L64_X; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 215) + return OPCODE_AE_L64_XC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 216) + return OPCODE_AE_L64_XP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 217) + return OPCODE_CLAMPS; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 218) + return OPCODE_SEXT; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 219) + return OPCODE_AE_L16M_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 220) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 221) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 222) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 223) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 224) + return OPCODE_AE_L16_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 225) + return OPCODE_AE_L16_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 226) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 227) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 228) + return OPCODE_AE_L32M_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 229) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 230) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 231) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 232) + return OPCODE_AE_L32_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 233) + return OPCODE_AE_L32_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 234) + return OPCODE_AE_L64_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 235) + return OPCODE_AE_L64_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 236) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 237) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 238) + return OPCODE_SRLI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 239 && + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 239 && + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 240 && + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 240 && + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 15) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 13) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 12) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 11) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 9) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 241 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 242 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 242 && + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_LBI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_SSAI; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_SRA; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 5) + return OPCODE_SRL; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get (insn) == 243 && + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_AE_LB; + if (Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_get (insn) == 80) + return OPCODE_SLLI; + if (Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_get (insn) == 81) + return OPCODE_SRAI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get (insn) == 9) + return OPCODE_AE_SEL16I; + if (Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (insn) == 61954) + return OPCODE_SSA8B; + if (Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (insn) == 61955) + return OPCODE_SSA8L; + if (Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (insn) == 61970) + return OPCODE_SSL; + if (Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get (insn) == 61971) + return OPCODE_SSR; + if (Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get (insn) == 3904) + return OPCODE_MOV_N; + if (Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get (insn) == 3905 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 0) + return OPCODE_AE_MOVAE; + if (Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get (insn) == 3905 && + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get (insn) == 1) + return OPCODE_AE_MOVEA; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_get (insn) == 2601477) + return OPCODE_NOP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 452) + return OPCODE_ADD; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 453) + return OPCODE_ADDX2; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 454) + return OPCODE_ADDX4; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 455) + return OPCODE_ADDX8; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 456) + return OPCODE_AND; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 457) + return OPCODE_MAX; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 458) + return OPCODE_MAXU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 459) + return OPCODE_MIN; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 460) + return OPCODE_MINU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 461) + return OPCODE_MOVEQZ; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 462) + return OPCODE_MOVGEZ; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 463) + return OPCODE_MOVLTZ; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 464) + return OPCODE_MOVNEZ; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 465) + return OPCODE_OR; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 466) + return OPCODE_SUB; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 467) + return OPCODE_SUBX2; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 468) + return OPCODE_SUBX4; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 469) + return OPCODE_SUBX8; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 470) + return OPCODE_XOR; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 471) + return OPCODE_CLAMPS; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 472) + return OPCODE_SEXT; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 473) + return OPCODE_AE_L16M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 474) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 475) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 476) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 477) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 478) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 479) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 480) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 481) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 482) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 483) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 484) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 485) + return OPCODE_AE_L16_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 486) + return OPCODE_AE_L16_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 487) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 488) + return OPCODE_AE_L16_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 489) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 490) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 491) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 492) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 493) + return OPCODE_AE_L32M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 494) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 495) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 496) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 497) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 498) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 499) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 500) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 501) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 502) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 503) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 504) + return OPCODE_AE_L32_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 505) + return OPCODE_AE_L32_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 506) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 507) + return OPCODE_AE_L32_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 508) + return OPCODE_AE_L64_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 509) + return OPCODE_AE_L64_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 510) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 511) + return OPCODE_AE_L64_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 512) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 513) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 514) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 515) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 516) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 517) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 518) + return OPCODE_AE_S16X2M_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 519) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 520) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 521) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 522) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 523) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 524) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 525) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 526) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 527) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 528) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 529) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 530) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 531) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 532) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 533) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 534) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 535) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 536) + return OPCODE_AE_S32M_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 537) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 538) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 539) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 540) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 541) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 542) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 543) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 544) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 545) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 546) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 547) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 548) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 549) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 550) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 551) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 552) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 553) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 554) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 555) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 556) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 557) + return OPCODE_AE_S64_X; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 558) + return OPCODE_AE_S64_XC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 559) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 560) + return OPCODE_AE_S64_XP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 561) + return OPCODE_AE_L16M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 562) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 563) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 564) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 565) + return OPCODE_AE_L16_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 566) + return OPCODE_AE_L16_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 567) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 568) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 569) + return OPCODE_AE_L32M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 570) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 571) + return OPCODE_AE_L32_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 572) + return OPCODE_AE_L32_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 573) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 574) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 575) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 576) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 577) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 578) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 579) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 580) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 581) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 582) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 583) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 584) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 585) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 586) + return OPCODE_AE_S32M_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 587) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 588) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 589) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 590) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 591) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 592) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 593) + return OPCODE_SRLI; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 594) + return OPCODE_AE_ADD32; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 595) + return OPCODE_AE_ADD32S; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 604 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 604 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 604 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 604 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 608 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 608 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 609 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 609 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 610 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 610 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 611 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 611 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 612 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 612 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 613 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 613 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 614 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 614 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 615 && + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 615 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 616 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 616 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 616 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 617 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 617 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 617 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 618 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 618 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 618 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 619 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 619 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 619 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 620 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 620 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 620 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 621 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 621 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 621 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 622 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 622 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 622 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 623 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 623 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 623 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 624 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 624 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 624 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 624 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 625 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 625 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 625 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 625 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 626 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 626 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 626 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 626 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 627 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 627 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 627 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 627 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 628 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 628 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 628 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 628 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 629 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 629 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 629 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 629 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 630 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 630 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 630 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 630 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 12) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 13) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 14) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 15) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 631 && + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_SRA; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_SRL; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 10) + return OPCODE_AE_MOV; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 9) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 7) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 6) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 5) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get (insn) == 636 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_get (insn) == 224) + return OPCODE_SLLI; + if (Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_get (insn) == 225) + return OPCODE_SRAI; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 149 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 149 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 149 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 149 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 150 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_L64_IP; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 150 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 150 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 150 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 151 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 151 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_S64_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 151 && + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_AE_S64_IP; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 158 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get (insn) == 158 && + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 18) + return OPCODE_ADDI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 19) + return OPCODE_ADDMI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 20) + return OPCODE_L16SI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 21) + return OPCODE_L16UI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 22) + return OPCODE_L32I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 23) + return OPCODE_L8UI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 24) + return OPCODE_S16I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 25) + return OPCODE_S32I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 26) + return OPCODE_S8I; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 27) + return OPCODE_MOVI; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 38 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_LOOP; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 38 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 1) + return OPCODE_LOOPGTZ; + if (Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get (insn) == 38 && + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get (insn) == 2) + return OPCODE_LOOPNEZ; + if (Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_get (insn) == 8) + return OPCODE_EXTUI; + if (Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_L32R; + if (Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_get (insn) == 162364) + return OPCODE_AE_VLDL16C_IC1; + if (Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_get (insn) == 162365) + return OPCODE_AE_VLES16C_IC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40460) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40461) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40462) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40463) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40520) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40521) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40522) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40523) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40524) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40525) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40526) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40527) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40584) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40585) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40586) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40587) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40588) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40589) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40590) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40648 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 4) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get (insn) == 40648 && + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get (insn) == 0) + return OPCODE_AE_MOVALIGN; + if (Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get (insn) == 10114) + return OPCODE_MOV_N; + if (Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get (insn) == 10176 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_RUR_AE_BITPTR; + if (Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get (insn) == 10177 && + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get (insn) == 11) + return OPCODE_AE_MOVSARD7; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot0_20_0_Slot_ae_slot0_get (insn) == 1973269) + return OPCODE_NOP; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 210) + return OPCODE_ADD; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 211) + return OPCODE_ADDX2; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 212) + return OPCODE_ADDX4; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 213) + return OPCODE_ADDX8; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 214) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 215) + return OPCODE_AND; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 216 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LALIGN64_I; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 217 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SALIGN64_I; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 218 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_SLL; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 416) + return OPCODE_MAX; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 417) + return OPCODE_MAXU; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 418) + return OPCODE_MIN; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 419) + return OPCODE_MINU; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 420) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 421) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 422) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 423) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 424) + return OPCODE_OR; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 425) + return OPCODE_SRC; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 426) + return OPCODE_SUB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 427) + return OPCODE_SUBX2; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 428) + return OPCODE_SUBX4; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 429) + return OPCODE_SUBX8; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 430) + return OPCODE_XOR; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 431) + return OPCODE_MOVF; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 432) + return OPCODE_MOVT; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 433) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 434) + return OPCODE_SEXT; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 435) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 436) + return OPCODE_SRLI; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 437) + return OPCODE_ANDB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 438) + return OPCODE_ANDBC; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 439) + return OPCODE_ORB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 440) + return OPCODE_ORBC; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 441) + return OPCODE_XORB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 442 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA1X2; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_SRA; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_SRL; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_MOVAB4; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_MOVAB2; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_MOVAB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_MOVBA; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 42) + return OPCODE_AE_MOVASAR; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 480 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LB; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 481 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MOVBA4; + if (Field_fld_ae_slot0_20_12_Slot_ae_slot0_get (insn) == 481 && + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVBA2; + if (Field_fld_ae_slot0_20_13_Slot_ae_slot0_get (insn) == 104) + return OPCODE_SRAI; + if (Field_fld_ae_slot0_20_13_Slot_ae_slot0_get (insn) == 200 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 123) + return OPCODE_SSAI; + if (Field_fld_ae_slot0_20_14_Slot_ae_slot0_get (insn) == 111 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_DBI; + if (Field_fld_ae_slot0_20_14_Slot_ae_slot0_get (insn) == 116 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot0_20_15_Slot_ae_slot0_get (insn) == 27 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_SLLI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_TRUNCA32F64S_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_TRUNCA32X2F64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 5) + return OPCODE_L32I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 6) + return OPCODE_S16I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 7) + return OPCODE_S32I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRA64_32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SLAA32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SLAA16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SRAA16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SRAA16RS; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLAA32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SLAAQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SLAA64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SLAASQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_SLAA64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S16X2M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S16X2M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S16X2M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S16X4_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16M_L_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_S16M_L_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16M_L_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 16 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_S16M_L_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S16X4_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S16X4_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32F24_L_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32F24_L_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_S32F24_L_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S32F24_L_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S16_0_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S16_0_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S16_0_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S16_0_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32M_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S24RA64S_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_S24RA64S_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S24RA64S_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 17 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S24RA64S_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S32X2F24_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S32X2F24_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S32X2F24_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S32X2_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S32X2_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32M_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32M_XU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S32RA64S_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32RA64S_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32RA64S_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 18 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32_L_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S32_L_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32_L_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32_L_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S64_XC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S64_XC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S64_X; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 19 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S64_XP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_S16X2M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_S16X2M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S16M_L_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S16M_L_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32F24_L_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_S16_0_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_S16_0_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_S24RA64S_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S24RA64S_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 20 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S24X2RA64S_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32F24_L_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_S32_L_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_S32_L_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S32M_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S32M_IU; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_S32RA64S_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_S32RA64S_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_S32X2RA64S_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 21 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 22 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_MOVT64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_MOVF64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 23 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SRLA32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SRAA32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_SRAA32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SRAA32RS; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SRLAQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SRAAQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SRLA64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 24 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_SRAA64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 59) + return OPCODE_AE_S32X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 63) + return OPCODE_AE_S32X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_S64_I; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_S64_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 223) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 159) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 31) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 95) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 27) + return OPCODE_AE_LT16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 47) + return OPCODE_AE_LE16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get (insn) == 15) + return OPCODE_AE_EQ16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_8_4_Slot_ae_slot0_get (insn) == 11) + return OPCODE_AE_LT32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_8_4_Slot_ae_slot0_get (insn) == 23) + return OPCODE_AE_LE32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_8_4_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_EQ32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_AND; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 9) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 13) + return OPCODE_AE_OR; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 14) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_LT64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LE64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 25 && + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get (insn) == 12) + return OPCODE_AE_EQ64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 135) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 139) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 143) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 195) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 207) + return OPCODE_AE_S32X2F24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 199) + return OPCODE_AE_S32X2F24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 203) + return OPCODE_AE_S32X2F24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2F24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SA16X4_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA16X4_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 8 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 12 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 2 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA32X2F24_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SA24_L_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24_L_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 6 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 10 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 14 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_IP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIP; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIC; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 5 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA24X2_RIC1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get (insn) == 131) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 28 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_0_Slot_ae_slot0_get (insn) == 74) + return OPCODE_AE_MOVSARD7; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVTA32F24S_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVTA32F24S_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 10) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 8) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 199) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 197) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 135) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 72) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 129) + return OPCODE_AE_TRUNCA32Q48; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 194) + return OPCODE_AE_MOVAD32_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 192) + return OPCODE_AE_MOVAD32_H; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 130) + return OPCODE_AE_MOVAD16_3; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 128) + return OPCODE_AE_MOVAD16_2; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 66) + return OPCODE_AE_MOVAD16_1; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 64) + return OPCODE_AE_MOVAD16_0; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 67) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 131) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 7) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 134) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 195) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 69) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 196) + return OPCODE_AE_SRAS32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 193) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 70) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 133) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 5) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 6) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 71) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 198) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 132) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 68) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_NSA64; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_NSAZ16_0; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get (insn) == 65) + return OPCODE_AE_NSAZ32_L; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 29 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_OLT_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 4) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 13) + return OPCODE_MOVT_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 3) + return OPCODE_MOVF_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 4) + return OPCODE_MOVEQZ_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 11) + return OPCODE_MOVNEZ_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 7) + return OPCODE_MOVGEZ_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 9) + return OPCODE_MOVLTZ_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_TRUNC_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 0 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 1) + return OPCODE_UTRUNC_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 0) + return OPCODE_FLOAT_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get (insn) == 2) + return OPCODE_UFLOAT_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_OLE_S; + if (Field_fld_ae_slot0_20_16_Slot_ae_slot0_get (insn) == 31 && + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get (insn) == 15 && + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_OEQ_S; + if (Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (insn) == 102527) + return OPCODE_SSA8B; + if (Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (insn) == 102783) + return OPCODE_SSA8L; + if (Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (insn) == 103035) + return OPCODE_SSL; + if (Field_fld_ae_slot0_20_4_Slot_ae_slot0_get (insn) == 103039) + return OPCODE_SSR; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 3504 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA64_PP; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 3508 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA64NEG_FP; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 3512 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_SA64POS_FP; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7073) + return OPCODE_DPFW_B; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7075) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7077) + return OPCODE_MOV_N; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7079) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7081) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7083) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7085) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7087) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7088) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7089) + return OPCODE_DPFW_BF; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7090) + return OPCODE_DPFM_B; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7091) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7092) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7093) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7094) + return OPCODE_DPFM_BF; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7095) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7096) + return OPCODE_AE_DB; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7097) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7098) + return OPCODE_DPFR_B; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7099) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7100) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7101) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7102) + return OPCODE_DPFR_BF; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7103) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7104) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7108 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2NEG_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7108 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4NEG_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7108 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2NEG_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7120) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7124 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24X2POS_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7124 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24X2POS_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7124 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4NEG_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7136) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7140 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7140 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2NEG_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7140 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2NEG_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7152 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA24POS_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7152 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_LA24NEG_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7152 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA24POS_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7152 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA24NEG_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7156 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2POS_PC; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7156 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2POS_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7156 && + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4POS_PC1; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7696 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ALL4; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7700 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7704 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_0_0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ALL8; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7704 && + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get (insn) == 1 && + Field_fld_ae_slot0_0_0_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANY8; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7708 && + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get (insn) == 20) + return OPCODE_AE_ZALIGN64; + if (Field_fld_ae_slot0_20_8_Slot_ae_slot0_get (insn) == 7708 && + Field_fld_ae_slot0_5_2_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_MOVALIGN; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot1_19_0_Slot_ae_slot1_get (insn) == 988784) + return OPCODE_NOP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 148) + return OPCODE_ADD; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 149) + return OPCODE_ADDX2; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 150) + return OPCODE_ADDX4; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 151) + return OPCODE_ADDX8; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 152) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 153) + return OPCODE_AE_MOVDA32X2; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 154) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 155) + return OPCODE_AND; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 156) + return OPCODE_MAX; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 157) + return OPCODE_MAXU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 158) + return OPCODE_MIN; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 159) + return OPCODE_MINU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 160) + return OPCODE_MOVEQZ; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 161) + return OPCODE_MOVGEZ; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 162) + return OPCODE_MOVLTZ; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 163) + return OPCODE_MOVNEZ; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 164) + return OPCODE_OR; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 165) + return OPCODE_SRC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 166) + return OPCODE_SUB; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 167) + return OPCODE_SUBX2; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 168) + return OPCODE_SUBX4; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 169) + return OPCODE_SUBX8; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 170) + return OPCODE_XOR; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 171) + return OPCODE_AE_L16M_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 172) + return OPCODE_AE_L16M_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 173) + return OPCODE_AE_L16M_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 174) + return OPCODE_AE_L16M_XU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 175) + return OPCODE_AE_L16X2M_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 176) + return OPCODE_AE_L16X2M_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 177) + return OPCODE_AE_L16X2M_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 178) + return OPCODE_AE_L16X2M_XU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 179) + return OPCODE_AE_L16X4_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 180) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 181) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 182) + return OPCODE_AE_L16X4_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 183) + return OPCODE_AE_L16_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 184) + return OPCODE_AE_L16_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 185) + return OPCODE_AE_L16_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 186) + return OPCODE_AE_L16_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 187) + return OPCODE_AE_L32F24_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 188) + return OPCODE_AE_L32F24_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 189) + return OPCODE_AE_L32F24_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 190) + return OPCODE_AE_L32F24_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 191) + return OPCODE_AE_L32M_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 192) + return OPCODE_AE_L32M_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 193) + return OPCODE_AE_L32M_XU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 194) + return OPCODE_AE_L32X2F24_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 195) + return OPCODE_AE_L32X2F24_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 196) + return OPCODE_AE_L32X2F24_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 197) + return OPCODE_AE_L32X2F24_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 198) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 199) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 200) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 201) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 202) + return OPCODE_AE_L32_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 203) + return OPCODE_AE_L32_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 204) + return OPCODE_AE_L32_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 205) + return OPCODE_AE_L32_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 206) + return OPCODE_AE_L64_X; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 207) + return OPCODE_AE_L64_XC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 208) + return OPCODE_AE_L64_XC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 209) + return OPCODE_AE_L64_XP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 210) + return OPCODE_CLAMPS; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 211) + return OPCODE_SEXT; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 212) + return OPCODE_AE_L16M_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 213) + return OPCODE_AE_L16M_IU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 214) + return OPCODE_AE_L16X2M_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 215) + return OPCODE_AE_L16X2M_IU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 216) + return OPCODE_AE_L16_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 217) + return OPCODE_AE_L16_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 218) + return OPCODE_AE_L32F24_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 219) + return OPCODE_AE_L32F24_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 220) + return OPCODE_AE_L32M_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 221) + return OPCODE_AE_L32M_IU; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 222) + return OPCODE_AE_L32_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 223) + return OPCODE_AE_L32_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 224) + return OPCODE_AE_L8X4F_I; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 225) + return OPCODE_AE_L8X4F_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 226) + return OPCODE_SRLI; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 227 && + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 227 && + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 228 && + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RI; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 228 && + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 8) + return OPCODE_SLL; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_6_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L32X2F24_RIP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 14) + return OPCODE_AE_L32X2F24_RIC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 15) + return OPCODE_AE_L32X2F24_RIC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 13) + return OPCODE_AE_MOVDA32; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 12) + return OPCODE_AE_MOVDA16; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_6_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 11) + return OPCODE_AE_CVTQ56A32S; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 9) + return OPCODE_AE_CVT48A32; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 229 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 10) + return OPCODE_AE_CVT64A32; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 0) + return OPCODE_ABS; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 3) + return OPCODE_NEG; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 4) + return OPCODE_SRA; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 5) + return OPCODE_SRL; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_BITSWAP; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 230 && + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_LB; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 240 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 240 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 7) + return OPCODE_AE_L32X2_RIC1; + if (Field_fld_ae_slot1_19_12_Slot_ae_slot1_get (insn) == 241 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 6) + return OPCODE_AE_LBI; + if (Field_fld_ae_slot1_19_13_Slot_ae_slot1_get (insn) == 72) + return OPCODE_SLLI; + if (Field_fld_ae_slot1_19_13_Slot_ae_slot1_get (insn) == 73) + return OPCODE_SRAI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 2) + return OPCODE_ADDI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 3) + return OPCODE_ADDMI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 4) + return OPCODE_L16SI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 5) + return OPCODE_L16UI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 6) + return OPCODE_L32I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 7) + return OPCODE_L8UI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 8) + return OPCODE_MOVI; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_L32X2F24_I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_L64_I; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_L64_IP; + if (Field_fld_ae_slot1_19_16_Slot_ae_slot1_get (insn) == 15 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 5) + return OPCODE_AE_ADDICIRC; + if (Field_fld_ae_slot1_19_17_Slot_ae_slot1_get (insn) == 0) + return OPCODE_EXTUI; + if (Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (insn) == 61735) + return OPCODE_SSA8B; + if (Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (insn) == 61751) + return OPCODE_SSA8L; + if (Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (insn) == 61767) + return OPCODE_SSL; + if (Field_fld_ae_slot1_19_4_Slot_ae_slot1_get (insn) == 61783) + return OPCODE_SSR; + if (Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (insn) == 3696) + return OPCODE_AE_ADDCIRC_XC; + if (Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (insn) == 3697) + return OPCODE_AE_ADDCIRC_XC1; + if (Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (insn) == 3698) + return OPCODE_AE_MOVSARA7X2; + if (Field_fld_ae_slot1_19_8_Slot_ae_slot1_get (insn) == 3699) + return OPCODE_MOV_N; + if (Field_fld_ae_slot1_19_9_Slot_ae_slot1_get (insn) == 1928 && + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get (insn) == 7) + return OPCODE_SSAI; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae2_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_get (insn) == 18088096) + return OPCODE_NOP; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 256) + return OPCODE_AE_MUL16X4; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 257) + return OPCODE_AE_MULA16X4; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 258) + return OPCODE_AE_MULAF16X4SS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 259) + return OPCODE_AE_MULF16X4SS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 260) + return OPCODE_AE_MULS16X4; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 261) + return OPCODE_AE_MULSF16X4SS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 262 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 263 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 264 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 265 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 266 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 267 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 268 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 269 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 270 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 271 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 272 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 273 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULAC32; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 274 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULC32; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 275 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 276 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_MADD_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_MSUB_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 277 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_ADD_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 278 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 278 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 278 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 278 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 279 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 279 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 279 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 279 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 280 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_MUL_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 281 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_SUB_S; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 282 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 282 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 282 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 282 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 283 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 283 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 283 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 283 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 284 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 284 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 284 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 284 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 285 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 285 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 285 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 285 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 286 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 286 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 286 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 286 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 287 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 287 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 287 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get (insn) == 287 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULAFD32X16X2_FIR_HH; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAFD32X16X2_FIR_HL; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULAFD32X16X2_FIR_LH; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULAFD32X16X2_FIR_LL; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 4) + return OPCODE_AE_MULAFD32X2RA_FIR_H; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 5) + return OPCODE_AE_MULAFD32X2RA_FIR_L; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 6) + return OPCODE_AE_MULAFD32X2S_FIR_H; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 7) + return OPCODE_AE_MULAFD32X2S_FIR_L; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 8) + return OPCODE_AE_MULFD32X16X2_FIR_HH; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 9) + return OPCODE_AE_MULFD32X16X2_FIR_HL; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 10) + return OPCODE_AE_MULFD32X16X2_FIR_LH; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 11) + return OPCODE_AE_MULFD32X16X2_FIR_LL; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 12) + return OPCODE_AE_MULFD32X2RA_FIR_H; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 13) + return OPCODE_AE_MULFD32X2RA_FIR_L; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 14) + return OPCODE_AE_MULFD32X2S_FIR_H; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 15) + return OPCODE_AE_MULFD32X2S_FIR_L; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 17 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 17 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 0) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 17 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ32X16; + if (Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get (insn) == 17 && + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae4_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 4) + return OPCODE_BALL_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 5) + return OPCODE_BANY_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 6) + return OPCODE_BBC_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 7) + return OPCODE_BBS_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 8) + return OPCODE_BEQI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 9) + return OPCODE_BEQ_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 10) + return OPCODE_BGEI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 11) + return OPCODE_BGEUI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 12) + return OPCODE_BGEU_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 13) + return OPCODE_BGE_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 14) + return OPCODE_BLTI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 15) + return OPCODE_BLTUI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 16) + return OPCODE_BLTU_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 17) + return OPCODE_BLT_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 18) + return OPCODE_BNALL_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 19) + return OPCODE_BNEI_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 20) + return OPCODE_BNE_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 21) + return OPCODE_BNONE_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 22 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_BEQZ_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 22 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_BGEZ_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 22 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 2) + return OPCODE_BLTZ_W15; + if (Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get (insn) == 22 && + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get (insn) == 3) + return OPCODE_BNEZ_W15; + if (Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_BBCI_W15; + if (Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_get (insn) == 1) + return OPCODE_BBSI_W15; + if (Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_get (insn) == 23068680 && + Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae5_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_get (insn) == 1019904) + return OPCODE_NOP; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 0) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 1) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 2) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 3) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 4) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 5) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 6) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 7) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 8) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 9) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 10) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 11) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 12) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 13) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 14) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 15) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 16) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 17) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 18) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 19) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 20) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 21) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 22) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 23) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 24) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 25) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 26) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 27) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 28) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 29) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 30) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 31) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 32) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 33) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 34) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 35) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 36) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 37) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 38) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 39) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 40) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 41) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 42) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 43) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 44) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 45) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 46) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 47) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 48) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 49) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 50) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 51) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 52) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 53) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 54) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 55) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 56) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 57) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 58) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 59) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 60) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 61) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 62) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 63) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 64) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 65) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 66) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 67) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 68) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 69) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 70) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 71) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 72) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 73) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 74) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 75) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 76) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 77) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 78) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 79) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 80) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 81) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 82) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 83) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 84) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 85) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 86) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 87) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 88) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 89) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 90) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 91) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 92) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 93) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 94) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 95) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 96) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 97) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 98) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 99) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 100) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 101) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 102) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 103) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 104) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 105) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 106) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 107) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 108) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 109) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 110) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 111) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 112) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 113) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 114) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 115) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 116) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 117) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 118) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 119) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 120) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 121) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 122) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 123) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 124) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 125) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 126) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 127) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 128) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 129) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 130) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 131) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 132) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 133) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 134) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 135) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 136) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 137) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 138) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 139) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 140) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 141) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 142) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 143) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 144) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 145) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 146) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 147) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 148) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 149) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 150) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 151) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 152) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 153) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 154) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 155) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 156) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 157) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 158) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 159) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 160) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 161) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 162) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 163) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 164) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 165) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 166) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 167) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 168) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 169) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 170) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 171) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 172) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 173) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 174) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 175) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 176) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 177) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 178) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 179) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 180) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 181) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 182) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 183) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 184) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 185) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 186) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 187) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 188) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 189) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 190) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 191) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 192) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 193) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 194) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 195) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 196) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 197) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 198) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 199) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 200) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 201) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 202) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 203) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 204) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 205) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 206) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 207) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 208) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 209) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 210) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 211) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 212) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 213) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 214) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 215) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 216) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 217) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 218) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 219) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 220) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 221) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 222) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 223) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 224) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 225) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 226) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 227) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 228) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 229) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 230) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 231) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 232) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 233) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 234) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 235) + return OPCODE_AE_MULAC32; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 236) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 237) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 238) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 239) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 240) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 241) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 242) + return OPCODE_AE_MULC32; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 243) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 244) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 245) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 246) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 247) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 248) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 250) + return OPCODE_MSUB_S; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 251) + return OPCODE_MUL_S; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 252) + return OPCODE_SUB_S; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 253) + return OPCODE_MADD_S; + if (Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get (insn) == 254) + return OPCODE_ADD_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_get (insn) == 40960) + return OPCODE_NOP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_I; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_I; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 2) + return OPCODE_AE_S32X2RNG_I; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 3) + return OPCODE_AE_S32X2RNG_X; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 4) + return OPCODE_AE_S32X2RNG_XP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 5) + return OPCODE_AE_S32X2_I; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 6) + return OPCODE_AE_S32X2_X; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 7) + return OPCODE_AE_S32X2_XP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 8 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2F24_IP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 8 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S16X4_IP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 9 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 1) + return OPCODE_AE_S32X2_IP; + if (Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get (insn) == 9 && + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get (insn) == 0) + return OPCODE_AE_S32X2RNG_IP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_get (insn) == 28864) + return OPCODE_NOP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_ADDBRBA32; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_X; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 4) + return OPCODE_AE_L32X2_XP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 5 && + Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 2) + return OPCODE_AE_LA32X2F24_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 6 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 3) + return OPCODE_AE_LA32X2F24_RIP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 0) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get (insn) == 7 && + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_get (insn) == 450) + return OPCODE_AE_LA64_PP; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_get (insn) == 12289) + return OPCODE_NOP; + if (Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (insn) == 1) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (insn) == 2) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get (insn) == 3 && + Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_get (insn) == 0) + return OPCODE_AE_MUL32JS; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae6_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_get (insn) == 131072) + return OPCODE_NOP; + if (Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_get (insn) == 0) + return OPCODE_AE_ADDANDSUB32S; + if (Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_get (insn) == 1) + return OPCODE_AE_ADDANDSUBRNG32; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_get (insn) == 41104) + return OPCODE_NOP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 4) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 5) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 6) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 7 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 7 && + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 8 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_IC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 8 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA16X4_IC1; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 8 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA16X4_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 8 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA16X4_RIC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 9 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_IC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 9 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 2) + return OPCODE_AE_LA32X2_IC1; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 9 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 3) + return OPCODE_AE_LA32X2_IP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 9 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA16X4_RIP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 10 && + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get (insn) == 8) + return OPCODE_AE_L32X2_RIC; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 10 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 1) + return OPCODE_AE_LA32X2_RIP; + if (Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get (insn) == 10 && + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get (insn) == 0) + return OPCODE_AE_LA32X2_RIC; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_get (insn) == 32784) + return OPCODE_NOP; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_I; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L16X4_XC; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 2) + return OPCODE_AE_L16X4_XC1; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 3) + return OPCODE_AE_L32X2_I; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 4) + return OPCODE_AE_L32X2_XC; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 5) + return OPCODE_AE_L32X2_XC1; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 6) + return OPCODE_AE_L64_IP; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 7 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 1) + return OPCODE_AE_L32X2_IP; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 7 && + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L16X4_IP; + if (Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get (insn) == 8 && + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get (insn) == 0) + return OPCODE_AE_L32X2_RIC; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_get (insn) == 262144) + return OPCODE_NOP; + if (Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (insn) == 0) + return OPCODE_AE_MULAAAAFQ32X16; + if (Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16; + if (Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16; + if (Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ32X16; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae7_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_get (insn) == 262144) + return OPCODE_NOP; + if (Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (insn) == 0) + return OPCODE_AE_MULAAAAFQ32X16_S2; + if (Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (insn) == 1) + return OPCODE_AE_MULAAAAQ32X16_S2; + if (Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (insn) == 2) + return OPCODE_AE_MULZAAAAFQ32X16_S2; + if (Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get (insn) == 3) + return OPCODE_AE_MULZAAAAQ32X16_S2; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot2_20_0_Slot_ae_slot2_get (insn) == 1531921) + return OPCODE_NOP; + if (Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (insn) == 1484 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_SEXT72; + if (Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (insn) == 1488) + return OPCODE_AE_ADD72X64; + if (Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (insn) == 1489) + return OPCODE_AE_SUB72X64; + if (Field_fld_ae_slot2_20_10_Slot_ae_slot2_get (insn) == 1490) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 56) + return OPCODE_AE_MUL16_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 57) + return OPCODE_AE_MUL32U_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 58) + return OPCODE_AE_MUL32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 59) + return OPCODE_AE_MUL32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 60) + return OPCODE_AE_MUL32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 61) + return OPCODE_AE_MUL32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 62) + return OPCODE_AE_MUL32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 63) + return OPCODE_AE_MUL32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 64) + return OPCODE_AE_MUL32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 65) + return OPCODE_AE_MUL32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 66) + return OPCODE_AE_MUL32_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 67) + return OPCODE_AE_MUL32_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 68) + return OPCODE_AE_MUL32_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 69) + return OPCODE_AE_MULA16_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 70) + return OPCODE_AE_MULA32U_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 71) + return OPCODE_AE_MULA32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 72) + return OPCODE_AE_MULA32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 73) + return OPCODE_AE_MULA32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 74) + return OPCODE_AE_MULA32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 75) + return OPCODE_AE_MULA32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 76) + return OPCODE_AE_MULA32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 77) + return OPCODE_AE_MULA32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 78) + return OPCODE_AE_MULA32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 79) + return OPCODE_AE_MULA32_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 80) + return OPCODE_AE_MULA32_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 81) + return OPCODE_AE_MULA32_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 82) + return OPCODE_AE_MULAAAAQ16; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 83) + return OPCODE_AE_MULAAD32X16_H0_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 84) + return OPCODE_AE_MULAAD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 85) + return OPCODE_AE_MULAAD32X16_H2_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 86) + return OPCODE_AE_MULAAD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 87) + return OPCODE_AE_MULAAD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 88) + return OPCODE_AE_MULAAD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 89) + return OPCODE_AE_MULAAFD16SS_11_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 90) + return OPCODE_AE_MULAAFD16SS_13_02; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 91) + return OPCODE_AE_MULAAFD16SS_33_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 92) + return OPCODE_AE_MULAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 93) + return OPCODE_AE_MULAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 94) + return OPCODE_AE_MULAAFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 95) + return OPCODE_AE_MULAAFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 96) + return OPCODE_AE_MULAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 97) + return OPCODE_AE_MULAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 98) + return OPCODE_AE_MULAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 99) + return OPCODE_AE_MULAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 100) + return OPCODE_AE_MULAF16SS_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 101) + return OPCODE_AE_MULAF16SS_10; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 102) + return OPCODE_AE_MULAF16SS_11; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 103) + return OPCODE_AE_MULAF16SS_20; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 104) + return OPCODE_AE_MULAF16SS_21; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 105) + return OPCODE_AE_MULAF16SS_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 106) + return OPCODE_AE_MULAF16SS_30; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 107) + return OPCODE_AE_MULAF16SS_31; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 108) + return OPCODE_AE_MULAF16SS_32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 109) + return OPCODE_AE_MULAF16SS_33; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 110) + return OPCODE_AE_MULAF32RA_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 111) + return OPCODE_AE_MULAF32RA_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 112) + return OPCODE_AE_MULAF32RA_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 113) + return OPCODE_AE_MULAF32R_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 114) + return OPCODE_AE_MULAF32R_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 115) + return OPCODE_AE_MULAF32R_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 116) + return OPCODE_AE_MULAF32S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 117) + return OPCODE_AE_MULAF32S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 118) + return OPCODE_AE_MULAF32S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 119) + return OPCODE_AE_MULAF32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 120) + return OPCODE_AE_MULAF32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 121) + return OPCODE_AE_MULAF32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 122) + return OPCODE_AE_MULAF32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 123) + return OPCODE_AE_MULAF32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 124) + return OPCODE_AE_MULAF32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 125) + return OPCODE_AE_MULAF32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 126) + return OPCODE_AE_MULAF32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 127) + return OPCODE_AE_MULAF48Q32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 128) + return OPCODE_AE_MULAF48Q32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 129) + return OPCODE_AE_MULAFP24X2R; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 130) + return OPCODE_AE_MULAFP24X2RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 131) + return OPCODE_AE_MULAFP32X16X2RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 132) + return OPCODE_AE_MULAFP32X16X2RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 133) + return OPCODE_AE_MULAFP32X16X2RS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 134) + return OPCODE_AE_MULAFP32X16X2RS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 135) + return OPCODE_AE_MULAFP32X16X2S_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 136) + return OPCODE_AE_MULAFP32X16X2S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 137) + return OPCODE_AE_MULAFP32X2RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 138) + return OPCODE_AE_MULAFP32X2RS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 139) + return OPCODE_AE_MULAP32X16X2_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 140) + return OPCODE_AE_MULAP32X16X2_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 141) + return OPCODE_AE_MULAP32X2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 142) + return OPCODE_AE_MULAQ32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 143) + return OPCODE_AE_MULAQ32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 144) + return OPCODE_AE_MULAS32F48P16S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 145) + return OPCODE_AE_MULAS32F48P16S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 146) + return OPCODE_AE_MULAS32F48P16S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 147) + return OPCODE_AE_MULASD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 148) + return OPCODE_AE_MULASD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 149) + return OPCODE_AE_MULASD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 150) + return OPCODE_AE_MULASD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 151) + return OPCODE_AE_MULASFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 152) + return OPCODE_AE_MULASFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 153) + return OPCODE_AE_MULASFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 154) + return OPCODE_AE_MULASFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 155) + return OPCODE_AE_MULASFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 156) + return OPCODE_AE_MULASFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 157) + return OPCODE_AE_MULF16SS_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 158) + return OPCODE_AE_MULF16SS_10; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 159) + return OPCODE_AE_MULF16SS_11; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 160) + return OPCODE_AE_MULF16SS_20; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 161) + return OPCODE_AE_MULF16SS_21; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 162) + return OPCODE_AE_MULF16SS_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 163) + return OPCODE_AE_MULF16SS_30; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 164) + return OPCODE_AE_MULF16SS_31; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 165) + return OPCODE_AE_MULF16SS_32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 166) + return OPCODE_AE_MULF16SS_33; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 167) + return OPCODE_AE_MULF32RA_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 168) + return OPCODE_AE_MULF32RA_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 169) + return OPCODE_AE_MULF32RA_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 170) + return OPCODE_AE_MULF32R_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 171) + return OPCODE_AE_MULF32R_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 172) + return OPCODE_AE_MULF32R_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 173) + return OPCODE_AE_MULF32S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 174) + return OPCODE_AE_MULF32S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 175) + return OPCODE_AE_MULF32S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 176) + return OPCODE_AE_MULF32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 177) + return OPCODE_AE_MULF32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 178) + return OPCODE_AE_MULF32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 179) + return OPCODE_AE_MULF32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 180) + return OPCODE_AE_MULF32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 181) + return OPCODE_AE_MULF32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 182) + return OPCODE_AE_MULF32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 183) + return OPCODE_AE_MULF32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 184) + return OPCODE_AE_MULF48Q32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 185) + return OPCODE_AE_MULF48Q32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 186) + return OPCODE_AE_MULFP24X2R; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 187) + return OPCODE_AE_MULFP24X2RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 188) + return OPCODE_AE_MULFP32X16X2RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 189) + return OPCODE_AE_MULFP32X16X2RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 190) + return OPCODE_AE_MULFP32X16X2RS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 191) + return OPCODE_AE_MULFP32X16X2RS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 192) + return OPCODE_AE_MULFP32X16X2S_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 193) + return OPCODE_AE_MULFP32X16X2S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 194) + return OPCODE_AE_MULFP32X2RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 195) + return OPCODE_AE_MULFP32X2RS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 196) + return OPCODE_AE_MULP32X16X2_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 197) + return OPCODE_AE_MULP32X16X2_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 198) + return OPCODE_AE_MULP32X2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 199) + return OPCODE_AE_MULQ32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 200) + return OPCODE_AE_MULQ32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 201) + return OPCODE_AE_MULS32F48P16S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 202) + return OPCODE_AE_MULS32F48P16S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 203) + return OPCODE_AE_MULS32F48P16S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 204) + return OPCODE_AE_MULS32U_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 205) + return OPCODE_AE_MULS32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 206) + return OPCODE_AE_MULS32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 207) + return OPCODE_AE_MULS32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 208) + return OPCODE_AE_MULS32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 209) + return OPCODE_AE_MULS32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 210) + return OPCODE_AE_MULS32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 211) + return OPCODE_AE_MULS32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 212) + return OPCODE_AE_MULS32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 213) + return OPCODE_AE_MULS32_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 214) + return OPCODE_AE_MULS32_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 215) + return OPCODE_AE_MULS32_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 216) + return OPCODE_AE_MULSAD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 217) + return OPCODE_AE_MULSAD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 218) + return OPCODE_AE_MULSAD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 219) + return OPCODE_AE_MULSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 220) + return OPCODE_AE_MULSAFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 221) + return OPCODE_AE_MULSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 222) + return OPCODE_AE_MULSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 223) + return OPCODE_AE_MULSF16SS_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 224) + return OPCODE_AE_MULSF16SS_10; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 225) + return OPCODE_AE_MULSF16SS_11; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 226) + return OPCODE_AE_MULSF16SS_20; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 227) + return OPCODE_AE_MULSF16SS_21; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 228) + return OPCODE_AE_MULSF16SS_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 229) + return OPCODE_AE_MULSF16SS_30; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 230) + return OPCODE_AE_MULSF16SS_31; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 231) + return OPCODE_AE_MULSF16SS_32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 232) + return OPCODE_AE_MULSF16SS_33; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 233) + return OPCODE_AE_MULSF32RA_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 234) + return OPCODE_AE_MULSF32RA_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 235) + return OPCODE_AE_MULSF32RA_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 236) + return OPCODE_AE_MULSF32R_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 237) + return OPCODE_AE_MULSF32R_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 238) + return OPCODE_AE_MULSF32R_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 239) + return OPCODE_AE_MULSF32S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 240) + return OPCODE_AE_MULSF32S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 241) + return OPCODE_AE_MULSF32S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 242) + return OPCODE_AE_MULSF32X16_H0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 243) + return OPCODE_AE_MULSF32X16_H1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 244) + return OPCODE_AE_MULSF32X16_H2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 245) + return OPCODE_AE_MULSF32X16_H3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 246) + return OPCODE_AE_MULSF32X16_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 247) + return OPCODE_AE_MULSF32X16_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 248) + return OPCODE_AE_MULSF32X16_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 249) + return OPCODE_AE_MULSF32X16_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 250) + return OPCODE_AE_MULSF48Q32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 251) + return OPCODE_AE_MULSF48Q32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 252) + return OPCODE_AE_MULSFP24X2R; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 253) + return OPCODE_AE_MULSFP24X2RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 254) + return OPCODE_AE_MULSFP32X16X2RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 255) + return OPCODE_AE_MULSFP32X16X2RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 256) + return OPCODE_AE_MULSFP32X16X2RS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 257) + return OPCODE_AE_MULSFP32X16X2RS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 258) + return OPCODE_AE_MULSFP32X16X2S_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 259) + return OPCODE_AE_MULSFP32X16X2S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 260) + return OPCODE_AE_MULSFP32X2RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 261) + return OPCODE_AE_MULSFP32X2RS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 262) + return OPCODE_AE_MULSP32X16X2_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 263) + return OPCODE_AE_MULSP32X16X2_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 264) + return OPCODE_AE_MULSP32X2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 265) + return OPCODE_AE_MULSQ32SP16S_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 266) + return OPCODE_AE_MULSQ32SP16U_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 267) + return OPCODE_AE_MULSS32F48P16S_HH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 268) + return OPCODE_AE_MULSS32F48P16S_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 269) + return OPCODE_AE_MULSS32F48P16S_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 270) + return OPCODE_AE_MULSSD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 271) + return OPCODE_AE_MULSSD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 272) + return OPCODE_AE_MULSSD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 273) + return OPCODE_AE_MULSSD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 274) + return OPCODE_AE_MULSSFD16SS_11_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 275) + return OPCODE_AE_MULSSFD16SS_13_02; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 276) + return OPCODE_AE_MULSSFD16SS_33_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 277) + return OPCODE_AE_MULSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 278) + return OPCODE_AE_MULSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 279) + return OPCODE_AE_MULSSFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 280) + return OPCODE_AE_MULSSFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 281) + return OPCODE_AE_MULSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 282) + return OPCODE_AE_MULSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 283) + return OPCODE_AE_MULZAAAAQ16; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 284) + return OPCODE_AE_MULZAAD32X16_H0_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 285) + return OPCODE_AE_MULZAAD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 286) + return OPCODE_AE_MULZAAD32X16_H2_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 287) + return OPCODE_AE_MULZAAD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 288) + return OPCODE_AE_MULZAAD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 289) + return OPCODE_AE_MULZAAD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 290) + return OPCODE_AE_MULZAAFD16SS_11_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 291) + return OPCODE_AE_MULZAAFD16SS_13_02; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 292) + return OPCODE_AE_MULZAAFD16SS_33_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 293) + return OPCODE_AE_MULZAAFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 294) + return OPCODE_AE_MULZAAFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 295) + return OPCODE_AE_MULZAAFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 296) + return OPCODE_AE_MULZAAFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 297) + return OPCODE_AE_MULZAAFD32X16_H0_L1; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 298) + return OPCODE_AE_MULZAAFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 299) + return OPCODE_AE_MULZAAFD32X16_H2_L3; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 300) + return OPCODE_AE_MULZAAFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 301) + return OPCODE_AE_MULZASD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 302) + return OPCODE_AE_MULZASD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 303) + return OPCODE_AE_MULZASD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 304) + return OPCODE_AE_MULZASD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 305) + return OPCODE_AE_MULZASFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 306) + return OPCODE_AE_MULZASFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 307) + return OPCODE_AE_MULZASFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 308) + return OPCODE_AE_MULZASFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 309) + return OPCODE_AE_MULZASFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 310) + return OPCODE_AE_MULZASFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 311) + return OPCODE_AE_MULZSAD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 312) + return OPCODE_AE_MULZSAD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 313) + return OPCODE_AE_MULZSAD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 314) + return OPCODE_AE_MULZSAFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 315) + return OPCODE_AE_MULZSAFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 316) + return OPCODE_AE_MULZSAFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 317) + return OPCODE_AE_MULZSAFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 318) + return OPCODE_AE_MULZSSD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 319) + return OPCODE_AE_MULZSSD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 320) + return OPCODE_AE_MULZSSD32_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 321) + return OPCODE_AE_MULZSSD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 322) + return OPCODE_AE_MULZSSFD16SS_11_00; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 323) + return OPCODE_AE_MULZSSFD16SS_13_02; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 324) + return OPCODE_AE_MULZSSFD16SS_33_22; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 325) + return OPCODE_AE_MULZSSFD32RA_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 326) + return OPCODE_AE_MULZSSFD32RA_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 327) + return OPCODE_AE_MULZSSFD32S_HH_LL; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 328) + return OPCODE_AE_MULZSSFD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 329) + return OPCODE_AE_MULZSSFD32X16_H1_L0; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 330) + return OPCODE_AE_MULZSSFD32X16_H3_L2; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 331) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 332) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 333) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 334) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 335) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 336) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 337) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 338) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 339) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 340) + return OPCODE_AE_ADD72; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 341) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 342) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 343) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 344) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 345) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 346) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 347) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 348) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 349) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 350) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 351) + return OPCODE_AE_SUB72; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 352) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 353) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 354) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 355) + return OPCODE_AE_MULAC32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 356) + return OPCODE_AE_MULAC32X16_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 357) + return OPCODE_AE_MULAC32X16_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 358) + return OPCODE_AE_MULAFC24RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 359) + return OPCODE_AE_MULAFC32RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 360) + return OPCODE_AE_MULAFC32X16RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 361) + return OPCODE_AE_MULAFC32X16RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 362) + return OPCODE_AE_MULC32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 363) + return OPCODE_AE_MULC32X16_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 364) + return OPCODE_AE_MULC32X16_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 365) + return OPCODE_AE_MULFC24RA; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 366) + return OPCODE_AE_MULFC32RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 367) + return OPCODE_AE_MULFC32X16RAS_H; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 368) + return OPCODE_AE_MULFC32X16RAS_L; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 369) + return OPCODE_AE_MULFP16X4RAS; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 370) + return OPCODE_AE_MULFP16X4S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_2_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_PKSR32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_2_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_PKSR24; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_2_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_PKSRF32; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 15) + return OPCODE_MKDADJ_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 14) + return OPCODE_ADDEXP_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 371 && + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get (insn) == 13) + return OPCODE_ADDEXPM_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 373 && + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 374 && + Field_fld_ae_slot2_7_4_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 374 && + Field_fld_ae_slot2_7_0_Slot_ae_slot2_get (insn) == 16) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 374 && + Field_fld_ae_slot2_7_4_Slot_ae_slot2_get (insn) == 8) + return OPCODE_ABS_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 374 && + Field_fld_ae_slot2_7_4_Slot_ae_slot2_get (insn) == 9) + return OPCODE_NEG_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 375) + return OPCODE_MAX_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 376) + return OPCODE_MIN_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 377) + return OPCODE_ADD_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 378) + return OPCODE_MADDN_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 379) + return OPCODE_MADD_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 380) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 381) + return OPCODE_MUL_S; + if (Field_fld_ae_slot2_20_12_Slot_ae_slot2_get (insn) == 382) + return OPCODE_SUB_S; + if (Field_fld_ae_slot2_20_13_Slot_ae_slot2_get (insn) == 196) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 0) + return OPCODE_AE_MUL32EP_HH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 1) + return OPCODE_AE_MUL32USEP_LH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 2) + return OPCODE_AE_MUL32USEP_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 3) + return OPCODE_AE_MULA32EP_HH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 4) + return OPCODE_AE_MULA32USEP_LH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 5) + return OPCODE_AE_MULA32USEP_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 6) + return OPCODE_AE_MULAAD32EP_HH_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 7) + return OPCODE_AE_MULAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 8) + return OPCODE_AE_MULS32EP_HH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 9) + return OPCODE_AE_MULSSD32EP_HH_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 10) + return OPCODE_AE_MULZAAD32EP_HH_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 11) + return OPCODE_AE_MULZAAD32USEP_HL_LH; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 12) + return OPCODE_AE_MULZSSD32EP_HH_LL; + if (Field_fld_ae_slot2_20_14_Slot_ae_slot2_get (insn) == 13) + return OPCODE_AE_SEL16I_N; + if (Field_fld_ae_slot2_20_15_Slot_ae_slot2_get (insn) == 48) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot2_20_4_Slot_ae_slot2_get (insn) == 98160) + return OPCODE_AE_MOVFCRFSRV; + if (Field_fld_ae_slot2_20_4_Slot_ae_slot2_get (insn) == 98161) + return OPCODE_AE_MOVVFCRFSR; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5964) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5965) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5966) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5967) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5969) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5970) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5971) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5973) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5974) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5975) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5977) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5978) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5979) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5981) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5982) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 5983) + return OPCODE_CONJC_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6128) + return OPCODE_DIV0_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6129) + return OPCODE_MKSADJ_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6130) + return OPCODE_NEXP01_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6131) + return OPCODE_RECIP0_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6132) + return OPCODE_RSQRT0_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6133) + return OPCODE_SQRT0_S; + if (Field_fld_ae_slot2_20_8_Slot_ae_slot2_get (insn) == 6134) + return OPCODE_CONST_S; + return XTENSA_UNDEFINED; +} + +static int +Slot_ae_slot3_decode (const xtensa_insnbuf insn) +{ + if (Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (insn) == 461585) + return OPCODE_AE_CALCRNG1; + if (Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (insn) == 461589) + return OPCODE_AE_CALCRNG2; + if (Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (insn) == 461593) + return OPCODE_AE_CALCRNG3; + if (Field_fld_ae_slot3_20_0_Slot_ae_slot3_get (insn) == 461597) + return OPCODE_NOP; + if (Field_fld_ae_slot3_20_10_Slot_ae_slot3_get (insn) == 1752) + return OPCODE_AE_MOVI; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 97) + return OPCODE_AE_MUL32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 101) + return OPCODE_AE_MUL32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 105) + return OPCODE_AE_MUL32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 109) + return OPCODE_AE_MUL32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 110) + return OPCODE_AE_MUL16_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 111) + return OPCODE_AE_MUL32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 116) + return OPCODE_AE_MUL32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 117) + return OPCODE_AE_MUL32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 118) + return OPCODE_AE_MUL32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 119) + return OPCODE_AE_MUL32_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 120) + return OPCODE_AE_MUL32_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 121) + return OPCODE_AE_MUL32_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 122) + return OPCODE_AE_MULA16_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 123) + return OPCODE_AE_MULA32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 124) + return OPCODE_AE_MULA32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 125) + return OPCODE_AE_MULA32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 126) + return OPCODE_AE_MULA32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 127) + return OPCODE_AE_MULA32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 128) + return OPCODE_AE_MULA32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 129) + return OPCODE_AE_MULA32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 130) + return OPCODE_AE_MULA32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 131) + return OPCODE_AE_MULA32_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 132) + return OPCODE_AE_MULA32_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 133) + return OPCODE_AE_MULA32_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 134) + return OPCODE_AE_MULAAAAQ16_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 135) + return OPCODE_AE_MULAAD32X16_H0_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 136) + return OPCODE_AE_MULAAD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 137) + return OPCODE_AE_MULAAD32X16_H2_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 138) + return OPCODE_AE_MULAAD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 139) + return OPCODE_AE_MULAAD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 140) + return OPCODE_AE_MULAAD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 141) + return OPCODE_AE_MULAAFD16SS_11_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 142) + return OPCODE_AE_MULAAFD16SS_13_02_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 143) + return OPCODE_AE_MULAAFD16SS_33_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 144) + return OPCODE_AE_MULAAFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 145) + return OPCODE_AE_MULAAFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 146) + return OPCODE_AE_MULAAFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 147) + return OPCODE_AE_MULAAFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 148) + return OPCODE_AE_MULAAFD32X16_H0_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 149) + return OPCODE_AE_MULAAFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 150) + return OPCODE_AE_MULAAFD32X16_H2_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 151) + return OPCODE_AE_MULAAFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 152) + return OPCODE_AE_MULAF16SS_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 153) + return OPCODE_AE_MULAF16SS_10_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 154) + return OPCODE_AE_MULAF16SS_11_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 155) + return OPCODE_AE_MULAF16SS_20_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 156) + return OPCODE_AE_MULAF16SS_21_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 157) + return OPCODE_AE_MULAF16SS_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 158) + return OPCODE_AE_MULAF16SS_30_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 159) + return OPCODE_AE_MULAF16SS_31_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 160) + return OPCODE_AE_MULAF16SS_32_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 161) + return OPCODE_AE_MULAF16SS_33_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 162) + return OPCODE_AE_MULAF32RA_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 163) + return OPCODE_AE_MULAF32RA_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 164) + return OPCODE_AE_MULAF32RA_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 165) + return OPCODE_AE_MULAF32R_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 166) + return OPCODE_AE_MULAF32R_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 167) + return OPCODE_AE_MULAF32R_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 168) + return OPCODE_AE_MULAF32S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 169) + return OPCODE_AE_MULAF32S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 170) + return OPCODE_AE_MULAF32S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 171) + return OPCODE_AE_MULAF32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 172) + return OPCODE_AE_MULAF32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 173) + return OPCODE_AE_MULAF32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 174) + return OPCODE_AE_MULAF32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 175) + return OPCODE_AE_MULAF32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 176) + return OPCODE_AE_MULAF32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 177) + return OPCODE_AE_MULAF32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 178) + return OPCODE_AE_MULAF32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 179) + return OPCODE_AE_MULAF48Q32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 180) + return OPCODE_AE_MULAF48Q32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 181) + return OPCODE_AE_MULAFP24X2RA_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 182) + return OPCODE_AE_MULAFP24X2R_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 183) + return OPCODE_AE_MULAFP32X16X2RAS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 184) + return OPCODE_AE_MULAFP32X16X2RAS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 185) + return OPCODE_AE_MULAFP32X16X2RS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 186) + return OPCODE_AE_MULAFP32X16X2RS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 187) + return OPCODE_AE_MULAFP32X16X2S_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 188) + return OPCODE_AE_MULAFP32X16X2S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 189) + return OPCODE_AE_MULAFP32X2RAS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 190) + return OPCODE_AE_MULAFP32X2RS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 191) + return OPCODE_AE_MULAP32X16X2_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 192) + return OPCODE_AE_MULAP32X16X2_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 193) + return OPCODE_AE_MULAP32X2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 194) + return OPCODE_AE_MULAQ32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 195) + return OPCODE_AE_MULAQ32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 196) + return OPCODE_AE_MULAS32F48P16S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 197) + return OPCODE_AE_MULAS32F48P16S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 198) + return OPCODE_AE_MULAS32F48P16S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 199) + return OPCODE_AE_MULASD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 200) + return OPCODE_AE_MULASD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 201) + return OPCODE_AE_MULASD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 202) + return OPCODE_AE_MULASD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 203) + return OPCODE_AE_MULASFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 204) + return OPCODE_AE_MULASFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 205) + return OPCODE_AE_MULASFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 206) + return OPCODE_AE_MULASFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 207) + return OPCODE_AE_MULASFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 208) + return OPCODE_AE_MULASFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 209) + return OPCODE_AE_MULF16SS_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 210) + return OPCODE_AE_MULF16SS_10_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 211) + return OPCODE_AE_MULF16SS_11_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 212) + return OPCODE_AE_MULF16SS_20_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 213) + return OPCODE_AE_MULF16SS_21_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 214) + return OPCODE_AE_MULF16SS_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 215) + return OPCODE_AE_MULF16SS_30_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 216) + return OPCODE_AE_MULF16SS_31_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 217) + return OPCODE_AE_MULF16SS_32_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 218) + return OPCODE_AE_MULF16SS_33_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 219) + return OPCODE_AE_MULF32RA_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 220) + return OPCODE_AE_MULF32RA_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 221) + return OPCODE_AE_MULF32RA_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 222) + return OPCODE_AE_MULF32R_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 223) + return OPCODE_AE_MULF32R_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 224) + return OPCODE_AE_MULF32R_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 225) + return OPCODE_AE_MULF32S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 226) + return OPCODE_AE_MULF32S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 227) + return OPCODE_AE_MULF32S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 228) + return OPCODE_AE_MULF32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 229) + return OPCODE_AE_MULF32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 230) + return OPCODE_AE_MULF32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 231) + return OPCODE_AE_MULF32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 232) + return OPCODE_AE_MULF32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 233) + return OPCODE_AE_MULF32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 234) + return OPCODE_AE_MULF32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 235) + return OPCODE_AE_MULF32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 236) + return OPCODE_AE_MULF48Q32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 237) + return OPCODE_AE_MULF48Q32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 238) + return OPCODE_AE_MULFP24X2RA_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 239) + return OPCODE_AE_MULFP24X2R_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 240) + return OPCODE_AE_MULFP32X16X2RAS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 241) + return OPCODE_AE_MULFP32X16X2RAS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 242) + return OPCODE_AE_MULFP32X16X2RS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 243) + return OPCODE_AE_MULFP32X16X2RS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 244) + return OPCODE_AE_MULFP32X16X2S_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 245) + return OPCODE_AE_MULFP32X16X2S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 246) + return OPCODE_AE_MULFP32X2RAS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 247) + return OPCODE_AE_MULFP32X2RS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 248) + return OPCODE_AE_MULP32X16X2_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 249) + return OPCODE_AE_MULP32X16X2_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 250) + return OPCODE_AE_MULP32X2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 251) + return OPCODE_AE_MULQ32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 252) + return OPCODE_AE_MULQ32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 253) + return OPCODE_AE_MULS32F48P16S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 254) + return OPCODE_AE_MULS32F48P16S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 255) + return OPCODE_AE_MULS32F48P16S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 256) + return OPCODE_AE_MULS32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 257) + return OPCODE_AE_MULS32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 258) + return OPCODE_AE_MULS32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 259) + return OPCODE_AE_MULS32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 260) + return OPCODE_AE_MULS32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 261) + return OPCODE_AE_MULS32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 262) + return OPCODE_AE_MULS32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 263) + return OPCODE_AE_MULS32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 264) + return OPCODE_AE_MULS32_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 265) + return OPCODE_AE_MULS32_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 266) + return OPCODE_AE_MULS32_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 267) + return OPCODE_AE_MULSAD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 268) + return OPCODE_AE_MULSAD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 269) + return OPCODE_AE_MULSAD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 270) + return OPCODE_AE_MULSAFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 271) + return OPCODE_AE_MULSAFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 272) + return OPCODE_AE_MULSAFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 273) + return OPCODE_AE_MULSAFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 274) + return OPCODE_AE_MULSF16SS_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 275) + return OPCODE_AE_MULSF16SS_10_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 276) + return OPCODE_AE_MULSF16SS_11_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 277) + return OPCODE_AE_MULSF16SS_20_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 278) + return OPCODE_AE_MULSF16SS_21_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 279) + return OPCODE_AE_MULSF16SS_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 280) + return OPCODE_AE_MULSF16SS_30_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 281) + return OPCODE_AE_MULSF16SS_31_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 282) + return OPCODE_AE_MULSF16SS_32_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 283) + return OPCODE_AE_MULSF16SS_33_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 284) + return OPCODE_AE_MULSF32RA_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 285) + return OPCODE_AE_MULSF32RA_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 286) + return OPCODE_AE_MULSF32RA_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 287) + return OPCODE_AE_MULSF32R_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 288) + return OPCODE_AE_MULSF32R_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 289) + return OPCODE_AE_MULSF32R_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 290) + return OPCODE_AE_MULSF32S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 291) + return OPCODE_AE_MULSF32S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 292) + return OPCODE_AE_MULSF32S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 293) + return OPCODE_AE_MULSF32X16_H0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 294) + return OPCODE_AE_MULSF32X16_H1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 295) + return OPCODE_AE_MULSF32X16_H2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 296) + return OPCODE_AE_MULSF32X16_H3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 297) + return OPCODE_AE_MULSF32X16_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 298) + return OPCODE_AE_MULSF32X16_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 299) + return OPCODE_AE_MULSF32X16_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 300) + return OPCODE_AE_MULSF32X16_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 301) + return OPCODE_AE_MULSF48Q32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 302) + return OPCODE_AE_MULSF48Q32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 303) + return OPCODE_AE_MULSFP24X2RA_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 304) + return OPCODE_AE_MULSFP24X2R_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 305) + return OPCODE_AE_MULSFP32X16X2RAS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 306) + return OPCODE_AE_MULSFP32X16X2RAS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 307) + return OPCODE_AE_MULSFP32X16X2RS_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 308) + return OPCODE_AE_MULSFP32X16X2RS_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 309) + return OPCODE_AE_MULSFP32X16X2S_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 310) + return OPCODE_AE_MULSFP32X16X2S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 311) + return OPCODE_AE_MULSFP32X2RAS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 312) + return OPCODE_AE_MULSFP32X2RS_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 313) + return OPCODE_AE_MULSP32X16X2_H_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 314) + return OPCODE_AE_MULSP32X16X2_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 315) + return OPCODE_AE_MULSP32X2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 316) + return OPCODE_AE_MULSQ32SP16S_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 317) + return OPCODE_AE_MULSQ32SP16U_L_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 318) + return OPCODE_AE_MULSS32F48P16S_HH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 319) + return OPCODE_AE_MULSS32F48P16S_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 320) + return OPCODE_AE_MULSS32F48P16S_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 321) + return OPCODE_AE_MULSSD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 322) + return OPCODE_AE_MULSSD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 323) + return OPCODE_AE_MULSSD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 324) + return OPCODE_AE_MULSSD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 325) + return OPCODE_AE_MULSSFD16SS_11_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 326) + return OPCODE_AE_MULSSFD16SS_13_02_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 327) + return OPCODE_AE_MULSSFD16SS_33_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 328) + return OPCODE_AE_MULSSFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 329) + return OPCODE_AE_MULSSFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 330) + return OPCODE_AE_MULSSFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 331) + return OPCODE_AE_MULSSFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 332) + return OPCODE_AE_MULSSFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 333) + return OPCODE_AE_MULSSFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 334) + return OPCODE_AE_MULZAAAAQ16_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 335) + return OPCODE_AE_MULZAAD32X16_H0_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 336) + return OPCODE_AE_MULZAAD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 337) + return OPCODE_AE_MULZAAD32X16_H2_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 338) + return OPCODE_AE_MULZAAD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 339) + return OPCODE_AE_MULZAAD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 340) + return OPCODE_AE_MULZAAD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 341) + return OPCODE_AE_MULZAAFD16SS_11_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 342) + return OPCODE_AE_MULZAAFD16SS_13_02_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 343) + return OPCODE_AE_MULZAAFD16SS_33_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 344) + return OPCODE_AE_MULZAAFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 345) + return OPCODE_AE_MULZAAFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 346) + return OPCODE_AE_MULZAAFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 347) + return OPCODE_AE_MULZAAFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 348) + return OPCODE_AE_MULZAAFD32X16_H0_L1_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 349) + return OPCODE_AE_MULZAAFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 350) + return OPCODE_AE_MULZAAFD32X16_H2_L3_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 351) + return OPCODE_AE_MULZAAFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 352) + return OPCODE_AE_MULZASD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 353) + return OPCODE_AE_MULZASD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 354) + return OPCODE_AE_MULZASD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 355) + return OPCODE_AE_MULZASD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 356) + return OPCODE_AE_MULZASFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 357) + return OPCODE_AE_MULZASFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 358) + return OPCODE_AE_MULZASFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 359) + return OPCODE_AE_MULZASFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 360) + return OPCODE_AE_MULZASFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 361) + return OPCODE_AE_MULZASFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 362) + return OPCODE_AE_MULZSAD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 363) + return OPCODE_AE_MULZSAD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 364) + return OPCODE_AE_MULZSAD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 365) + return OPCODE_AE_MULZSAFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 366) + return OPCODE_AE_MULZSAFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 367) + return OPCODE_AE_MULZSAFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 368) + return OPCODE_AE_MULZSAFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 369) + return OPCODE_AE_MULZSSD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 370) + return OPCODE_AE_MULZSSD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 371) + return OPCODE_AE_MULZSSD32_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 372) + return OPCODE_AE_MULZSSD32_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 373) + return OPCODE_AE_MULZSSFD16SS_11_00_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 374) + return OPCODE_AE_MULZSSFD16SS_13_02_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 375) + return OPCODE_AE_MULZSSFD16SS_33_22_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 376) + return OPCODE_AE_MULZSSFD32RA_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 377) + return OPCODE_AE_MULZSSFD32RA_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 378) + return OPCODE_AE_MULZSSFD32S_HH_LL_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 379) + return OPCODE_AE_MULZSSFD32S_HL_LH_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 380) + return OPCODE_AE_MULZSSFD32X16_H1_L0_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 381) + return OPCODE_AE_MULZSSFD32X16_H3_L2_S2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 382) + return OPCODE_AE_ADD16; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 383) + return OPCODE_AE_ADD16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 384) + return OPCODE_AE_ADD24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 385) + return OPCODE_AE_ADD32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 386) + return OPCODE_AE_ADD32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 387) + return OPCODE_AE_ADD32S_HL_LH; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 388) + return OPCODE_AE_ADD32_HL_LH; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 389) + return OPCODE_AE_ADD64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 390) + return OPCODE_AE_ADD64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 391) + return OPCODE_AE_ADDRNG32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 392) + return OPCODE_AE_ADDSQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 393) + return OPCODE_AE_ADDSUB32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 394) + return OPCODE_AE_ADDSUB32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 395) + return OPCODE_AE_MAX32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 396) + return OPCODE_AE_MAX64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 397) + return OPCODE_AE_MAXABS32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 398) + return OPCODE_AE_MAXABS64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 399) + return OPCODE_AE_MIN32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 400) + return OPCODE_AE_MIN64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 401) + return OPCODE_AE_MINABS32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 402) + return OPCODE_AE_MINABS64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 403) + return OPCODE_AE_ROUND16X4F32SASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 404) + return OPCODE_AE_ROUND16X4F32SSYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 405) + return OPCODE_AE_ROUND24X2F48SASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 406) + return OPCODE_AE_ROUND24X2F48SSYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 407) + return OPCODE_AE_ROUND32X2F48SASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 408) + return OPCODE_AE_ROUND32X2F48SSYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 409) + return OPCODE_AE_ROUND32X2F64SASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 410) + return OPCODE_AE_ROUND32X2F64SSYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 411) + return OPCODE_AE_ROUNDSP16Q48X2ASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 412) + return OPCODE_AE_ROUNDSP16Q48X2SYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 413) + return OPCODE_AE_SAT16X4; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 414) + return OPCODE_AE_SUB16; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 415) + return OPCODE_AE_SUB16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 416) + return OPCODE_AE_SUB24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 417) + return OPCODE_AE_SUB32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 418) + return OPCODE_AE_SUB32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 419) + return OPCODE_AE_SUB64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 420) + return OPCODE_AE_SUB64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 421) + return OPCODE_AE_SUBADD32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 422) + return OPCODE_AE_SUBADD32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 423) + return OPCODE_AE_SUBRNG32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 424) + return OPCODE_AE_SUBSQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 425) + return OPCODE_AE_SLAI16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 426) + return OPCODE_AE_SRAI16; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 427) + return OPCODE_AE_SRAI16R; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 428) + return OPCODE_AE_AND; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 429) + return OPCODE_AE_NAND; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 430) + return OPCODE_AE_OR; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 431) + return OPCODE_AE_SEXT32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 432) + return OPCODE_AE_TRUNCP24Q48X2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 433) + return OPCODE_AE_XOR; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 434) + return OPCODE_AE_MOVF64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 435) + return OPCODE_AE_MOVT64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 436 && + Field_fld_ae_slot3_0_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MOVT32X2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 436 && + Field_fld_ae_slot3_0_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MOVF32X2; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 437 && + Field_fld_ae_slot3_1_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MOVT16X4; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 437 && + Field_fld_ae_slot3_1_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_MOVF16X4; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_TRUNCP16; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_CVTQ56P32S_L; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_CVTQ56P32S_H; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_CVT64F32_H; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_CVT48F32_L; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_CVT48F32_H; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 7) + return OPCODE_AE_SAT48S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_SATQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 6) + return OPCODE_AE_SAT24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_TRUNCQ32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 5) + return OPCODE_AE_ROUNDSQ32F48SYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 4) + return OPCODE_AE_ROUNDSQ32F48ASYM; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_NEG32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_NEG64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_NEGSQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 439 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_NEG64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 440 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_ABS16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 440 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_ABS64; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 440 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_ABS64S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 441 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_ABS24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 441 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_ABSSQ56S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 441 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_DIV64D32_H; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 442 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_ABS32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 442 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_NEG16S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 442 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_DIV64D32_L; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 443 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_NEG32; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 443 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_NEG24S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 443 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_ABS32S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 444) + return OPCODE_ADD_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 445) + return OPCODE_MADD_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 446) + return OPCODE_MSUBN_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 447) + return OPCODE_MSUB_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 480) + return OPCODE_MUL_S; + if (Field_fld_ae_slot3_20_12_Slot_ae_slot3_get (insn) == 481) + return OPCODE_SUB_S; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 34) + return OPCODE_AE_SLAI24; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 35) + return OPCODE_AE_SLAI24S; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 36) + return OPCODE_AE_SLAI32; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 37) + return OPCODE_AE_SLAI32S; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 38) + return OPCODE_AE_SRAI24; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 39) + return OPCODE_AE_SRAI32; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 49) + return OPCODE_AE_SRAI32R; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 51) + return OPCODE_AE_SRLI24; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 53) + return OPCODE_AE_SRLI32; + if (Field_fld_ae_slot3_20_13_Slot_ae_slot3_get (insn) == 241) + return OPCODE_MULMUX_S; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 8) + return OPCODE_AE_MUL32EP_HH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 9) + return OPCODE_AE_MULA32EP_HH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 10) + return OPCODE_AE_MULAAD32EP_HH_LL_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 11) + return OPCODE_AE_MULAAD32USEP_HL_LH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 12) + return OPCODE_AE_MULS32EP_HH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 13) + return OPCODE_AE_MULSSD32EP_HH_LL_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 14) + return OPCODE_AE_MULZAAD32EP_HH_LL_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 15) + return OPCODE_AE_MULZAAD32USEP_HL_LH_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 16) + return OPCODE_AE_MULZSSD32EP_HH_LL_S2; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 28 && + Field_fld_ae_slot3_11_4_Slot_ae_slot3_get (insn) == 176 && + Field_fld_ae_slot3_1_0_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_MOVEEP; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 28 && + Field_fld_ae_slot3_11_11_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SLAI72; + if (Field_fld_ae_slot3_20_14_Slot_ae_slot3_get (insn) == 110 && + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SAT64S; + if (Field_fld_ae_slot3_20_15_Slot_ae_slot3_get (insn) == 58) + return OPCODE_MADDMUX_S; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SRAI72; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_SEL16I; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SLAI64; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 3) + return OPCODE_AE_SRAI64; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 2) + return OPCODE_AE_SLAISQ56S; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 5 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 1) + return OPCODE_AE_SLAI64S; + if (Field_fld_ae_slot3_20_16_Slot_ae_slot3_get (insn) == 6 && + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_SRLI64; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1800) + return OPCODE_AE_SRAS64; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1801) + return OPCODE_AE_SRLS64; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1802) + return OPCODE_AE_MOV; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1803 && + Field_fld_ae_slot3_3_0_Slot_ae_slot3_get (insn) == 0) + return OPCODE_AE_RNG32X2; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1804) + return OPCODE_NEG_S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1816) + return OPCODE_AE_SRASQ56; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1817) + return OPCODE_AE_SRLSQ56; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1818) + return OPCODE_AE_SEXT32X2D16_10; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1832) + return OPCODE_AE_SRLS24; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1833) + return OPCODE_AE_CVT32X2F16_10; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1834) + return OPCODE_AE_SEXT32X2D16_32; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1848) + return OPCODE_AE_SRLS32; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1849) + return OPCODE_AE_CVT32X2F16_32; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 1850) + return OPCODE_AE_SHORTSWAP; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7012) + return OPCODE_AE_ROUNDSP16F24ASYM; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7013) + return OPCODE_AE_ROUNDSP16F24SYM; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7014) + return OPCODE_AE_SLAS24; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7015) + return OPCODE_AE_SLAS24S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7016) + return OPCODE_AE_SLAS32; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7017) + return OPCODE_AE_SLAS32S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7018) + return OPCODE_AE_SLAS64; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7019) + return OPCODE_AE_SLAS64S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7020) + return OPCODE_AE_SLASQ56; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7021) + return OPCODE_AE_SLASSQ56S; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7022) + return OPCODE_AE_SRAS24; + if (Field_fld_ae_slot3_20_8_Slot_ae_slot3_get (insn) == 7023) + return OPCODE_AE_SRAS32; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_ae_format88_Format_ae_slot3_32_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[1] & 0xf); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c0000) >> 18) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0x18000000) >> 27) << 12); + slotbuf[0] = (slotbuf[0] & ~0x1fc000) | (((insn[2] & 0xfe0000) >> 17) << 14); +} + +static void +Slot_ae_format88_Format_ae_slot3_32_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf) | (slotbuf[0] & 0xf); + insn[1] = (insn[1] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[1] = (insn[1] & ~0x3c0000) | (((slotbuf[0] & 0xf00) >> 8) << 18); + insn[1] = (insn[1] & ~0x18000000) | (((slotbuf[0] & 0x3000) >> 12) << 27); + insn[2] = (insn[2] & ~0xfe0000) | (((slotbuf[0] & 0x1fc000) >> 14) << 17); +} + +static void +Slot_ae_format88_Format_ae_slot2_28_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x20) >> 5) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x1c00) >> 10) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x2000) >> 13) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x4000000) >> 26) << 13); + slotbuf[0] = (slotbuf[0] & ~0x1fc000) | (((insn[2] & 0x1fc00) >> 10) << 14); +} + +static void +Slot_ae_format88_Format_ae_slot2_28_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); + insn[1] = (insn[1] & ~0x20) | (((slotbuf[0] & 0x10) >> 4) << 5); + insn[1] = (insn[1] & ~0x1c00) | (((slotbuf[0] & 0xe0) >> 5) << 10); + insn[1] = (insn[1] & ~0x3c000) | (((slotbuf[0] & 0xf00) >> 8) << 14); + insn[1] = (insn[1] & ~0x2000) | (((slotbuf[0] & 0x1000) >> 12) << 13); + insn[1] = (insn[1] & ~0x4000000) | (((slotbuf[0] & 0x2000) >> 13) << 26); + insn[2] = (insn[2] & ~0x1fc00) | (((slotbuf[0] & 0x1fc000) >> 14) << 10); +} + +static void +Slot_ae_format88_Format_ae_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xfff0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xff000) | (((insn[2] & 0x3fc) >> 2) << 12); +} + +static void +Slot_ae_format88_Format_ae_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0000) | ((slotbuf[0] & 0xfff) << 16); + insn[2] = (insn[2] & ~0x3fc) | (((slotbuf[0] & 0xff000) >> 12) << 2); +} + +static void +Slot_ae_format88_Format_ae_slot0_5_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c0) >> 6) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x10) >> 4) << 12); + slotbuf[0] = (slotbuf[0] & ~0xe000) | (((insn[0] & 0xe0) >> 5) << 13); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[1] & 0xe0000000) >> 29) << 16); + slotbuf[0] = (slotbuf[0] & ~0x180000) | ((insn[2] & 0x3) << 19); +} + +static void +Slot_ae_format88_Format_ae_slot0_5_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[1] = (insn[1] & ~0x3c0) | (((slotbuf[0] & 0xf00) >> 8) << 6); + insn[1] = (insn[1] & ~0x10) | (((slotbuf[0] & 0x1000) >> 12) << 4); + insn[0] = (insn[0] & ~0xe0) | (((slotbuf[0] & 0xe000) >> 13) << 5); + insn[1] = (insn[1] & ~0xe0000000) | (((slotbuf[0] & 0x70000) >> 16) << 29); + insn[2] = (insn[2] & ~0x3) | ((slotbuf[0] & 0x180000) >> 19); +} + +static void +Slot_ae_format88_2_Format_ae2_slot2_28_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); + slotbuf[0] = (slotbuf[0] & ~0xf0) | ((insn[1] & 0xf) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x20) >> 5) << 12); + slotbuf[0] = (slotbuf[0] & ~0xe000) | (((insn[1] & 0x1c00) >> 10) << 13); + slotbuf[0] = (slotbuf[0] & ~0xf0000) | (((insn[1] & 0x3c0000) >> 18) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1f00000) | (((insn[2] & 0xf800) >> 11) << 20); +} + +static void +Slot_ae_format88_2_Format_ae2_slot2_28_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); + insn[1] = (insn[1] & ~0xf) | ((slotbuf[0] & 0xf0) >> 4); + insn[1] = (insn[1] & ~0x3c000) | (((slotbuf[0] & 0xf00) >> 8) << 14); + insn[1] = (insn[1] & ~0x20) | (((slotbuf[0] & 0x1000) >> 12) << 5); + insn[1] = (insn[1] & ~0x1c00) | (((slotbuf[0] & 0xe000) >> 13) << 10); + insn[1] = (insn[1] & ~0x3c0000) | (((slotbuf[0] & 0xf0000) >> 16) << 18); + insn[2] = (insn[2] & ~0xf800) | (((slotbuf[0] & 0x1f00000) >> 20) << 11); +} + +static void +Slot_ae_format88_2_Format_ae2_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf000000) >> 24) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf00000) >> 20) << 8); + slotbuf[0] = (slotbuf[0] & ~0xff000) | (((insn[2] & 0x7f8) >> 3) << 12); +} + +static void +Slot_ae_format88_2_Format_ae2_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000) | ((slotbuf[0] & 0xf) << 16); + insn[0] = (insn[0] & ~0xf000000) | (((slotbuf[0] & 0xf0) >> 4) << 24); + insn[0] = (insn[0] & ~0xf00000) | (((slotbuf[0] & 0xf00) >> 8) << 20); + insn[2] = (insn[2] & ~0x7f8) | (((slotbuf[0] & 0xff000) >> 12) << 3); +} + +static void +Slot_ae_format88_2_Format_ae2_slot0_6_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c0) >> 6) << 8); + slotbuf[0] = (slotbuf[0] & ~0x1000) | (((insn[1] & 0x10) >> 4) << 12); + slotbuf[0] = (slotbuf[0] & ~0x2000) | (((insn[1] & 0x2000) >> 13) << 13); + slotbuf[0] = (slotbuf[0] & ~0xc000) | (((insn[0] & 0xc0) >> 6) << 14); + slotbuf[0] = (slotbuf[0] & ~0x3ff0000) | (((insn[1] & 0xffc00000) >> 22) << 16); + slotbuf[0] = (slotbuf[0] & ~0x1c000000) | ((insn[2] & 0x7) << 26); +} + +static void +Slot_ae_format88_2_Format_ae2_slot0_6_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[1] = (insn[1] & ~0x3c0) | (((slotbuf[0] & 0xf00) >> 8) << 6); + insn[1] = (insn[1] & ~0x10) | (((slotbuf[0] & 0x1000) >> 12) << 4); + insn[1] = (insn[1] & ~0x2000) | (((slotbuf[0] & 0x2000) >> 13) << 13); + insn[0] = (insn[0] & ~0xc0) | (((slotbuf[0] & 0xc000) >> 14) << 6); + insn[1] = (insn[1] & ~0xffc00000) | (((slotbuf[0] & 0x3ff0000) >> 16) << 22); + insn[2] = (insn[2] & ~0x7) | ((slotbuf[0] & 0x1c000000) >> 26); +} + +static void +Slot_ae_format48_Format_ae3_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf000000) >> 24) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf00000) >> 20) << 8); + slotbuf[0] = (slotbuf[0] & ~0xff000) | (((insn[1] & 0x3fc0) >> 6) << 12); +} + +static void +Slot_ae_format48_Format_ae3_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000) | ((slotbuf[0] & 0xf) << 16); + insn[0] = (insn[0] & ~0xf000000) | (((slotbuf[0] & 0xf0) >> 4) << 24); + insn[0] = (insn[0] & ~0xf00000) | (((slotbuf[0] & 0xf00) >> 8) << 20); + insn[1] = (insn[1] & ~0x3fc0) | (((slotbuf[0] & 0xff000) >> 12) << 6); +} + +static void +Slot_ae_format48_Format_ae3_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[0] & 0xf0000000) >> 28) << 12); + slotbuf[0] = (slotbuf[0] & ~0x3f0000) | ((insn[1] & 0x3f) << 16); +} + +static void +Slot_ae_format48_Format_ae3_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf000) >> 12) << 28); + insn[1] = (insn[1] & ~0x3f) | ((slotbuf[0] & 0x3f0000) >> 16); +} + +static void +Slot_ae_format48_2_Format_ae4_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf000000) >> 24) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf00000) >> 20) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0x3000) >> 12) << 12); +} + +static void +Slot_ae_format48_2_Format_ae4_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000) | ((slotbuf[0] & 0xf) << 16); + insn[0] = (insn[0] & ~0xf000000) | (((slotbuf[0] & 0xf0) >> 4) << 24); + insn[0] = (insn[0] & ~0xf00000) | (((slotbuf[0] & 0xf00) >> 8) << 20); + insn[1] = (insn[1] & ~0x3000) | (((slotbuf[0] & 0x3000) >> 12) << 12); +} + +static void +Slot_ae_format48_2_Format_ae4_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[0] & 0xf0000000) >> 28) << 12); + slotbuf[0] = (slotbuf[0] & ~0xfff0000) | ((insn[1] & 0xfff) << 16); +} + +static void +Slot_ae_format48_2_Format_ae4_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf000) >> 12) << 28); + insn[1] = (insn[1] & ~0xfff) | ((slotbuf[0] & 0xfff0000) >> 16); +} + +static void +Slot_ae_format48_3_Format_ae5_slot2_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xfff0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xff000) | (((insn[1] & 0x7f80) >> 7) << 12); +} + +static void +Slot_ae_format48_3_Format_ae5_slot2_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0000) | ((slotbuf[0] & 0xfff) << 16); + insn[1] = (insn[1] & ~0x7f80) | (((slotbuf[0] & 0xff000) >> 12) << 7); +} + +static void +Slot_ae_format48_3_Format_ae5_slot1_38_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[1] & 0x40) >> 6); +} + +static void +Slot_ae_format48_3_Format_ae5_slot1_38_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x40) | ((slotbuf[0] & 0x1) << 6); +} + +static void +Slot_ae_format48_3_Format_ae5_slot0_4_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf0) >> 4) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[0] & 0xf0000000) >> 28) << 12); + slotbuf[0] = (slotbuf[0] & ~0x3f0000) | ((insn[1] & 0x3f) << 16); +} + +static void +Slot_ae_format48_3_Format_ae5_slot0_4_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xf0) | (((slotbuf[0] & 0xf0) >> 4) << 4); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf000) >> 12) << 28); + insn[1] = (insn[1] & ~0x3f) | ((slotbuf[0] & 0x3f0000) >> 16); +} + +static void +Slot_ae_format88_3_Format_ae6_slot3_32_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[1] & 0x3c00000) >> 22); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0x3c0000) >> 18) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | ((insn[1] & 0xf) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[1] & 0x3c0) >> 6) << 12); + slotbuf[0] = (slotbuf[0] & ~0x30000) | (((insn[2] & 0x18) >> 3) << 16); +} + +static void +Slot_ae_format88_3_Format_ae6_slot3_32_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3c00000) | ((slotbuf[0] & 0xf) << 22); + insn[1] = (insn[1] & ~0x3c0000) | (((slotbuf[0] & 0xf0) >> 4) << 18); + insn[1] = (insn[1] & ~0xf) | ((slotbuf[0] & 0xf00) >> 8); + insn[1] = (insn[1] & ~0x3c0) | (((slotbuf[0] & 0xf000) >> 12) << 6); + insn[2] = (insn[2] & ~0x18) | (((slotbuf[0] & 0x30000) >> 16) << 3); +} + +static void +Slot_ae_format88_3_Format_ae6_slot2_28_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[1] & 0x3c000) >> 14); + slotbuf[0] = (slotbuf[0] & ~0x10) | (((insn[1] & 0x20) >> 5) << 4); + slotbuf[0] = (slotbuf[0] & ~0xe0) | (((insn[1] & 0x1c00) >> 10) << 5); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf0000000) >> 28) << 8); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[2] & 0x6) >> 1) << 12); +} + +static void +Slot_ae_format88_3_Format_ae6_slot2_28_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3c000) | ((slotbuf[0] & 0xf) << 14); + insn[1] = (insn[1] & ~0x20) | (((slotbuf[0] & 0x10) >> 4) << 5); + insn[1] = (insn[1] & ~0x1c00) | (((slotbuf[0] & 0xe0) >> 5) << 10); + insn[0] = (insn[0] & ~0xf0000000) | (((slotbuf[0] & 0xf00) >> 8) << 28); + insn[2] = (insn[2] & ~0x6) | (((slotbuf[0] & 0x3000) >> 12) << 1); +} + +static void +Slot_ae_format88_3_Format_ae6_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xfff0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0xc0000000) >> 30) << 12); + slotbuf[0] = (slotbuf[0] & ~0x4000) | ((insn[2] & 0x1) << 14); +} + +static void +Slot_ae_format88_3_Format_ae6_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfff0000) | ((slotbuf[0] & 0xfff) << 16); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x3000) >> 12) << 30); + insn[2] = (insn[2] & ~0x1) | ((slotbuf[0] & 0x4000) >> 14); +} + +static void +Slot_ae_format88_3_Format_ae6_slot0_6_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xff00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x100) | (((insn[1] & 0x10) >> 4) << 8); + slotbuf[0] = (slotbuf[0] & ~0x200) | (((insn[1] & 0x2000) >> 13) << 9); + slotbuf[0] = (slotbuf[0] & ~0xc00) | (((insn[0] & 0xc0) >> 6) << 10); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[1] & 0x3c000000) >> 26) << 12); +} + +static void +Slot_ae_format88_3_Format_ae6_slot0_6_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff00) | ((slotbuf[0] & 0xff) << 8); + insn[1] = (insn[1] & ~0x10) | (((slotbuf[0] & 0x100) >> 8) << 4); + insn[1] = (insn[1] & ~0x2000) | (((slotbuf[0] & 0x200) >> 9) << 13); + insn[0] = (insn[0] & ~0xc0) | (((slotbuf[0] & 0xc00) >> 10) << 6); + insn[1] = (insn[1] & ~0x3c000000) | (((slotbuf[0] & 0xf000) >> 12) << 26); +} + +static void +Slot_ae_format88_4_Format_ae7_slot3_12_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = (insn[1] & 0xf); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[1] & 0x3c00000) >> 22) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf000) >> 12) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[1] & 0x3c000000) >> 26) << 12); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[2] & 0xe00) >> 9) << 16); +} + +static void +Slot_ae_format88_4_Format_ae7_slot3_12_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xf) | (slotbuf[0] & 0xf); + insn[1] = (insn[1] & ~0x3c00000) | (((slotbuf[0] & 0xf0) >> 4) << 22); + insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf00) >> 8) << 12); + insn[1] = (insn[1] & ~0x3c000000) | (((slotbuf[0] & 0xf000) >> 12) << 26); + insn[2] = (insn[2] & ~0xe00) | (((slotbuf[0] & 0x70000) >> 16) << 9); +} + +static void +Slot_ae_format88_4_Format_ae7_slot2_20_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000000) >> 28); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf00000) >> 20) << 4); + slotbuf[0] = (slotbuf[0] & ~0xff00) | (((insn[1] & 0x3fc000) >> 14) << 8); + slotbuf[0] = (slotbuf[0] & ~0x70000) | (((insn[2] & 0x1c0) >> 6) << 16); +} + +static void +Slot_ae_format88_4_Format_ae7_slot2_20_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28); + insn[0] = (insn[0] & ~0xf00000) | (((slotbuf[0] & 0xf0) >> 4) << 20); + insn[1] = (insn[1] & ~0x3fc000) | (((slotbuf[0] & 0xff00) >> 8) << 14); + insn[2] = (insn[2] & ~0x1c0) | (((slotbuf[0] & 0x70000) >> 16) << 6); +} + +static void +Slot_ae_format88_4_Format_ae7_slot1_16_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf0000) >> 16); + slotbuf[0] = (slotbuf[0] & ~0xf0) | (((insn[0] & 0xf000000) >> 24) << 4); + slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[1] & 0x3c00) >> 10) << 8); + slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[2] & 0x3c) >> 2) << 12); +} + +static void +Slot_ae_format88_4_Format_ae7_slot1_16_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf0000) | ((slotbuf[0] & 0xf) << 16); + insn[0] = (insn[0] & ~0xf000000) | (((slotbuf[0] & 0xf0) >> 4) << 24); + insn[1] = (insn[1] & ~0x3c00) | (((slotbuf[0] & 0xf00) >> 8) << 10); + insn[2] = (insn[2] & ~0x3c) | (((slotbuf[0] & 0xf000) >> 12) << 2); +} + +static void +Slot_ae_format88_4_Format_ae7_slot0_6_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[2] = 0; + slotbuf[0] = ((insn[0] & 0xf00) >> 8); + slotbuf[0] = (slotbuf[0] & ~0x30) | (((insn[0] & 0xc0) >> 6) << 4); + slotbuf[0] = (slotbuf[0] & ~0xfc0) | (((insn[1] & 0x3f0) >> 4) << 6); + slotbuf[0] = (slotbuf[0] & ~0x3000) | (((insn[1] & 0xc0000000) >> 30) << 12); + slotbuf[0] = (slotbuf[0] & ~0xc000) | ((insn[2] & 0x3) << 14); +} + +static void +Slot_ae_format88_4_Format_ae7_slot0_6_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xf00) | ((slotbuf[0] & 0xf) << 8); + insn[0] = (insn[0] & ~0xc0) | (((slotbuf[0] & 0x30) >> 4) << 6); + insn[1] = (insn[1] & ~0x3f0) | (((slotbuf[0] & 0xfc0) >> 6) << 4); + insn[1] = (insn[1] & ~0xc0000000) | (((slotbuf[0] & 0x3000) >> 12) << 30); + insn[2] = (insn[2] & ~0x3) | ((slotbuf[0] & 0xc000) >> 14); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_r_disp_Slot_inst_get, + Field_r_3_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_ae_fld_fhba4_Slot_inst_get, + Field_ae_fld_fhba4_2_Slot_inst_get, + Field_ae_fld_tp7_Slot_inst_get, + Field_ae_fld_osa32_Slot_inst_get, + Field_ae_fld_osa64_Slot_inst_get, + Field_ae_fld_imm2_Slot_inst_get, + Field_ae_fld_immls64_Slot_inst_get, + Field_ae_fld_immls64pos_Slot_inst_get, + Field_ae_fld_immls64half_Slot_inst_get, + Field_ae_fld_immls32_Slot_inst_get, + Field_ae_fld_immls16_Slot_inst_get, + 0, + Field_inst_15_12_Slot_inst_get, + Field_inst_11_8_Slot_inst_get, + Field_inst_7_4_Slot_inst_get, + Field_inst_12_Slot_inst_get, + Field_inst_7_Slot_inst_get, + Field_inst_5_4_Slot_inst_get, + Field_inst_7_6_Slot_inst_get, + Field_inst_19_17_Slot_inst_get, + Field_inst_19_18_Slot_inst_get, + Field_inst_9_8_Slot_inst_get, + Field_inst_4_Slot_inst_get, + Field_ae_fld_ls_v_Slot_inst_get, + Field_ae_fld_ls_uu_Slot_inst_get, + Field_ae_fld_ls_su_Slot_inst_get, + Field_ae_fld_ls_av_Slot_inst_get, + Field_ae_fld_ls_v1_Slot_inst_get, + Field_ae_fld_ls_v2_Slot_inst_get, + Field_ae_fld_cmpp_v0_Slot_inst_get, + Field_ae_fld_cmpp_v1_Slot_inst_get, + Field_ae_fld_cmpp_v_Slot_inst_get, + Field_ae_fld_uu_v_Slot_inst_get, + Field_ae_fld_uu_uu_Slot_inst_get, + Field_ae_fld_dr_to_ar_v0_Slot_inst_get, + Field_ae_fld_cmov_v_Slot_inst_get, + Field_ae_fld_cmov_v0_Slot_inst_get, + Field_ae_fld_pks_d_Slot_inst_get, + Field_ae_fld_pks_s_Slot_inst_get, + Field_ae_fld_shift_d_Slot_inst_get, + Field_ae_fld_shift_d0_Slot_inst_get, + Field_ae_fld_shift_sd_Slot_inst_get, + Field_ae_fld_dr_to_dr_v_Slot_inst_get, + Field_ae_fld_dr_to_dr_v0_Slot_inst_get, + Field_ae_fld_dr_to_dr_v1_Slot_inst_get, + Field_ae_fld_to_dr_v_Slot_inst_get, + Field_ae_fld_to_dr_v0_Slot_inst_get, + Field_fld_ae_immls64neg_Slot_inst_get, + Field_ae_fld_selimm_Slot_inst_get, + 0, + Field_fld_ar_to_dr_imm_Slot_inst_get, + Field_ae_fld_arth_v_Slot_inst_get, + Field_ae_fld_arth_v0_Slot_inst_get, + Field_ae_fld_arth_v1_Slot_inst_get, + Field_ae_fld_ar_to_dr_v_Slot_inst_get, + Field_fld_inst_23_12_Slot_inst_get, + Field_fld_inst_23_16_Slot_inst_get, + Field_fld_inst_7_7_Slot_inst_get, + Field_fld_inst_11_8_Slot_inst_get, + Field_fld_inst_13_8_Slot_inst_get, + Field_fld_inst_12_8_Slot_inst_get, + Field_fld_inst_9_8_Slot_inst_get, + Field_fld_inst_4_4_Slot_inst_get, + Field_fld_inst_5_4_Slot_inst_get, + Field_fld_inst_7_4_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_vr_Slot_inst_get, + Field_fld_ae_sem_cmov_bt_Slot_inst_get, + Field_fld_ae_sem_cmov_arr_Slot_inst_get, + Field_fld_vfpu2_sem_mov_vt_Slot_inst_get, + Field_fld_vfpu2_sem_mov_vr_Slot_inst_get, + Field_fld_vfpu2_sem_spfma_vt_Slot_inst_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_inst_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_inst_get, + Field_fld_vfpu2_sem_spmisc_brt_Slot_inst_get, + Field_fld_vfpu2_sem_spmisc_vs_Slot_inst_get, + Field_fld_vfpu2_sem_spmisc_vr_Slot_inst_get, + Field_fld_vfpu2_sem_mov_i_imm4_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_op1_Slot_inst_get, + Field_dfp_fld_op2_Slot_inst_get, + Field_dfp_fld_r_0_Slot_inst_get, + Field_dfp_fld_r_2_1_Slot_inst_get, + Field_dfp_fld_r_3_Slot_inst_get, + Field_dfp_fld_r_3_1_Slot_inst_get, + Field_dfp_fld_s_0_Slot_inst_get, + Field_dfp_fld_s_3_1_Slot_inst_get, + Field_dfp_fld_op2_0_Slot_inst_get, + Field_dfp_fld_op2_1_0_Slot_inst_get, + Field_dfp_fld_op2_2_Slot_inst_get, + Field_dfp_fld_op2_3_Slot_inst_get, + Field_dfp_fld_op2_3_2_Slot_inst_get, + Field_dfp_fld_op2_3_1_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Field_fld_sigmoid_q15_x_Slot_inst_get, + Field_fld_sigmoid_q15_y_Slot_inst_get, + Field_fld_inst_3_0_Slot_inst_get, + Field_fld_sigmoid_fp32_x_Slot_inst_get, + Field_fld_sigmoid_fp32_y_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_r_disp_Slot_inst_set, + Field_r_3_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_ae_fld_fhba4_Slot_inst_set, + Field_ae_fld_fhba4_2_Slot_inst_set, + Field_ae_fld_tp7_Slot_inst_set, + Field_ae_fld_osa32_Slot_inst_set, + Field_ae_fld_osa64_Slot_inst_set, + Field_ae_fld_imm2_Slot_inst_set, + Field_ae_fld_immls64_Slot_inst_set, + Field_ae_fld_immls64pos_Slot_inst_set, + Field_ae_fld_immls64half_Slot_inst_set, + Field_ae_fld_immls32_Slot_inst_set, + Field_ae_fld_immls16_Slot_inst_set, + 0, + Field_inst_15_12_Slot_inst_set, + Field_inst_11_8_Slot_inst_set, + Field_inst_7_4_Slot_inst_set, + Field_inst_12_Slot_inst_set, + Field_inst_7_Slot_inst_set, + Field_inst_5_4_Slot_inst_set, + Field_inst_7_6_Slot_inst_set, + Field_inst_19_17_Slot_inst_set, + Field_inst_19_18_Slot_inst_set, + Field_inst_9_8_Slot_inst_set, + Field_inst_4_Slot_inst_set, + Field_ae_fld_ls_v_Slot_inst_set, + Field_ae_fld_ls_uu_Slot_inst_set, + Field_ae_fld_ls_su_Slot_inst_set, + Field_ae_fld_ls_av_Slot_inst_set, + Field_ae_fld_ls_v1_Slot_inst_set, + Field_ae_fld_ls_v2_Slot_inst_set, + Field_ae_fld_cmpp_v0_Slot_inst_set, + Field_ae_fld_cmpp_v1_Slot_inst_set, + Field_ae_fld_cmpp_v_Slot_inst_set, + Field_ae_fld_uu_v_Slot_inst_set, + Field_ae_fld_uu_uu_Slot_inst_set, + Field_ae_fld_dr_to_ar_v0_Slot_inst_set, + Field_ae_fld_cmov_v_Slot_inst_set, + Field_ae_fld_cmov_v0_Slot_inst_set, + Field_ae_fld_pks_d_Slot_inst_set, + Field_ae_fld_pks_s_Slot_inst_set, + Field_ae_fld_shift_d_Slot_inst_set, + Field_ae_fld_shift_d0_Slot_inst_set, + Field_ae_fld_shift_sd_Slot_inst_set, + Field_ae_fld_dr_to_dr_v_Slot_inst_set, + Field_ae_fld_dr_to_dr_v0_Slot_inst_set, + Field_ae_fld_dr_to_dr_v1_Slot_inst_set, + Field_ae_fld_to_dr_v_Slot_inst_set, + Field_ae_fld_to_dr_v0_Slot_inst_set, + Field_fld_ae_immls64neg_Slot_inst_set, + Field_ae_fld_selimm_Slot_inst_set, + 0, + Field_fld_ar_to_dr_imm_Slot_inst_set, + Field_ae_fld_arth_v_Slot_inst_set, + Field_ae_fld_arth_v0_Slot_inst_set, + Field_ae_fld_arth_v1_Slot_inst_set, + Field_ae_fld_ar_to_dr_v_Slot_inst_set, + Field_fld_inst_23_12_Slot_inst_set, + Field_fld_inst_23_16_Slot_inst_set, + Field_fld_inst_7_7_Slot_inst_set, + Field_fld_inst_11_8_Slot_inst_set, + Field_fld_inst_13_8_Slot_inst_set, + Field_fld_inst_12_8_Slot_inst_set, + Field_fld_inst_9_8_Slot_inst_set, + Field_fld_inst_4_4_Slot_inst_set, + Field_fld_inst_5_4_Slot_inst_set, + Field_fld_inst_7_4_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_dr_to_ar_vr_Slot_inst_set, + Field_fld_ae_sem_cmov_bt_Slot_inst_set, + Field_fld_ae_sem_cmov_arr_Slot_inst_set, + Field_fld_vfpu2_sem_mov_vt_Slot_inst_set, + Field_fld_vfpu2_sem_mov_vr_Slot_inst_set, + Field_fld_vfpu2_sem_spfma_vt_Slot_inst_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_inst_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_inst_set, + Field_fld_vfpu2_sem_spmisc_brt_Slot_inst_set, + Field_fld_vfpu2_sem_spmisc_vs_Slot_inst_set, + Field_fld_vfpu2_sem_spmisc_vr_Slot_inst_set, + Field_fld_vfpu2_sem_mov_i_imm4_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_op1_Slot_inst_set, + Field_dfp_fld_op2_Slot_inst_set, + Field_dfp_fld_r_0_Slot_inst_set, + Field_dfp_fld_r_2_1_Slot_inst_set, + Field_dfp_fld_r_3_Slot_inst_set, + Field_dfp_fld_r_3_1_Slot_inst_set, + Field_dfp_fld_s_0_Slot_inst_set, + Field_dfp_fld_s_3_1_Slot_inst_set, + Field_dfp_fld_op2_0_Slot_inst_set, + Field_dfp_fld_op2_1_0_Slot_inst_set, + Field_dfp_fld_op2_2_Slot_inst_set, + Field_dfp_fld_op2_3_Slot_inst_set, + Field_dfp_fld_op2_3_2_Slot_inst_set, + Field_dfp_fld_op2_3_1_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Field_fld_sigmoid_q15_x_Slot_inst_set, + Field_fld_sigmoid_q15_y_Slot_inst_set, + Field_fld_inst_3_0_Slot_inst_set, + Field_fld_sigmoid_fp32_x_Slot_inst_set, + Field_fld_sigmoid_fp32_y_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16a_get, + Field_dfp_fld_r_2_1_Slot_inst16a_get, + Field_dfp_fld_r_3_Slot_inst16a_get, + Field_dfp_fld_r_3_1_Slot_inst16a_get, + Field_dfp_fld_s_0_Slot_inst16a_get, + Field_dfp_fld_s_3_1_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16a_set, + Field_dfp_fld_r_2_1_Slot_inst16a_set, + Field_dfp_fld_r_3_Slot_inst16a_set, + Field_dfp_fld_r_3_1_Slot_inst16a_set, + Field_dfp_fld_s_0_Slot_inst16a_set, + Field_dfp_fld_s_3_1_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_get, + Field_ae_fld_inst16b_15_13_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16b_get, + Field_dfp_fld_r_2_1_Slot_inst16b_get, + Field_dfp_fld_r_3_Slot_inst16b_get, + Field_dfp_fld_r_3_1_Slot_inst16b_get, + Field_dfp_fld_s_0_Slot_inst16b_get, + Field_dfp_fld_s_3_1_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_inst16b_12_Slot_inst16b_set, + Field_ae_fld_inst16b_15_13_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_inst16b_set, + Field_dfp_fld_r_2_1_Slot_inst16b_set, + Field_dfp_fld_r_3_Slot_inst16b_set, + Field_dfp_fld_r_3_1_Slot_inst16b_set, + Field_dfp_fld_s_0_Slot_inst16b_set, + Field_dfp_fld_s_3_1_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot3_get_field_fns[] = { + Field_t_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot3_get, + 0, + 0, + Field_t4_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_tp7_Slot_ae_slot3_get, + Field_ae_fld_osa32_Slot_ae_slot3_get, + Field_ae_fld_osa64_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_osa16_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_cmov_v_Slot_ae_slot3_get, + Field_ae_fld_cmov_v0_Slot_ae_slot3_get, + 0, + 0, + Field_ae_fld_shift_d_Slot_ae_slot3_get, + Field_ae_fld_shift_d0_Slot_ae_slot3_get, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot3_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot3_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot3_get, + Field_ae_fld_to_dr_v_Slot_ae_slot3_get, + Field_ae_fld_to_dr_v0_Slot_ae_slot3_get, + 0, + Field_ae_fld_selimm_Slot_ae_slot3_get, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot3_get, + Field_ae_fld_arth_v_Slot_ae_slot3_get, + Field_ae_fld_arth_v0_Slot_ae_slot3_get, + Field_ae_fld_arth_v1_Slot_ae_slot3_get, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_0_Slot_ae_slot3_get, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_get, + Field_fld_ae_slot3_3_0_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_slot3_1_0_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_8_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d1_Slot_ae_slot3_get, + Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae_slot3_get, + Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_12_Slot_ae_slot3_get, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot3_get, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot3_get, + 0, + Field_fld_ae_slot3_11_4_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_acc_ep_Slot_ae_slot3_get, + Field_fld_ae_slot3_20_14_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_get, + Field_fld_ae_slot3_20_16_Slot_ae_slot3_get, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_get, + Field_fld_ae_slot3_11_11_Slot_ae_slot3_get, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_get, + 0, + Field_fld_ae_slot3_7_4_Slot_ae_slot3_get, + 0, + 0, + 0, + Field_fld_ae_slot3_20_10_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_0_0_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_13_Slot_ae_slot3_get, + 0, + 0, + Field_fld_ae_slot3_13_12_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot3_get, + Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot3_get, + 0, + Field_fld_ae_slot3_20_15_Slot_ae_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot3_set_field_fns[] = { + Field_t_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot3_set, + 0, + 0, + Field_t4_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_tp7_Slot_ae_slot3_set, + Field_ae_fld_osa32_Slot_ae_slot3_set, + Field_ae_fld_osa64_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_osa16_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_cmov_v_Slot_ae_slot3_set, + Field_ae_fld_cmov_v0_Slot_ae_slot3_set, + 0, + 0, + Field_ae_fld_shift_d_Slot_ae_slot3_set, + Field_ae_fld_shift_d0_Slot_ae_slot3_set, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot3_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot3_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot3_set, + Field_ae_fld_to_dr_v_Slot_ae_slot3_set, + Field_ae_fld_to_dr_v0_Slot_ae_slot3_set, + 0, + Field_ae_fld_selimm_Slot_ae_slot3_set, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot3_set, + Field_ae_fld_arth_v_Slot_ae_slot3_set, + Field_ae_fld_arth_v0_Slot_ae_slot3_set, + Field_ae_fld_arth_v1_Slot_ae_slot3_set, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_0_Slot_ae_slot3_set, + Field_fld_ae_sem_rng_d_Slot_ae_slot3_set, + Field_fld_ae_slot3_3_0_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_slot3_1_0_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_8_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d1_Slot_ae_slot3_set, + Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae_slot3_set, + Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_12_Slot_ae_slot3_set, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot3_set, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot3_set, + 0, + Field_fld_ae_slot3_11_4_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_acc_ep_Slot_ae_slot3_set, + Field_fld_ae_slot3_20_14_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_e_Slot_ae_slot3_set, + Field_fld_ae_slot3_20_16_Slot_ae_slot3_set, + Field_fld_ae_sem_shift_i8_Slot_ae_slot3_set, + Field_fld_ae_slot3_11_11_Slot_ae_slot3_set, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot3_set, + 0, + Field_fld_ae_slot3_7_4_Slot_ae_slot3_set, + 0, + 0, + 0, + Field_fld_ae_slot3_20_10_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_0_0_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot3_20_13_Slot_ae_slot3_set, + 0, + 0, + Field_fld_ae_slot3_13_12_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot3_set, + Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot3_set, + 0, + Field_fld_ae_slot3_20_15_Slot_ae_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_imm2_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_pks_d_Slot_ae_slot2_get, + Field_ae_fld_pks_s_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot2_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot2_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot2_get, + Field_ae_fld_to_dr_v_Slot_ae_slot2_get, + Field_ae_fld_to_dr_v0_Slot_ae_slot2_get, + 0, + 0, + Field_ae_fld_selimm_n_Slot_ae_slot2_get, + Field_fld_ar_to_dr_imm_Slot_ae_slot2_get, + Field_ae_fld_arth_v_Slot_ae_slot2_get, + Field_ae_fld_arth_v0_Slot_ae_slot2_get, + Field_ae_fld_arth_v1_Slot_ae_slot2_get, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_20_0_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x4_d0_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x4_q0_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_20_12_Slot_ae_slot2_get, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot2_get, + Field_fld_ae_slot2_7_0_Slot_ae_slot2_get, + 0, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_get, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_get, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_10_Slot_ae_slot2_get, + Field_fld_ae_sem_mul_x2_s1_acc_ep_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_14_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_get, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_get, + 0, + Field_fld_ae_slot2_20_8_Slot_ae_slot2_get, + 0, + 0, + 0, + Field_fld_ae_slot2_7_4_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_3_2_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot2_get, + 0, + Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_mov_i_imm4_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spmisc_vt_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spmisc_vsm_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_18_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spmisc_vtm_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot2_get, + Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_13_Slot_ae_slot2_get, + 0, + Field_fld_ae_slot2_20_15_Slot_ae_slot2_get, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_get, + Field_fld_ae_slot2_20_4_Slot_ae_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_imm2_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_pks_d_Slot_ae_slot2_set, + Field_ae_fld_pks_s_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot2_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot2_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot2_set, + Field_ae_fld_to_dr_v_Slot_ae_slot2_set, + Field_ae_fld_to_dr_v0_Slot_ae_slot2_set, + 0, + 0, + Field_ae_fld_selimm_n_Slot_ae_slot2_set, + Field_fld_ar_to_dr_imm_Slot_ae_slot2_set, + Field_ae_fld_arth_v_Slot_ae_slot2_set, + Field_ae_fld_arth_v0_Slot_ae_slot2_set, + Field_ae_fld_arth_v1_Slot_ae_slot2_set, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_20_0_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x4_d0_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x4_q0_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_20_12_Slot_ae_slot2_set, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_eo_Slot_ae_slot2_set, + Field_fld_ae_slot2_7_0_Slot_ae_slot2_set, + 0, + Field_fld_ae_sem_arithmetic_ep_Slot_ae_slot2_set, + Field_fld_ae_slot2_3_0_Slot_ae_slot2_set, + Field_fld_ae_sem_arithmetic_ep1_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_10_Slot_ae_slot2_set, + Field_fld_ae_sem_mul_x2_s1_acc_ep_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_14_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_e_Slot_ae_slot2_set, + Field_fld_ae_slot2_9_8_Slot_ae_slot2_set, + 0, + Field_fld_ae_slot2_20_8_Slot_ae_slot2_set, + 0, + 0, + 0, + Field_fld_ae_slot2_7_4_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot2_3_2_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_mov_vt_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_mov_vr_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae_slot2_set, + 0, + Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_mov_i_imm4_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spmisc_vt_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spmisc_vsm_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_18_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spmisc_vtm_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_i_imm1_Slot_ae_slot2_set, + Field_fld_vfpu2_sem_spfma_i_imm3_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_13_Slot_ae_slot2_set, + 0, + Field_fld_ae_slot2_20_15_Slot_ae_slot2_set, + Field_fld_ae_sem_movfpstate_v_Slot_ae_slot2_set, + Field_fld_ae_slot2_20_4_Slot_ae_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot1_get_field_fns[] = { + Field_t_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_get, + Field_s_Slot_ae_slot1_get, + Field_imm12b_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_get, + Field_r_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_get, + Field_sal_Slot_ae_slot1_get, + Field_sargt_Slot_ae_slot1_get, + 0, + Field_sas_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae_slot1_get, + Field_ae_fld_immls64pos_Slot_ae_slot1_get, + Field_ae_fld_immls64half_Slot_ae_slot1_get, + Field_ae_fld_immls32_Slot_ae_slot1_get, + Field_ae_fld_immls16_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_immls64neg_Slot_ae_slot1_get, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_12_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_16_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_17_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_0_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_13_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_4_Slot_ae_slot1_get, + 0, + 0, + Field_fld_ae_slot1_19_9_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_get, + 0, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_get, + 0, + 0, + 0, + Field_fld_ae_slot1_19_8_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_7_6_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_7_7_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae_slot1_get, + Field_dfp_fld_r_3_Slot_ae_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae_slot1_get, + Field_dfp_fld_s_0_Slot_ae_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot1_set_field_fns[] = { + Field_t_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot1_set, + Field_s_Slot_ae_slot1_set, + Field_imm12b_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae_slot1_set, + Field_r_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae_slot1_set, + Field_sal_Slot_ae_slot1_set, + Field_sargt_Slot_ae_slot1_set, + 0, + Field_sas_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae_slot1_set, + Field_ae_fld_immls64pos_Slot_ae_slot1_set, + Field_ae_fld_immls64half_Slot_ae_slot1_set, + Field_ae_fld_immls32_Slot_ae_slot1_set, + Field_ae_fld_immls16_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_immls64neg_Slot_ae_slot1_set, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_3_0_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_12_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_16_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_17_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_0_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_13_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_19_4_Slot_ae_slot1_set, + 0, + 0, + Field_fld_ae_slot1_19_9_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot1_set, + 0, + Field_fld_ae_slot1_7_4_Slot_ae_slot1_set, + 0, + 0, + 0, + Field_fld_ae_slot1_19_8_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_7_6_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot1_7_7_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae_slot1_set, + Field_dfp_fld_r_3_Slot_ae_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae_slot1_set, + Field_dfp_fld_s_0_Slot_ae_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae_slot0_get_field_fns[] = { + Field_t_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_get, + Field_s_Slot_ae_slot0_get, + Field_imm12b_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_sal_Slot_ae_slot0_get, + Field_sargt_Slot_ae_slot0_get, + 0, + Field_sas_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_get, + 0, + Field_r2_Slot_ae_slot0_get, + Field_t4_Slot_ae_slot0_get, + Field_s4_Slot_ae_slot0_get, + Field_r4_Slot_ae_slot0_get, + 0, + Field_s8_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae_slot0_get, + 0, + 0, + Field_ae_fld_osa32_Slot_ae_slot0_get, + Field_ae_fld_osa64_Slot_ae_slot0_get, + Field_ae_fld_imm2_Slot_ae_slot0_get, + Field_ae_fld_immls64_Slot_ae_slot0_get, + Field_ae_fld_immls64pos_Slot_ae_slot0_get, + Field_ae_fld_immls64half_Slot_ae_slot0_get, + Field_ae_fld_immls32_Slot_ae_slot0_get, + Field_ae_fld_immls16_Slot_ae_slot0_get, + Field_ae_fld_osa16_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae_slot0_get, + Field_ae_fld_ls_uu_Slot_ae_slot0_get, + Field_ae_fld_ls_su_Slot_ae_slot0_get, + Field_ae_fld_ls_av_Slot_ae_slot0_get, + Field_ae_fld_ls_v1_Slot_ae_slot0_get, + Field_ae_fld_ls_v2_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae_slot0_get, + Field_ae_fld_uu_uu_Slot_ae_slot0_get, + Field_ae_fld_dr_to_ar_v0_Slot_ae_slot0_get, + Field_ae_fld_cmov_v_Slot_ae_slot0_get, + Field_ae_fld_cmov_v0_Slot_ae_slot0_get, + Field_ae_fld_pks_d_Slot_ae_slot0_get, + Field_ae_fld_pks_s_Slot_ae_slot0_get, + Field_ae_fld_shift_d_Slot_ae_slot0_get, + Field_ae_fld_shift_d0_Slot_ae_slot0_get, + Field_ae_fld_shift_sd_Slot_ae_slot0_get, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot0_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot0_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot0_get, + Field_ae_fld_to_dr_v_Slot_ae_slot0_get, + Field_ae_fld_to_dr_v0_Slot_ae_slot0_get, + Field_fld_ae_immls64neg_Slot_ae_slot0_get, + Field_ae_fld_selimm_Slot_ae_slot0_get, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot0_get, + Field_ae_fld_arth_v_Slot_ae_slot0_get, + Field_ae_fld_arth_v0_Slot_ae_slot0_get, + Field_ae_fld_arth_v1_Slot_ae_slot0_get, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_0_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_15_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_20_13_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_fld_ae_slot0_20_4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_0_0_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_20_12_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_8_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_11_0_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_4_Slot_ae_slot0_get, + 0, + 0, + 0, + Field_fld_ae_slot0_8_4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_get, + 0, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_5_2_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_7_7_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_slot0_20_14_Slot_ae_slot0_get, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_get, + 0, + 0, + Field_fld_ae_sem_cmov_bt_Slot_ae_slot0_get, + Field_fld_ae_sem_cmov_arr_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spmisc_brt_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot0_get, + 0, + Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_arr_Slot_ae_slot0_get, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae_slot0_get, + Field_dfp_fld_r_3_Slot_ae_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae_slot0_get, + Field_dfp_fld_s_0_Slot_ae_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae_slot0_set_field_fns[] = { + Field_t_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae_slot0_set, + Field_s_Slot_ae_slot0_set, + Field_imm12b_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_sal_Slot_ae_slot0_set, + Field_sargt_Slot_ae_slot0_set, + 0, + Field_sas_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae_slot0_set, + 0, + Field_r2_Slot_ae_slot0_set, + Field_t4_Slot_ae_slot0_set, + Field_s4_Slot_ae_slot0_set, + Field_r4_Slot_ae_slot0_set, + 0, + Field_s8_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae_slot0_set, + 0, + 0, + Field_ae_fld_osa32_Slot_ae_slot0_set, + Field_ae_fld_osa64_Slot_ae_slot0_set, + Field_ae_fld_imm2_Slot_ae_slot0_set, + Field_ae_fld_immls64_Slot_ae_slot0_set, + Field_ae_fld_immls64pos_Slot_ae_slot0_set, + Field_ae_fld_immls64half_Slot_ae_slot0_set, + Field_ae_fld_immls32_Slot_ae_slot0_set, + Field_ae_fld_immls16_Slot_ae_slot0_set, + Field_ae_fld_osa16_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae_slot0_set, + Field_ae_fld_ls_uu_Slot_ae_slot0_set, + Field_ae_fld_ls_su_Slot_ae_slot0_set, + Field_ae_fld_ls_av_Slot_ae_slot0_set, + Field_ae_fld_ls_v1_Slot_ae_slot0_set, + Field_ae_fld_ls_v2_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae_slot0_set, + Field_ae_fld_uu_uu_Slot_ae_slot0_set, + Field_ae_fld_dr_to_ar_v0_Slot_ae_slot0_set, + Field_ae_fld_cmov_v_Slot_ae_slot0_set, + Field_ae_fld_cmov_v0_Slot_ae_slot0_set, + Field_ae_fld_pks_d_Slot_ae_slot0_set, + Field_ae_fld_pks_s_Slot_ae_slot0_set, + Field_ae_fld_shift_d_Slot_ae_slot0_set, + Field_ae_fld_shift_d0_Slot_ae_slot0_set, + Field_ae_fld_shift_sd_Slot_ae_slot0_set, + Field_ae_fld_dr_to_dr_v_Slot_ae_slot0_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae_slot0_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae_slot0_set, + Field_ae_fld_to_dr_v_Slot_ae_slot0_set, + Field_ae_fld_to_dr_v0_Slot_ae_slot0_set, + Field_fld_ae_immls64neg_Slot_ae_slot0_set, + Field_ae_fld_selimm_Slot_ae_slot0_set, + 0, + Field_fld_ar_to_dr_imm_Slot_ae_slot0_set, + Field_ae_fld_arth_v_Slot_ae_slot0_set, + Field_ae_fld_arth_v0_Slot_ae_slot0_set, + Field_ae_fld_arth_v1_Slot_ae_slot0_set, + Field_ae_fld_ar_to_dr_v_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_3_0_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_0_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_15_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_20_13_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_fld_ae_slot0_20_4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_3_2_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_0_0_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_20_12_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_20_8_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_8_8_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_11_0_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_7_0_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_20_16_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_9_4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_11_8_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_4_Slot_ae_slot0_set, + 0, + 0, + 0, + Field_fld_ae_slot0_8_4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_4_0_Slot_ae_slot0_set, + 0, + Field_fld_ae_slot0_9_8_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_4_4_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_5_2_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae_slot0_7_4_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_7_7_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_5_4_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_slot0_20_14_Slot_ae_slot0_set, + Field_fld_ae_slot0_5_0_Slot_ae_slot0_set, + 0, + 0, + Field_fld_ae_sem_cmov_bt_Slot_ae_slot0_set, + Field_fld_ae_sem_cmov_arr_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spmisc_brt_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_spmisc_vs_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_spmisc_vr_Slot_ae_slot0_set, + 0, + Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_arr_Slot_ae_slot0_set, + Field_fld_ae_slot0_11_11_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae_slot0_set, + Field_dfp_fld_r_3_Slot_ae_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae_slot0_set, + Field_dfp_fld_s_0_Slot_ae_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae2_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x4_d0_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x4_q0_Slot_ae2_slot2_get, + 0, + Field_fld_ae_sem_mul_x4_q1_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x4_d2_Slot_ae2_slot2_get, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_get, + 0, + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_get, + 0, + Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae2_slot2_get, + Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae2_slot2_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae2_slot2_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot2_24_0_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae2_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x4_d0_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x4_q0_Slot_ae2_slot2_set, + 0, + Field_fld_ae_sem_mul_x4_q1_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_16_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x4_d2_Slot_ae2_slot2_set, + Field_fld_ae2_slot2_24_20_Slot_ae2_slot2_set, + 0, + Field_fld_ae2_slot2_7_4_Slot_ae2_slot2_set, + 0, + Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae2_slot2_set, + Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae2_slot2_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae2_slot2_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot1_get_field_fns[] = { + Field_t_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_get, + Field_s_Slot_ae2_slot1_get, + Field_imm12b_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_get, + Field_r_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_get, + Field_sal_Slot_ae2_slot1_get, + Field_sargt_Slot_ae2_slot1_get, + 0, + Field_sas_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae2_slot1_get, + Field_ae_fld_immls64pos_Slot_ae2_slot1_get, + Field_ae_fld_immls64half_Slot_ae2_slot1_get, + Field_ae_fld_immls32_Slot_ae2_slot1_get, + Field_ae_fld_immls16_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae2_slot1_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot1_get, + 0, + Field_ae_fld_to_dr_v_Slot_ae2_slot1_get, + Field_ae_fld_to_dr_v0_Slot_ae2_slot1_get, + Field_fld_ae_immls64neg_Slot_ae2_slot1_get, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_get, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_get, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_get, + 0, + 0, + Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae2_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae2_slot1_get, + Field_dfp_fld_r_3_Slot_ae2_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae2_slot1_get, + Field_dfp_fld_s_0_Slot_ae2_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot1_set_field_fns[] = { + Field_t_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae2_slot1_set, + Field_s_Slot_ae2_slot1_set, + Field_imm12b_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot1_set, + Field_r_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot1_set, + Field_sal_Slot_ae2_slot1_set, + Field_sargt_Slot_ae2_slot1_set, + 0, + Field_sas_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae2_slot1_set, + Field_ae_fld_immls64pos_Slot_ae2_slot1_set, + Field_ae_fld_immls64half_Slot_ae2_slot1_set, + Field_ae_fld_immls32_Slot_ae2_slot1_set, + Field_ae_fld_immls16_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae2_slot1_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot1_set, + 0, + Field_ae_fld_to_dr_v_Slot_ae2_slot1_set, + Field_ae_fld_to_dr_v0_Slot_ae2_slot1_set, + Field_fld_ae_immls64neg_Slot_ae2_slot1_set, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_3_0_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_12_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_16_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_17_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_0_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_13_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_4_Slot_ae2_slot1_set, + 0, + 0, + 0, + Field_fld_ae2_slot1_19_9_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot1_set, + Field_fld_ae2_slot1_7_4_Slot_ae2_slot1_set, + 0, + 0, + Field_fld_ae2_slot1_19_8_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_0_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_6_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot1_7_7_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae2_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae2_slot1_set, + Field_dfp_fld_r_3_Slot_ae2_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae2_slot1_set, + Field_dfp_fld_s_0_Slot_ae2_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae2_slot0_get_field_fns[] = { + Field_t_Slot_ae2_slot0_get, + 0, + Field_bbi_Slot_ae2_slot0_get, + 0, + Field_imm8_Slot_ae2_slot0_get, + Field_s_Slot_ae2_slot0_get, + Field_imm12b_Slot_ae2_slot0_get, + Field_imm16_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot0_get, + Field_r_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_get, + Field_sal_Slot_ae2_slot0_get, + Field_sargt_Slot_ae2_slot0_get, + 0, + Field_sas_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_get, + 0, + Field_r2_Slot_ae2_slot0_get, + Field_t4_Slot_ae2_slot0_get, + Field_s4_Slot_ae2_slot0_get, + Field_r4_Slot_ae2_slot0_get, + 0, + Field_s8_Slot_ae2_slot0_get, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_ae_fld_osa32_Slot_ae2_slot0_get, + Field_ae_fld_osa64_Slot_ae2_slot0_get, + 0, + Field_ae_fld_immls64_Slot_ae2_slot0_get, + Field_ae_fld_immls64pos_Slot_ae2_slot0_get, + Field_ae_fld_immls64half_Slot_ae2_slot0_get, + Field_ae_fld_immls32_Slot_ae2_slot0_get, + Field_ae_fld_immls16_Slot_ae2_slot0_get, + Field_ae_fld_osa16_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae2_slot0_get, + Field_ae_fld_ls_uu_Slot_ae2_slot0_get, + Field_ae_fld_ls_su_Slot_ae2_slot0_get, + Field_ae_fld_ls_av_Slot_ae2_slot0_get, + Field_ae_fld_ls_v1_Slot_ae2_slot0_get, + Field_ae_fld_ls_v2_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae2_slot0_get, + Field_ae_fld_uu_uu_Slot_ae2_slot0_get, + Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot0_get, + Field_ae_fld_cmov_v_Slot_ae2_slot0_get, + Field_ae_fld_cmov_v0_Slot_ae2_slot0_get, + 0, + 0, + Field_ae_fld_shift_d_Slot_ae2_slot0_get, + Field_ae_fld_shift_d0_Slot_ae2_slot0_get, + Field_ae_fld_shift_sd_Slot_ae2_slot0_get, + Field_ae_fld_dr_to_dr_v_Slot_ae2_slot0_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot0_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae2_slot0_get, + Field_ae_fld_to_dr_v_Slot_ae2_slot0_get, + Field_ae_fld_to_dr_v0_Slot_ae2_slot0_get, + Field_fld_ae_immls64neg_Slot_ae2_slot0_get, + Field_ae_fld_selimm_Slot_ae2_slot0_get, + 0, + Field_fld_ar_to_dr_imm_Slot_ae2_slot0_get, + Field_ae_fld_arth_v_Slot_ae2_slot0_get, + Field_ae_fld_arth_v0_Slot_ae2_slot0_get, + Field_ae_fld_arth_v1_Slot_ae2_slot0_get, + Field_ae_fld_ar_to_dr_v_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_get, + 0, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_get, + 0, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_get, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_get, + 0, + Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_get, + 0, + 0, + Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_get, + 0, + 0, + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_get, + 0, + 0, + Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_get, + 0, + 0, + 0, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_get, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_get, + 0, + 0, + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae2_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae2_slot0_get, + Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae2_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae2_slot0_get, + Field_dfp_fld_r_3_Slot_ae2_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae2_slot0_get, + Field_dfp_fld_s_0_Slot_ae2_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae2_slot0_set_field_fns[] = { + Field_t_Slot_ae2_slot0_set, + 0, + Field_bbi_Slot_ae2_slot0_set, + 0, + Field_imm8_Slot_ae2_slot0_set, + Field_s_Slot_ae2_slot0_set, + Field_imm12b_Slot_ae2_slot0_set, + Field_imm16_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae2_slot0_set, + Field_r_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae2_slot0_set, + Field_sal_Slot_ae2_slot0_set, + Field_sargt_Slot_ae2_slot0_set, + 0, + Field_sas_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae2_slot0_set, + 0, + Field_r2_Slot_ae2_slot0_set, + Field_t4_Slot_ae2_slot0_set, + Field_s4_Slot_ae2_slot0_set, + Field_r4_Slot_ae2_slot0_set, + 0, + Field_s8_Slot_ae2_slot0_set, + 0, + Field_xt_wbr15_imm_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_ae_fld_osa32_Slot_ae2_slot0_set, + Field_ae_fld_osa64_Slot_ae2_slot0_set, + 0, + Field_ae_fld_immls64_Slot_ae2_slot0_set, + Field_ae_fld_immls64pos_Slot_ae2_slot0_set, + Field_ae_fld_immls64half_Slot_ae2_slot0_set, + Field_ae_fld_immls32_Slot_ae2_slot0_set, + Field_ae_fld_immls16_Slot_ae2_slot0_set, + Field_ae_fld_osa16_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae2_slot0_set, + Field_ae_fld_ls_uu_Slot_ae2_slot0_set, + Field_ae_fld_ls_su_Slot_ae2_slot0_set, + Field_ae_fld_ls_av_Slot_ae2_slot0_set, + Field_ae_fld_ls_v1_Slot_ae2_slot0_set, + Field_ae_fld_ls_v2_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae2_slot0_set, + Field_ae_fld_uu_uu_Slot_ae2_slot0_set, + Field_ae_fld_dr_to_ar_v0_Slot_ae2_slot0_set, + Field_ae_fld_cmov_v_Slot_ae2_slot0_set, + Field_ae_fld_cmov_v0_Slot_ae2_slot0_set, + 0, + 0, + Field_ae_fld_shift_d_Slot_ae2_slot0_set, + Field_ae_fld_shift_d0_Slot_ae2_slot0_set, + Field_ae_fld_shift_sd_Slot_ae2_slot0_set, + Field_ae_fld_dr_to_dr_v_Slot_ae2_slot0_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae2_slot0_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae2_slot0_set, + Field_ae_fld_to_dr_v_Slot_ae2_slot0_set, + Field_ae_fld_to_dr_v0_Slot_ae2_slot0_set, + Field_fld_ae_immls64neg_Slot_ae2_slot0_set, + Field_ae_fld_selimm_Slot_ae2_slot0_set, + 0, + Field_fld_ar_to_dr_imm_Slot_ae2_slot0_set, + Field_ae_fld_arth_v_Slot_ae2_slot0_set, + Field_ae_fld_arth_v0_Slot_ae2_slot0_set, + Field_ae_fld_arth_v1_Slot_ae2_slot0_set, + Field_ae_fld_ar_to_dr_v_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_11_4_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_4_Slot_ae2_slot0_set, + 0, + Field_fld_ae2_slot0_11_9_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_28_27_Slot_ae2_slot0_set, + 0, + Field_fld_ae2_slot0_11_8_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_3_0_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_17_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_20_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_13_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_3_2_Slot_ae2_slot0_set, + 0, + Field_fld_ae2_slot0_0_0_Slot_ae2_slot0_set, + 0, + Field_fld_ae2_slot0_28_12_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_loads_stores_end_Slot_ae2_slot0_set, + 0, + 0, + Field_fld_ae2_slot0_28_8_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_11_0_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae2_slot0_28_16_Slot_ae2_slot0_set, + 0, + 0, + Field_fld_ae2_slot0_9_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_8_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_4_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae2_slot0_5_2_Slot_ae2_slot0_set, + 0, + 0, + Field_fld_ae2_slot0_5_0_Slot_ae2_slot0_set, + 0, + 0, + 0, + Field_fld_ae2_slot0_7_0_Slot_ae2_slot0_set, + Field_fld_ae2_slot0_7_7_Slot_ae2_slot0_set, + 0, + 0, + Field_fld_ae2_slot0_5_4_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_sp32cvt_vr_Slot_ae2_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_vt_Slot_ae2_slot0_set, + Field_fld_vfpu2_sem_sp32cvt_i_imm5_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae2_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae2_slot0_set, + Field_dfp_fld_r_3_Slot_ae2_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae2_slot0_set, + Field_dfp_fld_s_0_Slot_ae2_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot1_get_field_fns[] = { + Field_t_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_get, + Field_s_Slot_ae3_slot1_get, + Field_imm12b_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_get, + Field_r_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_get, + Field_sal_Slot_ae3_slot1_get, + Field_sargt_Slot_ae3_slot1_get, + 0, + Field_sas_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae3_slot1_get, + Field_ae_fld_immls64pos_Slot_ae3_slot1_get, + Field_ae_fld_immls64half_Slot_ae3_slot1_get, + Field_ae_fld_immls32_Slot_ae3_slot1_get, + Field_ae_fld_immls16_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae3_slot1_get, + Field_ae_fld_dr_to_dr_v0_Slot_ae3_slot1_get, + Field_ae_fld_dr_to_dr_v1_Slot_ae3_slot1_get, + Field_ae_fld_to_dr_v_Slot_ae3_slot1_get, + Field_ae_fld_to_dr_v0_Slot_ae3_slot1_get, + Field_fld_ae_immls64neg_Slot_ae3_slot1_get, + Field_ae_fld_selimm_Slot_ae3_slot1_get, + 0, + Field_fld_ar_to_dr_imm_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_get, + 0, + 0, + 0, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_get, + 0, + 0, + Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot1_get, + 0, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_get, + Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot1_get, + Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae3_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae3_slot1_get, + Field_dfp_fld_r_3_Slot_ae3_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae3_slot1_get, + Field_dfp_fld_s_0_Slot_ae3_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae3_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot1_set_field_fns[] = { + Field_t_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot1_set, + Field_s_Slot_ae3_slot1_set, + Field_imm12b_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot1_set, + Field_r_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot1_set, + Field_sal_Slot_ae3_slot1_set, + Field_sargt_Slot_ae3_slot1_set, + 0, + Field_sas_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae3_slot1_set, + Field_ae_fld_immls64pos_Slot_ae3_slot1_set, + Field_ae_fld_immls64half_Slot_ae3_slot1_set, + Field_ae_fld_immls32_Slot_ae3_slot1_set, + Field_ae_fld_immls16_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_dr_to_dr_v_Slot_ae3_slot1_set, + Field_ae_fld_dr_to_dr_v0_Slot_ae3_slot1_set, + Field_ae_fld_dr_to_dr_v1_Slot_ae3_slot1_set, + Field_ae_fld_to_dr_v_Slot_ae3_slot1_set, + Field_ae_fld_to_dr_v0_Slot_ae3_slot1_set, + Field_fld_ae_immls64neg_Slot_ae3_slot1_set, + Field_ae_fld_selimm_Slot_ae3_slot1_set, + 0, + Field_fld_ar_to_dr_imm_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_8_Slot_ae3_slot1_set, + 0, + 0, + 0, + Field_fld_ae3_slot1_3_0_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_12_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_16_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_17_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_0_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_4_Slot_ae3_slot1_set, + 0, + 0, + Field_fld_ae3_slot1_19_13_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_19_4_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_1_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot1_set, + 0, + Field_fld_ae3_slot1_3_2_Slot_ae3_slot1_set, + Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot1_set, + Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_6_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot1_7_7_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae3_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae3_slot1_set, + Field_dfp_fld_r_3_Slot_ae3_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae3_slot1_set, + Field_dfp_fld_s_0_Slot_ae3_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae3_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae3_slot0_get_field_fns[] = { + Field_t_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot0_get, + Field_s_Slot_ae3_slot0_get, + Field_imm12b_Slot_ae3_slot0_get, + Field_imm16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot0_get, + Field_r_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_get, + Field_sal_Slot_ae3_slot0_get, + Field_sargt_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_get, + 0, + Field_r2_Slot_ae3_slot0_get, + Field_t4_Slot_ae3_slot0_get, + 0, + Field_r4_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae3_slot0_get, + Field_ae_fld_fhba4_2_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae3_slot0_get, + Field_ae_fld_immls64pos_Slot_ae3_slot0_get, + Field_ae_fld_immls64half_Slot_ae3_slot0_get, + Field_ae_fld_immls32_Slot_ae3_slot0_get, + Field_ae_fld_immls16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae3_slot0_get, + Field_ae_fld_ls_uu_Slot_ae3_slot0_get, + Field_ae_fld_ls_su_Slot_ae3_slot0_get, + Field_ae_fld_ls_av_Slot_ae3_slot0_get, + Field_ae_fld_ls_v1_Slot_ae3_slot0_get, + Field_ae_fld_ls_v2_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae3_slot0_get, + Field_ae_fld_uu_uu_Slot_ae3_slot0_get, + Field_ae_fld_dr_to_ar_v0_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_to_dr_v_Slot_ae3_slot0_get, + Field_ae_fld_to_dr_v0_Slot_ae3_slot0_get, + Field_fld_ae_immls64neg_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_get, + 0, + Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot0_get, + Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_get, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_get, + 0, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_get, + Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_get, + 0, + 0, + Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae3_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae3_slot0_get, + Field_dfp_fld_r_3_Slot_ae3_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae3_slot0_get, + Field_dfp_fld_s_0_Slot_ae3_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae3_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae3_slot0_set_field_fns[] = { + Field_t_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae3_slot0_set, + Field_s_Slot_ae3_slot0_set, + Field_imm12b_Slot_ae3_slot0_set, + Field_imm16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae3_slot0_set, + Field_r_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae3_slot0_set, + Field_sal_Slot_ae3_slot0_set, + Field_sargt_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_ae3_slot0_set, + 0, + Field_r2_Slot_ae3_slot0_set, + Field_t4_Slot_ae3_slot0_set, + 0, + Field_r4_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_fhba4_Slot_ae3_slot0_set, + Field_ae_fld_fhba4_2_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae3_slot0_set, + Field_ae_fld_immls64pos_Slot_ae3_slot0_set, + Field_ae_fld_immls64half_Slot_ae3_slot0_set, + Field_ae_fld_immls32_Slot_ae3_slot0_set, + Field_ae_fld_immls16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae3_slot0_set, + Field_ae_fld_ls_uu_Slot_ae3_slot0_set, + Field_ae_fld_ls_su_Slot_ae3_slot0_set, + Field_ae_fld_ls_av_Slot_ae3_slot0_set, + Field_ae_fld_ls_v1_Slot_ae3_slot0_set, + Field_ae_fld_ls_v2_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae3_slot0_set, + Field_ae_fld_uu_uu_Slot_ae3_slot0_set, + Field_ae_fld_dr_to_ar_v0_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_to_dr_v_Slot_ae3_slot0_set, + Field_ae_fld_to_dr_v0_Slot_ae3_slot0_set, + Field_fld_ae_immls64neg_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_ae_fld_ar_to_dr_v_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_3_0_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_12_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_16_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_17_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_20_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae3_slot0_7_4_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_0_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_13_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_11_8_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_8_8_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_ep_ls_ei_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_3_2_Slot_ae3_slot0_set, + 0, + Field_fld_ae_sem_ep_ls_ar_s_Slot_ae3_slot0_set, + Field_fld_ae_sem_ep_ls_eo_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_4_Slot_ae3_slot0_set, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_0_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_4_0_Slot_ae3_slot0_set, + 0, + Field_fld_ae3_slot0_9_8_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_7_6_Slot_ae3_slot0_set, + Field_fld_ae3_slot0_21_14_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_5_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_5_2_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae3_slot0_21_2_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae3_slot0_21_8_Slot_ae3_slot0_set, + 0, + 0, + Field_fld_ae3_slot0_21_4_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae3_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae3_slot0_set, + Field_dfp_fld_r_3_Slot_ae3_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae3_slot0_set, + Field_dfp_fld_s_0_Slot_ae3_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae3_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot1_get_field_fns[] = { + Field_t_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_get, + 0, + Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae4_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae4_slot1_get, + Field_dfp_fld_r_3_Slot_ae4_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae4_slot1_get, + Field_dfp_fld_s_0_Slot_ae4_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae4_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot1_set_field_fns[] = { + Field_t_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_8_Slot_ae4_slot1_set, + 0, + Field_fld_ae4_slot1_13_11_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_12_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot1_13_0_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae4_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae4_slot1_set, + Field_dfp_fld_r_3_Slot_ae4_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae4_slot1_set, + Field_dfp_fld_s_0_Slot_ae4_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae4_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae4_slot0_get_field_fns[] = { + Field_t_Slot_ae4_slot0_get, + 0, + Field_bbi_Slot_ae4_slot0_get, + 0, + 0, + Field_s_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_get, + 0, + 0, + Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_get, + 0, + 0, + Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_get, + Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae4_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae4_slot0_get, + Field_dfp_fld_r_3_Slot_ae4_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae4_slot0_get, + Field_dfp_fld_s_0_Slot_ae4_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae4_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae4_slot0_set_field_fns[] = { + Field_t_Slot_ae4_slot0_set, + 0, + Field_bbi_Slot_ae4_slot0_set, + 0, + 0, + Field_s_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_xt_wbr15_imm_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_7_4_Slot_ae4_slot0_set, + 0, + 0, + Field_fld_ae4_slot0_27_24_Slot_ae4_slot0_set, + 0, + 0, + Field_fld_ae4_slot0_27_23_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae4_slot0_2_0_Slot_ae4_slot0_set, + Field_fld_ae4_slot0_27_3_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae4_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae4_slot0_set, + Field_dfp_fld_r_3_Slot_ae4_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae4_slot0_set, + Field_dfp_fld_s_0_Slot_ae4_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae4_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae5_slot2_get, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae5_slot2_get, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae5_slot2_get, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae5_slot2_get, + Field_fld_ae_sem_mul_x4_d0_Slot_ae5_slot2_get, + Field_fld_ae_sem_mul_x4_q0_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae5_slot2_get, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae5_slot2_get, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae5_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_19_0_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d1_Slot_ae5_slot2_set, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae5_slot2_set, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae5_slot2_set, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae5_slot2_set, + Field_fld_ae_sem_mul_x4_d0_Slot_ae5_slot2_set, + Field_fld_ae_sem_mul_x4_q0_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot2_19_12_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_vfpu2_sem_spfma_vt_Slot_ae5_slot2_set, + Field_fld_vfpu2_sem_spfma_vs_Slot_ae5_slot2_set, + Field_fld_vfpu2_sem_spfma_vr_Slot_ae5_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot1_0_0_Slot_ae5_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae5_slot0_get_field_fns[] = { + Field_t_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_imm8_Slot_ae5_slot0_get, + Field_s_Slot_ae5_slot0_get, + Field_imm12b_Slot_ae5_slot0_get, + Field_imm16_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae5_slot0_get, + Field_r_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_get, + Field_sal_Slot_ae5_slot0_get, + Field_sargt_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae5_slot0_get, + Field_ae_fld_immls64pos_Slot_ae5_slot0_get, + Field_ae_fld_immls64half_Slot_ae5_slot0_get, + Field_ae_fld_immls32_Slot_ae5_slot0_get, + Field_ae_fld_immls16_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae5_slot0_get, + Field_ae_fld_ls_uu_Slot_ae5_slot0_get, + Field_ae_fld_ls_su_Slot_ae5_slot0_get, + Field_ae_fld_ls_av_Slot_ae5_slot0_get, + Field_ae_fld_ls_v1_Slot_ae5_slot0_get, + Field_ae_fld_ls_v2_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae5_slot0_get, + Field_ae_fld_uu_uu_Slot_ae5_slot0_get, + Field_ae_fld_dr_to_ar_v0_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_to_dr_v_Slot_ae5_slot0_get, + Field_ae_fld_to_dr_v0_Slot_ae5_slot0_get, + Field_fld_ae_immls64neg_Slot_ae5_slot0_get, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae5_slot0_get, + Field_ae_fld_arth_v_Slot_ae5_slot0_get, + Field_ae_fld_arth_v0_Slot_ae5_slot0_get, + Field_ae_fld_arth_v1_Slot_ae5_slot0_get, + Field_ae_fld_ar_to_dr_v_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_get, + 0, + 0, + 0, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_get, + 0, + 0, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_get, + 0, + Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_get, + Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae5_slot0_get, + Field_dfp_fld_r_2_1_Slot_ae5_slot0_get, + Field_dfp_fld_r_3_Slot_ae5_slot0_get, + Field_dfp_fld_r_3_1_Slot_ae5_slot0_get, + Field_dfp_fld_s_0_Slot_ae5_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae5_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae5_slot0_set_field_fns[] = { + Field_t_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_imm8_Slot_ae5_slot0_set, + Field_s_Slot_ae5_slot0_set, + Field_imm12b_Slot_ae5_slot0_set, + Field_imm16_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_ae5_slot0_set, + Field_r_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + Field_sae_Slot_ae5_slot0_set, + Field_sal_Slot_ae5_slot0_set, + Field_sargt_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae5_slot0_set, + Field_ae_fld_immls64pos_Slot_ae5_slot0_set, + Field_ae_fld_immls64half_Slot_ae5_slot0_set, + Field_ae_fld_immls32_Slot_ae5_slot0_set, + Field_ae_fld_immls16_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae5_slot0_set, + Field_ae_fld_ls_uu_Slot_ae5_slot0_set, + Field_ae_fld_ls_su_Slot_ae5_slot0_set, + Field_ae_fld_ls_av_Slot_ae5_slot0_set, + Field_ae_fld_ls_v1_Slot_ae5_slot0_set, + Field_ae_fld_ls_v2_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_ae_fld_uu_v_Slot_ae5_slot0_set, + Field_ae_fld_uu_uu_Slot_ae5_slot0_set, + Field_ae_fld_dr_to_ar_v0_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_to_dr_v_Slot_ae5_slot0_set, + Field_ae_fld_to_dr_v0_Slot_ae5_slot0_set, + Field_fld_ae_immls64neg_Slot_ae5_slot0_set, + 0, + 0, + Field_fld_ar_to_dr_imm_Slot_ae5_slot0_set, + Field_ae_fld_arth_v_Slot_ae5_slot0_set, + Field_ae_fld_arth_v0_Slot_ae5_slot0_set, + Field_ae_fld_arth_v1_Slot_ae5_slot0_set, + Field_ae_fld_ar_to_dr_v_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_8_Slot_ae5_slot0_set, + 0, + 0, + 0, + Field_fld_ae5_slot0_3_0_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_12_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_16_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_17_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_20_Slot_ae5_slot0_set, + 0, + 0, + Field_fld_ae5_slot0_7_4_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_0_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_13_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_11_8_Slot_ae5_slot0_set, + 0, + Field_fld_ae5_slot0_21_6_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_21_4_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_7_6_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_5_4_Slot_ae5_slot0_set, + Field_fld_ae5_slot0_21_14_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_7_7_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae5_slot0_3_2_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae5_slot0_set, + Field_dfp_fld_r_2_1_Slot_ae5_slot0_set, + Field_dfp_fld_r_3_Slot_ae5_slot0_set, + Field_dfp_fld_r_3_1_Slot_ae5_slot0_set, + Field_dfp_fld_s_0_Slot_ae5_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae5_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_arth_v_Slot_ae6_slot3_get, + Field_ae_fld_arth_v0_Slot_ae6_slot3_get, + Field_ae_fld_arth_v1_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_get, + Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_arth_v_Slot_ae6_slot3_set, + Field_ae_fld_arth_v0_Slot_ae6_slot3_set, + Field_ae_fld_arth_v1_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot3_17_0_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_arithmetic_ds_Slot_ae6_slot3_set, + Field_fld_ae6_slot3_17_16_Slot_ae6_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_arth_v_Slot_ae6_slot2_get, + 0, + Field_ae_fld_arth_v1_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae6_slot2_get, + Field_fld_ae_sem_mul_x4_d0_Slot_ae6_slot2_get, + Field_fld_ae_sem_mul_x4_q0_Slot_ae6_slot2_get, + Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_arth_v_Slot_ae6_slot2_set, + 0, + Field_ae_fld_arth_v1_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_13_0_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot2_3_0_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x4_d1_Slot_ae6_slot2_set, + Field_fld_ae_sem_mul_x4_d0_Slot_ae6_slot2_set, + Field_fld_ae_sem_mul_x4_q0_Slot_ae6_slot2_set, + Field_fld_ae6_slot2_13_12_Slot_ae6_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot1_get_field_fns[] = { + Field_t_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae6_slot1_get, + Field_ae_fld_immls64pos_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae6_slot1_get, + Field_ae_fld_ls_uu_Slot_ae6_slot1_get, + 0, + Field_ae_fld_ls_av_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_get, + Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae6_slot1_get, + Field_dfp_fld_r_2_1_Slot_ae6_slot1_get, + Field_dfp_fld_r_3_Slot_ae6_slot1_get, + Field_dfp_fld_r_3_1_Slot_ae6_slot1_get, + Field_dfp_fld_s_0_Slot_ae6_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae6_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot1_set_field_fns[] = { + Field_t_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae6_slot1_set, + Field_ae_fld_immls64pos_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae6_slot1_set, + Field_ae_fld_ls_uu_Slot_ae6_slot1_set, + 0, + Field_ae_fld_ls_av_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_0_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_14_12_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_7_7_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot1_7_6_Slot_ae6_slot1_set, + Field_fld_ae6_slot1_14_6_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_r_0_Slot_ae6_slot1_set, + Field_dfp_fld_r_2_1_Slot_ae6_slot1_set, + Field_dfp_fld_r_3_Slot_ae6_slot1_set, + Field_dfp_fld_r_3_1_Slot_ae6_slot1_set, + Field_dfp_fld_s_0_Slot_ae6_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae6_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae6_slot0_get_field_fns[] = { + Field_t_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae6_slot0_get, + Field_ae_fld_immls64pos_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_get, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae6_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae6_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae6_slot0_set_field_fns[] = { + Field_t_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae6_slot0_set, + Field_ae_fld_immls64pos_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_15_0_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae6_slot0_15_12_Slot_ae6_slot0_set, + Field_fld_ae6_slot0_7_7_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae6_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae6_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot3_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae7_slot3_get, + Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_get, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d2_Slot_ae7_slot3_get, + Field_fld_ae_sem_mul_x2_s2_v1_Slot_ae7_slot3_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot3_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_18_0_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d0_Slot_ae7_slot3_set, + Field_fld_ae_sem_mul_x2_s2_q0_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot3_18_16_Slot_ae7_slot3_set, + 0, + 0, + Field_fld_ae_sem_mul_x2_s2_d2_Slot_ae7_slot3_set, + Field_fld_ae_sem_mul_x2_s2_v1_Slot_ae7_slot3_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae7_slot2_get, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_get, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae7_slot2_get, + Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae7_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_18_0_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d0_Slot_ae7_slot2_set, + Field_fld_ae_sem_mul_x2_s1_q0_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot2_18_16_Slot_ae7_slot2_set, + 0, + 0, + Field_fld_ae_sem_mul_x2_s1_d2_Slot_ae7_slot2_set, + Field_fld_ae_sem_mul_x2_s1_v1_Slot_ae7_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot1_get_field_fns[] = { + Field_t_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae7_slot1_get, + Field_ae_fld_immls64pos_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae7_slot1_get, + Field_dfp_fld_s_3_1_Slot_ae7_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot1_set_field_fns[] = { + Field_t_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae7_slot1_set, + Field_ae_fld_immls64pos_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_15_0_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_7_4_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_15_12_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot1_7_7_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae7_slot1_set, + Field_dfp_fld_s_3_1_Slot_ae7_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_ae7_slot0_get_field_fns[] = { + Field_t_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae7_slot0_get, + Field_ae_fld_immls64pos_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae7_slot0_get, + Field_ae_fld_ls_uu_Slot_ae7_slot0_get, + 0, + Field_ae_fld_ls_av_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae7_slot0_get, + Field_dfp_fld_s_3_1_Slot_ae7_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_ae7_slot0_set_field_fns[] = { + Field_t_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_immls64_Slot_ae7_slot0_set, + Field_ae_fld_immls64pos_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_ae_fld_ls_v_Slot_ae7_slot0_set, + Field_ae_fld_ls_uu_Slot_ae7_slot0_set, + 0, + Field_ae_fld_ls_av_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_15_0_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_4_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_15_12_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_7_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_fld_ae7_slot0_7_6_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dfp_fld_s_0_Slot_ae7_slot0_set, + Field_dfp_fld_s_3_1_Slot_ae7_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "ae_slot3", "ae_format88", 3, + Slot_ae_format88_Format_ae_slot3_32_get, Slot_ae_format88_Format_ae_slot3_32_set, + Slot_ae_slot3_get_field_fns, Slot_ae_slot3_set_field_fns, + Slot_ae_slot3_decode, "nop" }, + { "ae_slot2", "ae_format88", 2, + Slot_ae_format88_Format_ae_slot2_28_get, Slot_ae_format88_Format_ae_slot2_28_set, + Slot_ae_slot2_get_field_fns, Slot_ae_slot2_set_field_fns, + Slot_ae_slot2_decode, "nop" }, + { "ae_slot1", "ae_format88", 1, + Slot_ae_format88_Format_ae_slot1_16_get, Slot_ae_format88_Format_ae_slot1_16_set, + Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, + Slot_ae_slot1_decode, "nop" }, + { "ae_slot0", "ae_format88", 0, + Slot_ae_format88_Format_ae_slot0_5_get, Slot_ae_format88_Format_ae_slot0_5_set, + Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, + Slot_ae_slot0_decode, "nop" }, + { "ae2_slot2", "ae_format88_2", 2, + Slot_ae_format88_2_Format_ae2_slot2_28_get, Slot_ae_format88_2_Format_ae2_slot2_28_set, + Slot_ae2_slot2_get_field_fns, Slot_ae2_slot2_set_field_fns, + Slot_ae2_slot2_decode, "nop" }, + { "ae2_slot1", "ae_format88_2", 1, + Slot_ae_format88_2_Format_ae2_slot1_16_get, Slot_ae_format88_2_Format_ae2_slot1_16_set, + Slot_ae2_slot1_get_field_fns, Slot_ae2_slot1_set_field_fns, + Slot_ae2_slot1_decode, "nop" }, + { "ae2_slot0", "ae_format88_2", 0, + Slot_ae_format88_2_Format_ae2_slot0_6_get, Slot_ae_format88_2_Format_ae2_slot0_6_set, + Slot_ae2_slot0_get_field_fns, Slot_ae2_slot0_set_field_fns, + Slot_ae2_slot0_decode, "nop" }, + { "ae3_slot1", "ae_format48", 1, + Slot_ae_format48_Format_ae3_slot1_16_get, Slot_ae_format48_Format_ae3_slot1_16_set, + Slot_ae3_slot1_get_field_fns, Slot_ae3_slot1_set_field_fns, + Slot_ae3_slot1_decode, "nop" }, + { "ae3_slot0", "ae_format48", 0, + Slot_ae_format48_Format_ae3_slot0_4_get, Slot_ae_format48_Format_ae3_slot0_4_set, + Slot_ae3_slot0_get_field_fns, Slot_ae3_slot0_set_field_fns, + Slot_ae3_slot0_decode, "nop" }, + { "ae4_slot1", "ae_format48_2", 1, + Slot_ae_format48_2_Format_ae4_slot1_16_get, Slot_ae_format48_2_Format_ae4_slot1_16_set, + Slot_ae4_slot1_get_field_fns, Slot_ae4_slot1_set_field_fns, + Slot_ae4_slot1_decode, "nop" }, + { "ae4_slot0", "ae_format48_2", 0, + Slot_ae_format48_2_Format_ae4_slot0_4_get, Slot_ae_format48_2_Format_ae4_slot0_4_set, + Slot_ae4_slot0_get_field_fns, Slot_ae4_slot0_set_field_fns, + Slot_ae4_slot0_decode, "nop" }, + { "ae5_slot2", "ae_format48_3", 2, + Slot_ae_format48_3_Format_ae5_slot2_16_get, Slot_ae_format48_3_Format_ae5_slot2_16_set, + Slot_ae5_slot2_get_field_fns, Slot_ae5_slot2_set_field_fns, + Slot_ae5_slot2_decode, "nop" }, + { "ae5_slot1", "ae_format48_3", 1, + Slot_ae_format48_3_Format_ae5_slot1_38_get, Slot_ae_format48_3_Format_ae5_slot1_38_set, + Slot_ae5_slot1_get_field_fns, Slot_ae5_slot1_set_field_fns, + Slot_ae5_slot1_decode, "nop" }, + { "ae5_slot0", "ae_format48_3", 0, + Slot_ae_format48_3_Format_ae5_slot0_4_get, Slot_ae_format48_3_Format_ae5_slot0_4_set, + Slot_ae5_slot0_get_field_fns, Slot_ae5_slot0_set_field_fns, + Slot_ae5_slot0_decode, "nop" }, + { "ae6_slot3", "ae_format88_3", 3, + Slot_ae_format88_3_Format_ae6_slot3_32_get, Slot_ae_format88_3_Format_ae6_slot3_32_set, + Slot_ae6_slot3_get_field_fns, Slot_ae6_slot3_set_field_fns, + Slot_ae6_slot3_decode, "nop" }, + { "ae6_slot2", "ae_format88_3", 2, + Slot_ae_format88_3_Format_ae6_slot2_28_get, Slot_ae_format88_3_Format_ae6_slot2_28_set, + Slot_ae6_slot2_get_field_fns, Slot_ae6_slot2_set_field_fns, + Slot_ae6_slot2_decode, "nop" }, + { "ae6_slot1", "ae_format88_3", 1, + Slot_ae_format88_3_Format_ae6_slot1_16_get, Slot_ae_format88_3_Format_ae6_slot1_16_set, + Slot_ae6_slot1_get_field_fns, Slot_ae6_slot1_set_field_fns, + Slot_ae6_slot1_decode, "nop" }, + { "ae6_slot0", "ae_format88_3", 0, + Slot_ae_format88_3_Format_ae6_slot0_6_get, Slot_ae_format88_3_Format_ae6_slot0_6_set, + Slot_ae6_slot0_get_field_fns, Slot_ae6_slot0_set_field_fns, + Slot_ae6_slot0_decode, "nop" }, + { "ae7_slot3", "ae_format88_4", 3, + Slot_ae_format88_4_Format_ae7_slot3_12_get, Slot_ae_format88_4_Format_ae7_slot3_12_set, + Slot_ae7_slot3_get_field_fns, Slot_ae7_slot3_set_field_fns, + Slot_ae7_slot3_decode, "nop" }, + { "ae7_slot2", "ae_format88_4", 2, + Slot_ae_format88_4_Format_ae7_slot2_20_get, Slot_ae_format88_4_Format_ae7_slot2_20_set, + Slot_ae7_slot2_get_field_fns, Slot_ae7_slot2_set_field_fns, + Slot_ae7_slot2_decode, "nop" }, + { "ae7_slot1", "ae_format88_4", 1, + Slot_ae_format88_4_Format_ae7_slot1_16_get, Slot_ae_format88_4_Format_ae7_slot1_16_set, + Slot_ae7_slot1_get_field_fns, Slot_ae7_slot1_set_field_fns, + Slot_ae7_slot1_decode, "nop" }, + { "ae7_slot0", "ae_format88_4", 0, + Slot_ae_format88_4_Format_ae7_slot0_6_get, Slot_ae_format88_4_Format_ae7_slot0_6_set, + Slot_ae7_slot0_get_field_fns, Slot_ae7_slot0_set_field_fns, + Slot_ae7_slot0_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_ae_format88_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x1f; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_ae_format88_2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_ae_format48_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0xc000; + insn[2] = 0; +} + +static void +Format_ae_format48_2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0x8000; + insn[2] = 0; +} + +static void +Format_ae_format48_3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xe; + insn[1] = 0; + insn[2] = 0; +} + +static void +Format_ae_format88_3_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0x11000; +} + +static void +Format_ae_format88_4_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; + insn[2] = 0x10000; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_ae_format88_slots[] = { 6, 5, 4, 3 }; + +static int Format_ae_format88_2_slots[] = { 9, 8, 7 }; + +static int Format_ae_format48_slots[] = { 11, 10 }; + +static int Format_ae_format48_2_slots[] = { 13, 12 }; + +static int Format_ae_format48_3_slots[] = { 16, 14, 15 }; + +static int Format_ae_format88_3_slots[] = { 20, 19, 18, 17 }; + +static int Format_ae_format88_4_slots[] = { 24, 21, 23, 22 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "ae_format88", 11, Format_ae_format88_encode, 4, Format_ae_format88_slots }, + { "ae_format88_2", 11, Format_ae_format88_2_encode, 3, Format_ae_format88_2_slots }, + { "ae_format48", 6, Format_ae_format48_encode, 2, Format_ae_format48_slots }, + { "ae_format48_2", 6, Format_ae_format48_2_encode, 2, Format_ae_format48_2_slots }, + { "ae_format48_3", 6, Format_ae_format48_3_encode, 3, Format_ae_format48_3_slots }, + { "ae_format88_3", 11, Format_ae_format88_3_encode, 4, Format_ae_format88_3_slots }, + { "ae_format88_4", 11, Format_ae_format88_4_encode, 4, Format_ae_format88_4_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0 && (insn[2] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0 && (insn[2] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0x1f) == 0x1f && (insn[1] & 0) == 0 && (insn[2] & 0) == 0) + return 3; /* ae_format88 */ + if ((insn[0] & 0x3f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0xff0000) == 0) + return 4; /* ae_format88_2 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0xc000) == 0xc000 && (insn[2] & 0) == 0) + return 5; /* ae_format48 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0xc000) == 0x8000 && (insn[2] & 0) == 0) + return 6; /* ae_format48_2 */ + if ((insn[0] & 0xf) == 0xe && (insn[1] & 0x8000) == 0 && (insn[2] & 0) == 0) + return 7; /* ae_format48_3 */ + if ((insn[0] & 0x3f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0xffffe0) == 0x11000) + return 8; /* ae_format88_3 */ + if ((insn[0] & 0x3f) == 0xf && (insn[1] & 0) == 0 && (insn[2] & 0xfff000) == 0x10000) + return 9; /* ae_format88_4 */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 6, + 11 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 11 /* insn_size */, 0, + 10, formats, format_decoder, length_decoder, + 25, slots, + 406 /* num_fields */, + 554, operands, + 1548, iclasses, + 1713, opcodes, 0, + 10, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 6, interfaces, 0, + 9, funcUnits, 0 +}; diff --git a/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/gdbserver/xtensa-regmap.c b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/gdbserver/xtensa-regmap.c new file mode 100644 index 00000000..399943bb --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/gdbserver/xtensa-regmap.c @@ -0,0 +1,86 @@ +/* Customized table mapping between kernel xtregset and GDB register cache. + + Copyright (c) 2007-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +typedef struct { + int gdb_regnum; + int gdb_offset; + int ptrace_cp_offset; + int ptrace_offset; + int size; + int coproc; + int dbnum; + char* name +;} xtensa_regtable_t; + +#define XTENSA_ELF_XTREG_SIZE 256 + +const xtensa_regtable_t xtensa_regmap_table[] = { + /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ + { 44, 176, 8, 8, 4, -1, 0x0204, "br" }, + { 45, 180, 12, 12, 4, -1, 0x020c, "scompare1" }, + { 46, 184, 0, 0, 4, -1, 0x0210, "acclo" }, + { 47, 188, 4, 4, 4, -1, 0x0211, "acchi" }, + { 48, 192, 16, 16, 4, -1, 0x0220, "m0" }, + { 49, 196, 20, 20, 4, -1, 0x0221, "m1" }, + { 50, 200, 24, 24, 4, -1, 0x0222, "m2" }, + { 51, 204, 28, 28, 4, -1, 0x0223, "m3" }, + { 53, 212, 32, 32, 4, -1, 0x03ea, "f64r_lo" }, + { 54, 216, 36, 36, 4, -1, 0x03eb, "f64r_hi" }, + { 55, 220, 40, 40, 4, -1, 0x03ec, "f64s" }, + { 56, 224, 8, 56, 4, 1, 0x03f0, "ae_ovf_sar" }, + { 57, 228, 12, 60, 4, 1, 0x03f1, "ae_bithead" }, + { 58, 232, 16, 64, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, + { 59, 236, 20, 68, 4, 1, 0x03f3, "ae_cw_sd_no" }, + { 60, 240, 24, 72, 4, 1, 0x03f6, "ae_cbegin0" }, + { 61, 244, 28, 76, 4, 1, 0x03f7, "ae_cend0" }, + { 62, 248, 32, 80, 4, 1, 0x03f8, "ae_cbegin1" }, + { 63, 252, 36, 84, 4, 1, 0x03f9, "ae_cend1" }, + { 64, 256, 40, 88, 8, 1, 0x1010, "aed0" }, + { 65, 264, 48, 96, 8, 1, 0x1011, "aed1" }, + { 66, 272, 56, 104, 8, 1, 0x1012, "aed2" }, + { 67, 280, 64, 112, 8, 1, 0x1013, "aed3" }, + { 68, 288, 72, 120, 8, 1, 0x1014, "aed4" }, + { 69, 296, 80, 128, 8, 1, 0x1015, "aed5" }, + { 70, 304, 88, 136, 8, 1, 0x1016, "aed6" }, + { 71, 312, 96, 144, 8, 1, 0x1017, "aed7" }, + { 72, 320, 104, 152, 8, 1, 0x1018, "aed8" }, + { 73, 328, 112, 160, 8, 1, 0x1019, "aed9" }, + { 74, 336, 120, 168, 8, 1, 0x101a, "aed10" }, + { 75, 344, 128, 176, 8, 1, 0x101b, "aed11" }, + { 76, 352, 136, 184, 8, 1, 0x101c, "aed12" }, + { 77, 360, 144, 192, 8, 1, 0x101d, "aed13" }, + { 78, 368, 152, 200, 8, 1, 0x101e, "aed14" }, + { 79, 376, 160, 208, 8, 1, 0x101f, "aed15" }, + { 80, 384, 176, 224, 8, 1, 0x1020, "u0" }, + { 81, 392, 184, 232, 8, 1, 0x1021, "u1" }, + { 82, 400, 192, 240, 8, 1, 0x1022, "u2" }, + { 83, 408, 200, 248, 8, 1, 0x1023, "u3" }, + { 84, 416, 168, 216, 1, 1, 0x1024, "aep0" }, + { 85, 417, 169, 217, 1, 1, 0x1025, "aep1" }, + { 86, 418, 170, 218, 1, 1, 0x1026, "aep2" }, + { 87, 419, 171, 219, 1, 1, 0x1027, "aep3" }, + { 88, 420, 0, 48, 4, 1, 0x1029, "fcr_fsr" }, + { 0 } +}; + diff --git a/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/gdbserver/xtensa-xtregs.c b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/gdbserver/xtensa-xtregs.c new file mode 100644 index 00000000..399943bb --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/gdbserver/xtensa-xtregs.c @@ -0,0 +1,86 @@ +/* Customized table mapping between kernel xtregset and GDB register cache. + + Copyright (c) 2007-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +typedef struct { + int gdb_regnum; + int gdb_offset; + int ptrace_cp_offset; + int ptrace_offset; + int size; + int coproc; + int dbnum; + char* name +;} xtensa_regtable_t; + +#define XTENSA_ELF_XTREG_SIZE 256 + +const xtensa_regtable_t xtensa_regmap_table[] = { + /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ + { 44, 176, 8, 8, 4, -1, 0x0204, "br" }, + { 45, 180, 12, 12, 4, -1, 0x020c, "scompare1" }, + { 46, 184, 0, 0, 4, -1, 0x0210, "acclo" }, + { 47, 188, 4, 4, 4, -1, 0x0211, "acchi" }, + { 48, 192, 16, 16, 4, -1, 0x0220, "m0" }, + { 49, 196, 20, 20, 4, -1, 0x0221, "m1" }, + { 50, 200, 24, 24, 4, -1, 0x0222, "m2" }, + { 51, 204, 28, 28, 4, -1, 0x0223, "m3" }, + { 53, 212, 32, 32, 4, -1, 0x03ea, "f64r_lo" }, + { 54, 216, 36, 36, 4, -1, 0x03eb, "f64r_hi" }, + { 55, 220, 40, 40, 4, -1, 0x03ec, "f64s" }, + { 56, 224, 8, 56, 4, 1, 0x03f0, "ae_ovf_sar" }, + { 57, 228, 12, 60, 4, 1, 0x03f1, "ae_bithead" }, + { 58, 232, 16, 64, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, + { 59, 236, 20, 68, 4, 1, 0x03f3, "ae_cw_sd_no" }, + { 60, 240, 24, 72, 4, 1, 0x03f6, "ae_cbegin0" }, + { 61, 244, 28, 76, 4, 1, 0x03f7, "ae_cend0" }, + { 62, 248, 32, 80, 4, 1, 0x03f8, "ae_cbegin1" }, + { 63, 252, 36, 84, 4, 1, 0x03f9, "ae_cend1" }, + { 64, 256, 40, 88, 8, 1, 0x1010, "aed0" }, + { 65, 264, 48, 96, 8, 1, 0x1011, "aed1" }, + { 66, 272, 56, 104, 8, 1, 0x1012, "aed2" }, + { 67, 280, 64, 112, 8, 1, 0x1013, "aed3" }, + { 68, 288, 72, 120, 8, 1, 0x1014, "aed4" }, + { 69, 296, 80, 128, 8, 1, 0x1015, "aed5" }, + { 70, 304, 88, 136, 8, 1, 0x1016, "aed6" }, + { 71, 312, 96, 144, 8, 1, 0x1017, "aed7" }, + { 72, 320, 104, 152, 8, 1, 0x1018, "aed8" }, + { 73, 328, 112, 160, 8, 1, 0x1019, "aed9" }, + { 74, 336, 120, 168, 8, 1, 0x101a, "aed10" }, + { 75, 344, 128, 176, 8, 1, 0x101b, "aed11" }, + { 76, 352, 136, 184, 8, 1, 0x101c, "aed12" }, + { 77, 360, 144, 192, 8, 1, 0x101d, "aed13" }, + { 78, 368, 152, 200, 8, 1, 0x101e, "aed14" }, + { 79, 376, 160, 208, 8, 1, 0x101f, "aed15" }, + { 80, 384, 176, 224, 8, 1, 0x1020, "u0" }, + { 81, 392, 184, 232, 8, 1, 0x1021, "u1" }, + { 82, 400, 192, 240, 8, 1, 0x1022, "u2" }, + { 83, 408, 200, 248, 8, 1, 0x1023, "u3" }, + { 84, 416, 168, 216, 1, 1, 0x1024, "aep0" }, + { 85, 417, 169, 217, 1, 1, 0x1025, "aep1" }, + { 86, 418, 170, 218, 1, 1, 0x1026, "aep2" }, + { 87, 419, 171, 219, 1, 1, 0x1027, "aep3" }, + { 88, 420, 0, 48, 4, 1, 0x1029, "fcr_fsr" }, + { 0 } +}; + diff --git a/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/regformats/reg-xtensa.dat b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/regformats/reg-xtensa.dat new file mode 100644 index 00000000..dd339128 --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/regformats/reg-xtensa.dat @@ -0,0 +1,91 @@ +name:xtensa +expedite:pc,windowbase,windowstart +32:pc +32:ar0 +32:ar1 +32:ar2 +32:ar3 +32:ar4 +32:ar5 +32:ar6 +32:ar7 +32:ar8 +32:ar9 +32:ar10 +32:ar11 +32:ar12 +32:ar13 +32:ar14 +32:ar15 +32:ar16 +32:ar17 +32:ar18 +32:ar19 +32:ar20 +32:ar21 +32:ar22 +32:ar23 +32:ar24 +32:ar25 +32:ar26 +32:ar27 +32:ar28 +32:ar29 +32:ar30 +32:ar31 +32:lbeg +32:lend +32:lcount +32:sar +32:prefctl +32:windowbase +32:windowstart +32:configid0 +32:configid1 +32:ps +32:threadptr +32:br +32:scompare1 +32:acclo +32:acchi +32:m0 +32:m1 +32:m2 +32:m3 +32:expstate +32:f64r_lo +32:f64r_hi +32:f64s +32:ae_ovf_sar +32:ae_bithead +32:ae_ts_fts_bu_bp +32:ae_cw_sd_no +32:ae_cbegin0 +32:ae_cend0 +32:ae_cbegin1 +32:ae_cend1 +64:aed0 +64:aed1 +64:aed2 +64:aed3 +64:aed4 +64:aed5 +64:aed6 +64:aed7 +64:aed8 +64:aed9 +64:aed10 +64:aed11 +64:aed12 +64:aed13 +64:aed14 +64:aed15 +64:u0 +64:u1 +64:u2 +64:u3 +8:aep0 +8:aep1 +8:aep2 +8:aep3 +32:fcr_fsr diff --git a/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/xtensa-config.c b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/xtensa-config.c new file mode 100644 index 00000000..21c07ecd --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/xtensa-config.c @@ -0,0 +1,421 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2023 Cadence Design Systems, Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#define XTENSA_CONFIG_VERSION 0x70 + +#include "defs.h" +#include "xtensa-config.h" +#include "xtensa-tdep.h" + + + +/* Masked registers. */ +xtensa_reg_mask_t xtensa_submask0[] = { { 44, 0, 1 } }; +const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 }; +xtensa_reg_mask_t xtensa_submask1[] = { { 44, 1, 1 } }; +const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 }; +xtensa_reg_mask_t xtensa_submask2[] = { { 44, 2, 1 } }; +const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 }; +xtensa_reg_mask_t xtensa_submask3[] = { { 44, 3, 1 } }; +const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 }; +xtensa_reg_mask_t xtensa_submask4[] = { { 44, 4, 1 } }; +const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 }; +xtensa_reg_mask_t xtensa_submask5[] = { { 44, 5, 1 } }; +const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 }; +xtensa_reg_mask_t xtensa_submask6[] = { { 44, 6, 1 } }; +const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 }; +xtensa_reg_mask_t xtensa_submask7[] = { { 44, 7, 1 } }; +const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 }; +xtensa_reg_mask_t xtensa_submask8[] = { { 44, 8, 1 } }; +const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 }; +xtensa_reg_mask_t xtensa_submask9[] = { { 44, 9, 1 } }; +const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 }; +xtensa_reg_mask_t xtensa_submask10[] = { { 44, 10, 1 } }; +const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 }; +xtensa_reg_mask_t xtensa_submask11[] = { { 44, 11, 1 } }; +const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 }; +xtensa_reg_mask_t xtensa_submask12[] = { { 44, 12, 1 } }; +const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 }; +xtensa_reg_mask_t xtensa_submask13[] = { { 44, 13, 1 } }; +const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 }; +xtensa_reg_mask_t xtensa_submask14[] = { { 44, 14, 1 } }; +const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 }; +xtensa_reg_mask_t xtensa_submask15[] = { { 44, 15, 1 } }; +const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 }; +xtensa_reg_mask_t xtensa_submask16[] = { { 42, 0, 4 } }; +const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 }; +xtensa_reg_mask_t xtensa_submask17[] = { { 42, 5, 1 } }; +const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 }; +xtensa_reg_mask_t xtensa_submask18[] = { { 42, 18, 1 } }; +const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 }; +xtensa_reg_mask_t xtensa_submask19[] = { { 42, 4, 1 } }; +const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 }; +xtensa_reg_mask_t xtensa_submask20[] = { { 42, 16, 2 } }; +const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 }; +xtensa_reg_mask_t xtensa_submask21[] = { { 42, 8, 4 } }; +const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 }; +xtensa_reg_mask_t xtensa_submask22[] = { { 46, 0, 32 }, { 47, 0, 8 } }; +const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 }; +xtensa_reg_mask_t xtensa_submask23[] = { { 122, 8, 4 } }; +const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 }; +xtensa_reg_mask_t xtensa_submask24[] = { { 56, 7, 1 } }; +const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 }; +xtensa_reg_mask_t xtensa_submask25[] = { { 56, 0, 7 }, { 56, 8, 7 } }; +const xtensa_mask_t xtensa_mask25 = { 2, xtensa_submask25 }; +xtensa_reg_mask_t xtensa_submask26[] = { { 59, 28, 1 } }; +const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 }; +xtensa_reg_mask_t xtensa_submask27[] = { { 58, 0, 4 } }; +const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 }; +xtensa_reg_mask_t xtensa_submask28[] = { { 58, 4, 4 } }; +const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 }; +xtensa_reg_mask_t xtensa_submask29[] = { { 58, 12, 4 } }; +const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 }; +xtensa_reg_mask_t xtensa_submask30[] = { { 58, 8, 4 } }; +const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 }; +xtensa_reg_mask_t xtensa_submask31[] = { { 59, 0, 27 } }; +const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 }; +xtensa_reg_mask_t xtensa_submask32[] = { { 59, 27, 1 } }; +const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 }; +xtensa_reg_mask_t xtensa_submask33[] = { { 88, 5, 2 } }; +const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 }; +xtensa_reg_mask_t xtensa_submask34[] = { { 88, 4, 1 } }; +const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 }; +xtensa_reg_mask_t xtensa_submask35[] = { { 88, 3, 1 } }; +const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 }; +xtensa_reg_mask_t xtensa_submask36[] = { { 88, 2, 1 } }; +const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 }; +xtensa_reg_mask_t xtensa_submask37[] = { { 88, 1, 1 } }; +const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 }; +xtensa_reg_mask_t xtensa_submask38[] = { { 88, 0, 1 } }; +const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 }; +xtensa_reg_mask_t xtensa_submask39[] = { { 53, 0, 32 }, { 54, 0, 32 } }; +const xtensa_mask_t xtensa_mask39 = { 2, xtensa_submask39 }; + + +/* Register map. */ +xtensa_register_t rmap[] = +{ + /* idx ofs bi sz al targno flags cp typ group name */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 37,148,20, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0) + XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) + XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) + XTREG( 46,184,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0) + XTREG( 47,188, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0) + XTREG( 48,192,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0) + XTREG( 49,196,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0) + XTREG( 50,200,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0) + XTREG( 51,204,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0) + XTREG( 52,208,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) + XTREG( 53,212,32, 4, 4,0x03ea,0x0006,-1, 3,0x0100,f64r_lo, 0,0,0,0,0,0) + XTREG( 54,216,32, 4, 4,0x03eb,0x0006,-1, 3,0x0100,f64r_hi, 0,0,0,0,0,0) + XTREG( 55,220,32, 4, 4,0x03ec,0x0006,-1, 3,0x0110,f64s, 0,0,0,0,0,0) + XTREG( 56,224,15, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0) + XTREG( 57,228,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0) + XTREG( 58,232,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0) + XTREG( 59,236,29, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_cw_sd_no, 0,0,0,0,0,0) + XTREG( 60,240,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0) + XTREG( 61,244,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0) + XTREG( 62,248,32, 4, 4,0x03f8,0x0006, 1, 3,0x0110,ae_cbegin1, 0,0,0,0,0,0) + XTREG( 63,252,32, 4, 4,0x03f9,0x0006, 1, 3,0x0110,ae_cend1, 0,0,0,0,0,0) + XTREG( 64,256,64, 8, 8,0x1010,0x0006, 1, 4,0x0101,aed0, + "03:04:04:01","03:04:04:cf",0,0,0,0) + XTREG( 65,264,64, 8, 8,0x1011,0x0006, 1, 4,0x0101,aed1, + "03:04:14:01","03:04:14:cf",0,0,0,0) + XTREG( 66,272,64, 8, 8,0x1012,0x0006, 1, 4,0x0101,aed2, + "03:04:24:01","03:04:24:cf",0,0,0,0) + XTREG( 67,280,64, 8, 8,0x1013,0x0006, 1, 4,0x0101,aed3, + "03:04:34:01","03:04:34:cf",0,0,0,0) + XTREG( 68,288,64, 8, 8,0x1014,0x0006, 1, 4,0x0101,aed4, + "03:04:44:01","03:04:44:cf",0,0,0,0) + XTREG( 69,296,64, 8, 8,0x1015,0x0006, 1, 4,0x0101,aed5, + "03:04:54:01","03:04:54:cf",0,0,0,0) + XTREG( 70,304,64, 8, 8,0x1016,0x0006, 1, 4,0x0101,aed6, + "03:04:64:01","03:04:64:cf",0,0,0,0) + XTREG( 71,312,64, 8, 8,0x1017,0x0006, 1, 4,0x0101,aed7, + "03:04:74:01","03:04:74:cf",0,0,0,0) + XTREG( 72,320,64, 8, 8,0x1018,0x0006, 1, 4,0x0101,aed8, + "03:04:84:01","03:04:84:cf",0,0,0,0) + XTREG( 73,328,64, 8, 8,0x1019,0x0006, 1, 4,0x0101,aed9, + "03:04:94:01","03:04:94:cf",0,0,0,0) + XTREG( 74,336,64, 8, 8,0x101a,0x0006, 1, 4,0x0101,aed10, + "03:04:a4:01","03:04:a4:cf",0,0,0,0) + XTREG( 75,344,64, 8, 8,0x101b,0x0006, 1, 4,0x0101,aed11, + "03:04:b4:01","03:04:b4:cf",0,0,0,0) + XTREG( 76,352,64, 8, 8,0x101c,0x0006, 1, 4,0x0101,aed12, + "03:04:c4:01","03:04:c4:cf",0,0,0,0) + XTREG( 77,360,64, 8, 8,0x101d,0x0006, 1, 4,0x0101,aed13, + "03:04:d4:01","03:04:d4:cf",0,0,0,0) + XTREG( 78,368,64, 8, 8,0x101e,0x0006, 1, 4,0x0101,aed14, + "03:04:e4:01","03:04:e4:cf",0,0,0,0) + XTREG( 79,376,64, 8, 8,0x101f,0x0006, 1, 4,0x0101,aed15, + "03:04:f4:01","03:04:f4:cf",0,0,0,0) + XTREG( 80,384,64, 8, 8,0x1020,0x0006, 1, 4,0x0101,u0, + "0b:9f:24:70:16:3d:00:6c:a4:c5:77:39","0b:9f:24:70:16:2d:00:6c:a4:c5:77:39",0,0,0,0) + XTREG( 81,392,64, 8, 8,0x1021,0x0006, 1, 4,0x0101,u1, + "0b:9f:64:70:16:3d:00:6c:a4:c5:77:39","0b:9f:64:70:16:2d:00:6c:a4:c5:77:39",0,0,0,0) + XTREG( 82,400,64, 8, 8,0x1022,0x0006, 1, 4,0x0101,u2, + "0b:9f:a4:70:16:3d:00:6c:a4:c5:77:39","0b:9f:a4:70:16:2d:00:6c:a4:c5:77:39",0,0,0,0) + XTREG( 83,408,64, 8, 8,0x1023,0x0006, 1, 4,0x0101,u3, + "0b:9f:e4:70:16:3d:00:6c:a4:c5:77:39","0b:9f:e4:70:16:2d:00:6c:a4:c5:77:39",0,0,0,0) + XTREG( 84,416, 8, 1, 1,0x1024,0x0006, 1, 4,0x0101,aep0, + "03:52:64:01:06:5e:f0:06:01:e6:fc:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:06:5e:f4:06:01:e6:fc:03:52:24:01",0,0,0,0) + XTREG( 85,417, 8, 1, 1,0x1025,0x0006, 1, 4,0x0101,aep1, + "03:52:64:01:06:5e:f1:06:01:e6:fc:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:06:5e:f5:06:01:e6:fc:03:52:24:01",0,0,0,0) + XTREG( 86,418, 8, 1, 1,0x1026,0x0006, 1, 4,0x0101,aep2, + "03:52:64:01:06:5e:f2:06:01:e6:fc:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:06:5e:f6:06:01:e6:fc:03:52:24:01",0,0,0,0) + XTREG( 87,419, 8, 1, 1,0x1027,0x0006, 1, 4,0x0101,aep3, + "03:52:64:01:06:5e:f3:06:01:e6:fc:03:52:44:00:03:52:24:01","03:52:64:01:03:52:04:00:06:5e:f7:06:01:e6:fc:03:52:24:01",0,0,0,0) + XTREG( 88,420, 7, 4, 4,0x1029,0x0006, 1, 3,0x0200,fcr_fsr, + "03:14:04:01:0b:1f:15:70:06:3d:e3:6d:c4:c7:7f:39:03:04:04:01:03:14:04:cf","03:14:04:01:03:04:04:cf:0b:1f:15:70:06:1d:e3:6d:c4:c7:7f:39:03:14:04:cf",0,0,0,0) + XTREG( 89,424,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG( 90,428, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG( 91,432, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0) + XTREG( 92,436, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG( 93,440,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG( 94,444,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG( 95,448,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG( 96,452,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG( 97,456,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG( 98,460,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG( 99,464,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG(100,468,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG(101,472,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG(102,476,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG(103,480,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG(104,484,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG(105,488,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG(106,492,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG(107,496,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG(108,500,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG(109,504,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG(110,508,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG(111,512,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG(112,516,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG(113,520,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG(114,524,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG(115,528, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG(116,532,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG(117,536,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG(118,540,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG(119,544,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG(120,548,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG(121,552, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG(122,556,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG(123,560,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG(124,564,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG(125,568,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG(126,572, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG(127,576,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG(128,580,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG(129,584,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG(130,588,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG(131,592,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG(132,596,32, 4, 4,0x2024,0x000f,-2, 4,0x0101,pwrctl, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(133,600,32, 4, 4,0x2025,0x000f,-2, 4,0x0101,pwrstat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(134,604, 1, 4, 4,0x2026,0x000f,-2, 4,0x0101,eristat, + "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(135,608,32, 4, 4,0x2027,0x000f,-2, 4,0x0101,cs_itctrl, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(136,612,16, 4, 4,0x2028,0x000f,-2, 4,0x0101,cs_claimset, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(137,616,16, 4, 4,0x2029,0x000f,-2, 4,0x0101,cs_claimclr, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(138,620,32, 4, 4,0x202a,0x000d,-2, 4,0x0101,cs_lockaccess, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(139,624,32, 4, 4,0x202b,0x000b,-2, 4,0x0101,cs_lockstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(140,628, 1, 4, 4,0x202c,0x000b,-2, 4,0x0101,cs_authstatus, + "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(141,632,32, 4, 4,0x203b,0x000f,-2, 4,0x0101,pmg, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(142,636,32, 4, 4,0x203c,0x000f,-2, 4,0x0101,pmpc, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(143,640,32, 4, 4,0x203d,0x000f,-2, 4,0x0101,pm0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(144,644,32, 4, 4,0x203e,0x000f,-2, 4,0x0101,pm1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(145,648,32, 4, 4,0x203f,0x000f,-2, 4,0x0101,pmctrl0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(146,652,32, 4, 4,0x2040,0x000f,-2, 4,0x0101,pmctrl1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(147,656,32, 4, 4,0x2041,0x000f,-2, 4,0x0101,pmstat0, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(148,660,32, 4, 4,0x2042,0x000f,-2, 4,0x0101,pmstat1, + "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(149,664,32, 4, 4,0x2043,0x0003,-2, 4,0x0101,ocdid, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(150,668,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,ocd_dcrclr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(151,672,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,ocd_dcrset, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(152,676,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,ocd_dsr, + "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0) + XTREG(153,680,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0) + XTREG(154,684,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0) + XTREG(155,688,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0) + XTREG(156,692,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0) + XTREG(157,696,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0) + XTREG(158,700,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0) + XTREG(159,704,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0) + XTREG(160,708,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0) + XTREG(161,712,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0) + XTREG(162,716,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0) + XTREG(163,720,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0) + XTREG(164,724,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0) + XTREG(165,728,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0) + XTREG(166,732,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0) + XTREG(167,736,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0) + XTREG(168,740,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0) + XTREG(169,744, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(170,745, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(171,746, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(172,747, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(173,748, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(174,749, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(175,750, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(176,751, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(177,752, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(178,753, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(179,754, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(180,755, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(181,756, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(182,757, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(183,758, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(184,759, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(185,760, 4, 4, 4,0x2006,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask16,0,0,0) + XTREG(186,764, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask17,0,0,0) + XTREG(187,768, 1, 4, 4,0x2008,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask18,0,0,0) + XTREG(188,772, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask19,0,0,0) + XTREG(189,776, 2, 4, 4,0x200a,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask20,0,0,0) + XTREG(190,780, 4, 4, 4,0x200b,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask21,0,0,0) + XTREG(191,784,40, 8, 4,0x200c,0x0006,-2, 6,0x1010,acc, + 0,0,&xtensa_mask22,0,0,0) + XTREG(192,792, 4, 4, 4,0x2011,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask23,0,0,0) + XTREG(193,796, 1, 4, 4,0x2014,0x0006, 1, 6,0x1010,ae_overflow, + 0,0,&xtensa_mask24,0,0,0) + XTREG(194,800,14, 4, 4,0x2015,0x0006, 1, 6,0x1010,ae_sar, + 0,0,&xtensa_mask25,0,0,0) + XTREG(195,804, 1, 4, 4,0x2016,0x0006, 1, 6,0x1010,ae_cwrap, + 0,0,&xtensa_mask26,0,0,0) + XTREG(196,808, 4, 4, 4,0x2017,0x0006, 1, 6,0x1010,ae_bitptr, + 0,0,&xtensa_mask27,0,0,0) + XTREG(197,812, 4, 4, 4,0x2018,0x0006, 1, 6,0x1010,ae_bitsused, + 0,0,&xtensa_mask28,0,0,0) + XTREG(198,816, 4, 4, 4,0x2019,0x0006, 1, 6,0x1010,ae_tablesize, + 0,0,&xtensa_mask29,0,0,0) + XTREG(199,820, 4, 4, 4,0x201a,0x0006, 1, 6,0x1010,ae_first_ts, + 0,0,&xtensa_mask30,0,0,0) + XTREG(200,824,27, 4, 4,0x201b,0x0006, 1, 6,0x1010,ae_nextoffset, + 0,0,&xtensa_mask31,0,0,0) + XTREG(201,828, 1, 4, 4,0x201c,0x0006, 1, 6,0x1010,ae_searchdone, + 0,0,&xtensa_mask32,0,0,0) + XTREG(202,832, 2, 4, 4,0x201d,0x0006, 1, 6,0x1010,roundmode, + 0,0,&xtensa_mask33,0,0,0) + XTREG(203,836, 1, 4, 4,0x201e,0x0006, 1, 6,0x1010,invalidflag, + 0,0,&xtensa_mask34,0,0,0) + XTREG(204,840, 1, 4, 4,0x201f,0x0006, 1, 6,0x1010,divzeroflag, + 0,0,&xtensa_mask35,0,0,0) + XTREG(205,844, 1, 4, 4,0x2020,0x0006, 1, 6,0x1010,overflowflag, + 0,0,&xtensa_mask36,0,0,0) + XTREG(206,848, 1, 4, 4,0x2021,0x0006, 1, 6,0x1010,underflowflag, + 0,0,&xtensa_mask37,0,0,0) + XTREG(207,852, 1, 4, 4,0x2022,0x0006, 1, 6,0x1010,inexactflag, + 0,0,&xtensa_mask38,0,0,0) + XTREG_END +}; + + + +#ifdef XTENSA_CONFIG_INSTANTIATE +XTENSA_CONFIG_INSTANTIATE(rmap,16) +#endif + +xtensa_gdbarch_tdep xtensa_tdep (rmap); diff --git a/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/xtensa-xtregs.c b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/xtensa-xtregs.c new file mode 100644 index 00000000..399943bb --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/gdb/gdb/xtensa-xtregs.c @@ -0,0 +1,86 @@ +/* Customized table mapping between kernel xtregset and GDB register cache. + + Copyright (c) 2007-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +typedef struct { + int gdb_regnum; + int gdb_offset; + int ptrace_cp_offset; + int ptrace_offset; + int size; + int coproc; + int dbnum; + char* name +;} xtensa_regtable_t; + +#define XTENSA_ELF_XTREG_SIZE 256 + +const xtensa_regtable_t xtensa_regmap_table[] = { + /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */ + { 44, 176, 8, 8, 4, -1, 0x0204, "br" }, + { 45, 180, 12, 12, 4, -1, 0x020c, "scompare1" }, + { 46, 184, 0, 0, 4, -1, 0x0210, "acclo" }, + { 47, 188, 4, 4, 4, -1, 0x0211, "acchi" }, + { 48, 192, 16, 16, 4, -1, 0x0220, "m0" }, + { 49, 196, 20, 20, 4, -1, 0x0221, "m1" }, + { 50, 200, 24, 24, 4, -1, 0x0222, "m2" }, + { 51, 204, 28, 28, 4, -1, 0x0223, "m3" }, + { 53, 212, 32, 32, 4, -1, 0x03ea, "f64r_lo" }, + { 54, 216, 36, 36, 4, -1, 0x03eb, "f64r_hi" }, + { 55, 220, 40, 40, 4, -1, 0x03ec, "f64s" }, + { 56, 224, 8, 56, 4, 1, 0x03f0, "ae_ovf_sar" }, + { 57, 228, 12, 60, 4, 1, 0x03f1, "ae_bithead" }, + { 58, 232, 16, 64, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" }, + { 59, 236, 20, 68, 4, 1, 0x03f3, "ae_cw_sd_no" }, + { 60, 240, 24, 72, 4, 1, 0x03f6, "ae_cbegin0" }, + { 61, 244, 28, 76, 4, 1, 0x03f7, "ae_cend0" }, + { 62, 248, 32, 80, 4, 1, 0x03f8, "ae_cbegin1" }, + { 63, 252, 36, 84, 4, 1, 0x03f9, "ae_cend1" }, + { 64, 256, 40, 88, 8, 1, 0x1010, "aed0" }, + { 65, 264, 48, 96, 8, 1, 0x1011, "aed1" }, + { 66, 272, 56, 104, 8, 1, 0x1012, "aed2" }, + { 67, 280, 64, 112, 8, 1, 0x1013, "aed3" }, + { 68, 288, 72, 120, 8, 1, 0x1014, "aed4" }, + { 69, 296, 80, 128, 8, 1, 0x1015, "aed5" }, + { 70, 304, 88, 136, 8, 1, 0x1016, "aed6" }, + { 71, 312, 96, 144, 8, 1, 0x1017, "aed7" }, + { 72, 320, 104, 152, 8, 1, 0x1018, "aed8" }, + { 73, 328, 112, 160, 8, 1, 0x1019, "aed9" }, + { 74, 336, 120, 168, 8, 1, 0x101a, "aed10" }, + { 75, 344, 128, 176, 8, 1, 0x101b, "aed11" }, + { 76, 352, 136, 184, 8, 1, 0x101c, "aed12" }, + { 77, 360, 144, 192, 8, 1, 0x101d, "aed13" }, + { 78, 368, 152, 200, 8, 1, 0x101e, "aed14" }, + { 79, 376, 160, 208, 8, 1, 0x101f, "aed15" }, + { 80, 384, 176, 224, 8, 1, 0x1020, "u0" }, + { 81, 392, 184, 232, 8, 1, 0x1021, "u1" }, + { 82, 400, 192, 240, 8, 1, 0x1022, "u2" }, + { 83, 408, 200, 248, 8, 1, 0x1023, "u3" }, + { 84, 416, 168, 216, 1, 1, 0x1024, "aep0" }, + { 85, 417, 169, 217, 1, 1, 0x1025, "aep1" }, + { 86, 418, 170, 218, 1, 1, 0x1026, "aep2" }, + { 87, 419, 171, 219, 1, 1, 0x1027, "aep3" }, + { 88, 420, 0, 48, 4, 1, 0x1029, "fcr_fsr" }, + { 0 } +}; + diff --git a/overlays/xtensa_nxp_rt600_adsp/gdb/include/xtensa-config.h b/overlays/xtensa_nxp_rt600_adsp/gdb/include/xtensa-config.h new file mode 100644 index 00000000..22016cae --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/gdb/include/xtensa-config.h @@ -0,0 +1,189 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 0 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 1 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 1 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 1 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 1 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_ACCEL +#define XCHAL_HAVE_DFP_ACCEL 1 +/* For backward compatibility */ +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 32 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_HAVE_PREDICTED_BRANCHES +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 32768 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 65536 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 256 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 256 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 8 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 8 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 0 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 4 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 11 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 16 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + + +#undef XCHAL_M_STAGE +#define XCHAL_M_STAGE 3 + +#undef XTENSA_MARCH_LATEST +#define XTENSA_MARCH_LATEST 260004 + +#undef XTENSA_MARCH_EARLIEST +#define XTENSA_MARCH_EARLIEST 260004 + + +#endif /* !XTENSA_CONFIG_H */ diff --git a/overlays/xtensa_nxp_rt600_adsp/newlib/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h b/overlays/xtensa_nxp_rt600_adsp/newlib/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h new file mode 100644 index 00000000..c16b8ff3 --- /dev/null +++ b/overlays/xtensa_nxp_rt600_adsp/newlib/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h @@ -0,0 +1,813 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Copyright (c) 1999-2023 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_CORE_CONFIGURATION_H_ +#define XTENSA_CORE_CONFIGURATION_H_ + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 11 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ +#define XCHAL_HAVE_LX 1 /* LX core */ +#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */ +#define XCHAL_HAVE_RNX 0 /* RNX core (starting RJ) */ + +#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion */ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */ +#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */ +#define XCHAL_HAVE_HIFI4 1 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 1 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI1 0 /* HiFi1 */ +#define XCHAL_HAVE_HIFI1_VFPU 0 /* HiFi1 VFPU option */ +#define XCHAL_HAVE_HIFI1_LOW_LATENCY_MAC_FMA 0 /* HiFi1 Low-latency MAC/FMA option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */ +#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */ +#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */ +#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */ +#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */ + +#define XCHAL_HAVE_PDX 0 /* PDX-LX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */ +#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */ +#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */ +#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BALL 0 +#define XCHAL_HAVE_BALLAP 0 +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/ +#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/ +#define XCHAL_HAVE_CONNX_B_DP_VFPU 0 /* Double-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_DPX_VFPU 0 /* Double-precision Vector Floating-point option on FP Machine*/ +#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HP_VFPU 0 /* Half-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6, Q7 or Q8 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_DP_VFPU 0 /* dp_vfpu option on Vision Q7/Q8 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */ +#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */ +#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +#define XCHAL_HAVE_XNNE 0 /* XNNE */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 32 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 16 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_UNIFIED_LOADSTORE 0 + +#define XCHAL_SW_VERSION 1411000 /* sw version of this header */ +#define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */ +#define XCHAL_SW_VERSION_MINOR 11 /* minor ver# of sw */ +#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */ +#define XCHAL_SW_MINOR_VERSION 1411000 /* with zeroed micro */ +#define XCHAL_SW_MICRO_VERSION 1411000 + +#define XCHAL_CORE_ID "nxp_rt600_RI23_11_newlib" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x000A98E8 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC2F3FFFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1D06FB2F /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.4" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */ +#define XCHAL_HW_VERSION 260004 /* major*100+(major<2810 ? minor : minor*10+micro) */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_4 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260004 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260004 /* latest targeted hw */ + +/* Config is enabled for functional safety: */ +#define XCHAL_HAVE_FUNC_SAFETY 0 + +/* Config is enabled for secure operation: */ +#define XCHAL_HAVE_SECURE 0 + +#define XCHAL_HAVE_APB 0 + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 256 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 256 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 8 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 8 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */ +#define XCHAL_ICACHE_SIZE_LOG2 15 +#define XCHAL_DCACHE_SIZE 65536 /* D-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE_LOG2 16 + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 cache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 8 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 1 /* block prefetch for caches */ +#define XCHAL_HAVE_CME_DOWNGRADES 0 +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ +#define XCHAL_HAVE_ICACHE_DYN_ENABLE 0 /* Icache enabled via MEMCTL */ +#define XCHAL_HAVE_DCACHE_DYN_ENABLE 0 /* Dcache enabled via MEMCTL */ + +#define XCHAL_L1SCACHE_SIZE 0 +#define XCHAL_L1SCACHE_SIZE_LOG2 0 +#define XCHAL_L1SCACHE_WAYS 1 +#define XCHAL_L1SCACHE_WAYS_LOG2 0 +#define XCHAL_L1SCACHE_ACCESS_SIZE 0 +#define XCHAL_L1SCACHE_BANKS 1 + +#define XCHAL_L1VCACHE_SIZE 0 + +#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */ +#define XCHAL_HAVE_L2_CACHE 0 +#define XCHAL_NUM_CORES_IN_CLUSTER 0 + +/* PRID_ID macros are for internal use only ... subject to removal */ +#define PRID_ID_SHIFT 0 +#define PRID_ID_BITS 4 +#define PRID_ID_MASK 0x0000000F + +/* This one is a form of caching, though not architecturally visible: */ +#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 0 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 5 +#define XCHAL_DCACHE_SETWIDTH 6 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_ICACHE_WAYS_LOG2 2 +#define XCHAL_DCACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS_LOG2 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 +#define XCHAL_ICACHE_ECC_WIDTH 4 +#define XCHAL_DCACHE_ECC_WIDTH 1 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 16 +#define XCHAL_DCACHE_ACCESS_SIZE 16 + +#define XCHAL_DCACHE_BANKS 4 /* number of banks */ + +/* The number of Cache lines associated with a single cache tag */ +#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0 + +/* Number of encoded cache attr bits (see for decoded bits): */ +#define XCHAL_CA_BITS 4 + +/* Extended memory attributes supported. */ +#define XCHAL_HAVE_EXT_CA 0 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ +#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */ +#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x24020000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x24020000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 65536 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 1 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x24000000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x24000000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 65536 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 4 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 1 +#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + IDMA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_IDMA 0 + + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 28 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_INTERRUPT_RANGE 32 /* range of interrupt numbers */ + + +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_EXCM_LEVEL 2 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x0000FFE0 +#define XCHAL_INTLEVEL2_MASK 0x00FF0006 +#define XCHAL_INTLEVEL3_MASK 0xFF000018 +#define XCHAL_INTLEVEL4_MASK 0x00000000 +#define XCHAL_INTLEVEL5_MASK 0x00000001 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000FFE0 +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00FFFFE6 +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0xFFFFFFFE +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0xFFFFFFFE +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFFFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFFFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 5 +#define XCHAL_INT1_LEVEL 2 +#define XCHAL_INT2_LEVEL 2 +#define XCHAL_INT3_LEVEL 3 +#define XCHAL_INT4_LEVEL 3 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 1 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 1 +#define XCHAL_INT11_LEVEL 1 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_INT13_LEVEL 1 +#define XCHAL_INT14_LEVEL 1 +#define XCHAL_INT15_LEVEL 1 +#define XCHAL_INT16_LEVEL 2 +#define XCHAL_INT17_LEVEL 2 +#define XCHAL_INT18_LEVEL 2 +#define XCHAL_INT19_LEVEL 2 +#define XCHAL_INT20_LEVEL 2 +#define XCHAL_INT21_LEVEL 2 +#define XCHAL_INT22_LEVEL 2 +#define XCHAL_INT23_LEVEL 2 +#define XCHAL_INT24_LEVEL 3 +#define XCHAL_INT25_LEVEL 3 +#define XCHAL_INT26_LEVEL 3 +#define XCHAL_INT27_LEVEL 3 +#define XCHAL_INT28_LEVEL 3 +#define XCHAL_INT29_LEVEL 3 +#define XCHAL_INT30_LEVEL 3 +#define XCHAL_INT31_LEVEL 3 +#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 5 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0xFFFFFFE0 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 +#define XCHAL_INTTYPE_MASK_NMI 0x00000001 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000002 +#define XCHAL_INTTYPE_MASK_TIMER 0x0000000C +#define XCHAL_INTTYPE_MASK_ETIE 0x00000000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000 +#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000 +#define XCHAL_INTTYPE_MASK_TRAX 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000010 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000 +#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_WWDT 0x00000000 +#define XCHAL_INTTYPE_MASK_FXLK 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 2 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 3 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 0 /* non-maskable interrupt */ +#define XCHAL_PROFILING_INTERRUPT 4 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL5_NUM 0 +/* (There are many interrupts each at level(s) 1, 2, 3.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 5) */ +#define XCHAL_EXTINT1_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 6 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 7 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 8 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 9 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 10 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 11 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 12 /* (intlevel 1) */ +#define XCHAL_EXTINT9_NUM 13 /* (intlevel 1) */ +#define XCHAL_EXTINT10_NUM 14 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 15 /* (intlevel 1) */ +#define XCHAL_EXTINT12_NUM 16 /* (intlevel 2) */ +#define XCHAL_EXTINT13_NUM 17 /* (intlevel 2) */ +#define XCHAL_EXTINT14_NUM 18 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 19 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 20 /* (intlevel 2) */ +#define XCHAL_EXTINT17_NUM 21 /* (intlevel 2) */ +#define XCHAL_EXTINT18_NUM 22 /* (intlevel 2) */ +#define XCHAL_EXTINT19_NUM 23 /* (intlevel 2) */ +#define XCHAL_EXTINT20_NUM 24 /* (intlevel 3) */ +#define XCHAL_EXTINT21_NUM 25 /* (intlevel 3) */ +#define XCHAL_EXTINT22_NUM 26 /* (intlevel 3) */ +#define XCHAL_EXTINT23_NUM 27 /* (intlevel 3) */ +#define XCHAL_EXTINT24_NUM 28 /* (intlevel 3) */ +#define XCHAL_EXTINT25_NUM 29 /* (intlevel 3) */ +#define XCHAL_EXTINT26_NUM 30 /* (intlevel 3) */ +#define XCHAL_EXTINT27_NUM 31 /* (intlevel 3) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 5) */ +#define XCHAL_INT5_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT6_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT7_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT9_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT10_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT11_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT12_EXTNUM 8 /* (intlevel 1) */ +#define XCHAL_INT13_EXTNUM 9 /* (intlevel 1) */ +#define XCHAL_INT14_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT15_EXTNUM 11 /* (intlevel 1) */ +#define XCHAL_INT16_EXTNUM 12 /* (intlevel 2) */ +#define XCHAL_INT17_EXTNUM 13 /* (intlevel 2) */ +#define XCHAL_INT18_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT19_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT20_EXTNUM 16 /* (intlevel 2) */ +#define XCHAL_INT21_EXTNUM 17 /* (intlevel 2) */ +#define XCHAL_INT22_EXTNUM 18 /* (intlevel 2) */ +#define XCHAL_INT23_EXTNUM 19 /* (intlevel 2) */ +#define XCHAL_INT24_EXTNUM 20 /* (intlevel 3) */ +#define XCHAL_INT25_EXTNUM 21 /* (intlevel 3) */ +#define XCHAL_INT26_EXTNUM 22 /* (intlevel 3) */ +#define XCHAL_INT27_EXTNUM 23 /* (intlevel 3) */ +#define XCHAL_INT28_EXTNUM 24 /* (intlevel 3) */ +#define XCHAL_INT29_EXTNUM 25 /* (intlevel 3) */ +#define XCHAL_INT30_EXTNUM 26 /* (intlevel 3) */ +#define XCHAL_INT31_EXTNUM 27 /* (intlevel 3) */ + +#define XCHAL_HAVE_ISB 0 /* No ISB */ +#define XCHAL_ISB_VADDR 0 /* N/A */ +#define XCHAL_HAVE_ITB 0 /* No ITB */ +#define XCHAL_ITB_VADDR 0 /* N/A */ + +#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */ +#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ +#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (until T1050) + 2 == XEA2 (LX) + 3 == XEA3 (NX) + 0 == XEA5 (RNX) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */ +#define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */ +#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x24020400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x24020400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */ + +#define XCHAL_RESET_VECTOR0_VADDR 0x24020000 +#define XCHAL_RESET_VECTOR0_PADDR 0x24020000 +#define XCHAL_RESET_VECTOR1_VADDR 0x20100000 +#define XCHAL_RESET_VECTOR1_PADDR 0x20100000 +#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR0_VADDR +#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR0_PADDR +#define XCHAL_USER_VECOFS 0x0000021C +#define XCHAL_USER_VECTOR_VADDR 0x2402061C +#define XCHAL_USER_VECTOR_PADDR 0x2402061C +#define XCHAL_KERNEL_VECOFS 0x000001FC +#define XCHAL_KERNEL_VECTOR_VADDR 0x240205FC +#define XCHAL_KERNEL_VECTOR_PADDR 0x240205FC +#define XCHAL_DOUBLEEXC_VECOFS 0x0000023C +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x2402063C +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x2402063C +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x24020400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x24020400 +#define XCHAL_INTLEVEL2_VECOFS 0x0000017C +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x2402057C +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x2402057C +#define XCHAL_INTLEVEL3_VECOFS 0x0000019C +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x2402059C +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x2402059C +#define XCHAL_INTLEVEL4_VECOFS 0x000001BC +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x240205BC +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x240205BC +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000001DC +#define XCHAL_NMI_VECTOR_VADDR 0x240205DC +#define XCHAL_NMI_VECTOR_PADDR 0x240205DC +#define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ +#define XCHAL_HAVE_MPU 0 +#define XCHAL_MPU_ENTRIES 0 +#define XCHAL_MPU_LOCK 0 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 0 +#define XCHAL_MPU_ALIGN 0 + +/*----------------------------------------------------------------------- + CSR Parity +------------------------------------------------------------------------*/ +#define XCHAL_HAVE_CSR_PARITY 0 + + +/*---------------------------------------------------------------------- + FLEX-LOCK +------------------------------------------------------------------------*/ + +#define XCHAL_HAVE_FXLK 0 + +/*---------------------------------------------------------------------- + WWDT (Windowed Watchdog Timer) +------------------------------------------------------------------------*/ +#define XCHAL_HAVE_WWDT 0 +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* XTENSA_CORE_CONFIGURATION_H_ */ +