You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
We may just define SMP system in OpenOCD configuration:
target smp $_TARGETNAME1 $_TARGETNAME2
And then reset & resume commands will be sent to all cores in the SMP.
Which means with proper openocd.cfg generic OpenOCD runner could be used in Zephyr for running SMP-aware applications on SMP HW.
The problem is this SMP-related functionality requires architecture-specific changes and so far it has not been implemented for ARC.
OpenOCD might be used to work nicely with SMP targets, see http://openocd.org/doc/html/Config-File-Guidelines.html#definecputargetsworkinginsmp.
We may just define SMP system in OpenOCD configuration:
And then
reset
&resume
commands will be sent to all cores in the SMP.Which means with proper
openocd.cfg
generic OpenOCD runner could be used in Zephyr for running SMP-aware applications on SMP HW.The problem is this SMP-related functionality requires architecture-specific changes and so far it has not been implemented for ARC.
Just as a reference to how it all started for ARM Cortex-A: https://repo.or.cz/openocd.git/blobdiff/b778b36f29b74d6d571df85f984ae684672ea162..5578935eff66ed6db4a8f6b6957ab671dd36732b:/src/target/cortex_a.c
But there're some more changes after :)
The text was updated successfully, but these errors were encountered: