diff --git a/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5.h b/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5.h index 1dcf393a3..133da053f 100644 --- a/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5.h +++ b/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5.h @@ -72,7 +72,7 @@ #define PSI5_CHANNEL_CH_PMR_COUNT 32u #define PSI5_CHANNEL_CH_SFR_COUNT 6u #define PSI5_CHANNEL_CH_SFCR_COUNT 6u -#define PSI5_CHANNEL_COUNT 4u +#define PSI5_CHANNEL_COUNT 4 /** PSI5 - Register Layout Typedef */ typedef struct { @@ -132,7 +132,7 @@ typedef struct { } PSI5_Type, *PSI5_MemMapPtr; /** Number of instances of the PSI5 module. */ -#define PSI5_INSTANCE_COUNT (2u) +#define PSI5_INSTANCE_COUNT 2 /* PSI5 - Peripheral instance base addresses */ /** Peripheral PSI5_0 base address */ diff --git a/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5_S.h b/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5_S.h index d1b54df44..673a9b313 100644 --- a/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5_S.h +++ b/s32/drivers/s32ze/BaseNXP/header/S32Z2_PSI5_S.h @@ -135,7 +135,7 @@ typedef struct { } PSI5_S_Type, *PSI5_S_MemMapPtr; /** Number of instances of the PSI5_S module. */ -#define PSI5_S_INSTANCE_COUNT (2u) +#define PSI5_S_INSTANCE_COUNT 2 /* PSI5_S - Peripheral instance base addresses */ /** Peripheral PSI5_S_0 base address */ diff --git a/s32/drivers/s32ze/BaseNXP/include/Psi5_MemMap.h b/s32/drivers/s32ze/BaseNXP/include/Psi5_MemMap.h new file mode 100644 index 000000000..7fbbf83b9 --- /dev/null +++ b/s32/drivers/s32ze/BaseNXP/include/Psi5_MemMap.h @@ -0,0 +1,5 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ diff --git a/s32/drivers/s32ze/CMakeLists.txt b/s32/drivers/s32ze/CMakeLists.txt index e9ee2a3ba..b7d5d5052 100644 --- a/s32/drivers/s32ze/CMakeLists.txt +++ b/s32/drivers/s32ze/CMakeLists.txt @@ -13,3 +13,5 @@ if (CONFIG_ETH_NXP_S32_NETC) add_subdirectory(EthSwt_NETC) endif() add_subdirectory_ifdef(CONFIG_CAN_NXP_S32_CANXL Can_CANEXCEL) +add_subdirectory_ifdef(CONFIG_PSI5_NXP_S32 Psi5) +add_subdirectory_ifdef(CONFIG_PSI5_S_NXP_S32 Psi5_S) diff --git a/s32/drivers/s32ze/Psi5/CMakeLists.txt b/s32/drivers/s32ze/Psi5/CMakeLists.txt new file mode 100644 index 000000000..cdb9b2314 --- /dev/null +++ b/s32/drivers/s32ze/Psi5/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: BSD-3-Clause + +zephyr_include_directories(include) +zephyr_library_sources(src/Psi5_Ip.c) +zephyr_library_sources(src/Psi5_Ip_Irq.c) diff --git a/s32/drivers/s32ze/Psi5/include/Psi5_Ip.h b/s32/drivers/s32ze/Psi5/include/Psi5_Ip.h new file mode 100644 index 000000000..eca979a6f --- /dev/null +++ b/s32/drivers/s32ze/Psi5/include/Psi5_Ip.h @@ -0,0 +1,247 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_H +#define PSI5_IP_H + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Psi5_Ip_Types.h" +#include "Psi5_Ip_Cfg.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFOPSI5ATION +==================================================================================================*/ +#define PSI5_IP_VENDOR_ID 43 +#define PSI5_IP_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_SW_MAJOR_VERSION 2 +#define PSI5_IP_SW_MINOR_VERSION 0 +#define PSI5_IP_SW_PATCH_VERSION 0 + + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Checks against Psi5_Ip_Types.h */ +#if (PSI5_IP_VENDOR_ID != PSI5_IP_TYPES_VENDOR_ID) + #error "Psi5_Ip.h and Psi5_Ip_Types.h have different vendor ids" +#endif +#if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_REVISION_VERSION != PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.h and Psi5_Ip_Types.h are different" +#endif +#if ((PSI5_IP_SW_MAJOR_VERSION != PSI5_IP_TYPES_SW_MAJOR_VERSION) || \ + (PSI5_IP_SW_MINOR_VERSION != PSI5_IP_TYPES_SW_MINOR_VERSION) || \ + (PSI5_IP_SW_PATCH_VERSION != PSI5_IP_TYPES_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip.h and Psi5_Ip_Types.h are different" +#endif + +/* Checks against Psi5_Ip_Cfg.h */ +#if (PSI5_IP_VENDOR_ID != PSI5_IP_CFG_VENDOR_ID) + #error "Psi5_Ip.h and Psi5_Ip_Cfg.h have different vendor ids" +#endif +#if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION != PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION != PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_REVISION_VERSION != PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.h and Psi5_Ip_Cfg.h are different" +#endif +#if ((PSI5_IP_SW_MAJOR_VERSION != PSI5_IP_CFG_SW_MAJOR_VERSION) || \ + (PSI5_IP_SW_MINOR_VERSION != PSI5_IP_CFG_SW_MINOR_VERSION) || \ + (PSI5_IP_SW_PATCH_VERSION != PSI5_IP_CFG_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip.h and Psi5_Ip_Cfg.h are different" +#endif + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#define PSI5_START_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" +/** +* @brief Export PSI5 configurations. +*/ +PSI5_IP_CONFIG_EXT + +#define PSI5_STOP_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + + +/** +* @brief Interrupt handler signature for PSI5 module. +* +* @param[in] Psi5InstanceId Instance number +* @param[in] Psi5ChannelId Instance channel number +* @return void +* +*/ +void Psi5_Ip_IRQ_Handler(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +/*! + * @brief Main initializer for the driver + * + * Initializes the driver for a given peripheral + * according to the given configuration structure. + * + * @param[in] configPtr Pointer to the configuration structure + */ +void Psi5_Ip_Init(const Psi5_Ip_ConfigType *configPtr); + +/*! + * @brief Reset the peripheral. + * + * De-Initializes the peripheral and brings it's registers into a reset state. + * + */ +void Psi5_Ip_DeInit(void); + +#if (STD_ON == PSI5_IP_TRANSMIT_API) +/*! + * @brief Transmit a data frame + * + * Transmits a data frame according to configuration. + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Channel number + * @param[in] Psi5Data Data to send + * @return STATUS_SUCCESS If transmit succeeded + * @return STATUS_ERROR If not configured or not enabled or not ready + */ +Std_ReturnType Psi5_Ip_Transmit(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const uint64 Psi5Data + ); +#endif + +#if (STD_ON == PSI5_IP_GET_TRANSMISSION_STATUS_API) +/*! + * @brief Transmission status + * + * Returns the status of the transmission. + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Channel number + * @return true If transmission ready + * @return false If transmission pending + */ +boolean Psi5_Ip_GetTransmissionStatus(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +#endif + +#if (STD_ON == PSI5_IP_GET_PSI5_FRAME_API) +/*! + * @brief Gets a PSI5 frame + * + * Returns the last received PSI5 frame. + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Channel number + * @param[out] Psi5FramePtr Target variable + */ +Std_ReturnType Psi5_Ip_GetPsi5Frame(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_Psi5FrameType *PsiFramePtr + ); +#endif + +#if (STD_ON == PSI5_IP_GET_SMC_FRAME_API) +/*! + * @brief Gets a SMC frame + * + * Returns the last received SMC frame. + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Channel number + * @param[out] Psi5FramePtr Target variable + */ +Std_ReturnType Psi5_Ip_GetSmcFrame(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_SmcFrameType *Psi5SmcFramePtr + ); +#endif + +#if (STD_ON == PSI5_IP_SET_GLOBAL_SYNC_API) +/*! + * @brief Global sync state + * + * Changes the global sync pulse generator state + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5State Desired state + */ +Std_ReturnType Psi5_Ip_SetGlobalSync(const uint8 Psi5InstanceId, + const boolean PsiState + ); +#endif + +#if (STD_ON == PSI5_IP_SET_CHANNEL_SYNC_API) +/*! + * @brief Channel sync state + * + * Changes the channel sync pulse generator state + * + * @param[in] Psi5InstanceId Instance number + * @param[in] Psi5ChannelId Instance channel number + * @param[in] Psi5State Desired state + */ +Std_ReturnType Psi5_Ip_SetChannelSync(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const boolean PsiState + ); +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +/*! @}*/ /* End of addtogroup psi5 */ + +#endif /* PSI5_IP_H */ diff --git a/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Irq.h b/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Irq.h new file mode 100644 index 000000000..bc8872cee --- /dev/null +++ b/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Irq.h @@ -0,0 +1,174 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_IRQ_H +#define PSI5_IP_IRQ_H + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Psi5_Ip_Cfg_Defines.h" +#include "Mcal.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFOPSI5ATION +==================================================================================================*/ +#define PSI5_IP_IRQ_VENDOR_ID 43 +#define PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_IRQ_SW_MAJOR_VERSION 2 +#define PSI5_IP_IRQ_SW_MINOR_VERSION 0 +#define PSI5_IP_IRQ_SW_PATCH_VERSION 0 + + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + /* Checks against Mcal.h */ + #if ((PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip_Irq.h and Mcal.h are different" + #endif +#endif + +/* Checks against Psi5_Ip_Cfg_Defines.h */ +#if (PSI5_IP_IRQ_VENDOR_ID != PSI5_IP_CFG_DEFINES_VENDOR_ID) + #error "Psi5_Ip_Irq.h and Psi5_Ip_Cfg_Defines.h have different vendor ids" +#endif +#if ((PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip_Irq.h and Psi5_Ip_Cfg_Defines.h are different" +#endif +#if ((PSI5_IP_IRQ_SW_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_SW_MINOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ + (PSI5_IP_IRQ_SW_PATCH_VERSION != PSI5_IP_CFG_DEFINES_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip_Irq.h and Psi5_Ip_Cfg_Defines.h are different" +#endif + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 0. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_0_CH0); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 1. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_0_CH1); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH2 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 2. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_0_CH2); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH3 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 3. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_0_CH3); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 0. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_1_CH0); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 1. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_1_CH1); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH2 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 2. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_1_CH2); +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH3 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 3. + *END**************************************************************************/ +ISR(Psi5_IRQ_Handle_PSI5_1_CH3); +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +/*! @}*/ /* End of addtogroup psi5 */ + +#endif /* PSI5_IP_H */ diff --git a/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Types.h b/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Types.h new file mode 100644 index 000000000..7ac7373c8 --- /dev/null +++ b/s32/drivers/s32ze/Psi5/include/Psi5_Ip_Types.h @@ -0,0 +1,440 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_TYPES_H +#define PSI5_IP_TYPES_H + +/** +* @file Psi5_Ip_Types.h +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + +/*=============================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +===============================================================================================*/ +#include "Psi5_Ip_Cfg_Defines.h" +/*=============================================================================================== + SOURCE FILE VERSION INFORMATION +===============================================================================================*/ +#define PSI5_IP_TYPES_VENDOR_ID 43 +#define PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_TYPES_SW_MAJOR_VERSION 2 +#define PSI5_IP_TYPES_SW_MINOR_VERSION 0 +#define PSI5_IP_TYPES_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Checks against Psi5_Ip_Cfg_Defines.h */ +#if (PSI5_IP_TYPES_VENDOR_ID != PSI5_IP_CFG_DEFINES_VENDOR_ID) + #error "Psi5_Ip_Types.h and Psi5_Ip_Cfg_Defines.h have different vendor ids" +#endif +#if ((PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip_Types.h and Psi5_Ip_Cfg_Defines.h are different" +#endif +#if ((PSI5_IP_TYPES_SW_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ + (PSI5_IP_TYPES_SW_MINOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ + (PSI5_IP_TYPES_SW_PATCH_VERSION != PSI5_IP_CFG_DEFINES_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_Ip_Types.h and Psi5_Ip_Cfg_Defines.h are different" +#endif +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ +/*! + * @brief PSI5 Rx mode + * + * Possible values for setting the reception mode + * + * Implements : psi5_rx_mode_Class + */ +typedef enum +{ + PSI5_ASYNCHRONOUS = 0, /*!< Asynchronous mode (Rx only)*/ + PSI5_SYNCHRONOUS /*!< Synchronous mode (Rx and Tx)*/ +} Psi5_Ip_ChannelModeType; + +/*! + * @brief PSI5 Tx mode + * + * Possible values for setting the transmission mode + * + * Implements : psi5x_mode_Class + */ +typedef enum +{ + PSI5_TX_MODE_0 = 0, /*!< Short Frame(V1.3) with 31 "1s" as the start condition */ + PSI5_TX_MODE_1, /*!< Short Frame(V1.3) with 5 "0s" as the start condition */ + PSI5_TX_MODE_2, /*!< Long Frame(V1.3) with 31 "1s" as the start condition */ + PSI5_TX_MODE_3, /*!< Long Frame(V1.3) with 5 "0s" as the start condition */ + PSI5_TX_MODE_4, /*!< X-Long Frame(V1.3) with 31 "1s" as the start condition */ + PSI5_TX_MODE_5, /*!< X-Long Frame(V1.3) with 5 "0s" as the start condition */ + PSI5_TX_MODE_6, /*!< XX-Long (V2.0) */ + PSI5_TX_MODE_7 /*!< Non Standard Length */ +} Psi5_Ip_TxModeType; + +/*! + * @brief PSI5 Sync state + * + * Possible values for setting the pulse generation state + * + * Implements : psi5_sync_state_Class + */ +typedef enum +{ + PSI5_SYNC_STATE_2 = 1, /*!< Periodic Sync Pulse Generation with ECU-to-sensor Communication */ + PSI5_SYNC_STATE_1 = 3, /*!< Periodic Sync Pulse Generation (without pulse length modulation) */ + PSI5_SYNC_STATE_4 = 5, /*!< Event triggered sync pulse, including ECU-to-sensor communication */ + PSI5_SYNC_STATE_3 = 7 /*!< Event triggered (e.g. angle synchronous) sync pulses */ +} Psi5_Ip_SyncStateType; + +/*! + * @brief PSI5 instance id type + * + * Type for holding instance id + * + * Implements : Psi5_InstanceType_Class + */ +typedef enum +{ + PSI5_INSTANCE0 = 0u, /*!< Instance 0*/ + PSI5_INSTANCE1 /*!< Instance 1*/ +} Psi5_Ip_InstanceIdType; + +/*! + * @brief PSI5 DMA mode type + * + * Type for holding Dma mode + * + */ +typedef enum +{ + PSI5_DMA_MODE_CONF1 = 0u, /*!< DMA rewquest is disable*/ + PSI5_DMA_MODE_CONF2 = 1u, /*!< DMA request transfer for PSI5 message and diagnostic*/ + PSI5_DMA_MODE_CONF3 = 2u, /*!< DMA request transfer for PSI5 message only*/ + PSI5_DMA_MODE_CONF4 = 3u, /*!< DMA request transfer for PSI5 diagnostic only*/ +} Psi5_Ip_Psi5DmaModeType; + + +typedef uint8 Psi5_Ip_HwChannelIdType; + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/* Get PSI5 hw Instance Id */ +#define PSI5_GET_HW_INSTANCE(internalMappingCh) (((((uint8)internalMappingCh) >> ((uint8)4u)) == 0u) ? PSI5_INSTANCE0 : PSI5_INSTANCE1) + +/* Get PSI5 hw channel Id */ +#define PSI5_GET_HW_CHANNEL(internalMappingCh) ((uint8)(((uint8)internalMappingCh) & (uint8)0x0Fu)) + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/** + * @brief PSI5 event structure + * + * Contains data of event flags. + */ +typedef struct +{ + /* PSI5 event flags */ + boolean Psi5_Psi5MessageReceived; /*!< PSI5 Message Received Event */ + boolean Psi5_Psi5MessageOverwrite; /*!< PSI5 Message Overwrite Event */ + boolean Psi5_Psi5MessageErrorsPresent; /*!< PSI5 Message Errors Present Event */ + + /* SMC event flags */ + boolean Psi5_SmcMessageReceived; /*!< SMC Message Received Event */ + boolean Psi5_SmcMessageOverwrite; /*!< SMC Message Overwrite Event */ + boolean Psi5_SmcMessageCRCError; /*!< SMC Message CRC Error Event */ + + /* Tx event flags */ + boolean Psi5_TxDataOverwrite; /*!< Data register overwrite */ + boolean Psi5_DriverReadyToTransmit; /*!< Driver is ready to transmit new data */ + + /* PSI5 DMA event flags */ + boolean Psi5_Psi5DmaOverflow; /*!< DMA FIFO is FULL */ + boolean Psi5_Psi5DmaUnderflow; /*!< Underflow happens when the software reads the PSI5 message/error FIFO though the DPMR/DDSR, beyond the available message */ + boolean Psi5_Psi5DmaTransferComplete; /*!< DMA Transfer is complete */ + + /* SMC DMA event flags */ + boolean Psi5_SmcDmaUnderflow; /*!< This happens when the DSFR has been read without a proper DMA request being asserted. The DSFR is empty and it is read with DMA */ + boolean Psi5_SmcDmaTransferComplete; /*!< DMA Transfer is complete */ +} Psi5_Ip_EventType; + +/*! + * @brief Psi5 event type needed for callback + * + * Workaround because notification is defined in IP layer + * + * Implements : Psi5_EventType_Class +*/ +typedef Psi5_Ip_EventType Psi5_EventType; + +/*! + * @brief Callback function + * + * PSI5 callback prototype. Called from IRQ. + * + * Implements : Psi5_CallbackType_func_Class + */ +typedef void(* Psi5_Ip_CallbackType)(Psi5_EventType Event); + +/*! + * @brief PSI5 slot data type + * + * Slot configuration structure + * + * Implements : psi5_slot_config_Class + */ +typedef struct +{ + uint8 slotId; /*!< Slot id number (1-6) */ + uint16 slotLen; /*!< Slot size (in us) */ + uint16 startOffs; /*!< Slot start offset (from sync pulse, in us) */ + uint8 dataSize; /*!< Data region length */ + boolean msbFirst; /*!< Data is interpreted as MSB first */ + boolean hasSMC; /*!< Contains a Slow Message Channel in bits M0/M1 */ + boolean tsCapS0; /*!< Capture time-stamp at S0, otherwise at sync */ + boolean hasParity; /*!< Contains parity error detection, CRC otherwise */ +} Psi5_Ip_SlotConfigType; + +/*! + * @brief Raw data frame + * + * A raw PSI5/SMC frame. Contains hardware specific fields. Needs conversion. + * + * Implements : psi5_raw_frame_Class + */ +typedef uint32 Psi5_Ip_RawFrameType[2u]; + +/*! + * @brief PSI5 data frame + * + * A PSI5 frame. Contains specific fields. + * + * Implements : Psi5_Ip_Psi5FrameType_Class + */ +typedef struct +{ + uint32 DATA_REGION; /*!< Data region (28 bits) */ + uint32 TIME_STAMP; /*!< Time stamp value (24 bits) */ + uint8 CRC; /*!< CRC value Parity (3 bits, 1 bit parity in C[2] if configured) */ + uint8 C; /*!< CRC error (1 bit) */ + uint8 F; /*!< No Frame error (1 bit) */ + uint8 EM; /*!< M0/1 Error (1 bit) */ + uint8 E; /*!< Electrical error (1 bit) */ + uint8 T; /*!< Timing error (1 bit) */ + uint8 SLOT_COUNTER; /*!< Slot number (3 bits) */ +} Psi5_Ip_Psi5FrameType; + +/*! + * @brief SMC data frame + * + * A SMC frame. Contains specific fields. + * + * Implements : Psi5_SmcFrameType_Class + */ +typedef struct +{ + uint16 DATA; /*!< DATA payload */ + uint8 SLOT_NO; /*!< Slot number (3 bit)*/ + uint8 CER; /*!< CRC error (1 bit) */ + uint8 OW; /*!< Overwrite status (1 bit) */ + uint8 CRC; /*!< CRC (6 bit) */ + uint8 C; /*!< Configuration bit (1 bit) */ + uint8 ID; /*!< Message ID: If C = '0' indicates ID[7:4], if C = '1' indicates ID[3:0] */ + uint8 IDDATA; /*!< Message ID/DATA: If C = '0' indicates ID[3:0], if C = '1' indicates DATA[15:12] */ +} Psi5_Ip_SmcFrameType; + +typedef Psi5_Ip_RawFrameType Psi5_RawFrameType; + +/*! + * @brief Channel rx Psi5 Dmaconfiguration structure + * + * Contains configuration data for one channel. + * + */ +typedef struct +{ + Psi5_Ip_Psi5DmaModeType psi5DmaMode; /*!< Mode of PSI5 DMA Frame*/ + const uint32 psi5DmaWatermarkDmaTrigger; /*!< Interrupt request enabled when any new message (fault-free/with fault) is received in the RAM buffer Register 'x' location [x: 0 to 31] */ + Psi5_Ip_Psi5FrameType *psi5DmaUserBuffer; /*!< DMA user data buffer for PSI5 messages */ + uint32 *psi5DmaUserDiagnosticBuffer; /*!< DMA user diagnostic buffer for PSI5 messages */ + Psi5_Ip_RawFrameType *psi5DmaInternalBuffer; /*!< DMA raw internal buffer for PSI5 messages */ + const uint8 psi5DmaChannel; /*!< Assigned DMA channel for PSI5 frames */ +} Psi5_Ip_ChannelRxPsi5DmaConfigType; + +/*! + * @brief Channel rx Smc Dmaconfiguration structure + * + * Contains configuration data for one channel. + * + */ +typedef struct +{ + Psi5_Ip_SmcFrameType *smcDmaUserBuffer; /*!< DMA user data buffer for Smc messages */ + Psi5_Ip_RawFrameType *smcDmaInternalBuffer; /*!< DMA raw internal buffer for PSI5 messages */ + const uint8 smcDmaChannel; /*!< Assigned DMA channel for SMC frames */ +} Psi5_Ip_ChannelRxSmcDmaConfigType; + +/*! + * @brief Channel rx configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5_channel_rx_config_Class + */ +typedef struct +{ + const uint8 rxBufSize; /*!< Size of RX buffer for PSI5 messages (1 - 32) */ + const uint32 watermarkInterruptLevel; /*!< Interrupt request enabled when any new message (fault-free/with fault) is received in the RAM buffer Register 'x' location [x: 0 to 31] */ + const uint8 bitRate; /*!< 0 - 125 Kbit/s bit rate, 1 - 189 Kbit/s bit rate*/ + const Psi5_Ip_ChannelRxPsi5DmaConfigType *psi5DmaConfig; /*!< DMA buffer for PSI5 messages */ + const Psi5_Ip_ChannelRxSmcDmaConfigType *smcDmaConfig; /*!< DMA buffer for SMC messages */ + const Psi5_Ip_SlotConfigType *slotConfig; /*!< Pointer to a slot configuration list */ + const uint8 numOfSlotConfigs; /*!< Number of configurations in the slot configuration list */ +} Psi5_Ip_ChannelRxConfigType; + +/*! + * @brief Channel tx configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5_channel_tx_config_Class + */ +typedef struct +{ + const boolean syncGlobal; /*!< Sync generator controlled by the instance */ + const boolean asyncReset; /*!< GTM reset is treated asynchronous */ + const uint16 initialPulse; /*!< Initial reset reload value for the integrated pulse generator */ + const uint16 targetPulse; /*!< Subsequent reload values for the integrated pulse generator */ + const uint8 decoderOffset; /*!< Time in us for which the manchester decoder is disabled after the falling edge of a sync pulse */ + const uint8 pulse0Width; /*!< Width (in us) for a "0" output pulse */ + const uint8 pulse1Width; /*!< Width (in us) for a "1" output pulse */ + const Psi5_Ip_TxModeType txMode; /*!< Transmitter mode, please refer to RM */ + const Psi5_Ip_SyncStateType syncState; /*!< Pulse generator state, please refer to RM */ + const uint8 txSize; /*!< Tx data length (only for TX_MODE_7) */ + const boolean txDefault1; /*!< All bits in Tx registers will default to "1" */ +} Psi5_Ip_ChannelTxConfigType; + +typedef struct +{ + const boolean errorSelect0; + const boolean errorSelect1; + const boolean errorSelect2; + const boolean errorSelect3; + const boolean errorSelect4; +} Psi5_Ip_ErrorSelectConfigType; + + +/*! + * @brief Channel configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5_channel_config_Class + */ +typedef struct +{ + const uint8 channelId; /*!< Channel id number (0-3) */ + const Psi5_Ip_ChannelModeType channelMode; /*!< Communication mode */ + const boolean debugEnable; /*!< Enable/Disable debug mode */ + const boolean debugFreeze; /*!< Enable/Disable debug freeze */ + const Psi5_Ip_CallbackType callback; /*!< Callback data */ + const Psi5_Ip_ChannelRxConfigType *rxConfig; /*!< Rx Configuration */ + const Psi5_Ip_ChannelTxConfigType *txConfig; /*!< Tx Configuration */ + const Psi5_Ip_ErrorSelectConfigType *errorSelectConfig; /*!< Error Select Configuration */ +} Psi5_Ip_ChannelConfigType; + +/*! + * @brief Instance configuration structure + * + * PSI5 instance configuration structure. Contains all data required to configure the instance. + * + * Implements : psi5_driver_user_config_Class + */ +typedef struct +{ + const Psi5_Ip_InstanceIdType instanceId; /*!< PSI5 instance id */ + const boolean globalCtcEn; /*!< Pulse generation automatically starts at init (outcome depends on channel configuration) */ + const Psi5_Ip_ChannelConfigType *channelConfig; /*!< Pointer to a channel configuration list */ + const uint8 numOfChannels; /*!< Number of channels configured */ + const uint8 *chHwIdToIndexArrayConfig; /*!< Array with mapping of channel hw id to the index in channel config array */ +} Psi5_Ip_InstanceType; +/*! + * @brief Channels configuration structure + * + * PSI5 instance configuration structure. Contains all data required to configure the channels of an instance. + * + * Implements : psi5_driver_user_config_Class + */ +typedef struct +{ + const Psi5_Ip_InstanceType *instancesConfig; /*!< Pointer to instances configuration list */ + const uint8 numOfInstances; /*!< Number of instances configured */ + const uint8 *logicalChToHwCh; /*!< Pointer to array mapping logical channel to hardware channel */ +} Psi5_Ip_ConfigType; + +/*! + * @brief Two arrays for both types of psi5 message format (psi5 and smc) + * + * Both arrays are used in FILO mode. Contains position of received messages. + * Last value from array different than 0 correspond with position of last received message. + * + * Implements : psi5_channel_config_Class + */ +typedef struct +{ + uint8 psi5CurrentIndex; /*!< Index of last position filled in messages array */ + uint8 psi5PosMsgAvailable[PSI5_CHANNEL_CH_PMR_COUNT]; /*!< Buffer with locations of PSI5 messages available for reading. 0xFF - default, no message aavailable. Value != 0 means Position in reg NDSR. (internal use) */ + uint8 smcCurrentIndex; /*!< Index of last position filled in array */ + uint8 smcPosMsgAvailable[PSI5_CHANNEL_CH_SFR_COUNT]; /*!< Buffer with locations of SMC messages available for reading. 0xFF - default, no message aavailable. Value != 0 means Position in reg (GISR & IS_NVSM_MASK). (internal use) */ +} Psi5_Ip_AvailableMessagesType; + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*=============================================================================================== + GLOBAL VARIABLE DECLARATIONS +===============================================================================================*/ + +/*=============================================================================================== +* FUNCTION PROTOTYPES +===============================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* PSI5_IP_TYPES_H */ + diff --git a/s32/drivers/s32ze/Psi5/src/Psi5_Ip.c b/s32/drivers/s32ze/Psi5/src/Psi5_Ip.c new file mode 100644 index 000000000..257d5b15b --- /dev/null +++ b/s32/drivers/s32ze/Psi5/src/Psi5_Ip.c @@ -0,0 +1,1825 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file Psi5_Ip.c +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ + +#include "Mcal.h" +#include "Psi5_Ip.h" +#include "Psi5_Ip_Cfg.h" +#include "SchM_Psi5.h" + +#if (STD_ON == PSI5_IP_DMA_IS_USED) +#include "CDD_Mcl.h" +#endif + +#ifdef PSI5_IP_DEV_ERROR_DETECT +#if (STD_ON == PSI5_IP_DEV_ERROR_DETECT) + #include "Devassert.h" +#endif +#endif + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_VENDOR_ID_C 43 +#define PSI5_IP_AR_RELEASE_MAJOR_VERSION_C 4 +#define PSI5_IP_AR_RELEASE_MINOR_VERSION_C 7 +#define PSI5_IP_AR_RELEASE_REVISION_VERSION_C 0 +#define PSI5_IP_SW_MAJOR_VERSION_C 2 +#define PSI5_IP_SW_MINOR_VERSION_C 0 +#define PSI5_IP_SW_PATCH_VERSION_C 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + /* Checks against Mcal.h */ + #if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION_C != MCAL_AR_RELEASE_MINOR_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.c and Mcal.h are different" + #endif +#endif + +/* Checks against Psi5_Ip.h */ +#if (PSI5_IP_VENDOR_ID_C != PSI5_IP_VENDOR_ID) + #error "Psi5_Ip.c and Psi5_Ip.h have different vendor ids" +#endif +#if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION_C != PSI5_IP_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION_C != PSI5_IP_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_REVISION_VERSION_C != PSI5_IP_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.c and Psi5_Ip.h are different" +#endif +#if ((PSI5_IP_SW_MAJOR_VERSION_C != PSI5_IP_SW_MAJOR_VERSION) || \ + (PSI5_IP_SW_MINOR_VERSION_C != PSI5_IP_SW_MINOR_VERSION) || \ + (PSI5_IP_SW_PATCH_VERSION_C != PSI5_IP_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip.c and Psi5_Ip.h are different" +#endif + +/* Checks against Psi5_Ip_Cfg.h */ +#if (PSI5_IP_VENDOR_ID_C != PSI5_IP_CFG_VENDOR_ID) + #error "Psi5_Ip.c and Psi5_Ip_Cfg.h have different vendor ids" +#endif +#if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION_C != PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION_C != PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_REVISION_VERSION_C != PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.c and Psi5_Ip_Cfg.h are different" +#endif +#if ((PSI5_IP_SW_MAJOR_VERSION_C != PSI5_IP_CFG_SW_MAJOR_VERSION) || \ + (PSI5_IP_SW_MINOR_VERSION_C != PSI5_IP_CFG_SW_MINOR_VERSION) || \ + (PSI5_IP_SW_PATCH_VERSION_C != PSI5_IP_CFG_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip.c and Psi5_Ip_Cfg.h are different" +#endif + +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + #ifdef AXBS_IP_DEV_ERROR_DETECT + #if (STD_ON == AXBS_IP_DEV_ERROR_DETECT) + /* Check if the files Psi5_Ip.c and Devassert.h are of the same version */ + #if ((PSI5_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip.c and Devassert.h are different" + #endif + #endif + #endif +#endif +/*================================================================================================== +* LOCAL MACROS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) +==================================================================================================*/ + +/*================================================================================================== +* LOCAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL VARIABLES +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + +/*! + *Instance base addresses + */ +static const PSI5_MemMapPtr Psi5_Ip_axBaseAddresses[PSI5_INSTANCE_COUNT] = IP_PSI5_BASE_PTRS; + +/*================================================================================================== +* GLOBAL VARIABLES +==================================================================================================*/ +#if (STD_ON == PSI5_IP_MULTIPARTITION_SUPPORT) +#define PSI5_START_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" + +static Psi5_Ip_ConfigType const *Psi5_Ip_pUsedConfig = NULL_PTR; +static Psi5_Ip_AvailableMessagesType Psi5_Ip_axMessages[PSI5_INSTANCE_COUNT][PSI5_CHANNEL_COUNT]; +static boolean Psi5_Ip_bDriverInitialized = FALSE; + +#define PSI5_STOP_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" +#else +#define PSI5_START_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +static Psi5_Ip_ConfigType const *Psi5_Ip_pUsedConfig = NULL_PTR; + +#define PSI5_STOP_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +#define PSI5_START_SEC_VAR_CLEARED_UNSPECIFIED +#include "Psi5_MemMap.h" + +static Psi5_Ip_AvailableMessagesType Psi5_Ip_axMessages[PSI5_INSTANCE_COUNT][PSI5_CHANNEL_COUNT]; + +static boolean Psi5_Ip_bDriverInitialized = FALSE; + +#define PSI5_STOP_SEC_VAR_CLEARED_UNSPECIFIED +#include "Psi5_MemMap.h" +#endif + +/*================================================================================================== +* LOCAL FUNCTION PROTOTYPES +==================================================================================================*/ + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" +#if (STD_ON == PSI5_IP_GET_PSI5_FRAME_API) +static Std_ReturnType Psi5_Hw_GetRawPsi5Frame(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_RawFrameType *raw + ); +#endif + +#if ((STD_ON == PSI5_IP_GET_PSI5_FRAME_API) || (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED)) +static void Psi5_Hw_ConvertRawPsi5Frame(Psi5_Ip_Psi5FrameType *frame, + Psi5_Ip_RawFrameType *raw, + const Psi5_Ip_SlotConfigType *states + ); +#endif +#if (STD_ON == PSI5_IP_GET_SMC_FRAME_API) +static Std_ReturnType Psi5_Hw_GetRawSmcFrame(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_RawFrameType *raw + ); +#endif +#if ((STD_ON == PSI5_IP_GET_SMC_FRAME_API) || (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED)) +static void Psi5_Hw_ConvertRawSmcFrame(Psi5_Ip_SmcFrameType *frame, + Psi5_Ip_RawFrameType *raw + ); +#endif +static void Psi5_Hw_ConfigureSlot(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const Psi5_Ip_SlotConfigType *slot + ); +static void Psi5_Hw_EnterConfigMode(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +static void Psi5_Hw_EnterNormalMode(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +static void Psi5_Hw_ConfigureTx(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ); +static void Psi5_Hw_ConfigureRx(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ); +static void Psi5_Hw_ConfigurePulseGenerator(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ); +#if (STD_ON == PSI5_IP_DMA_IS_USED) +static void Psi5_Hw_ConfigureDma(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ); +#endif +static void Psi5_Hw_InstanceDisable(const Psi5_Ip_InstanceIdType instanceId, + const boolean state + ); +static Std_ReturnType Psi5_Hw_StartGlobalCtc(const Psi5_Ip_InstanceIdType instanceId, + const boolean state + ); +static void Psi5_Hw_ResetRegisters(const Psi5_Ip_InstanceIdType instance); +#if ((STD_ON == PSI5_IP_GET_TRANSMISSION_STATUS_API) || (STD_ON == PSI5_IP_TRANSMIT_API)) +static boolean Psi5_Hw_IsDataRegisterReady(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); +#endif +static void Psi5_EnterConfigMode(const Psi5_Ip_InstanceType *instance); +static void Psi5_EnterNormalMode(const Psi5_Ip_InstanceType *instance); +static void Psi5_ConfigureSlots(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *channelConfig + ); +static void Psi5_ConfigureChannel(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType * chCfg + ); +static void Psi5_ConfigureChannels(const Psi5_Ip_InstanceType * instance); + +static void Psi5_Hw_GetTxEvents(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ); +static void Psi5_Hw_GetSmcEvents(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ); +static void Psi5_Hw_GetPsi5Events(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ); +static void Psi5_Hw_GetEvents(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ); +static void Psi5_Hw_EnableInterrupts(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_ChannelConfigType *chCfg, + const boolean Enable + ); +static void Psi5_Hw_ClearEvents(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ); + +/** + * + * Function Name : Psi5_Hw_GetTxEvents + * Description : Returns active Tx events + * + *END**************************************************************************/ +static void Psi5_Hw_GetTxEvents(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ) +{ + const PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); + uint32 regValue; + + if (NULL_PTR != config->txConfig) + { + uint32 txMaskOvr = (config->txConfig->txMode == PSI5_TX_MODE_7) ? PSI5_CH_GISR_IS_DSROW_MASK : PSI5_CH_GISR_IS_PROW_MASK; + uint32 txMaskOvrSet = (config->txConfig->txMode == PSI5_TX_MODE_7) ? PSI5_CH_GICR_IE_DSROW_MASK : PSI5_CH_GICR_IE_PROW_MASK; + uint32 txMaskRdy = (config->txConfig->txMode == PSI5_TX_MODE_7) ? PSI5_CH_GISR_DSR_RDY_MASK : PSI5_CH_GISR_DPR_RDY_MASK; + uint32 txMaskRdySet = (config->txConfig->txMode == PSI5_TX_MODE_7) ? PSI5_CH_GICR_IE_DSRR_MASK : PSI5_CH_GICR_IE_PRR_MASK; + + regValue = base->CHANNEL[Psi5ChannelId].CH_GISR & txMaskOvr; + + /* Data prep overwrite */ + if (0u != regValue) + { + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GICR & txMaskOvrSet)) + { + Events->Psi5_TxDataOverwrite = TRUE; + + /*Disable interrupt, it will be re-enabled in the transmit function*/ + base->CHANNEL[Psi5ChannelId].CH_GICR &= ~txMaskOvrSet; + } + /*clear interrupt*/ + base->CHANNEL[Psi5ChannelId].CH_GISR |= txMaskOvr; + } + + regValue = base->CHANNEL[Psi5ChannelId].CH_GISR & txMaskRdy; + /* Data prep ready */ + if (0u != regValue) + { + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GICR & txMaskRdySet)) + { + Events->Psi5_DriverReadyToTransmit = TRUE; + + /*Disable interrupt, it will be re-enabled in the transmit function*/ + base->CHANNEL[Psi5ChannelId].CH_GICR &= ~txMaskRdySet; + } + /*There is no interrupt flag, does not need clear interrupt*/ + } + } +} + +/** + * + * Function Name : Psi5_Hw_GetSmcEvents + * Description : Returns active SMC events + * + *END**************************************************************************/ +static void Psi5_Hw_GetSmcEvents(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ) +{ + const PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; +#if (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED) + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); +#endif + + uint8 tempPosition = 0u; + uint8 regRavlue; + +#if (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED) + /* SMC DMA / Normal */ + if (NULL_PTR != config->rxConfig->smcDmaConfig) + { + /* Ready */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_TF_SF_MASK)) + { + if (0u != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_TF_SF_MASK)) + { + Events->Psi5_SmcDmaTransferComplete = TRUE; + + /*Convert data*/ + Psi5_Hw_ConvertRawSmcFrame(config->rxConfig->smcDmaConfig->smcDmaUserBuffer, config->rxConfig->smcDmaConfig->smcDmaInternalBuffer); + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_TF_SF_MASK; + } + + /* Underflow */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_SFUF_MASK)) + { + if (0u != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_SFUF_MASK)) + { + Events->Psi5_SmcDmaUnderflow = TRUE; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_SFUF_MASK; + } + } + else +#endif + { + /* SMC Rx Complete */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_NVSM_MASK)) + { + /* Mark event */ + Events->Psi5_SmcMessageReceived = TRUE; + + regRavlue = (uint8)((base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_NVSM_MASK) >> PSI5_CH_GISR_IS_NVSM_SHIFT); + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_SFR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + if (0XFFu == Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex = 0u; + } + + /*increment index of array and save bit position*/ + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcPosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex] = tempPosition; + + if ((Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex + 1u) >= PSI5_CHANNEL_CH_SFR_COUNT) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex = 0u; + } + else + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_GISR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + + /* SMC Overwrite */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_OWSM_MASK)) + { + Events->Psi5_SmcMessageOverwrite = TRUE; + + regRavlue = (uint8)((base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_OWSM_MASK) >> PSI5_CH_GISR_IS_OWSM_SHIFT); + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_SFR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_GISR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + + /* SMC error */ + if (0u != (base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_CESM_MASK)) + { + Events->Psi5_SmcMessageCRCError = TRUE; + + regRavlue = (uint8)((base->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_IS_CESM_MASK) >> PSI5_CH_GISR_IS_CESM_SHIFT); + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_SFR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_GISR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + } +} + +/** + * + * Function Name : Psi5_Hw_GetPsi5Events + * Description : Returns active PSI5 events + * + *END**************************************************************************/ +static void Psi5_Hw_GetPsi5Events(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; +#if (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED) + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType * config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); + const Psi5_Ip_SlotConfigType * slotStates; + const Psi5_Ip_ChannelRxPsi5DmaConfigType * psi5DmaConfig; + uint8 index = 0; +#endif + + uint32 regRavlue; + uint8 tempPosition = 0u; + +#if (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED) + /* PSI5 DMA */ + if (NULL_PTR != config->rxConfig->psi5DmaConfig) + { + /* Ready */ + if ((0U != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_TF_PM_DS_MASK)) && (0U != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK))) + { + Events->Psi5_Psi5DmaTransferComplete = TRUE; + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_TF_PM_DS_MASK; + + psi5DmaConfig = config->rxConfig->psi5DmaConfig; + /*Convert data if Mode is PSI5_DMA_MODE_CONF2 or PSI5_DMA_MODE_CONF3*/ + if(PSI5_DMA_MODE_CONF4 != psi5DmaConfig->psi5DmaMode) + { + slotStates = config->rxConfig->slotConfig; + + for(index = 0U;index< psi5DmaConfig->psi5DmaWatermarkDmaTrigger; index++) + { + Psi5_Hw_ConvertRawPsi5Frame(&(psi5DmaConfig->psi5DmaUserBuffer[index]), &(psi5DmaConfig->psi5DmaInternalBuffer[index]), slotStates); + } + } + /*store diagnostic bits if Mode is PSI5_DMA_MODE_CONF2*/ + if(PSI5_DMA_MODE_CONF2 == psi5DmaConfig->psi5DmaMode) + { + psi5DmaConfig->psi5DmaUserDiagnosticBuffer[0U] = psi5DmaConfig->psi5DmaInternalBuffer[psi5DmaConfig->psi5DmaWatermarkDmaTrigger][0U]; + psi5DmaConfig->psi5DmaUserDiagnosticBuffer[1U] = psi5DmaConfig->psi5DmaInternalBuffer[psi5DmaConfig->psi5DmaWatermarkDmaTrigger][1U]; + } + /*store diagnostic bits if Mode is PSI5_DMA_MODE_CONF4*/ + if(PSI5_DMA_MODE_CONF4 == psi5DmaConfig->psi5DmaMode) + { + psi5DmaConfig->psi5DmaUserDiagnosticBuffer[0U] = psi5DmaConfig->psi5DmaInternalBuffer[0U][0U]; + psi5DmaConfig->psi5DmaUserDiagnosticBuffer[1U] = psi5DmaConfig->psi5DmaInternalBuffer[0U][1U]; + } + } + + /* Underflow */ + if ((0u != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_PM_DS_UF_MASK)) && (0u != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK))) + { + Events->Psi5_Psi5DmaUnderflow = TRUE; + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_PM_DS_UF_MASK; + } + + /* Overflow */ + if ((0u != (base->CHANNEL[Psi5ChannelId].CH_DSR & PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_MASK)) && (0u != (base->CHANNEL[Psi5ChannelId].CH_DCR & PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_MASK))) + { + Events->Psi5_Psi5DmaOverflow = TRUE; + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_DSR |= PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_MASK; + } + } + else +#endif + { + /* PSI5 Rx Complete */ + if ((0u != base->CHANNEL[Psi5ChannelId].CH_NDSR) && (0u != (base->CHANNEL[Psi5ChannelId].CH_NDICR & PSI5_CH_NDICR_IE_ND_MASK))) + { + /* Mark event */ + Events->Psi5_Psi5MessageReceived = TRUE; + + regRavlue = base->CHANNEL[Psi5ChannelId].CH_NDSR; + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_PMR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*0xFF means that there are no messages waiting to be read*/ + if (0xFFu == Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex = 0u; + } + + /*save bit position*/ + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5PosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex] = tempPosition; + + if ((Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex + 1u) >= PSI5_CHANNEL_CH_PMR_COUNT) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex = 0u; + } + else + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_NDSR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + + /* PSI5 Overwrite */ + if ((0u != base->CHANNEL[Psi5ChannelId].CH_OWSR) && (0u != (base->CHANNEL[Psi5ChannelId].CH_OWICR & PSI5_CH_OWICR_IE_OW_MASK))) + { + Events->Psi5_Psi5MessageOverwrite = TRUE; + + regRavlue = base->CHANNEL[Psi5ChannelId].CH_OWSR; + tempPosition = 0u; + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_PMR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_OWSR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + + /* PSI5 error */ + if ((0u != base->CHANNEL[Psi5ChannelId].CH_EISR) && (0u != (base->CHANNEL[Psi5ChannelId].CH_EICR & PSI5_CH_EICR_IE_ERROR_MASK))) + { + Events->Psi5_Psi5MessageErrorsPresent = TRUE; + + regRavlue = base->CHANNEL[Psi5ChannelId].CH_EISR; + tempPosition = 0u; + + /* Iterate through bits of regRavlue till we find a set bit */ + while ((((regRavlue >> tempPosition) & 1u) == 0u) && (tempPosition < (PSI5_CHANNEL_CH_PMR_COUNT - 1u))) + { + /* increment position */ + tempPosition++; + } + + /*clear interrupt flag*/ + base->CHANNEL[Psi5ChannelId].CH_EISR |= (uint32)((uint32)1u << (uint32)tempPosition); + } + } +} + +/** + * + * Function Name : Psi5_Hw_GetEvents + * Description : Returns active events + * + *END**************************************************************************/ +static void Psi5_Hw_GetEvents(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_EventType *const Events + ) +{ + /* Enter critical region */ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_05(); + + /* Tx events */ + Psi5_Hw_GetTxEvents(Psi5InstanceId, Psi5ChannelId, Events); + /* SMC events */ + Psi5_Hw_GetSmcEvents(Psi5InstanceId, Psi5ChannelId, Events); + /* PSI5 events */ + Psi5_Hw_GetPsi5Events(Psi5InstanceId, Psi5ChannelId, Events); + + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_05(); +} + +#if (STD_ON == PSI5_IP_GET_PSI5_FRAME_API) +/** + * + * Function Name : Psi5_Hw_GetRawPsi5Frame + * Description : Returns a raw PSI5 frame + * + */ +static Std_ReturnType Psi5_Hw_GetRawPsi5Frame(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_RawFrameType *raw + ) +{ + PSI5_Type const * base = Psi5_Ip_axBaseAddresses[instance]; + uint8 msgPosition = PSI5_CHANNEL_CH_PMR_COUNT; + Std_ReturnType retVal; + + /* Enter critical region*/ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_01(); + + if (0xFFu != Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex) + { + if (Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex > 0u) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex--; + + msgPosition = Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5PosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex]; + } + else if (0u == Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex) + { + msgPosition = Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5PosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex]; + + Psi5_Ip_axMessages[instance][Psi5ChannelId].psi5CurrentIndex = 0xFFu; + } + else + { + /* misra fix */ + } + + if (msgPosition < PSI5_CHANNEL_CH_PMR_COUNT) + { + /* Read message */ + (*raw)[0] = base->CHANNEL[Psi5ChannelId].CH_PMR[msgPosition].CH_PMRL; + (*raw)[1] = base->CHANNEL[Psi5ChannelId].CH_PMR[msgPosition].CH_PMRH; + + retVal = (Std_ReturnType)E_OK; + } + else + { + retVal = (Std_ReturnType)E_NOT_OK; + } + } + else + { + retVal = (Std_ReturnType)E_NOT_OK; + } + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_01(); + + return retVal; +} +#endif + +#if (STD_ON == PSI5_IP_GET_SMC_FRAME_API) +/** + * + * Function Name : Psi5_Hw_GetRawSmcFrame + * Description : Returns a raw SMC frame + * + */ +static Std_ReturnType Psi5_Hw_GetRawSmcFrame(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_RawFrameType *raw + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + uint8 msgPosition = PSI5_CHANNEL_CH_SFR_COUNT; + Std_ReturnType retVal; + + /* Enter critical region*/ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_02(); + if (0xFFu != Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex) + { + if (Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex > 0u) + { + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex--; + + msgPosition = Psi5_Ip_axMessages[instance][Psi5ChannelId].smcPosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex]; + } + else if (0u == Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex) + { + msgPosition = Psi5_Ip_axMessages[instance][Psi5ChannelId].smcPosMsgAvailable[Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex]; + + Psi5_Ip_axMessages[instance][Psi5ChannelId].smcCurrentIndex = 0xFFu; + } + else + { + /* misra fix */ + } + + if (msgPosition < PSI5_CHANNEL_CH_SFR_COUNT) + { + /* Read message (only 32 bits in lower data buffer) */ + (*raw)[0] = base->CHANNEL[Psi5ChannelId].CH_SFR[msgPosition]; + + retVal = (Std_ReturnType)E_OK; + } + else + { + retVal = (Std_ReturnType)E_NOT_OK; + } + } + else + { + retVal = (Std_ReturnType)E_NOT_OK; + } + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_02(); + + return retVal; +} +#endif + +#if ((STD_ON == PSI5_IP_GET_PSI5_FRAME_API) || (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED)) +/** + * + * Function Name : Psi5_Hw_ConvertRawPsi5Frame + * Description : Converts a raw PSI5 frame + * + */ +static void Psi5_Hw_ConvertRawPsi5Frame(Psi5_Ip_Psi5FrameType *frame, + Psi5_Ip_RawFrameType *raw, + const Psi5_Ip_SlotConfigType *states + ) +{ + frame->CRC = (uint8)(((*raw)[0] & PSI5_CH_PMRRL_CRC_MASK) >> PSI5_CH_PMRRL_CRC_SHIFT); + frame->C = (uint8)(((*raw)[0] & PSI5_CH_PMRRL_C_MASK) >> PSI5_CH_PMRRL_C_SHIFT); + frame->F = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_F_MASK) >> PSI5_CH_PMRRH_F_SHIFT); + frame->EM = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_EM_MASK) >> PSI5_CH_PMRRH_EM_SHIFT); + frame->E = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_E_MASK) >> PSI5_CH_PMRRH_E_SHIFT); + frame->T = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_T_MASK) >> PSI5_CH_PMRRH_T_SHIFT); + frame->SLOT_COUNTER = (uint8)(((*raw)[1] & PSI5_CH_PMRRH_SlotCounter_MASK) >> PSI5_CH_PMRRH_SlotCounter_SHIFT); + frame->TIME_STAMP = (uint32)(((*raw)[1] & PSI5_CH_PMRRH_TimeStampValue_MASK) >> PSI5_CH_PMRRH_TimeStampValue_SHIFT); + + /* If slot counter is 0 or any other out of range value, we assign settings from slot 1 (index 0) */ + uint32 slotIdx = (frame->SLOT_COUNTER < 1u) ? + 0u : (((frame->SLOT_COUNTER > PSI5_CHANNEL_CH_SFR_COUNT) ? + 5u : ((uint32)frame->SLOT_COUNTER - 1u))); + + /* 28 bits max, left aligned */ + uint32 dataRegion = (uint32)((*raw)[0] >> PSI5_CH_PMRRL_DATA_REGION_SHIFT); + + /* Number of normalization shifts */ + const uint8 shiftCount = (uint8)((uint8)PSI5_CH_PMRRL_DATA_REGION_WIDTH - (uint8)states[slotIdx].dataSize); + + /* If MSB first */ + if (states[slotIdx].msbFirst) + { + /* As we received it */ + frame->DATA_REGION = dataRegion >> shiftCount; + } + else + { + dataRegion = dataRegion >> shiftCount; + /* Reverse bits*/ + for (uint8 i = 0u; i < states[slotIdx].dataSize; i++) + { + if (0u != (dataRegion & (uint32)((uint32)1u << (uint32)i))) + { + frame->DATA_REGION |= (uint32)((uint32)1u << (uint32)((uint32)((uint32)states[slotIdx].dataSize - (uint32)1u) - (uint32)i)); + } + } + } +} +#endif + +#if ((STD_ON == PSI5_IP_GET_SMC_FRAME_API) || (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED)) +/** + * + * Function Name : Psi5_Hw_ConvertRawSmcFrame + * Description : Converts a raw SMC frame + * + */ +static void Psi5_Hw_ConvertRawSmcFrame(Psi5_Ip_SmcFrameType *frame, + Psi5_Ip_RawFrameType *raw + ) +{ + frame->SLOT_NO = (uint8)(((*raw)[0] & PSI5_CH_SFR_SLOT_NO_MASK) >> PSI5_CH_SFR_SLOT_NO_SHIFT); + frame->CER = (uint8)(((*raw)[0] & PSI5_CH_SFR_CER_MASK) >> PSI5_CH_SFR_CER_SHIFT); + frame->OW = (uint8)(((*raw)[0] & PSI5_CH_SFR_OW_MASK) >> PSI5_CH_SFR_OW_SHIFT); + frame->CRC = (uint8)(((*raw)[0] & PSI5_CH_SFR_CRC_MASK) >> PSI5_CH_SFR_CRC_SHIFT); + frame->C = (uint8)(((*raw)[0] & PSI5_CH_SFR_C_MASK) >> PSI5_CH_SFR_C_SHIFT); + frame->IDDATA = (uint8)(((*raw)[0] & PSI5_CH_SFR_IDDATA_MASK) >> PSI5_CH_SFR_IDDATA_SHIFT); + + /* Modify fields based on the C bit */ + if (0u != (frame->C)) + { + frame->ID = (uint8)(((*raw)[0] & PSI5_CH_SFR_ID_MASK) >> PSI5_CH_SFR_ID_SHIFT); + frame->DATA = (uint16)(((*raw)[0] & (PSI5_CH_SFR_IDDATA_MASK | PSI5_CH_SFR_DATA_MASK)) >> PSI5_CH_SFR_DATA_SHIFT); + } + else + { + frame->ID = (uint8)(((*raw)[0] & (PSI5_CH_SFR_ID_MASK | PSI5_CH_SFR_IDDATA_MASK)) >> PSI5_CH_SFR_IDDATA_SHIFT); + frame->DATA = (uint16)(((*raw)[0] & PSI5_CH_SFR_DATA_MASK) >> PSI5_CH_SFR_DATA_SHIFT); + } +} +#endif + +/** + * + * Function Name : Psi5_Hw_ConfigureSlot + * Description : Configures a single slot + * + */ +static void Psi5_Hw_ConfigureSlot(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const Psi5_Ip_SlotConfigType *slot + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + + switch(slot->slotId) + { + case 1u:{ base->CHANNEL[Psi5ChannelId].CH_S1SBR = PSI5_CH_S1SBR_S1SBT(slot->startOffs); break;} + case 2u:{ base->CHANNEL[Psi5ChannelId].CH_S2SBR = PSI5_CH_S2SBR_S2SBT(slot->startOffs); break;} + case 3u:{ base->CHANNEL[Psi5ChannelId].CH_S3SBR = PSI5_CH_S3SBR_S3SBT(slot->startOffs); break;} + case 4u:{ base->CHANNEL[Psi5ChannelId].CH_S4SBR = PSI5_CH_S4SBR_S4SBT(slot->startOffs); break;} + case 5u:{ base->CHANNEL[Psi5ChannelId].CH_S5SBR = PSI5_CH_S5SBR_S5SBT(slot->startOffs); break;} + case 6u:{ base->CHANNEL[Psi5ChannelId].CH_S6SBR = PSI5_CH_S6SBR_S6SBT(slot->startOffs); break;} + default: /*error, not possible by configuration */ break; + } + + /* Configuration */ + base->CHANNEL[Psi5ChannelId].CH_SFCR[slot->slotId - 1U] = PSI5_CH_SFCR_SLOT_EN(1u) | PSI5_CH_SFCR_TS_CAPT(((slot->tsCapS0 == FALSE) ? 0u : 1u)) | + PSI5_CH_SFCR_SMCL(((slot->hasSMC == FALSE) ? 0u : 1u)) | PSI5_CH_SFCR_DRL(slot->dataSize) | + PSI5_CH_SFCR_CRCP(((slot->hasParity == FALSE) ? 0u : 1u)); +} + +/** + * + * Function Name : Psi5_Hw_EnterConfigMode + * Description : Puts the channel in configuration mode + * + */ +static void Psi5_Hw_EnterConfigMode(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + + /* Configure channel */ + base->CHANNEL[Psi5ChannelId].CH_PCCR |= (PSI5_CH_PCCR_PSI5_CH_EN_MASK | PSI5_CH_PCCR_PSI5_CH_CONFIG_MASK); +} + +/** + * + * Function Name : Psi5_Hw_EnterNormalMode + * Description : Puts the channel in normal mode + * + */ +static void Psi5_Hw_EnterNormalMode(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + /* Configure channel */ + base->CHANNEL[Psi5ChannelId].CH_PCCR &= ~PSI5_CH_PCCR_PSI5_CH_CONFIG_MASK; +} + +/** + * + * Function Name : Psi5_Hw_ConfigureTx + * Description : Configures transmission + * + */ +static void Psi5_Hw_ConfigureTx(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + uint16 defaultSync = 0u; + + /* Set mode to synchronous */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_MODE_MASK; + + if (chCfg->txConfig->txDefault1) + { + defaultSync = 1u; + } + + /* Tx mode, Data length, default bit values, auto transfer from DBR to DSR */ + base->CHANNEL[chCfg->channelId].CH_DOBCR |= (PSI5_CH_DOBCR_CMD_TYPE(chCfg->txConfig->txMode) | PSI5_CH_DOBCR_DATA_LENGTH(((uint16)chCfg->txConfig->txSize) - ((uint16)1u)) + | PSI5_CH_DOBCR_DEFAULT_SYNC(defaultSync) + | (((chCfg->txConfig->txMode) == PSI5_TX_MODE_7) ? PSI5_CH_DOBCR_DSR_RST_MASK : PSI5_CH_DOBCR_DBR_RST_MASK) + | PSI5_CH_DOBCR_SW_READY_MASK); +} + +/** + * + * Function Name : Psi5_Hw_ConfigureRx + * Description : Configures reception + * + */ +static void Psi5_Hw_ConfigureRx(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + /* Buffer size */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_MEM_DEPTH(((uint32)chCfg->rxConfig->rxBufSize) - ((uint32)1u)); + + /* bit rate */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_BIT_RATE(chCfg->rxConfig->bitRate); + + /* Fast clearing for both */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_FAST_CLR_PSI5_MASK | PSI5_CH_PCCR_FAST_CLR_SMC_MASK; +} + +/** + * + * Function Name : Psi5_Hw_ConfigurePulseGenerator + * Description : Configures pulse generation + * + */ +static void Psi5_Hw_ConfigurePulseGenerator(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + /* CTC control */ + if (chCfg->txConfig->syncGlobal) + { + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_CTC_GED_SEL_MASK; + } + + /* GTM reset */ + if (chCfg->txConfig->asyncReset) + { + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_GTM_RESET_ASYNC_EN_MASK; + } + + /* Decoder offset */ + base->CHANNEL[chCfg->channelId].CH_MDDIS_OFF = chCfg->txConfig->decoderOffset; + + /* Sync states */ + if (((uint8)(chCfg->txConfig->syncState) & 4u) != 0u) + { + base->CHANNEL[chCfg->channelId].CH_DOBCR |= PSI5_CH_DOBCR_GTM_TRIG_SEL_MASK; + } + + if (((uint8)(chCfg->txConfig->syncState) & 2u) != 0u) + { + base->CHANNEL[chCfg->channelId].CH_DOBCR |= PSI5_CH_DOBCR_SP_PULSE_SEL_MASK; + } + + if (((uint8)(chCfg->txConfig->syncState) & 1u) != 0u) + { + base->CHANNEL[chCfg->channelId].CH_DOBCR |= PSI5_CH_DOBCR_OP_SEL_MASK; + } + + /* Pulse forming*/ + base->CHANNEL[chCfg->channelId].CH_PW0D = chCfg->txConfig->pulse0Width; + base->CHANNEL[chCfg->channelId].CH_PW1D = chCfg->txConfig->pulse1Width; + base->CHANNEL[chCfg->channelId].CH_CIPR = chCfg->txConfig->initialPulse; + base->CHANNEL[chCfg->channelId].CH_CTPR = chCfg->txConfig->targetPulse; +} + +#if (STD_ON == PSI5_IP_DMA_IS_USED) +/** + * + * Function Name : Psi5_Hw_ConfigureDma + * Description : Configures DMA + * + */ +static void Psi5_Hw_ConfigureDma(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + uint32 DCRvalue = 0; + Mcl_DmaChannelTransferListType global_Mcl_DmaChannelTransferList[11U]; + + const Psi5_Ip_ChannelRxPsi5DmaConfigType *psi5DmaConfig = chCfg->rxConfig->psi5DmaConfig; /*!< DMA config for PSI5 messages */ + const Psi5_Ip_ChannelRxSmcDmaConfigType *smcDmaConfig = chCfg->rxConfig->smcDmaConfig; /*!< DMA config for SMC messages */ + /* Pre - computed */ + boolean psi5DmaOk = psi5DmaConfig != NULL_PTR ? TRUE : FALSE; + boolean smcDmaOk = smcDmaConfig != NULL_PTR ? TRUE : FALSE; + + if (psi5DmaOk || smcDmaOk) + { + /* Create the desired configuration list. */ + global_Mcl_DmaChannelTransferList[0U].Param = MCL_DMA_CH_SET_SOURCE_ADDRESS; + /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. + * The application should ensure that only addresses that fit in uint32 are used for configuring DMA. */ + global_Mcl_DmaChannelTransferList[1U].Param = MCL_DMA_CH_SET_DESTINATION_ADDRESS; + + global_Mcl_DmaChannelTransferList[2U].Param = MCL_DMA_CH_SET_DESTINATION_TRANSFER_SIZE; + global_Mcl_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; + global_Mcl_DmaChannelTransferList[3U].Param = MCL_DMA_CH_SET_SOURCE_TRANSFER_SIZE; + global_Mcl_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; + global_Mcl_DmaChannelTransferList[4U].Param = MCL_DMA_CH_SET_SOURCE_SIGNED_OFFSET; + global_Mcl_DmaChannelTransferList[4U].Value = (uint32)0U; + global_Mcl_DmaChannelTransferList[5U].Param = MCL_DMA_CH_SET_DESTINATION_SIGNED_OFFSET; + global_Mcl_DmaChannelTransferList[5U].Value = (uint32)4U; + global_Mcl_DmaChannelTransferList[6U].Param = MCL_DMA_CH_SET_SOURCE_MODULO; + global_Mcl_DmaChannelTransferList[6U].Value = (uint32)0U; + global_Mcl_DmaChannelTransferList[7U].Param = MCL_DMA_CH_SET_DESTINATION_MODULO; + global_Mcl_DmaChannelTransferList[7U].Value = (uint32)0U; + global_Mcl_DmaChannelTransferList[8U].Param = MCL_DMA_CH_SET_MINORLOOP_SIZE; + global_Mcl_DmaChannelTransferList[9U].Param = MCL_DMA_CH_SET_MAJORLOOP_COUNT; + global_Mcl_DmaChannelTransferList[9U].Value = (uint32)1U; + global_Mcl_DmaChannelTransferList[10U].Param = MCL_DMA_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ; + + /* Read DCR value */ + DCRvalue = base->CHANNEL[chCfg->channelId].CH_DCR; + /* Clear old value*/ + DCRvalue = DCRvalue & (~(PSI5_CH_DCR_DMA_PM_DS_WM_MASK | PSI5_CH_DCR_DMA_PM_DS_CONFIG_MASK | PSI5_CH_DCR_DMA_EN_SF_MASK)); + /* Set new value*/ + DCRvalue |= (psi5DmaOk ? (PSI5_CH_DCR_DMA_PM_DS_WM(psi5DmaConfig->psi5DmaWatermarkDmaTrigger - 1u)) : (uint32)0U); + DCRvalue |= (psi5DmaOk ? PSI5_CH_DCR_DMA_PM_DS_CONFIG(psi5DmaConfig->psi5DmaMode) : (uint32)0U); + DCRvalue |= (smcDmaOk ? (uint32)PSI5_CH_DCR_DMA_EN_SF_MASK : (uint32)0u); + /*Store value to register*/ + base->CHANNEL[chCfg->channelId].CH_DCR = DCRvalue; + + /* DMA transfer */ + if (smcDmaOk) + { + /*Source address: address of DSFR register */ + global_Mcl_DmaChannelTransferList[0U].Value = (uint32)(&base->CHANNEL[chCfg->channelId].CH_DSFR); + + /*Dest address: the address of internal buffer*/ + global_Mcl_DmaChannelTransferList[1U].Value = (uint32)(smcDmaConfig->smcDmaInternalBuffer); + + /*4 bytes transfer for each request*/ + global_Mcl_DmaChannelTransferList[8U].Value = (uint32)4U; + + /*Back to the start address of the buffer after finish transfer*/ + global_Mcl_DmaChannelTransferList[10U].Value = (uint32)(0xFFFFFFFF-sizeof(uint32)+1); + + /*Config and start DMA channel*/ + Mcl_SetDmaChannelTransferList(smcDmaConfig->smcDmaChannel, global_Mcl_DmaChannelTransferList, (uint32)11U); + Mcl_SetDmaChannelCommand(smcDmaConfig->smcDmaChannel, MCL_DMA_CH_START_REQUEST); + } + + if (psi5DmaOk) + { + if (PSI5_DMA_MODE_CONF4 == psi5DmaConfig->psi5DmaMode) + { + /* Mode CONF4: Only the diagnostic bits are transferred through the DDSR*/ + global_Mcl_DmaChannelTransferList[0U].Value = (uint32)(&base->CHANNEL[chCfg->channelId].CH_DDSR); + + /*Number of bytes for each request*/ + global_Mcl_DmaChannelTransferList[8U].Value = ((uint32)sizeof(Psi5_Ip_RawFrameType)); + + /*Back to the start address of the buffer after finish each transfer*/ + global_Mcl_DmaChannelTransferList[10U].Value = (uint32)(0xFFFFFFFF-sizeof(Psi5_Ip_RawFrameType)+1); + } + else if (PSI5_DMA_MODE_CONF3 == psi5DmaConfig->psi5DmaMode) + { + /* Mode CONF3: Data and diagnostic bits are transferred through the CH_DPMR*/ + global_Mcl_DmaChannelTransferList[0U].Value = (uint32)(&base->CHANNEL[chCfg->channelId].CH_DPMR); + + /*Number of bytes for each request*/ + global_Mcl_DmaChannelTransferList[8U].Value = ((uint32)sizeof(Psi5_Ip_RawFrameType)) * (psi5DmaConfig->psi5DmaWatermarkDmaTrigger); + + /*Back to the start address of the buffer after finish each transfer*/ + global_Mcl_DmaChannelTransferList[10U].Value = -(sint32)(sizeof(Psi5_Ip_RawFrameType) * (psi5DmaConfig->psi5DmaWatermarkDmaTrigger)); + } + else + { + /* Mode CONF2: Data and diagnostic bits are transferred through the CH_DPMR*/ + global_Mcl_DmaChannelTransferList[0U].Value = (uint32)(&base->CHANNEL[chCfg->channelId].CH_DPMR); + + /*Number of bytes for each request*/ + global_Mcl_DmaChannelTransferList[8U].Value = ((uint32)sizeof(Psi5_Ip_RawFrameType)) * (psi5DmaConfig->psi5DmaWatermarkDmaTrigger + 1U); + + /*Back to the start address of the buffer after finish each transfer*/ + global_Mcl_DmaChannelTransferList[10U].Value = -(sint32)(sizeof(Psi5_Ip_RawFrameType) * (psi5DmaConfig->psi5DmaWatermarkDmaTrigger + 1U)); + } + + /*Dest address the address of internal buffer*/ + global_Mcl_DmaChannelTransferList[1U].Value = (uint32)(psi5DmaConfig->psi5DmaInternalBuffer); + + /*Config and start DMA channel*/ + Mcl_SetDmaChannelTransferList(psi5DmaConfig->psi5DmaChannel, global_Mcl_DmaChannelTransferList, (uint32)11U); + Mcl_SetDmaChannelCommand(psi5DmaConfig->psi5DmaChannel, MCL_DMA_CH_START_REQUEST); + } + } +} +#endif + +/** + * + * Function Name : Psi5_Hw_InstanceDisable + * Description : Global channel disabler + * + */ +static void Psi5_Hw_InstanceDisable(const Psi5_Ip_InstanceIdType instanceId, + const boolean state + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + base->GCR = (uint16)(base->GCR & ~(uint16)PSI5_GCR_GLOBAL_DISABLE_REQ_MASK) | PSI5_GCR_GLOBAL_DISABLE_REQ(((FALSE == state) ? 0U : 1U)); +} + +/** + * + * Function Name : Psi5_Hw_StartGlobalCtc + * Description : Global CTC (timer) enabler. + * + */ +static Std_ReturnType Psi5_Hw_StartGlobalCtc(const Psi5_Ip_InstanceIdType instanceId, + const boolean state + ) +{ + Std_ReturnType ret = (Std_ReturnType)E_NOT_OK; + uint8 ChIndex; + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + for (ChIndex = 0u; ChIndex < PSI5_CHANNEL_COUNT; ChIndex++) + { + if ((base->CHANNEL[ChIndex].CH_PCCR & PSI5_CH_PCCR_CTC_GED_SEL_MASK) != 0U) + { + base->GCR = (uint16)(base->GCR & ~(uint16)PSI5_GCR_CTC_GED_MASK) | PSI5_GCR_CTC_GED(((FALSE == state) ? 0U : 1U)); + ret = (Std_ReturnType)E_OK; + } + } + + return ret; +} + +/** + * + * Function Name : Psi5_Hw_ResetRegisters + * Description : Resets registers + * + */ +static void Psi5_Hw_ResetRegisters(const Psi5_Ip_InstanceIdType instance) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + uint8 ChIndex; + + for (ChIndex = 0u; ChIndex < PSI5_CHANNEL_COUNT; ChIndex++) + { + /* Control registers */ + base->CHANNEL[ChIndex].CH_DCR = 0u; + base->CHANNEL[ChIndex].CH_GICR = 0u; + base->CHANNEL[ChIndex].CH_NDICR = 0u; + base->CHANNEL[ChIndex].CH_OWICR = 0u; + base->CHANNEL[ChIndex].CH_EICR = 0u; + + /* Reset Slot configuration */ + base->CHANNEL[ChIndex].CH_S1SBR = 0u; + base->CHANNEL[ChIndex].CH_S2SBR = 0u; + base->CHANNEL[ChIndex].CH_S3SBR = 0u; + base->CHANNEL[ChIndex].CH_S4SBR = 0u; + base->CHANNEL[ChIndex].CH_S5SBR = 0u; + base->CHANNEL[ChIndex].CH_S6SBR = 0u; + + for (uint8 slotIdx = 0u; slotIdx < PSI5_CHANNEL_CH_SFR_COUNT; slotIdx++) + { + base->CHANNEL[ChIndex].CH_SFCR[slotIdx] = PSI5_CH_SFCR_DRL(8u); + } + + /* Boundary end */ + base->CHANNEL[ChIndex].CH_SNEBR = 0u; + + /* Tx block */ + base->CHANNEL[ChIndex].CH_DOBCR = 0u; + base->CHANNEL[ChIndex].CH_MDDIS_OFF = 0u; + base->CHANNEL[ChIndex].CH_PW0D = 0u; + base->CHANNEL[ChIndex].CH_PW1D = 0u; + base->CHANNEL[ChIndex].CH_CTPR = 0u; + base->CHANNEL[ChIndex].CH_CIPR = 0u; + + /* Normal and disable */ + base->CHANNEL[ChIndex].CH_PCCR = (PSI5_CH_PCCR_ERROR_SELECT0_MASK | PSI5_CH_PCCR_ERROR_SELECT1_MASK | + PSI5_CH_PCCR_ERROR_SELECT2_MASK | PSI5_CH_PCCR_ERROR_SELECT3_MASK | + PSI5_CH_PCCR_ERROR_SELECT4_MASK); + } +} + +#if ((STD_ON == PSI5_IP_GET_TRANSMISSION_STATUS_API) || (STD_ON == PSI5_IP_TRANSMIT_API)) +/** + * + * Function Name : Psi5_Hw_IsDataRegisterReady + * Description : Returns Tx register status + * + */ +static boolean Psi5_Hw_IsDataRegisterReady(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); + + boolean ret = FALSE; + + /* Depending on Tx type */ + if (NULL_PTR != config->txConfig) + { + if (PSI5_TX_MODE_7 == config->txConfig->txMode) + { + ret = (Psi5_Ip_axBaseAddresses[instance]->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_DSR_RDY_MASK) != 0u; + } + else + { + ret = (Psi5_Ip_axBaseAddresses[instance]->CHANNEL[Psi5ChannelId].CH_GISR & PSI5_CH_GISR_DPR_RDY_MASK) != 0u; + } + } + + return ret; +} +#endif + +/** + * + * Function Name : Psi5_EnterConfigMode + * Description : Enter CONFIG mode. + * + */ +static void Psi5_EnterConfigMode(const Psi5_Ip_InstanceType *instance) +{ + /* Disable the instance */ + Psi5_Hw_InstanceDisable(instance->instanceId, TRUE); + + /* Put all channels in configuration mode */ + for (uint8 chIdx = 0u; chIdx < instance->numOfChannels; chIdx++) + { + const Psi5_Ip_ChannelConfigType *chCfg = &instance->channelConfig[chIdx]; + + /* Enter configuration mode */ + Psi5_Hw_EnterConfigMode(instance->instanceId, chCfg->channelId); + } + + /* Enable the instance */ + Psi5_Hw_InstanceDisable(instance->instanceId, FALSE); +} + +/** + * + * Function Name : Psi5_EnterNormalMode + * Description : Enter NORMAL mode. + * + */ +static void Psi5_EnterNormalMode(const Psi5_Ip_InstanceType *instance) +{ + /* Put all channels in normal mode */ + for (uint32 chIdx = 0u; chIdx < instance->numOfChannels; chIdx++) + { + const Psi5_Ip_ChannelConfigType *chCfg = &instance->channelConfig[chIdx]; + + /* Enter normal mode */ + Psi5_Hw_EnterNormalMode(instance->instanceId, chCfg->channelId); + } +} + +/** + * + * Function Name : Psi5_ConfigureSlots + * Description : Configures a single slot. + * + */ +static void Psi5_ConfigureSlots(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *channelConfig + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + const Psi5_Ip_SlotConfigType *lastSlotCfg = &(channelConfig->rxConfig->slotConfig[(channelConfig->rxConfig->numOfSlotConfigs - 1u)]); + uint16 SnEBT_Value = lastSlotCfg->startOffs + lastSlotCfg->slotLen; + uint8 LastSlotId = lastSlotCfg->slotId; + + /* For each slot configuration */ + for (uint32 slotIdx = 0u; slotIdx < channelConfig->rxConfig->numOfSlotConfigs; slotIdx++) + { + const Psi5_Ip_SlotConfigType *slotCfg = &(channelConfig->rxConfig->slotConfig[slotIdx]); + + /* Configure current slot */ + Psi5_Hw_ConfigureSlot(instanceId, channelConfig->channelId, slotCfg); + } + + /* New time frame */ + base->CHANNEL[channelConfig->channelId].CH_SNEBR = PSI5_CH_SNEBR_SnEBT(SnEBT_Value) | PSI5_CH_SNEBR_SLOT_NO(LastSlotId); +} + +/** + * + * Function Name : Psi5_ConfigureChannel + * Description : Configures a single channel. + * + */ +static void Psi5_ConfigureChannel(const Psi5_Ip_InstanceIdType instanceId, + const Psi5_Ip_ChannelConfigType *chCfg + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instanceId]; + + /* Set debug mode */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= PSI5_CH_PCCR_DEBUG_EN(((chCfg->debugEnable == TRUE) ? 1u : 0u)) | PSI5_CH_PCCR_DEBUG_FREEZE_CTRL(((chCfg->debugFreeze == TRUE) ? 1u : 0u)); + + /* Configure Rx parameters */ + Psi5_Hw_ConfigureRx(instanceId, chCfg); + +#if (STD_ON == PSI5_IP_DMA_IS_USED) + /* Configure DMA */ + Psi5_Hw_ConfigureDma(instanceId, chCfg); +#endif + + /* Configure the Tx side */ + if (PSI5_SYNCHRONOUS == chCfg->channelMode) + { + /* Configure Tx mode */ + Psi5_Hw_ConfigureTx(instanceId, chCfg); + + /* Configure the pulse generator */ + Psi5_Hw_ConfigurePulseGenerator(instanceId, chCfg); + } + + /* Configure interrupts */ + Psi5_Hw_EnableInterrupts(instanceId, chCfg, TRUE); +} + +/** + * + * Function Name : Psi5_ConfigureChannels + * Description : Configures all the channels. + * + */ +static void Psi5_ConfigureChannels(const Psi5_Ip_InstanceType *instance) +{ + /* For each channel configuration */ + for (uint32 chIdx = 0u; chIdx < instance->numOfChannels; chIdx++) + { + const Psi5_Ip_ChannelConfigType *chCfg = &(instance->channelConfig[chIdx]); + + /* Configure the pulse generator */ + Psi5_ConfigureChannel(instance->instanceId, chCfg); + + /* Configure the slots */ + Psi5_ConfigureSlots(instance->instanceId, chCfg); + } + + /* Global Sync start */ + (void)Psi5_Hw_StartGlobalCtc(instance->instanceId, instance->globalCtcEn); +} + +/** + * + * Function Name : Psi5_Hw_EnableInterrupts + * Description : Interrupt enabler + * + */ +static void Psi5_Hw_EnableInterrupts(const Psi5_Ip_InstanceIdType instance, + const Psi5_Ip_ChannelConfigType *chCfg, + const boolean Enable + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[instance]; + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[instance].chHwIdToIndexArrayConfig[chCfg->channelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[instance].channelConfig[arrayIndex]); + const Psi5_Ip_ErrorSelectConfigType *errorSelect = config->errorSelectConfig; + uint32 ErrorSelectBits; + + /* Clear interrupts flag */ + Psi5_Hw_ClearEvents(instance, chCfg->channelId); + /* We need to enable ALL interrupts */ + if (Enable != (boolean)FALSE) + { + ErrorSelectBits = (uint32)((((errorSelect->errorSelect0 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT0_SHIFT) | + (((errorSelect->errorSelect1 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT1_SHIFT) | + (((errorSelect->errorSelect2 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT2_SHIFT) | + (((errorSelect->errorSelect3 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT3_SHIFT) | + (((errorSelect->errorSelect4 == FALSE) ? (uint32)0u : (uint32)1u) << PSI5_CH_PCCR_ERROR_SELECT4_SHIFT)); + } + else + { + ErrorSelectBits = 0U; + } + + /* Error interrupts */ + base->CHANNEL[chCfg->channelId].CH_PCCR |= ErrorSelectBits; + +#if (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED) + /* DMA interrupts (Only if DMA enabled) */ + if (NULL_PTR != chCfg->rxConfig->psi5DmaConfig) + { + base->CHANNEL[chCfg->channelId].CH_DCR = Enable ? base->CHANNEL[chCfg->channelId].CH_DCR | (PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK | PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_MASK | PSI5_CH_DCR_IE_DMA_PM_DS_UF_MASK) : base->CHANNEL[chCfg->channelId].CH_DCR & ~(PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK | PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_MASK | PSI5_CH_DCR_IE_DMA_PM_DS_UF_MASK); + + /*Disable all RX interrupts*/ + base->CHANNEL[chCfg->channelId].CH_NDICR = 0U; + base->CHANNEL[chCfg->channelId].CH_OWICR = 0U; + base->CHANNEL[chCfg->channelId].CH_EICR = 0U; + + } + else +#endif + { + /*Enable PSI5 Rx interrupts */ + base->CHANNEL[chCfg->channelId].CH_NDICR = Enable ? PSI5_CH_NDICR_IE_ND(chCfg->rxConfig->watermarkInterruptLevel) : 0U; + base->CHANNEL[chCfg->channelId].CH_OWICR = Enable ? PSI5_CH_OWICR_IE_OW(chCfg->rxConfig->watermarkInterruptLevel) : 0U; + base->CHANNEL[chCfg->channelId].CH_EICR = Enable ? PSI5_CH_EICR_IE_ERROR(chCfg->rxConfig->watermarkInterruptLevel) : 0U; + } + +#if (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED) + if (NULL_PTR != chCfg->rxConfig->smcDmaConfig) + { + base->CHANNEL[chCfg->channelId].CH_DCR = Enable ? base->CHANNEL[chCfg->channelId].CH_DCR | (PSI5_CH_DCR_IE_DMA_TF_SF_MASK | PSI5_CH_DCR_IE_DMA_SFUF_MASK) : base->CHANNEL[chCfg->channelId].CH_DCR & ~(PSI5_CH_DCR_IE_DMA_TF_SF_MASK | PSI5_CH_DCR_IE_DMA_SFUF_MASK); + } +#endif + +} + +/** + * + * Function Name : Psi5_Hw_ClearEvents + * Description : Clears all active events + * + */ +static void Psi5_Hw_ClearEvents(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[Psi5InstanceId]; + +#if (STD_ON == PSI5_IP_DMA_IS_USED) + uint32 Ch_Dsr_Value = 0; + +#if (STD_ON == PSI5_IP_DMA_PSI5_FRAME_IS_USED) + Ch_Dsr_Value = PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_MASK | PSI5_CH_DSR_IS_DMA_TF_PM_DS_MASK | PSI5_CH_DSR_IS_DMA_PM_DS_UF_MASK; +#endif + +#if (STD_ON == PSI5_IP_DMA_SMC_FRAME_IS_USED) + Ch_Dsr_Value |= PSI5_CH_DSR_IS_DMA_TF_SF_MASK | PSI5_CH_DSR_IS_DMA_SFUF_MASK; +#endif + + /* DMA flags */ + base->CHANNEL[Psi5ChannelId].CH_DSR = Ch_Dsr_Value; +#endif + + /* General flags */ + base->CHANNEL[Psi5ChannelId].CH_GISR = PSI5_CH_GISR_IS_CESM_MASK | PSI5_CH_GISR_IS_STS_MASK + | PSI5_CH_GISR_IS_DTS_MASK | PSI5_CH_GISR_IS_DSROW_MASK + | PSI5_CH_GISR_IS_BROW_MASK | PSI5_CH_GISR_IS_PROW_MASK + | PSI5_CH_GISR_IS_OWSM_MASK | PSI5_CH_GISR_IS_NVSM_MASK; + + /* PSI5 status */ + base->CHANNEL[Psi5ChannelId].CH_NDSR = PSI5_CH_NDSR_NDS_MASK; + base->CHANNEL[Psi5ChannelId].CH_OWSR = PSI5_CH_OWSR_OWS_MASK; + base->CHANNEL[Psi5ChannelId].CH_EISR = PSI5_CH_EISR_ERROR_MASK; +} + +/** + * + * Function Name : Psi5_Ip_IRQ_Handler + * Description : Gets called from the low level handler with instance and channel as parameter. + * + */ +void Psi5_Ip_IRQ_Handler(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + Psi5_Ip_EventType Events; + + /*Clear all values*/ + Events.Psi5_Psi5MessageReceived = FALSE; + Events.Psi5_Psi5MessageOverwrite = FALSE; + Events.Psi5_Psi5MessageErrorsPresent = FALSE; + Events.Psi5_SmcMessageReceived = FALSE; + Events.Psi5_SmcMessageOverwrite = FALSE; + Events.Psi5_SmcMessageCRCError = FALSE; + Events.Psi5_TxDataOverwrite = FALSE; + Events.Psi5_DriverReadyToTransmit = FALSE; + Events.Psi5_Psi5DmaOverflow = FALSE; + Events.Psi5_Psi5DmaUnderflow = FALSE; + Events.Psi5_Psi5DmaTransferComplete = FALSE; + Events.Psi5_SmcDmaUnderflow = FALSE; + Events.Psi5_SmcDmaTransferComplete = FALSE; + + Psi5_Hw_GetEvents(Psi5InstanceId, Psi5ChannelId, &Events); + + if(TRUE == Psi5_Ip_bDriverInitialized) + { + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType * chCfg = &(Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].channelConfig[arrayIndex]); + + if(NULL_PTR != chCfg->callback) + { + chCfg->callback(Events); + } + } +} + +/** + * + * Function Name : Psi5_Ip_Init + * Description : Initializes the driver for a given peripheral + * according to the given configuration structure. + * + * Implements : Psi5_Ip_Init_Activity + */ +void Psi5_Ip_Init(const Psi5_Ip_ConfigType *configPtr) +{ + uint8 instanceCnt = 0u; + uint8 channelCnt = 0u; + Psi5_Ip_pUsedConfig = configPtr; + Psi5_Ip_bDriverInitialized = TRUE; + + for (instanceCnt = 0u; instanceCnt < PSI5_INSTANCE_COUNT; instanceCnt++) + { + for (channelCnt = 0u; channelCnt < PSI5_CHANNEL_COUNT; channelCnt++) + { + Psi5_Ip_axMessages[instanceCnt][channelCnt].psi5CurrentIndex = 0xFFu; + Psi5_Ip_axMessages[instanceCnt][channelCnt].smcCurrentIndex = 0xFFu; + } + } + + for (instanceCnt = 0u; instanceCnt < Psi5_Ip_pUsedConfig->numOfInstances; instanceCnt++) + { + const Psi5_Ip_InstanceType *cfgInstance = &(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt]); + /* Enter configuration mode */ + Psi5_EnterConfigMode(cfgInstance); + + /* Configure channels */ + Psi5_ConfigureChannels(cfgInstance); + + /* Enter normal mode */ + Psi5_EnterNormalMode(cfgInstance); + } +} + +#if (STD_ON == PSI5_IP_GET_PSI5_FRAME_API) +/** + * + * Function Name : Psi5_Ip_GetPsi5Frame + * Description : Returns the last received PSI5 frame. + * + * Implements : Psi5_Ip_GetPsi5Frame_Activity + */ +Std_ReturnType Psi5_Ip_GetPsi5Frame(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_Psi5FrameType *PsiFramePtr + ) +{ + Std_ReturnType ret; + Psi5_Ip_RawFrameType Psi5_RawFrame; + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].channelConfig[arrayIndex]); + + ret = Psi5_Hw_GetRawPsi5Frame(Psi5InstanceId, Psi5ChannelId, &Psi5_RawFrame); + + if ((Std_ReturnType)E_OK == ret) + { + const Psi5_Ip_SlotConfigType *slotStates = config->rxConfig->slotConfig; + + Psi5_Hw_ConvertRawPsi5Frame(PsiFramePtr, &Psi5_RawFrame, slotStates); + } + + return ret; +} +#endif + +#if (STD_ON == PSI5_IP_GET_SMC_FRAME_API) +/** + * + * Function Name : Psi5_Ip_GetSmcFrame + * Description : Returns the last received SMC frame. + * + * Implements : Psi5_Ip_GetSmcFrame_Activity + */ +Std_ReturnType Psi5_Ip_GetSmcFrame(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + Psi5_Ip_SmcFrameType *Psi5SmcFramePtr + ) +{ + Std_ReturnType ret; + Psi5_Ip_RawFrameType Psi5_RawFrame; + + ret = Psi5_Hw_GetRawSmcFrame(Psi5InstanceId, Psi5ChannelId, &Psi5_RawFrame); + + if (ret == (Std_ReturnType)E_OK) + { + Psi5_Hw_ConvertRawSmcFrame(Psi5SmcFramePtr, &Psi5_RawFrame); + } + + return ret; +} +#endif + +/** + * + * Function Name : Psi5_Ip_DeInit + * Description : Stops the driver and resets the internal states. + * + * Implements : Psi5_Ip_DeInit_Activity + */ +void Psi5_Ip_DeInit(void) +{ + uint8 instanceCnt; + + Psi5_Ip_bDriverInitialized = FALSE; + + for (instanceCnt = 0u; instanceCnt < Psi5_Ip_pUsedConfig->numOfInstances; instanceCnt++) + { + /* Put all channels in configuration mode */ + for (uint8 chIdx = 0u; chIdx < Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].numOfChannels; chIdx++) + { + const Psi5_Ip_ChannelConfigType *chCfg = &(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].channelConfig[chIdx]); + + /* Disable the instance */ + Psi5_Hw_InstanceDisable(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, TRUE); + + /* Enter configuration mode */ + Psi5_Hw_EnterConfigMode(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, chCfg->channelId); + + /* Enable the instance */ + Psi5_Hw_InstanceDisable(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, FALSE); + + /* Disable interrupts */ + Psi5_Hw_EnableInterrupts(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, chCfg, FALSE); + + Psi5_Hw_ClearEvents(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, chIdx); + } + + (void)Psi5_Hw_StartGlobalCtc(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, FALSE); + + /* Clear all registers */ + Psi5_Hw_ResetRegisters(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId); + + /* Disable the instance */ + Psi5_Hw_InstanceDisable(Psi5_Ip_pUsedConfig->instancesConfig[instanceCnt].instanceId, TRUE); + } + + Psi5_Ip_pUsedConfig = NULL_PTR; +} + +#if (STD_ON == PSI5_IP_TRANSMIT_API) +/** + * + * Function Name : Psi5_Ip_Transmit + * Description : Transmits a frame (standard or custom). + * + * Implements : Psi5_Ip_Transmit_Activity + */ +Std_ReturnType Psi5_Ip_Transmit(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const uint64 Psi5Data + ) +{ + Std_ReturnType ret; + + const uint8 arrayIndex = Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].chHwIdToIndexArrayConfig[Psi5ChannelId]; + const Psi5_Ip_ChannelConfigType *config = &(Psi5_Ip_pUsedConfig->instancesConfig[Psi5InstanceId].channelConfig[arrayIndex]); + + /* Only if enabled */ + if (NULL_PTR != config->txConfig) + { + /* Check if ready for Tx */ + if (!Psi5_Hw_IsDataRegisterReady(Psi5InstanceId, Psi5ChannelId)) + { + ret = (Std_ReturnType)E_NOT_OK; + } + else + { + /* Write and trigger */ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[Psi5InstanceId]; + + /* Enter critical region*/ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_00(); + + if (PSI5_TX_MODE_7 == config->txConfig->txMode) + { + base->CHANNEL[Psi5ChannelId].CH_DSRH = (uint32)((Psi5Data >> 32u) & PSI5_CH_DSRH_DSR_MASK); + base->CHANNEL[Psi5ChannelId].CH_DSRL = (uint32)(Psi5Data & PSI5_CH_DSRL_DSR_MASK); + base->CHANNEL[Psi5ChannelId].CH_GISR |= PSI5_CH_GISR_DSR_RDY_MASK; + /* Tx interrupts */ + if ((NULL_PTR != config->callback) && ((PSI5_SYNC_STATE_2 == config->txConfig->syncState) || (PSI5_SYNC_STATE_4 == config->txConfig->syncState))) + { + base->CHANNEL[Psi5ChannelId].CH_GICR |= (PSI5_CH_GICR_IE_DSROW_MASK | PSI5_CH_GICR_IE_DSRR_MASK); + } + } + else + { + base->CHANNEL[Psi5ChannelId].CH_DPRL = (uint32)(Psi5Data & PSI5_CH_DPRL_DPR_MASK); + base->CHANNEL[Psi5ChannelId].CH_GISR |= PSI5_CH_GISR_DPR_RDY_MASK; + /* Tx interrupts */ + if ((NULL_PTR != config->callback) && ((PSI5_SYNC_STATE_2 == config->txConfig->syncState) || (PSI5_SYNC_STATE_4 == config->txConfig->syncState))) + { + base->CHANNEL[Psi5ChannelId].CH_GICR |= (PSI5_CH_GICR_IE_PROW_MASK | PSI5_CH_GICR_IE_PRR_MASK); + } + } + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_00(); + ret = (Std_ReturnType)E_OK; + } + } + else + { + ret = (Std_ReturnType)E_NOT_OK; + } + + return ret; +} +#endif + +#if (STD_ON == PSI5_IP_GET_TRANSMISSION_STATUS_API) +/** + * + * Function Name : Psi5_Ip_GetTransmissionStatus + * Description : Returns the status of the transmission part of the driver. + * + * Implements : Psi5_Ip_GetTransmissionStatus_Activity + */ +boolean Psi5_Ip_GetTransmissionStatus(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId + ) +{ + /* Status */ + return Psi5_Hw_IsDataRegisterReady(Psi5InstanceId, Psi5ChannelId); +} +#endif + +#if (STD_ON == PSI5_IP_SET_GLOBAL_SYNC_API) +/** + * + * Function Name : Psi5_Ip_SetGlobalSync + * Description : Sets the global Pulse Generator state. + * + * Implements : Psi5_Ip_SetGlobalSync_Activity + */ +Std_ReturnType Psi5_Ip_SetGlobalSync(const uint8 Psi5InstanceId, + const boolean PsiState + ) +{ + Std_ReturnType retVal; + /* Enter critical region */ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_03(); + + retVal = Psi5_Hw_StartGlobalCtc((Psi5InstanceId == 0U) ? PSI5_INSTANCE0 : PSI5_INSTANCE1, PsiState); + + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_03(); + + return retVal; +} +#endif + +#if (STD_ON == PSI5_IP_SET_CHANNEL_SYNC_API) +/** + * + * Function Name : Psi5_Ip_SetChannelSync + * Description : Sets the local (Psi5ChannelId) Pulse Generator state. + * + * Implements : Psi5_Ip_SetChannelSync_Activity + */ +Std_ReturnType Psi5_Ip_SetChannelSync(const Psi5_Ip_InstanceIdType Psi5InstanceId, + const Psi5_Ip_HwChannelIdType Psi5ChannelId, + const boolean PsiState + ) +{ + Std_ReturnType ret = (Std_ReturnType)E_NOT_OK; + /* Enable the local CTC */ + PSI5_MemMapPtr base = Psi5_Ip_axBaseAddresses[Psi5InstanceId]; + + /* Enter critical region */ + SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_04(); + + if (0u == (base->CHANNEL[Psi5ChannelId].CH_PCCR & PSI5_CH_PCCR_CTC_GED_SEL_MASK)) + { + base->CHANNEL[Psi5ChannelId].CH_PCCR = PsiState ? (base->CHANNEL[Psi5ChannelId].CH_PCCR | PSI5_CH_PCCR_CTC_ED_MASK) : (base->CHANNEL[Psi5ChannelId].CH_PCCR & ~PSI5_CH_PCCR_CTC_ED_MASK); + + ret = (Std_ReturnType)E_OK; + } + + /* Exit critical region*/ + SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_04(); + + return ret; +} +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/s32/drivers/s32ze/Psi5/src/Psi5_Ip_Irq.c b/s32/drivers/s32ze/Psi5/src/Psi5_Ip_Irq.c new file mode 100644 index 000000000..c23d063e2 --- /dev/null +++ b/s32/drivers/s32ze/Psi5/src/Psi5_Ip_Irq.c @@ -0,0 +1,204 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file Psi5_Ip_Irq.c +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ + +#include "Psi5_Ip.h" +#include "Psi5_Ip_Irq.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_IRQ_VENDOR_ID_C 43 +#define PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C 4 +#define PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION_C 7 +#define PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION_C 0 +#define PSI5_IP_IRQ_SW_MAJOR_VERSION_C 2 +#define PSI5_IP_IRQ_SW_MINOR_VERSION_C 0 +#define PSI5_IP_IRQ_SW_PATCH_VERSION_C 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + +/* Checks against Psi5_Ip.h */ +#if (PSI5_IP_IRQ_VENDOR_ID_C != PSI5_IP_VENDOR_ID) + #error "Psi5_Ip_Irq.c and Psi5_Ip.h have different vendor ids" +#endif +#if ((PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != PSI5_IP_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != PSI5_IP_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != PSI5_IP_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip_Irq.c and Psi5_Ip.h are different" +#endif +#if ((PSI5_IP_IRQ_SW_MAJOR_VERSION_C != PSI5_IP_SW_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_SW_MINOR_VERSION_C != PSI5_IP_SW_MINOR_VERSION) || \ + (PSI5_IP_IRQ_SW_PATCH_VERSION_C != PSI5_IP_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip_Irq.c and Psi5_Ip.h are different" +#endif + +/* Checks against Psi5_Ip_Irq.h */ +#if (PSI5_IP_IRQ_VENDOR_ID_C != PSI5_IP_IRQ_VENDOR_ID) + #error "Psi5_Ip_Irq.c and Psi5_Ip_Irq.h have different vendor ids" +#endif +#if ((PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != PSI5_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != PSI5_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != PSI5_IP_IRQ_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_Ip_Irq.c and Psi5_Ip_Irq.h are different" +#endif +#if ((PSI5_IP_IRQ_SW_MAJOR_VERSION_C != PSI5_IP_IRQ_SW_MAJOR_VERSION) || \ + (PSI5_IP_IRQ_SW_MINOR_VERSION_C != PSI5_IP_IRQ_SW_MINOR_VERSION) || \ + (PSI5_IP_IRQ_SW_PATCH_VERSION_C != PSI5_IP_IRQ_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip_Irq.c and Psi5_Ip_Irq.h are different" +#endif + +/*================================================================================================== +* LOCAL MACROS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) +==================================================================================================*/ + +/*================================================================================================== +* LOCAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL VARIABLES +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH0 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 0. + */ +ISR(Psi5_IRQ_Handle_PSI5_0_CH0) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE0, PSI5_0_CH0); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH1 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 1. + */ +ISR(Psi5_IRQ_Handle_PSI5_0_CH1) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE0, PSI5_0_CH1); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH2 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 2. + */ +ISR(Psi5_IRQ_Handle_PSI5_0_CH2) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE0, PSI5_0_CH2); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH3 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 0 channel 3. + */ +ISR(Psi5_IRQ_Handle_PSI5_0_CH3) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE0, PSI5_0_CH3); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH0 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 0. + */ +ISR(Psi5_IRQ_Handle_PSI5_1_CH0) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE1, PSI5_1_CH0); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH1 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 1. + */ +ISR(Psi5_IRQ_Handle_PSI5_1_CH1) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE1, PSI5_1_CH1); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH2 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_1_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 2. + */ +ISR(Psi5_IRQ_Handle_PSI5_1_CH2) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE1, PSI5_1_CH2); +} +#endif + +#ifdef PSI5_IP_ENABLE_INTERRUPTS_PSI5_1_CH3 +/** + * + * Function Name : Psi5_IRQ_Handle_PSI5_0_CH0 + * Description : Must be mapped to the generic interrupt of instace 1 channel 3. + */ +ISR(Psi5_IRQ_Handle_PSI5_1_CH3) +{ + Psi5_Ip_IRQ_Handler(PSI5_INSTANCE1, PSI5_1_CH3); +} +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/s32/drivers/s32ze/Psi5_S/CMakeLists.txt b/s32/drivers/s32ze/Psi5_S/CMakeLists.txt new file mode 100644 index 000000000..c48a6ac29 --- /dev/null +++ b/s32/drivers/s32ze/Psi5_S/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: BSD-3-Clause + +zephyr_include_directories(include) +zephyr_library_sources(src/Psi5_S_Ip.c) +zephyr_library_sources(src/Psi5_S_Ip_Irq.c) diff --git a/s32/drivers/s32ze/Psi5_S/include/Psi5_S_Ip.h b/s32/drivers/s32ze/Psi5_S/include/Psi5_S_Ip.h new file mode 100644 index 000000000..9099ed05e --- /dev/null +++ b/s32/drivers/s32ze/Psi5_S/include/Psi5_S_Ip.h @@ -0,0 +1,272 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_S_IP_H +#define PSI5_S_IP_H + +#if defined(__cplusplus) +extern "C" { +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "OsIf.h" +#include "Psi5_S_Ip_Types.h" +#include "Psi5_S_Ip_Cfg.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFOPSI5ATION +==================================================================================================*/ +#define PSI5_S_IP_VENDOR_ID 43 +#define PSI5_S_IP_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_S_IP_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_S_IP_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_S_IP_SW_MAJOR_VERSION 2 +#define PSI5_S_IP_SW_MINOR_VERSION 0 +#define PSI5_S_IP_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Checks against Psi5_S_Ip_Types.h */ +#if (PSI5_S_IP_VENDOR_ID != PSI5_S_IP_TYPES_VENDOR_ID) + #error "Psi5_S_Ip.h and Psi5_S_Ip_Types.h have different vendor ids" +#endif +#if ((PSI5_S_IP_AR_RELEASE_MAJOR_VERSION != PSI5_S_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_MINOR_VERSION != PSI5_S_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_REVISION_VERSION != PSI5_S_IP_TYPES_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip.h and Psi5_S_Ip_Types.h are different" +#endif +#if ((PSI5_S_IP_SW_MAJOR_VERSION != PSI5_S_IP_TYPES_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_SW_MINOR_VERSION != PSI5_S_IP_TYPES_SW_MINOR_VERSION) || \ + (PSI5_S_IP_SW_PATCH_VERSION != PSI5_S_IP_TYPES_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_S_Ip.h and Psi5_S_Ip_Types.h are different" +#endif + +/* Checks against Psi5_S_Ip_Cfg.h */ +#if (PSI5_S_IP_VENDOR_ID != PSI5_S_IP_CFG_VENDOR_ID) + #error "Psi5_S_Ip.h and Psi5_S_Ip_Cfg.h have different vendor ids" +#endif +#if ((PSI5_S_IP_AR_RELEASE_MAJOR_VERSION != PSI5_S_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_MINOR_VERSION != PSI5_S_IP_CFG_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_REVISION_VERSION != PSI5_S_IP_CFG_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip.h and Psi5_S_Ip_Cfg.h are different" +#endif +#if ((PSI5_S_IP_SW_MAJOR_VERSION != PSI5_S_IP_CFG_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_SW_MINOR_VERSION != PSI5_S_IP_CFG_SW_MINOR_VERSION) || \ + (PSI5_S_IP_SW_PATCH_VERSION != PSI5_S_IP_CFG_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_S_Ip.h and Psi5_S_Ip_Cfg.h are different" +#endif + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#define PSI5_START_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" +/** +* @brief Export PSI5 configurations. +*/ +PSI5_S_IP_CONFIG_EXT + +#define PSI5_STOP_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +/*! + * @brief Main initializer for the driver + * + * Initializes the driver for a given peripheral + * according to the given configuration structure. + * + * @param[in] configPtr Pointer to the configuration structure + */ +void Psi5_S_Ip_Init(const Psi5_S_Ip_ConfigType * configPtr); + +/*! + * @brief Reset the peripheral. + * + * De-Initializes the peripheral and brings it's registers into a reset state. + * + */ +void Psi5_S_Ip_DeInit(void); + +/*! + * @brief Transmit a data frame + * + * Transmits a data frame according to configuration. + * + * @param[in] Psi5SInstanceId Instance number + * @param[in] Psi5SChannelId Channel number + * @param[in] Psi5SData Data to send + * @return E_OK If transmit succeeded + * @return E_NOT_OK If not configured or not enabled or not ready + */ +Std_ReturnType Psi5_S_Ip_Transmit(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, const uint64 Psi5SData); + +/*! + * @brief Transmission status + * + * Returns the status of the transmission. + * + * @param[in] Psi5SInstanceId Instance number + * @param[in] Psi5SChannelId Channel number + * @return true If transmission ready + * @return false If transmission pending + */ +boolean Psi5_S_Ip_GetTransmissionStatus(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, const Psi5_S_Ip_HwChannelIdType Psi5SChannelId); + +/*! + * @brief Send direct command a data frame + * + * Send direct command a data frame according to configuration. + * + * @param[in] Psi5SInstanceId Instance number + * @param[in] Psi5SDirCmd Direct command to send + * @param[in] Psi5SDirCmdLen Direct command lenght to send + * @return E_OK If transmit succeeded + * @return E_NOT_OK If not configured or not enabled or not ready + */ +Std_ReturnType Psi5_S_Ip_SendDirectCommand(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, const uint32 Psi5SDirCmd, const uint8 Psi5SDirCmdLen); + +/*! + * @brief Gets a PSI5 frame + * + * Returns the last received PSI5 frame. + * + * @param[in] Psi5SInstanceId Instance number + * @param[in] Psi5SChannelId Channel number + * @param[out] Psi5SFramePtr Target variable + * @return E_OK If channel is active + * @return E_NOT_OK If channel is not active + */ +Std_ReturnType Psi5_S_Ip_GetPsi5SFrame(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr); + +/*! + * @brief Global sync all the DDSR's + * + * Changes the global sync all the DDSR's + * + * @param[in] Psi5SInstanceId Instance number + * @param[in] Psi5SState Sellect state + * @return E_OK If config succeeded + * @return E_NOT_OK If Channel Target Counter is controlled by Channel Target Counter Enable/Disable. + */ +Std_ReturnType Psi5_S_Ip_SetGlobalSync(const uint8 Psi5SInstanceId, const boolean Psi5SState); + +/*! + * @brief Channel sync the DDSR's + * + * Changes the channel sync the DDSR's + * + * @param[in] Psi5SInstanceId Instance number + * @param[in] Psi5SChannelId Instance channel number + * @param[in] Psi5SState Sellect state + * @return E_OK If config succeeded + * @return E_NOT_OK If Channel Target Counter is controlled by Channel Target Counter Enable/Disable. + */ +Std_ReturnType Psi5_S_Ip_SetChannelSync(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, const boolean Psi5SState); + +/** +* @brief Interrupt handler signature for Rx +* +* @param[in] Psi5SInstanceId Instance number +* @param[in] Psi5SChannelId Instance channel number +* @return void +* +*/ +void Psi5_S_Ip_IRQ_Handler_Rx(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, const Psi5_S_Ip_HwChannelIdType Psi5SChannelId); + +/** +* @brief Interrupt handler signature for Tx +* +* @param[in] Psi5SInstanceId Instance number +* @param[in] Psi5SChannelId Instance channel number +* @return void +* +*/ +void Psi5_S_Ip_IRQ_Handler_Tx(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, const Psi5_S_Ip_HwChannelIdType Psi5SChannelId); + +/** +* @brief Interrupt global handler signature +* +* @param[in] Psi5SInstanceId Instance number +* @return void +* +*/ +void Psi5_S_Ip_IRQ_Global_Handler(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId); + +/** + * @brief : Prepare for timeout checking + * @internal + * @return : None + */ +static inline void Psi5_S_Ip_StartTimeout(uint32 *StartTimeOut, uint32 *TimeoutTicksOut, uint32 TimeoutUs, OsIf_CounterType OsifCounter) +{ + *StartTimeOut = OsIf_GetCounter(OsifCounter); + *TimeoutTicksOut = OsIf_MicrosToTicks(TimeoutUs, OsifCounter); +} + +/** + * @brief : Checks for timeout condition + * @internal + * @return TRUE Timeout occurs + * FALSE Timeout does not occur + */ +static inline boolean Psi5_S_Ip_CheckTimeout(uint32 * StartTime, uint32 * ElapsedTicks, uint32 TimeoutTicks, OsIf_CounterType OsifCounter) +{ + boolean RetVal = FALSE; + uint32 CurrentElapsedTicks = OsIf_GetElapsed(StartTime, OsifCounter); + + *ElapsedTicks += CurrentElapsedTicks; + if (*ElapsedTicks >= TimeoutTicks) + { + RetVal = TRUE; + } + + return RetVal; +} + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ /* End of addtogroup psi5s */ + +#endif /* PSI5_S_IP_H */ diff --git a/s32/drivers/s32ze/Psi5_S/include/Psi5_S_Ip_Irq.h b/s32/drivers/s32ze/Psi5_S/include/Psi5_S_Ip_Irq.h new file mode 100644 index 000000000..70cb4bc7f --- /dev/null +++ b/s32/drivers/s32ze/Psi5_S/include/Psi5_S_Ip_Irq.h @@ -0,0 +1,358 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_S_IP_IRQ_H +#define PSI5_S_IP_IRQ_H + +#if defined(__cplusplus) +extern "C" { +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Psi5_S_Ip_Cfg_Defines.h" +#include "Mcal.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFOPSI5ATION +==================================================================================================*/ +#define PSI5_S_IP_IRQ_VENDOR_ID 43 +#define PSI5_S_IP_IRQ_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_S_IP_IRQ_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_S_IP_IRQ_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_S_IP_IRQ_SW_MAJOR_VERSION 2 +#define PSI5_S_IP_IRQ_SW_MINOR_VERSION 0 +#define PSI5_S_IP_IRQ_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + /* Checks against Mcal.h */ + #if ((PSI5_S_IP_IRQ_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_IRQ_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_S_Ip_Irq.h and Mcal.h are different" + #endif +#endif + +/* Checks against Psi5_S_Ip_Cfg_Defines.h */ +#if (PSI5_S_IP_IRQ_VENDOR_ID != PSI5_S_IP_CFG_DEFINES_VENDOR_ID) + #error "Psi5_S_Ip_Irq.h and Psi5_S_Ip_Cfg_Defines.h have different vendor ids" +#endif +#if ((PSI5_S_IP_IRQ_AR_RELEASE_MAJOR_VERSION != PSI5_S_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_IRQ_AR_RELEASE_MINOR_VERSION != PSI5_S_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_IRQ_AR_RELEASE_REVISION_VERSION != PSI5_S_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip_Irq.h and Psi5_S_Ip_Cfg_Defines.h are different" +#endif +#if ((PSI5_S_IP_IRQ_SW_MAJOR_VERSION != PSI5_S_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_IRQ_SW_MINOR_VERSION != PSI5_S_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ + (PSI5_S_IP_IRQ_SW_PATCH_VERSION != PSI5_S_IP_CFG_DEFINES_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_S_Ip_Irq.h and Psi5_S_Ip_Cfg_Defines.h are different" +#endif + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef PSI5_S_IP_ENABLE_GLOBAL_INTERRUPTS_PSI5_S_INSTANCE0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_IRQ_Global_Handle_0 + * Description : Must be mapped to the generic interrupt of global. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Global_Handle_PSI5S_0); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH0 + * Description : Must be mapped to the generic interrupt of instance 0 channel 0. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH0); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH1 + * Description : Must be mapped to the generic interrupt of instance 0 channel 1. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH1); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH1 + * Description : Must be mapped to the generic interrupt of instance 0 channel 1. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH1); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH2 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH2 + * Description : Must be mapped to the generic interrupt of instance 0 channel 2. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH2); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH2 + * Description : Must be mapped to the generic interrupt of instance 0 channel 2. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH2); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH3 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH3 + * Description : Must be mapped to the generic interrupt of instance 0 channel3. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH3); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH3 + * Description : Must be mapped to the generic interrupt of instance 0 channel 3. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH3); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH4 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH4 + * Description : Must be mapped to the generic interrupt of instance 0 channel 4. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH4); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH4 + * Description : Must be mapped to the generic interrupt of instance 0 channel 4. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH4); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH5 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH5 + * Description : Must be mapped to the generic interrupt of instance 0 channel 5. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH5); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH5 + * Description : Must be mapped to the generic interrupt of instance 0 channel 5. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH5); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH6 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH6 + * Description : Must be mapped to the generic interrupt of instance 0 channel 6. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH6); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH6 + * Description : Must be mapped to the generic interrupt of instance 0 channel 6. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH6); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH7 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH7 + * Description : Must be mapped to the generic interrupt of instance 0 channel 7. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH7); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH7 + * Description : Must be mapped to the generic interrupt of instance 0 channel 7. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH7); +#endif + +#ifdef PSI5_S_IP_ENABLE_GLOBAL_INTERRUPTS_PSI5_S_INSTANCE1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_IRQ_Global_Handle_1 + * Description : Must be mapped to the generic interrupt of global. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Global_Handle_PSI5S_1); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH0 + * Description : Must be mapped to the generic interrupt of instance 1 channel 0. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH0); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH1 + * Description : Must be mapped to the generic interrupt of instance 1 channel 1. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH1); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH1 + * Description : Must be mapped to the generic interrupt of instance 1 channel 1. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH1); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH2 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH2 + * Description : Must be mapped to the generic interrupt of instance 1 channel 2. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH2); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH2 + * Description : Must be mapped to the generic interrupt of instance 1 channel 2. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH2); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH3 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH3 + * Description : Must be mapped to the generic interrupt of instance 1 channel 3. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH3); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH3 + * Description : Must be mapped to the generic interrupt of instance 1 channel 3. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH3); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH4 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH4 + * Description : Must be mapped to the generic interrupt of instance 1 channel 4. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH4); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH4 + * Description : Must be mapped to the generic interrupt of instance 1 channel 4. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH4); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH5 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH5 + * Description : Must be mapped to the generic interrupt of instance 1 channel 5. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH5); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH5 + * Description : Must be mapped to the generic interrupt of instance 1 channel 5. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH5); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH6 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH6 + * Description : Must be mapped to the generic interrupt of instance 1 channel 6. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH6); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH6 + * Description : Must be mapped to the generic interrupt of instance 1 channel 6. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH6); +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH7 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH7 + * Description : Must be mapped to the generic interrupt of instance 1 channel 7. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH7); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH7 + * Description : Must be mapped to the generic interrupt of instance 1 channel 7. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH7); +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ /* End of addtogroup psi5s */ + +#endif /* PSI5_S_IP_H */ diff --git a/s32/drivers/s32ze/Psi5_S/include/Psi5_S_Ip_Types.h b/s32/drivers/s32ze/Psi5_S/include/Psi5_S_Ip_Types.h new file mode 100644 index 000000000..858317f12 --- /dev/null +++ b/s32/drivers/s32ze/Psi5_S/include/Psi5_S_Ip_Types.h @@ -0,0 +1,447 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_S_IP_TYPES_H +#define PSI5_S_IP_TYPES_H + +/** +* @file Psi5_S_Ip_Types.h +* +* @addtogroup PSI5_S_IP PSI5_S IPV Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C"{ +#endif + +/*=============================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +===============================================================================================*/ +#include "Mcal.h" + +/*=============================================================================================== + SOURCE FILE VERSION INFORMATION +===============================================================================================*/ +#define PSI5_S_IP_TYPES_VENDOR_ID 43 +#define PSI5_S_IP_TYPES_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_S_IP_TYPES_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_S_IP_TYPES_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_S_IP_TYPES_SW_MAJOR_VERSION 2 +#define PSI5_S_IP_TYPES_SW_MINOR_VERSION 0 +#define PSI5_S_IP_TYPES_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + /* Checks against Mcal.h */ + #if ((PSI5_S_IP_TYPES_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_TYPES_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip_Types.h and Mcal.h are different" + #endif +#endif +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ +/*! + * @brief PSI5_S instance id type + * + * Type for holding instance id + * + * Implements : psi5s_instanceId_class + */ +typedef enum +{ + PSI5_S_INSTANCE0 = 0u, /*!< Instance 0*/ + PSI5_S_INSTANCE1 /*!< Instance 1*/ +} Psi5_S_Ip_InstanceIdType; + +/*! + * @brief PSI5_S channel mode + * + * Possible values for setting the reception mode + * + * Implements : psi5s_channel_mode_class + */ +typedef enum +{ + PSI5_S_SYNCHRONOUS = 0u, /*!< Synchronous mode (Rx and Tx)*/ + PSI5_S_ASYNCHRONOUS /*!< Asynchronous mode (Rx only)*/ +} Psi5_S_Ip_ChannelModeType; + +/*! + * @brief PSI5_S channel time stamp + * + * Possible values for selecting the time stamp counter + * + * Implements : psi5s_channel_timestamp_class + */ +typedef enum +{ + PSI5_S_TIME_STAMP_A = 0, /*!< Timestamp counter A */ + PSI5_S_TIME_STAMP_B /*!< Timestamp counter B */ +} Psi5_S_Ip_ChannelTimeStampType; + +/*! + * @brief PSI5_S Tx mode + * + * Possible values for setting the transmission mode + * + * Implements : psi5s_tx_mode_class + */ +typedef enum +{ + PSI5_S_TX_MODE_0 = 0, /*!< Short Frame(V1.3) with 31 "1s" as the start condition */ + PSI5_S_TX_MODE_1, /*!< Short Frame(V1.3) with 5 "0s" as the start condition */ + PSI5_S_TX_MODE_2, /*!< Long Frame(V1.3) with 31 "1s" as the start condition */ + PSI5_S_TX_MODE_3, /*!< Long Frame(V1.3) with 5 "0s" as the start condition */ + PSI5_S_TX_MODE_4, /*!< X-Long Frame(V1.3) with 31 "1s" as the start condition */ + PSI5_S_TX_MODE_5, /*!< X-Long Frame(V1.3) with 5 "0s" as the start condition */ + PSI5_S_TX_MODE_6, /*!< XX-Long (V2.0) */ + PSI5_S_TX_MODE_7 /*!< Non Standard Length */ +} Psi5_S_Ip_TxModeType; + +/*! + * @brief PSI5_S Sync state + * + * Possible values for setting the pulse generation state + * + * Implements : psi5s_sync_state_class + */ +typedef enum +{ + IPG_CLK_PS_DDTRIG = 0, /*!< ipg_clk_ps_ddtrig clock. */ + GTM_TRIG /*!< gtm_trig is selected as the clock. */ +} Psi5_S_Ip_ClockSourceType; + +/** + * @brief PSI5S event structure + * + * Contains data of event flags. + */ +typedef struct +{ + /* UART event flags */ + boolean Psi5S_UartTX; /*!< UART Transmit Event */ + boolean Psi5S_UartRX; /*!< UART Received Event */ + boolean Psi5S_UartERR; /*!< UART Errors Present Event */ + /* Global event flags */ + boolean Psi5S_GlobalTrigger; /*!< PSI5 Global Trigger Event */ + /* Rx event flags */ + boolean Psi5S_MessageReceived; /*!< PSI5 Message Received Event */ + boolean Psi5S_MessageOverwrite; /*!< PSI5 Message Overwrite Event */ + boolean Psi5S_MessageErrorsPresent; /*!< PSI5 Message Errors Present Event */ + /* Tx event flags */ + boolean Psi5S_TxDataOverwrite; /*!< Data register overwrite */ + boolean Psi5S_ReadyToTransmit; /*!< Driver is ready to transmit new data */ +} Psi5_S_Ip_EventType; + +/*! + * @brief PSI5_S Uart baudrate configuration + * + * Contains configuration uart baudrate value. + * + * Implements : psi5s_uart_baudrate_class + */ +typedef enum +{ + PSI5_S_UART_BAUDRATE_1200 = 1200U, + PSI5_S_UART_BAUDRATE_2400 = 2400U, + PSI5_S_UART_BAUDRATE_4800 = 4800U, + PSI5_S_UART_BAUDRATE_7200 = 7200U, + PSI5_S_UART_BAUDRATE_9600 = 9600U, + PSI5_S_UART_BAUDRATE_14400 = 14400U, + PSI5_S_UART_BAUDRATE_19200 = 19200U, + PSI5_S_UART_BAUDRATE_28800 = 28800U, + PSI5_S_UART_BAUDRATE_38400 = 38400U, + PSI5_S_UART_BAUDRATE_57600 = 57600U, + PSI5_S_UART_BAUDRATE_115200 = 115200U, + PSI5_S_UART_BAUDRATE_230400 = 230400U, + PSI5_S_UART_BAUDRATE_460800 = 460800U, + PSI5_S_UART_BAUDRATE_921600 = 921600U, + PSI5_S_UART_BAUDRATE_1843200 = 1843200U +}Psi5_S_Ip_UartBaudrateType; + +/*! + * @brief PSI5_S MailBox Error + * + * Contains define mailbox error + * + * Implements : psi5s_mailbox_err_class + */ +typedef enum +{ + XCRC_ERR = 0, /*!< XCRC error (1 bit) */ + CRC_ERR_P_ERR, /*!< CRC error (1 bit) */ + HD_ERR, /*!< ERR occurs error (1 bit) */ + SCI_P_ERRE, /*!< UART message parity error (1 bit) */ + SCI_F_ERR, /*!< UART framing error (1 bit) */ + SCI_O_ERR, /*!< UART overrun error (1 bit) */ + F_WD_ERR, /*!< Frame watchdog error (1 bit) */ + R_OVL_ERR, /*!< Message overflow (1 bit) */ + N_ERR, /*!< UART packet does not match (1 bit) */ + R_UVL_ERR /*!< Message underflow (1 bit) */ +}Psi5_S_Ip_MailBoxErrType; + +/*! + * @brief PSI5_S event type needed for callback + * + * Workaround because notification is defined in IP layer + * + * Implements : psi5s_event_class +*/ +typedef Psi5_S_Ip_EventType Psi5_S_EventType; + +typedef uint8 Psi5_S_Ip_HwChannelIdType; + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/* Get PSI5_S Instance Id */ +#define PSI5_S_GET_HW_INSTANCE(internalMappingCh) (((((uint8)internalMappingCh) >> ((uint8)4u)) == 0u) ? PSI5_S_INSTANCE0 : PSI5_S_INSTANCE1) + +/* Get PSI5_S channel Id */ +#define PSI5_S_GET_HW_CHANNEL(internalMappingCh) ((uint8)(((uint8)internalMappingCh) & (uint8)0x0Fu)) + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*! + * @brief Callback function + * + * PSI5_S callback prototype. Called from IRQ. + * + * Implements : psi5s_callback_func_class + */ +typedef void(* Psi5_S_Ip_CallbackType)(Psi5_S_EventType Event); + +/*! + * @brief Raw data frame + * + * A raw PSI5_S frame. Contains hardware specific fields. Needs conversion. + * + * Implements : psi5s_raw_frame_class + */ +typedef uint32 Psi5_S_Ip_RawPsi5SFrameType[4u]; + +/*! + * @brief PSI5_S slot data type + * + * Slot configuration structure + * + * Implements : psi5s_slot_config_class + */ +typedef struct +{ + uint8 slotId; /*!< Slot id number (1-6) */ + boolean useCRC; /*!< Controls the local parity/CRC option for the message */ + uint8 payloadSize; /*!< Payload region length */ +} Psi5_S_Ip_SlotConfigType; + +/*! + * @brief PSI5_S data frame + * + * A PSI5_S frame. Contains specific fields. + * + * Implements : psi5s_psi5frame_class + */ +typedef struct +{ + uint32 TIME_STAMP; /*!< Time stamp value (24 bits) */ + uint32 PS_DATA; /*!< PSI5 data (28 bits) */ + uint8 DCI1; /*!< Data Consistency Indicator MRU_BUF2_REG1 (4 bits) */ + uint8 DCI2; /*!< Data Consistency Indicator MRU_BUF2_REG2 (4 bits) */ + uint8 DCI3; /*!< Data Consistency Indicator MRU_BUF2_REG3 (4 bits) */ + uint8 XCRC; /*!< XCRC value Parity (6 bits, 1 bit parity in C[5] if configured) */ + uint8 CRC; /*!< CRC value Parity (3 bits, 1 bit parity in C[2] if configured) */ + uint8 FID; /*!< Indicates Frame ID (3 bit) */ + uint8 CHID; /*!< Indicates Channel ID (3 bit) */ + uint8 ERR; /*!< Transceiver error (2 bit) */ + uint8 F_OV; /*!< Message overwrite (1 bit) */ + uint16 F_ERR; /*!< Message error (10 bit) */ +} Psi5_S_Ip_Psi5SFrameStructType; + +typedef Psi5_S_Ip_Psi5SFrameStructType Psi5_S_Ip_Psi5SFrameType; + +/*! + * @brief Callback function + * + * PSI5_S callback prototype. Called from IRQ. + * + * Implements : psi5s_callback_rx_func_class + */ +typedef void(* Psi5_S_Ip_CallbackRxType)(Psi5_S_Ip_InstanceIdType Psi5SInstanceId, Psi5_S_Ip_Psi5SFrameType Psi5SFramePtr); + +/*! + * @brief Channel rx configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5s_channel_rx_config_class + */ +typedef struct +{ + const Psi5_S_Ip_SlotConfigType *slotConfig; /*!< Pointer to a slot configuration list */ + const uint8 numOfSlotConfigs; /*!< Number of configurations in the slot configuration list */ +} Psi5_S_Ip_ChannelRxConfigType; + +/*! + * @brief Channel tx configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5s_channel_tx_config_class + */ +typedef struct +{ + const boolean syncGlobal; /*!< Sync the global shift trigger of all the DDSRs */ + const Psi5_S_Ip_ClockSourceType clockSel; /*!< Select clock source */ + const uint16 initCMD; /*!< Initial reset reload value for the integrated "CMD" format */ + const uint16 initACMD; /*!< Initial reset reload value for the integrated "ACMD" format */ + const uint16 targetPeriod; /*!< Subsequent reload values for the integrated period generator */ + const uint16 counterDelay; /*!< Time in us for which the manchester decoder is disabled after the falling edge of a sync pulse */ + const Psi5_S_Ip_TxModeType txMode; /*!< Transmitter mode, please refer to RM */ + const boolean txDefault1; /*!< All bits in Tx registers will default to "1" */ +} Psi5_S_Ip_ChannelTxConfigType; + +/*! + * @brief PSI5_S Uart configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5s_uart_config_class + */ +typedef struct +{ + const uint32 Uart_baud_clock; + const boolean Uart_transmit_MSB; + const boolean Uart_received_MSB; + const boolean Uart_baud_rate_cus_enable; + const Psi5_S_Ip_UartBaudrateType Uart_baud_rate; + const uint32 Uart_baud_rate_cus; + const boolean Uart_tx_parity_enable; + const boolean Uart_rx_parity_enable; + const boolean Uart_tx_data_level_inversion; + const boolean Uart_rx_data_level_inversion; + const uint16 Uart_preset_timeout; + const boolean Uart_tx_idle_delay_time_enable; + const uint8 Uart_tx_idle_delay_time; + const boolean Uart_reduced_over_sampling_enable; + const uint8 Uart_over_sampling_rate; + const uint8 Uart_sampling_point; + const boolean Uart_loop_back_enable; +}Psi5_S_Ip_UartConfigType; + +/*! + * @brief Psi5_S Dma configuration structure + * + * Contains configuration data for one channel. + * + */ +typedef struct +{ + const uint8 channelId; /*!< Assigned DMA logical channel for PSI5_S frames */ +} Psi5_S_Ip_DmaConfigType; + +/*! + * @brief PSI5_S channel configuration structure + * + * Contains configuration data for one channel. + * + * Implements : psi5s_channel_config_class + */ +typedef struct +{ + const uint8 channelId; /*!< Channel id number (0-7) */ + const Psi5_S_Ip_ChannelModeType mode; /*!< Communication mode */ + const Psi5_S_Ip_CallbackRxType callbackRx; /*!< Callback Rx data */ + const Psi5_S_Ip_CallbackType callbackTx; /*!< Callback Tx data */ + const Psi5_S_Ip_ChannelTimeStampType timestamp; /*!< Capture time-stamp at A or B, otherwise at sync */ + const boolean wdEnable; /*!< The watchdog counter for each channel */ + const uint32 wdTimeout; /*!< The watchdog time out value */ + const boolean LocalCtrl; /*!< Local set controlled globally on a channel basis or locally on a per frame basis */ + const boolean useCRC; /*!< Selects the Parity or the CRC option for all the Frames of that particular channel */ + const Psi5_S_Ip_ChannelRxConfigType * rxConfig; /*!< Rx Configuration */ + const Psi5_S_Ip_ChannelTxConfigType * txConfig; /*!< Tx Configuration */ +} Psi5_S_Ip_ChannelConfigType; + +/*! + * @brief Channel new message flags + * + * Implements : psi5s_channel_flag_class + */ +typedef struct +{ + uint32 psi5SNewMessageAvailable; /*!< Pending buffer flags for PSI5_S frames. (internal use) */ +} Psi5_S_Ip_ChannelFlagType; + +/*! + * @brief Instance configuration structure + * + * PSI5_S instance configuration structure. Contains all data required to configure the instance. + * + * Implements : psi5s_instance_class + */ +typedef struct +{ + const Psi5_S_Ip_InstanceIdType instanceId; /*!< PSI5_S instance id */ + const Psi5_S_Ip_ChannelConfigType * channelConfig; /*!< Pointer to a channel configuration list */ + const uint8 numOfChannels; /*!< Number of channels configured */ + const uint8 * chHwIdToIndexArrayConfig; /*!< Array with mapping of channel hw id to the index in channel config array */ + const Psi5_S_Ip_UartConfigType * uartConfig; /*!< Pointer to a uart configuration list*/ + const Psi5_S_Ip_DmaConfigType * dmaConfig; /*!< Assigned DMA config for frame */ + const Psi5_S_Ip_CallbackType callback; /*!< Callback data */ +} Psi5_S_Ip_InstanceType; + +/*! + * @brief configuration structure + * + * PSI5_S configuration structure. Contains all data required to configure if IP. + * + * Implements : psi5s_config_class + */ +typedef struct +{ + const Psi5_S_Ip_InstanceType * instancesConfig; /*!< Pointer to instances configuration list */ + const uint8 numOfInstances; /*!< Number of instances configured */ + const uint8 * logicalChToHwCh; /*!< Pointer to array mapping logical channel to hardware channel */ +} Psi5_S_Ip_ConfigType; + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*=============================================================================================== + GLOBAL VARIABLE DECLARATIONS +===============================================================================================*/ + +/*=============================================================================================== +* FUNCTION PROTOTYPES +===============================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* PSI5_S_IP_TYPES_H */ + diff --git a/s32/drivers/s32ze/Psi5_S/src/Psi5_S_Ip.c b/s32/drivers/s32ze/Psi5_S/src/Psi5_S_Ip.c new file mode 100644 index 000000000..54e407dc7 --- /dev/null +++ b/s32/drivers/s32ze/Psi5_S/src/Psi5_S_Ip.c @@ -0,0 +1,1794 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file Psi5_S_Ip.c +* +* @addtogroup PSI5_S_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Mcal.h" +#include "Psi5_S_Ip.h" +#include "Psi5_S_Ip_Cfg.h" + +#if (STD_ON == PSI5_S_IP_DMA_IS_USED) +#include "Dma_Ip.h" +#endif + +#ifdef PSI5_S_IP_DEV_ERROR_DETECT +#if (STD_ON == PSI5_S_IP_DEV_ERROR_DETECT) + #include "Devassert.h" +#endif +#endif + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_S_IP_VENDOR_ID_C 43 +#define PSI5_S_IP_AR_RELEASE_MAJOR_VERSION_C 4 +#define PSI5_S_IP_AR_RELEASE_MINOR_VERSION_C 7 +#define PSI5_S_IP_AR_RELEASE_REVISION_VERSION_C 0 +#define PSI5_S_IP_SW_MAJOR_VERSION_C 2 +#define PSI5_S_IP_SW_MINOR_VERSION_C 0 +#define PSI5_S_IP_SW_PATCH_VERSION_C 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + /* Checks against Mcal.h */ + #if ((PSI5_S_IP_AR_RELEASE_MAJOR_VERSION_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_MINOR_VERSION_C != MCAL_AR_RELEASE_MINOR_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip.c and Mcal.h are different" + #endif +#endif + +/* Checks against Psi5_S_Ip.h */ +#if (PSI5_S_IP_VENDOR_ID_C != PSI5_S_IP_VENDOR_ID) + #error "Psi5_S_Ip.c and Psi5_S_Ip.h have different vendor ids" +#endif +#if ((PSI5_S_IP_AR_RELEASE_MAJOR_VERSION_C != PSI5_S_IP_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_MINOR_VERSION_C != PSI5_S_IP_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_REVISION_VERSION_C != PSI5_S_IP_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip.c and Psi5_S_Ip.h are different" +#endif +#if ((PSI5_S_IP_SW_MAJOR_VERSION_C != PSI5_S_IP_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_SW_MINOR_VERSION_C != PSI5_S_IP_SW_MINOR_VERSION) || \ + (PSI5_S_IP_SW_PATCH_VERSION_C != PSI5_S_IP_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_S_Ip.c and Psi5_S_Ip.h are different" +#endif + +/* Checks against Psi5_S_Ip_Cfg.h */ +#if (PSI5_S_IP_VENDOR_ID_C != PSI5_S_IP_CFG_VENDOR_ID) + #error "Psi5_S_Ip.c and Psi5_S_Ip_Cfg.h have different vendor ids" +#endif +#if ((PSI5_S_IP_AR_RELEASE_MAJOR_VERSION_C != PSI5_S_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_MINOR_VERSION_C != PSI5_S_IP_CFG_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_REVISION_VERSION_C != PSI5_S_IP_CFG_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip.c and Psi5_S_Ip_Cfg.h are different" +#endif +#if ((PSI5_S_IP_SW_MAJOR_VERSION_C != PSI5_S_IP_CFG_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_SW_MINOR_VERSION_C != PSI5_S_IP_CFG_SW_MINOR_VERSION) || \ + (PSI5_S_IP_SW_PATCH_VERSION_C != PSI5_S_IP_CFG_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_S_Ip.c and Psi5_S_Ip_Cfg.h are different" +#endif + +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + #ifdef AXBS_IP_DEV_ERROR_DETECT + #if (STD_ON == AXBS_IP_DEV_ERROR_DETECT) + /* Check if the files Psi5_S_Ip.c and Devassert.h are of the same version */ + #if ((PSI5_S_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip.c and Devassert.h are different" + #endif + #endif + #endif +#endif +/*================================================================================================== +* LOCAL MACROS +==================================================================================================*/ +#define PSI5_S_GET_EVENT(events, ev) ((Psi5_S_Ip_EventType)((events) & ((uint32)ev))) +/*================================================================================================== +* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) +==================================================================================================*/ + +/*================================================================================================== +* LOCAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL VARIABLES +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + +/* Instance base addresses */ +static const PSI5_S_MemMapPtr s_psi5BaseAddresses[PSI5_S_INSTANCE_COUNT] = IP_PSI5_S_BASE_PTRS; + +/*================================================================================================== +* GLOBAL VARIABLES +==================================================================================================*/ +#if (STD_ON == PSI5_S_IP_MULTIPARTITION_SUPPORT) +#define PSI5_START_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" + +VAR_SEC_NOCACHE(Psi5_S_UsedConfig) static Psi5_S_Ip_ConfigType const * Psi5_S_UsedConfig = NULL_PTR; +VAR_SEC_NOCACHE(Psi5_S_DriverInitialized) static boolean Psi5_S_DriverInitialized = (boolean)FALSE; +VAR_SEC_NOCACHE(g_psi5_s_sram_mailbox) static uint32 g_psi5_s_sram_mailbox[PSI5_S_INSTANCE_COUNT][PSI5_S_CH_COUNT+1][6*3]; + +#define PSI5_STOP_SEC_VAR_SHARED_CLEARED_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" +#else +#define PSI5_START_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +static Psi5_S_Ip_ConfigType const * Psi5_S_UsedConfig = NULL_PTR; + +#define PSI5_STOP_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +#define PSI5_START_SEC_VAR_CLEARED_UNSPECIFIED +#include "Psi5_MemMap.h" + +static boolean Psi5_S_DriverInitialized = (boolean)FALSE; + +#define PSI5_STOP_SEC_VAR_CLEARED_UNSPECIFIED +#include "Psi5_MemMap.h" + +#define PSI5_START_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" + +VAR_SEC_NOCACHE(g_psi5_s_sram_mailbox) static uint32 g_psi5_s_sram_mailbox[PSI5_S_INSTANCE_COUNT][PSI5_S_CH_COUNT+1][6*3]; + +#define PSI5_STOP_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" +#endif + +#define PSI5_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" + +#if (STD_ON == PSI5_S_IP_DMA_IS_USED) +VAR_ALIGN(static Dma_Ip_SwTcdRegType STcd[4], 32U) +#endif + +#define PSI5_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE +#include "Psi5_MemMap.h" + +/*================================================================================================== +* LOCAL FUNCTION PROTOTYPES +==================================================================================================*/ + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +static Std_ReturnType Psi5_S_Hw_GetPsi5SFrame(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr); +static Std_ReturnType Psi5_S_Hw_GetPsi5SFrameCal(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + const uint32 frameID, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr); +static Std_ReturnType Psi5_S_Hw_GetPsi5SFrameSub(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr); +static void Psi5_S_Hw_ConvertRawPsi5SFrame(const uint32 * sram_mailbox, + Psi5_S_Ip_Psi5SFrameType * rawFrame); +static void Psi5_S_Hw_ConfigureSlot(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + const Psi5_S_Ip_SlotConfigType * slot); +static void Psi5_S_Hw_ConfigureSlotSub(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + const Psi5_S_Ip_SlotConfigType * slot, + const float32 minUARTbytes); +static void Psi5_S_Hw_EnterUartMode(const Psi5_S_Ip_InstanceIdType instanceId); +static void Psi5_S_Hw_EnterConfigMode(const Psi5_S_Ip_InstanceIdType instanceId); +static void Psi5_S_Hw_EnterNormalMode(const Psi5_S_Ip_InstanceIdType instanceId); +static void Psi5_S_Hw_ConfigureTx(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * chCfg); +static void Psi5_S_Hw_ConfigureRx(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * chCfg); +#if (STD_ON == PSI5_S_IP_DMA_IS_USED) +static void Psi5_S_Hw_ConfigureDma(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_DmaConfigType * dmaConfig); +#endif /* (STD_ON == PSI5_S_IP_DMA_IS_USED) */ +static void Psi5_S_Hw_InstanceDisable(const Psi5_S_Ip_InstanceIdType instanceId); +static void Psi5_S_Hw_ResetRegisters(const Psi5_S_Ip_InstanceIdType instanceId); +static boolean Psi5_S_Hw_IsDataRegisterReady(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId); +static boolean Psi5_S_Hw_IsDirectCommandRegisterReady(const Psi5_S_Ip_InstanceIdType instanceId); +static void Psi5_S_EnterUartMode(const Psi5_S_Ip_InstanceType * instance); +static void Psi5_S_EnterConfigMode(const Psi5_S_Ip_InstanceType * instance); +static void Psi5_S_EnterNormalMode(const Psi5_S_Ip_InstanceType * instance); +static void Psi5_S_ConfigureUartMode(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_UartConfigType * uartConfig); +static void Psi5_S_ConfigureUart(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_UartConfigType * uartConfig); +static void Psi5_S_ConfigureSlots(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * channelConfig); +static void Psi5_S_ConfigureChannel(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * chCfg); +static void Psi5_S_ConfigureChannels(const Psi5_S_Ip_InstanceType * instance); +static void Psi5_S_Hw_GetTxEvents(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_EventType *const Events); +static void Psi5_S_Hw_GetEvents(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_EventType *const Events); +static void Psi5_S_Hw_GetPsi5SFrameInt(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr); +static void Psi5_S_Hw_GetPsi5SFrameIntSub(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr); +static void Psi5_S_Hw_GetPsi5SEvents(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr); +static void Psi5_S_Hw_EnableGLInterrupts(const Psi5_S_Ip_InstanceIdType instanceId, + const boolean Enable); +static void Psi5_S_Hw_EnableRxInterrupts(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * chCfg, + const boolean Enable); +static void Psi5_S_Hw_ClearEvents(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId); + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_GetTxEvents + * Description : Returns active Tx events + * + *END**************************************************************************/ +static void Psi5_S_Hw_GetTxEvents(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_EventType *const Events) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[Psi5InstanceId]; + const uint8 arrayIndex = Psi5_S_UsedConfig->instancesConfig[Psi5InstanceId].chHwIdToIndexArrayConfig[Psi5SChannelId]; + const Psi5_S_Ip_ChannelConfigType * config = &(Psi5_S_UsedConfig->instancesConfig[Psi5InstanceId].channelConfig[arrayIndex]); + if (config->txConfig != NULL_PTR) + { + /* Data prep overwrite */ + if (((base->CH[(uint8)(Psi5SChannelId-1u)].E2SSR & PSI5_S_E2SSR_CMDTR_NWRT_MASK) != 0u) && ((base->CH[(uint8)(Psi5SChannelId-1u)].E2SCR & PSI5_S_E2SCR_CMDTR_NWRT_IE_MASK) != 0u)) + { + Events->Psi5S_TxDataOverwrite = TRUE; + /*disable interrupt*/ + base->CH[(uint8)(Psi5SChannelId-1u)].E2SCR &= ~PSI5_S_E2SCR_CMDTR_NWRT_IE_MASK; + } + /* Data prep ready */ + if (((base->CH[(uint8)(Psi5SChannelId-1u)].E2SSR & PSI5_S_E2SSR_DDSR_RDY_MASK) != 0u) && ((base->CH[(uint8)(Psi5SChannelId-1u)].E2SCR & PSI5_S_E2SCR_DDSR_RDY_IE_MASK) != 0u)) + { + Events->Psi5S_ReadyToTransmit = TRUE; + /*disable interrupt*/ + base->CH[(uint8)(Psi5SChannelId-1u)].E2SCR &= ~PSI5_S_E2SCR_DDSR_RDY_IE_MASK; + } + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_GetPsi5SFrameInt + * Description : Returns active PSI5 interrupt + * + *END**************************************************************************/ +static void Psi5_S_Hw_GetPsi5SFrameInt(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr) +{ + Psi5_S_Ip_Psi5SFrameType rawFrame; + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[Psi5InstanceId]; + uint32 mBoxIRQ = 0u; + uint32 frameID = 0u; + uint32 channelID = (uint32)Psi5SChannelId; + + mBoxIRQ = base->MBOX_SR_IRQ; + if (mBoxIRQ != 0u) + { + if (channelID == 0u) + { + /* MAILBOX0,LOC0 - MAILBOX0,LOC1 Check */ + if((base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F0_READ_MASK) != 0u) + { + frameID = 0u; + /* Read MailBox message */ + Psi5_S_Hw_ConvertRawPsi5SFrame(&g_psi5_s_sram_mailbox[Psi5InstanceId][channelID][frameID], &rawFrame); + Psi5SFramePtr->XCRC = rawFrame.XCRC; + Psi5SFramePtr->CRC = rawFrame.CRC; + Psi5SFramePtr->ERR = rawFrame.ERR; + Psi5SFramePtr->F_ERR = rawFrame.F_ERR; + Psi5SFramePtr->FID = rawFrame.FID; + Psi5SFramePtr->CHID = rawFrame.CHID; + Psi5SFramePtr->DCI1 = rawFrame.DCI1; + Psi5SFramePtr->PS_DATA = rawFrame.PS_DATA; + Psi5SFramePtr->DCI2 = rawFrame.DCI2; + Psi5SFramePtr->TIME_STAMP = rawFrame.TIME_STAMP; + Psi5SFramePtr->DCI3 = rawFrame.DCI3; + Psi5SFramePtr->F_OV = (uint8)(base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F0_OV_MASK); + if((base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F0_ERR_MASK) != 0u) + { + base->CH0_MBOX_SR &= PSI5_S_CH0_MBOX_SR_F0_ERR_MASK; + } + if((base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F0_OV_MASK) != 0u) + { + base->CH0_MBOX_SR &= PSI5_S_CH0_MBOX_SR_F0_OV_MASK; + } + base->CH0_MBOX_SR &= PSI5_S_CH0_MBOX_SR_F0_READ_MASK; + } + if((base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F1_READ_MASK) != 0u) + { + frameID = 1u; + /* Read MailBox message */ + Psi5_S_Hw_ConvertRawPsi5SFrame(&g_psi5_s_sram_mailbox[Psi5InstanceId][channelID][frameID*3u], &rawFrame); + Psi5SFramePtr->XCRC = rawFrame.XCRC; + Psi5SFramePtr->CRC = rawFrame.CRC; + Psi5SFramePtr->ERR = rawFrame.ERR; + Psi5SFramePtr->F_ERR = rawFrame.F_ERR; + Psi5SFramePtr->FID = rawFrame.FID; + Psi5SFramePtr->CHID = rawFrame.CHID; + Psi5SFramePtr->DCI1 = rawFrame.DCI1; + Psi5SFramePtr->PS_DATA = rawFrame.PS_DATA; + Psi5SFramePtr->DCI2 = rawFrame.DCI2; + Psi5SFramePtr->TIME_STAMP = rawFrame.TIME_STAMP; + Psi5SFramePtr->DCI3 = rawFrame.DCI3; + Psi5SFramePtr->F_OV = (uint8)(base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F1_OV_MASK); + if((base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F1_ERR_MASK) != 0u) + { + base->CH0_MBOX_SR &= PSI5_S_CH0_MBOX_SR_F1_ERR_MASK; + } + if((base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F1_OV_MASK) != 0u) + { + base->CH0_MBOX_SR &= PSI5_S_CH0_MBOX_SR_F1_OV_MASK; + } + base->CH0_MBOX_SR &= PSI5_S_CH0_MBOX_SR_F1_READ_MASK; + } + /* Check all error in MRU buf2 */ + if ((base->ERR_SR_IRQ & 0x3ffu) != 0u) + { + base->ERR_SR_IRQ &= 0x3ffu; /* clear error */ + } + } + else + { + Psi5_S_Hw_GetPsi5SFrameIntSub(Psi5InstanceId, Psi5SChannelId, Psi5SFramePtr); + } + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_GetPsi5SFrameIntSub + * Description : Returns active PSI5 interrupt + * + *END**************************************************************************/ +static void Psi5_S_Hw_GetPsi5SFrameIntSub(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr) +{ + Psi5_S_Ip_Psi5SFrameType rawFrame; + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[Psi5InstanceId]; + uint32 mBoxSR = 0u; + uint32 frameID = 0u; + uint32 channelID = (uint32)Psi5SChannelId; + Psi5_S_Ip_ChannelModeType channelMode; + channelMode = (((base->CH[(uint8)(Psi5SChannelId - 1u)].MSGA & PSI5_S_MSGA_MODE_MASK) >> PSI5_S_MSGA_MODE_SHIFT) == 1u) ? PSI5_S_ASYNCHRONOUS : PSI5_S_SYNCHRONOUS; + mBoxSR = base->CH[(uint8)(channelID-1u)].MBOX_SR; + while (((mBoxSR >> (frameID * 3u)) & 0x7u) == 0u) + { + frameID++; + } + if ((frameID <= 5u) && ((((base->CH[(uint8)(channelID-1u)].MBOX_SR)>>(frameID*3u)) & PSI5_S_MBOX_SR_F0_READ_MASK) != 0u)) + { + /* Read MailBox message */ + if (channelMode == PSI5_S_ASYNCHRONOUS) + { + Psi5_S_Hw_ConvertRawPsi5SFrame((uint32*)base->MRU_BUF2_REG0, &rawFrame); + Psi5SFramePtr->XCRC = rawFrame.XCRC; + Psi5SFramePtr->CRC = rawFrame.CRC; + Psi5SFramePtr->ERR = rawFrame.ERR; + Psi5SFramePtr->F_ERR = rawFrame.F_ERR; + Psi5SFramePtr->FID = rawFrame.FID; + Psi5SFramePtr->CHID = rawFrame.CHID; + Psi5SFramePtr->DCI1 = rawFrame.DCI1; + Psi5SFramePtr->PS_DATA = rawFrame.PS_DATA; + Psi5SFramePtr->DCI2 = rawFrame.DCI2; + Psi5SFramePtr->TIME_STAMP = rawFrame.TIME_STAMP; + Psi5SFramePtr->DCI3 = rawFrame.DCI3; + Psi5SFramePtr->F_OV = (uint8)(((base->CH[(uint8)(channelID-1u)].MBOX_SR)>>(frameID*3u)) & (PSI5_S_MBOX_SR_F0_OV_MASK >> PSI5_S_MBOX_SR_F0_OV_SHIFT)); + } + else + { + Psi5_S_Hw_ConvertRawPsi5SFrame(&g_psi5_s_sram_mailbox[Psi5InstanceId][channelID][frameID*3u], &rawFrame); + Psi5SFramePtr->XCRC = rawFrame.XCRC; + Psi5SFramePtr->CRC = rawFrame.CRC; + Psi5SFramePtr->ERR = rawFrame.ERR; + Psi5SFramePtr->F_ERR = rawFrame.F_ERR; + Psi5SFramePtr->FID = rawFrame.FID; + Psi5SFramePtr->CHID = rawFrame.CHID; + Psi5SFramePtr->DCI1 = rawFrame.DCI1; + Psi5SFramePtr->PS_DATA = rawFrame.PS_DATA; + Psi5SFramePtr->DCI2 = rawFrame.DCI2; + Psi5SFramePtr->TIME_STAMP = rawFrame.TIME_STAMP; + Psi5SFramePtr->DCI3 = rawFrame.DCI3; + Psi5SFramePtr->F_OV = (uint8)(((base->CH[(uint8)(channelID-1u)].MBOX_SR)>>(frameID*3u)) & (PSI5_S_MBOX_SR_F0_OV_MASK >> PSI5_S_MBOX_SR_F0_OV_SHIFT)); + } + if((((base->CH[(uint8)(channelID-1u)].MBOX_SR)>>(frameID*3u)) & PSI5_S_MBOX_SR_F0_ERR_MASK) != 0u) + { + base->CH[(uint8)(channelID-1u)].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_ERR_MASK<<(uint32)(frameID*3u)); + } + if((((base->CH[(uint8)(channelID-1u)].MBOX_SR)>>(frameID*3u)) & PSI5_S_MBOX_SR_F0_OV_MASK) != 0u) + { + base->CH[(uint8)(channelID-1u)].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_OV_MASK<<(uint32)(frameID*3u)); + } + base->CH[(uint8)(channelID-1u)].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_READ_MASK<<(uint32)(frameID*3u)); + } +} +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_GetEvents + * Description : Returns active events + * + *END**************************************************************************/ +static void Psi5_S_Hw_GetEvents(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_EventType *const Events) +{ + /* Tx events */ + Psi5_S_Hw_GetTxEvents(Psi5InstanceId, Psi5SChannelId, Events); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_GetPsi5SEvents + * Description : Returns active events + * + *END**************************************************************************/ +static void Psi5_S_Hw_GetPsi5SEvents(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr) +{ + /* PSI5S Frame interrupt */ + Psi5_S_Hw_GetPsi5SFrameInt(Psi5InstanceId, Psi5SChannelId, Psi5SFramePtr); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_GetPsi5SFrame + * Description : Returns a raw PSI5_S frame + * + *END**************************************************************************/ +static Std_ReturnType Psi5_S_Hw_GetPsi5SFrame(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType *Psi5SFramePtr) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + Std_ReturnType retVal = (Std_ReturnType)E_OK; + Psi5_S_Ip_Psi5SFrameType rawFrame; + rawFrame.XCRC = 0; + rawFrame.CRC = 0; + rawFrame.ERR = 0; + rawFrame.F_ERR = 0; + rawFrame.FID = 0; + rawFrame.CHID = 0; + rawFrame.DCI1 = 0; + rawFrame.PS_DATA = 0; + rawFrame.DCI2 = 0; + rawFrame.TIME_STAMP = 0; + rawFrame.DCI3 = 0; + uint32 mBoxIRQ = 0u; + uint8 arrayIndex = 0u; + const Psi5_S_Ip_ChannelConfigType *chConfig; + mBoxIRQ = base->MBOX_SR_IRQ; + if (mBoxIRQ != 0u) + { + arrayIndex = Psi5_S_UsedConfig->instancesConfig[instanceId].chHwIdToIndexArrayConfig[Psi5SChannelId]; + chConfig = &(Psi5_S_UsedConfig->instancesConfig[instanceId].channelConfig[arrayIndex]); + if (chConfig->callbackRx == NULL_PTR) + { + /* Check status MAILBOX0,LOC1 */ + if ((base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F1_READ_MASK) != 0u) + { + Psi5_S_Hw_ConvertRawPsi5SFrame(&g_psi5_s_sram_mailbox[instanceId][0][1], &rawFrame); + } + if ((rawFrame.CHID != Psi5SChannelId) || (Psi5SChannelId == 0u)) + { + retVal = Psi5_S_Hw_GetPsi5SFrameSub(instanceId, Psi5SChannelId, Psi5SFramePtr); + } + else + { + Psi5SFramePtr->XCRC = rawFrame.XCRC; + Psi5SFramePtr->CRC = rawFrame.CRC; + Psi5SFramePtr->ERR = rawFrame.ERR; + Psi5SFramePtr->F_ERR = rawFrame.F_ERR; + Psi5SFramePtr->FID = rawFrame.FID; + Psi5SFramePtr->CHID = rawFrame.CHID; + Psi5SFramePtr->DCI1 = rawFrame.DCI1; + Psi5SFramePtr->PS_DATA = rawFrame.PS_DATA; + Psi5SFramePtr->DCI2 = rawFrame.DCI2; + Psi5SFramePtr->TIME_STAMP = rawFrame.TIME_STAMP; + Psi5SFramePtr->DCI3 = rawFrame.DCI3; + Psi5SFramePtr->F_OV = (uint8)(base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F1_OV_MASK); + base->CH0_MBOX_SR &= PSI5_S_CH0_MBOX_SR_F1_READ_MASK; + base->CH[Psi5SFramePtr->CHID - 1u].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_ERR_MASK << (uint32)((uint32)rawFrame.FID * (uint32)3u)); + } + } + } + return retVal; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_GetPsi5SFrameSub + * Description : Returns a raw PSI5_S frame + * + *END**************************************************************************/ +static Std_ReturnType Psi5_S_Hw_GetPsi5SFrameSub(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType *Psi5SFramePtr) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + Std_ReturnType retVal = (Std_ReturnType)E_OK; + Psi5_S_Ip_Psi5SFrameType rawFrame; + uint32 mBoxSR = 0u; + uint32 frameID = 0u; + if (Psi5SChannelId == 0u) + { + if ((base->CH0_MBOX_SR & PSI5_S_CH0_MBOX_SR_F0_READ_MASK) != 0u) + { + frameID = 0u; + Psi5_S_Hw_ConvertRawPsi5SFrame(&g_psi5_s_sram_mailbox[instanceId][Psi5SChannelId][frameID*3u], &rawFrame); + Psi5SFramePtr->XCRC = rawFrame.XCRC; + Psi5SFramePtr->CRC = rawFrame.CRC; + Psi5SFramePtr->ERR = rawFrame.ERR; + Psi5SFramePtr->F_ERR = rawFrame.F_ERR; + Psi5SFramePtr->FID = rawFrame.FID; + Psi5SFramePtr->CHID = rawFrame.CHID; + Psi5SFramePtr->DCI1 = rawFrame.DCI1; + Psi5SFramePtr->PS_DATA = rawFrame.PS_DATA; + Psi5SFramePtr->DCI2 = rawFrame.DCI2; + Psi5SFramePtr->TIME_STAMP = rawFrame.TIME_STAMP; + Psi5SFramePtr->DCI3 = rawFrame.DCI3; + Psi5SFramePtr->F_OV = (uint8)(((base->CH0_MBOX_SR) >> (frameID * 3u)) & (PSI5_S_CH0_MBOX_SR_F0_OV_MASK >> PSI5_S_CH0_MBOX_SR_F0_OV_SHIFT)); + if ((((base->CH0_MBOX_SR) >> (frameID * 3u)) & PSI5_S_CH0_MBOX_SR_F0_ERR_MASK) != 0u) + { + base->CH0_MBOX_SR &= (uint32)((uint32)PSI5_S_CH0_MBOX_SR_F0_ERR_MASK << (uint32)(frameID * 3u)); + } + if ((((base->CH0_MBOX_SR) >> (frameID * 3u)) & PSI5_S_CH0_MBOX_SR_F0_OV_MASK) != 0u) + { + base->CH0_MBOX_SR &= (uint32)((uint32)PSI5_S_CH0_MBOX_SR_F0_OV_MASK << (uint32)(frameID * 3u)); + } + base->CH0_MBOX_SR &= (uint32)((uint32)PSI5_S_CH0_MBOX_SR_F0_READ_MASK << (uint32)(frameID * 3u)); + /* Error in current message */ + if (rawFrame.F_ERR != 0u) + { + retVal = (Std_ReturnType)E_NOT_OK; + } + } + } + else + { + mBoxSR = base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR; + if (mBoxSR != 0u) + { + while (((mBoxSR >> (frameID * 3u)) & 0x7u) == 0u) + { + frameID++; + } + if (frameID > 5u) + { + retVal = (Std_ReturnType)E_NOT_OK; + } + else + { + if ((((base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR) >> (frameID * 3u)) & PSI5_S_MBOX_SR_F0_READ_MASK) != 0u) + { + retVal = Psi5_S_Hw_GetPsi5SFrameCal(instanceId, Psi5SChannelId, frameID, Psi5SFramePtr); + } + } + } + } + return retVal; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_GetPsi5SFrameCal + * Description : Returns a raw PSI5_S frame + * + *END**************************************************************************/ +static Std_ReturnType Psi5_S_Hw_GetPsi5SFrameCal(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + const uint32 frameID, + Psi5_S_Ip_Psi5SFrameType *Psi5SFramePtr) +{ + Psi5_S_Ip_Psi5SFrameType rawFrame; + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + Std_ReturnType retVal = (Std_ReturnType)E_OK; + uint32 StartTime; + uint32 TimeoutTicks; + uint32 ElapsedTicks = 0; + Psi5_S_Ip_ChannelModeType channelMode; + channelMode = (((base->CH[(uint8)(Psi5SChannelId - 1u)].MSGA & PSI5_S_MSGA_MODE_MASK) >> PSI5_S_MSGA_MODE_SHIFT) == 1u) ? PSI5_S_ASYNCHRONOUS : PSI5_S_SYNCHRONOUS; + /* Read MailBox message */ + if (channelMode == PSI5_S_ASYNCHRONOUS) + { + Psi5_S_Ip_StartTimeout(&StartTime, &TimeoutTicks, PSI5_S_IP_TIMEOUT_VALUE_US, PSI5_S_IP_TIMEOUT_TYPE); + base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR |= (uint32)((uint32)PSI5_S_MBOX_SR_F0_READ_MASK << (uint32)(frameID * 3u)); + while((base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR == 0u) && !Psi5_S_Ip_CheckTimeout(&StartTime, &ElapsedTicks, TimeoutTicks, PSI5_S_IP_TIMEOUT_TYPE)) + {} + Psi5_S_Hw_ConvertRawPsi5SFrame((uint32 *)base->MRU_BUF2_REG0, &rawFrame); + Psi5SFramePtr->XCRC = rawFrame.XCRC; + Psi5SFramePtr->CRC = rawFrame.CRC; + Psi5SFramePtr->ERR = rawFrame.ERR; + Psi5SFramePtr->F_ERR = rawFrame.F_ERR; + Psi5SFramePtr->FID = rawFrame.FID; + Psi5SFramePtr->CHID = rawFrame.CHID; + Psi5SFramePtr->DCI1 = rawFrame.DCI1; + Psi5SFramePtr->PS_DATA = rawFrame.PS_DATA; + Psi5SFramePtr->DCI2 = rawFrame.DCI2; + Psi5SFramePtr->TIME_STAMP = rawFrame.TIME_STAMP; + Psi5SFramePtr->DCI3 = rawFrame.DCI3; + Psi5SFramePtr->F_OV = (uint8)(((base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR) >> (frameID * 3u)) & (PSI5_S_MBOX_SR_F0_OV_MASK >> PSI5_S_MBOX_SR_F0_OV_SHIFT)); + if ((((base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR) >> (frameID * 3u)) & PSI5_S_MBOX_SR_F0_ERR_MASK) != 0u) + { + base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_ERR_MASK << (uint32)(frameID * 3u)); + /* Error in current message */ + if (rawFrame.F_ERR != 0u) + { + retVal = (Std_ReturnType)E_NOT_OK; + } + } + if ((((base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR) >> (frameID * 3u)) & PSI5_S_MBOX_SR_F0_OV_MASK) != 0u) + { + base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_OV_MASK << (uint32)(frameID * 3u)); + } + base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_READ_MASK << (uint32)(frameID * 3u)); + } + else + { + Psi5_S_Hw_ConvertRawPsi5SFrame(&g_psi5_s_sram_mailbox[instanceId][Psi5SChannelId][frameID * 3u], &rawFrame); + Psi5SFramePtr->XCRC = rawFrame.XCRC; + Psi5SFramePtr->CRC = rawFrame.CRC; + Psi5SFramePtr->ERR = rawFrame.ERR; + Psi5SFramePtr->F_ERR = rawFrame.F_ERR; + Psi5SFramePtr->FID = rawFrame.FID; + Psi5SFramePtr->CHID = rawFrame.CHID; + Psi5SFramePtr->DCI1 = rawFrame.DCI1; + Psi5SFramePtr->PS_DATA = rawFrame.PS_DATA; + Psi5SFramePtr->DCI2 = rawFrame.DCI2; + Psi5SFramePtr->TIME_STAMP = rawFrame.TIME_STAMP; + Psi5SFramePtr->DCI3 = rawFrame.DCI3; + Psi5SFramePtr->F_OV = (uint8)(((base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR) >> (frameID * 3u)) & (PSI5_S_MBOX_SR_F0_OV_MASK >> PSI5_S_MBOX_SR_F0_OV_SHIFT)); + if ((((base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR) >> (frameID * 3u)) & PSI5_S_MBOX_SR_F0_ERR_MASK) != 0u) + { + base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_ERR_MASK << (uint32)(frameID * 3u)); + /* Error in current message */ + if (rawFrame.F_ERR != 0u) + { + retVal = (Std_ReturnType)E_NOT_OK; + } + } + if ((((base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR) >> (frameID * 3u)) & PSI5_S_MBOX_SR_F0_OV_MASK) != 0u) + { + base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_OV_MASK << (uint32)(frameID * 3u)); + } + base->CH[(uint8)(Psi5SChannelId - 1u)].MBOX_SR &= (uint32)((uint32)PSI5_S_MBOX_SR_F0_READ_MASK << (uint32)(frameID * 3u)); + } + return retVal; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_ConvertRawPsi5SFrame + * Description : Converts a raw PSI5_S frame + * + *END**************************************************************************/ +static void Psi5_S_Hw_ConvertRawPsi5SFrame(const uint32 * sram_mailbox, + Psi5_S_Ip_Psi5SFrameType * rawFrame) +{ + rawFrame->XCRC = (uint8)((sram_mailbox[0] & PSI5_S_MRU_BUF2_REG1_XCRC_MASK) >> PSI5_S_MRU_BUF2_REG1_XCRC_SHIFT); + rawFrame->CRC = (uint8)((sram_mailbox[0] & PSI5_S_MRU_BUF2_REG1_CRC_MASK) >> PSI5_S_MRU_BUF2_REG1_CRC_SHIFT); + rawFrame->ERR = (uint8)((sram_mailbox[0] & PSI5_S_MRU_BUF2_REG1_ERR_MASK) >> PSI5_S_MRU_BUF2_REG1_ERR_SHIFT); + rawFrame->F_ERR = (uint8)((uint16)(sram_mailbox[0] & PSI5_S_MRU_BUF2_REG1_XCRC_ERR_MASK) >> PSI5_S_MRU_BUF2_REG1_XCRC_ERR_SHIFT) + |(uint16)(((sram_mailbox[0] & PSI5_S_MRU_BUF2_REG1_CRC_ERR_P_ERR_MASK) >> PSI5_S_MRU_BUF2_REG1_CRC_ERR_P_ERR_SHIFT)<> PSI5_S_MRU_BUF2_REG1_HD_ERR_SHIFT)<> PSI5_S_MRU_BUF2_REG1_SCI_P_ERR_SHIFT)<> PSI5_S_MRU_BUF2_REG1_SCI_F_ERR_SHIFT)<> PSI5_S_MRU_BUF2_REG1_SCI_O_ERR_SHIFT)<> PSI5_S_MRU_BUF2_REG1_F_WD_ERR_SHIFT)<> PSI5_S_MRU_BUF2_REG1_R_OVL_ERR_SHIFT)<> PSI5_S_MRU_BUF2_REG1_N_ERR_SHIFT)<> PSI5_S_MRU_BUF2_REG1_R_UVL_ERR_SHIFT)<FID = (uint8)((sram_mailbox[0] & PSI5_S_MRU_BUF2_REG1_FID_MASK) >> PSI5_S_MRU_BUF2_REG1_FID_SHIFT); + rawFrame->CHID = (uint8)((sram_mailbox[0] & PSI5_S_MRU_BUF2_REG1_CHID_MASK) >> PSI5_S_MRU_BUF2_REG1_CHID_SHIFT); + rawFrame->DCI1 = (uint8)((sram_mailbox[0] & PSI5_S_MRU_BUF2_REG1_DCI_MASK) >> PSI5_S_MRU_BUF2_REG1_DCI_SHIFT); + rawFrame->PS_DATA = (uint32)((sram_mailbox[1] & PSI5_S_MRU_BUF2_REG2_PS_DATA_MASK) >> PSI5_S_MRU_BUF2_REG2_PS_DATA_SHIFT); + rawFrame->DCI2 = (uint8)((sram_mailbox[1] & PSI5_S_MRU_BUF2_REG2_DCI_MASK) >> PSI5_S_MRU_BUF2_REG2_DCI_SHIFT); + rawFrame->TIME_STAMP = (uint32)((sram_mailbox[2] & PSI5_S_MRU_BUF2_REG3_TIMESTAMP_MASK) >> PSI5_S_MRU_BUF2_REG3_TIMESTAMP_SHIFT); + rawFrame->DCI3 = (uint8)((sram_mailbox[2] & PSI5_S_MRU_BUF2_REG3_DCI_MASK) >> PSI5_S_MRU_BUF2_REG3_DCI_SHIFT); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_ConfigureSlot + * Description : Configures a single slot + * + *END**************************************************************************/ +static void Psi5_S_Hw_ConfigureSlot(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + const Psi5_S_Ip_SlotConfigType * slot + ) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + float32 minUARTbytes = (float32)0; + if (Psi5SChannelId == 0u) + { + minUARTbytes = (float32)((float32)8 + (float32)(slot->payloadSize) + (float32)0 + (float32)6) / (float32)8; + } + else + { + /* P/CRC controled by global*/ + if(!((base->CH[(uint8)(Psi5SChannelId-1u)].MSGA & PSI5_S_MSGA_L_PC_EN_MASK) != 0u)) + { + if((base->CH[(uint8)(Psi5SChannelId-1u)].MSGA & PSI5_S_MSGA_G_PC_MASK) != 0u) + { + minUARTbytes = (float32)((float32)8 + (float32)(slot->payloadSize) + (float32)3 + (float32)6) / (float32)8; + } + else + { + minUARTbytes = (float32)((float32)8 + (float32)(slot->payloadSize) + (float32)1 + (float32)6) / (float32)8; + } + } + /* P/CRC controled by local*/ + else + { + if((boolean)slot->useCRC) + { + minUARTbytes = (float32)((float32)8 + (float32)(slot->payloadSize) + (float32)3 + (float32)6) / (float32)8; + } + else + { + minUARTbytes = (float32)((float32)8 + (float32)(slot->payloadSize) + (float32)1 + (float32)6) / (float32)8; + } + } + } + if ((minUARTbytes - (float32)(uint8)minUARTbytes) > (float32)0) + { + minUARTbytes = (float32)((uint8)minUARTbytes) + (float32)1; + } + if (Psi5SChannelId == 0u) + { + base->CH0_MSGA |= PSI5_S_CH0_MSGA_F0_BYTE(minUARTbytes); + base->CH0_MSGB = (base->CH0_MSGB & ~PSI5_S_CH0_MSGB_F0_payload_MASK) | PSI5_S_CH0_MSGB_F0_payload(slot->payloadSize); + } + else + { + Psi5_S_Hw_ConfigureSlotSub(instanceId, Psi5SChannelId, slot, minUARTbytes); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_ConfigureSlotSub + * Description : Configures a single slot + * + *END**************************************************************************/ +static void Psi5_S_Hw_ConfigureSlotSub(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + const Psi5_S_Ip_SlotConfigType * slot, + const float32 minUARTbytes) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + uint8 slotIdx = (slot->slotId); + switch(slotIdx) + { + case 0u:{ + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_F0_BYTE(minUARTbytes); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_L_PC0((slot->useCRC == FALSE) ? 0u : 1u); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGB = (base->CH[(uint8)(Psi5SChannelId-1u)].MSGB & ~PSI5_S_MSGB_F0_payload_MASK) | PSI5_S_MSGB_F0_payload(slot->payloadSize); + break; + } + case 1u:{ + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_F1_BYTE(minUARTbytes); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_L_PC1((slot->useCRC == FALSE) ? 0u : 1u); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGB = (base->CH[(uint8)(Psi5SChannelId-1u)].MSGB & ~PSI5_S_MSGB_F1_payload_MASK) | PSI5_S_MSGB_F1_payload(slot->payloadSize); + break; + } + case 2u:{ + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_F2_BYTE(minUARTbytes); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_L_PC2((slot->useCRC == FALSE) ? 0u : 1u); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGB = (base->CH[(uint8)(Psi5SChannelId-1u)].MSGB & ~PSI5_S_MSGB_F2_payload_MASK) | PSI5_S_MSGB_F2_payload(slot->payloadSize); + break; + } + case 3u:{ + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_F3_BYTE(minUARTbytes); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_L_PC3((slot->useCRC == FALSE) ? 0u : 1u); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGB = (base->CH[(uint8)(Psi5SChannelId-1u)].MSGB & ~PSI5_S_MSGB_F3_payload_MASK) | PSI5_S_MSGB_F3_payload(slot->payloadSize); + break; + } + case 4u:{ + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_F4_BYTE(minUARTbytes); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_L_PC4((slot->useCRC == FALSE) ? 0u : 1u); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGB = (base->CH[(uint8)(Psi5SChannelId-1u)].MSGB & ~PSI5_S_MSGB_F4_payload_MASK) | PSI5_S_MSGB_F4_payload(slot->payloadSize); + break; + } + case 5u:{ + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_F5_BYTE(minUARTbytes); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGA |= PSI5_S_MSGA_L_PC5((slot->useCRC == FALSE) ? 0u : 1u); + base->CH[(uint8)(Psi5SChannelId-1u)].MSGB = (base->CH[(uint8)(Psi5SChannelId-1u)].MSGB & ~PSI5_S_MSGB_F5_payload_MASK) | PSI5_S_MSGB_F5_payload(slot->payloadSize); + break; + } + default: /*error, not possible by configuration */ + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_EnterUartMode + * Description : Enter into UART mode + * + *END**************************************************************************/ +static void Psi5_S_Hw_EnterUartMode(const Psi5_S_Ip_InstanceIdType instanceId) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + if((base->GLCR & PSI5_S_GLCR_GLOBAL_MODE_MASK) != 7u) + { + /* Global disable mode */ + base->GLCR |= (base->GLCR & ~PSI5_S_GLCR_GLOBAL_MODE_MASK) | PSI5_S_GLCR_GLOBAL_MODE(7u); + base->GLSR |= PSI5_S_GLSR_GL_MODETR_DONE_MASK; + } + /* Global uart mode */ + base->GLCR = PSI5_S_GLCR_GLOBAL_MODE(0u); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_EnterConfigMode + * Description : Puts the channel in configuration mode + * + *END**************************************************************************/ +static void Psi5_S_Hw_EnterConfigMode(const Psi5_S_Ip_InstanceIdType instanceId) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; +#if (STD_ON == PSI5_S_IP_DEBUG_MODE) + base->GLCR |= PSI5_S_GLCR_DEBUG_EN_MASK; +#endif + if((base->GLCR & PSI5_S_GLCR_GLOBAL_MODE_MASK) != 7u) + { + /* Global disable mode */ + base->GLCR |= (base->GLCR & ~PSI5_S_GLCR_GLOBAL_MODE_MASK) | PSI5_S_GLCR_GLOBAL_MODE(7u); + base->GLSR |= PSI5_S_GLSR_GL_MODETR_DONE_MASK; + } + /* Global config mode */ + base->GLCR &= PSI5_S_GLCR_GLOBAL_MODE(4u); + base->GLSR |= PSI5_S_GLSR_GL_MODETR_DONE_MASK; + base->GLCR |= PSI5_S_GLCR_TSCNTEN_G_L_MASK; + /* base->GLCR |= PSI5_S_GLCR_CLRTSCNT_G_L_MASK */ + base->GLCR |= PSI5_S_GLCR_TSCNT_EN_A_MASK; + base->GLCR |= PSI5_S_GLCR_TSCNT_EN_B_MASK; + /* base->GLCR |= PSI5_S_GLCR_CLRTSCNT_G_MASK */ + base->GLCR |= PSI5_S_GLCR_TSCNTEN_G_MASK; + /* Provide the base address of the mailbox in the system RAM */ + base->CH_BASE_ADDR |= (base->CH_BASE_ADDR & ~(uint16)PSI5_S_CH_BASE_ADDR_MAILBOX_BASE_ADDR_MASK) | (uint32)&g_psi5_s_sram_mailbox[instanceId]; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_EnterNormalMode + * Description : Puts the channel in normal mode + * + *END**************************************************************************/ +static void Psi5_S_Hw_EnterNormalMode(const Psi5_S_Ip_InstanceIdType instanceId) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + if((base->GLCR & PSI5_S_GLCR_GLOBAL_MODE_MASK) != 7u) + { + /* Global disable mode */ + base->GLCR |= (base->GLCR & ~PSI5_S_GLCR_GLOBAL_MODE_MASK) | PSI5_S_GLCR_GLOBAL_MODE(7u); + base->GLSR |= PSI5_S_GLSR_GL_MODETR_DONE_MASK; + } + /* Global config mode */ + base->GLCR &= PSI5_S_GLCR_GLOBAL_MODE(0x1U); + base->GLSR |= PSI5_S_GLSR_GL_MODETR_DONE_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_ConfigureTx + * Description : Configures transmission + * + *END**************************************************************************/ +static void Psi5_S_Hw_ConfigureTx(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * chCfg) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + /* Tx mode, Data length, default bit values */ + if ((chCfg->channelId > 0u) && (chCfg->txConfig != NULL_PTR)) + { + /* Set mode to synchronous */ + base->CH[(uint8)(chCfg->channelId-1u)].E2SCR |= PSI5_S_E2SCR_GL_TRIG_SEL((chCfg->txConfig->syncGlobal == FALSE) ? 0u : 1u); + base->CH[(uint8)(chCfg->channelId-1u)].E2SCR |= PSI5_S_E2SCR_DDSR_CLK_SEL((uint32)(chCfg->txConfig->clockSel)); + base->CH[(uint8)(chCfg->channelId-1u)].E2SCR |= PSI5_S_E2SCR_CMD_TYPE((uint32)(chCfg->txConfig->txMode)); + base->CH[(uint8)(chCfg->channelId-1u)].E2SCR |= PSI5_S_E2SCR_CMD((uint32)(chCfg->txConfig->initCMD)); + base->CH[(uint8)(chCfg->channelId-1u)].E2SCR |= PSI5_S_E2SCR_ACMD((uint32)(chCfg->txConfig->initACMD)); + base->CH[(uint8)(chCfg->channelId-1u)].E2SCR |= PSI5_S_E2SCR_DEFAULT_SYNC((chCfg->txConfig->txDefault1 == FALSE) ? 0u : 1u); + base->CH[(uint8)(chCfg->channelId-1u)].DDTRIG_OFFR |= PSI5_S_DDTRIG_OFFR_DDTRIG_OFFR((uint32)(chCfg->txConfig->counterDelay)); + base->CH[(uint8)(chCfg->channelId-1u)].DDTRIG_PERR |= PSI5_S_DDTRIG_PERR_DDTRIG_PERR((uint32)(chCfg->txConfig->targetPeriod)); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_ConfigureRx + * Description : Configures reception + * + *END**************************************************************************/ +static void Psi5_S_Hw_ConfigureRx(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * chCfg) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + if (chCfg->channelId == 0u) + { + base->CH0_MSGA |= PSI5_S_CH0_MSGA_TSBUF_EN(0x1U); /* enable to capture respective TIMESTAMP value */ + base->CH0_MSGA |= PSI5_S_CH0_MSGA_TIMESTAMP_A_B_SEL((uint32)(chCfg->timestamp)); + } + else + { + /* Enable channel 1-7 message A */ + base->CH[(uint8)(chCfg->channelId-1u)].MSGA |= PSI5_S_MSGA_CH_EN_MASK; + /* Configures mode for channel 1-7 message A */ + base->CH[(uint8)(chCfg->channelId-1u)].MSGA |= PSI5_S_MSGA_L_PC_EN((chCfg->LocalCtrl == FALSE) ? 0u : 1u); /* Parity/CRC option controlled locally. */ + base->CH[(uint8)(chCfg->channelId-1u)].MSGA |= PSI5_S_MSGA_MODE((uint32)(chCfg->mode)); /* synchronous or asynchronous mode */ + base->CH[(uint8)(chCfg->channelId-1u)].MSGA |= PSI5_S_MSGA_TSBUF_EN(0x1U); /* enable to capture respective TIMESTAMP value */ + base->CH[(uint8)(chCfg->channelId-1u)].MSGA |= PSI5_S_MSGA_TIME_STAMP_A_B_SEL((uint32)(chCfg->timestamp)); /* TIMESTAMP Counter A is to be use */ + base->CH[(uint8)(chCfg->channelId-1u)].MSGA |= PSI5_S_MSGA_TSBUF_CLR(0x1U); /* TIMESTAMP Buffer will be clear untill trigger come. */ + base->CH[(uint8)(chCfg->channelId-1u)].MSGA |= PSI5_S_MSGA_G_PC((chCfg->useCRC == FALSE) ? 0u : 1u); /* Selection CRC selected all frame */ + if(PSI5_S_ASYNCHRONOUS == chCfg->mode) + { + base->CH[(uint8)(chCfg->channelId-1u)].MSGA |= PSI5_S_MSGA_TMSG_TCMD(0x1U); + } + if((boolean)(chCfg->wdEnable)){ + /* Start watchdog counter for each channel */ + base->CH[(uint8)(chCfg->channelId-1u)].WD_CFGR |= PSI5_S_WD_CFGR_WDEN(0x1U); + base->CH[(uint8)(chCfg->channelId-1u)].WD_CFGR |= PSI5_S_WD_CFGR_WD_TO(chCfg->wdTimeout); + } + } +} + +#if (STD_ON == PSI5_S_IP_DMA_IS_USED) +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_ConfigureDma + * Description : Configures DMA + * + *END**************************************************************************/ +static void Psi5_S_Hw_ConfigureDma(const Psi5_S_Ip_InstanceIdType Psi5InstanceId, + const Psi5_S_Ip_DmaConfigType * dmaConfig) +{ + uint8 instanceId = (uint8)Psi5InstanceId; + Dma_Ip_LogicChannelScatterGatherListType global_DmaChannelTransferList[12U]; + /* TCD software */ + STcd[2U*instanceId].reg_SADDR = (uint32)(&(s_psi5BaseAddresses[instanceId]->MRU_BUF2_REG1)); + STcd[2U*instanceId].reg_SOFF = 4; + STcd[2U*instanceId].reg_ATTR = 514; /* SSIE = 2, DSIZE = 2*/ + STcd[2U*instanceId].reg_NBYTES.reg_MLOFFNO = 12; + STcd[2U*instanceId].reg_SLAST_SDA = 0; + STcd[2U*instanceId].reg_DADDR = 830475535; + STcd[2U*instanceId].reg_DOFF = 4; + STcd[2U*instanceId].reg_CITER.reg_ELINKNO = 1; + STcd[2U*instanceId].reg_DLAST_SGA = (uint32)(&(STcd[(2U*instanceId)+1U])); + STcd[2U*instanceId].reg_CSR = 273; /* Enable gather scatter gather and enable start */ + STcd[2U*instanceId].reg_BITER.reg_ELINKNO = 1; + + STcd[(2U*instanceId)+1U].reg_SADDR = (uint32)(&(s_psi5BaseAddresses[instanceId]->MRU_BUF2_REG0)); + STcd[(2U*instanceId)+1U].reg_SOFF = 0; + STcd[(2U*instanceId)+1U].reg_ATTR = 514; /* SSIZE = 2, DSIZE = 2*/ + STcd[(2U*instanceId)+1U].reg_NBYTES.reg_MLOFFNO = 4; + STcd[(2U*instanceId)+1U].reg_SLAST_SDA = 0; + STcd[(2U*instanceId)+1U].reg_DADDR = (uint32)(&(STcd[2U*instanceId].reg_DADDR)); + STcd[(2U*instanceId)+1U].reg_DOFF = 0; + STcd[(2U*instanceId)+1U].reg_CITER.reg_ELINKNO = 1; + STcd[(2U*instanceId)+1U].reg_DLAST_SGA = (uint32)(&(STcd[2U*instanceId])); + STcd[(2U*instanceId)+1U].reg_CSR = 16; /* Enable gather scatter gather */ + STcd[(2U*instanceId)+1U].reg_BITER.reg_ELINKNO = 1; + + /* Source address: address of DSFR register */ + global_DmaChannelTransferList[0U].Param = DMA_IP_CH_SET_SOURCE_ADDRESS; + global_DmaChannelTransferList[0U].Value = (uint32)(&(s_psi5BaseAddresses[instanceId]->MRU_BUF2_REG0)); + /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. + * The application should ensure that only addresses that fit in uint32 are used for configuring DMA. */ + /* Dest address: the address of internal buffer */ + global_DmaChannelTransferList[1U].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS; + global_DmaChannelTransferList[1U].Value = (uint32)((uint32)(&(STcd[2U*instanceId].reg_DADDR))); + global_DmaChannelTransferList[2U].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE; + global_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; + global_DmaChannelTransferList[3U].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE; + global_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; + global_DmaChannelTransferList[4U].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET; + global_DmaChannelTransferList[4U].Value = (uint32)0U; + global_DmaChannelTransferList[5U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET; + global_DmaChannelTransferList[5U].Value = (uint32)0U; + global_DmaChannelTransferList[6U].Param = DMA_IP_CH_SET_SOURCE_MODULO; + global_DmaChannelTransferList[6U].Value = (uint32)0U; + global_DmaChannelTransferList[7U].Param = DMA_IP_CH_SET_DESTINATION_MODULO; + global_DmaChannelTransferList[7U].Value = (uint32)0U; + /* 4 bytes transfer for each request */ + global_DmaChannelTransferList[8U].Param = DMA_IP_CH_SET_MINORLOOP_SIZE; + global_DmaChannelTransferList[8U].Value = (uint32)4U; + global_DmaChannelTransferList[9U].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT; + global_DmaChannelTransferList[9U].Value = (uint32)1U; + global_DmaChannelTransferList[10U].Param = DMA_IP_CH_SET_SOURCE_SIGNED_LAST_ADDR_ADJ; + global_DmaChannelTransferList[10U].Value = (uint32)0U; + global_DmaChannelTransferList[11U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ; + global_DmaChannelTransferList[11U].Value = (uint32)(&STcd[2U*instanceId]); + + /* Config and start DMA channel */ + (void)Dma_Ip_SetLogicChannelScatterGatherList(dmaConfig->channelId, 0, global_DmaChannelTransferList, (uint32)12U); + (void)Dma_Ip_SetLogicChannelScatterGatherConfig(dmaConfig->channelId, 0); +} +#endif /* (STD_ON == PSI5_S_IP_DMA_IS_USED) */ + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_InstanceDisable + * Description : Global channel disabler + * + *END**************************************************************************/ +static void Psi5_S_Hw_InstanceDisable(const Psi5_S_Ip_InstanceIdType instanceId) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + base->GLCR |= (base->GLCR & ~(uint16)PSI5_S_GLCR_GLOBAL_MODE_MASK) | PSI5_S_GLCR_GLOBAL_MODE_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_ResetRegisters + * Description : Resets registers + * + *END**************************************************************************/ +static void Psi5_S_Hw_ResetRegisters(const Psi5_S_Ip_InstanceIdType instanceId) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + uint32 Psi5SChannelId; + /* Control Uart registers */ + base->LINCR1 = 0x00000092; + base->LINIER = 0x00000000; + base->UARTCR = 0x00000000; + base->LINFBRR = 0x00000000; + base->LINIBRR = 0x00000000; + base->BDRL = 0x00000000; + base->BDRM = 0x00000000; + base->UARTPTO = 0x00000FFF; + base->DMATXE = 0x00000000; + base->DMARXE = 0x00000000; + base->PTD = 0x00000000; + + /* Control registers */ + base->GLCR = 0x00000000; + base->GLSR = 0x00106000; + base->CH_BASE_ADDR = 0x00000000; + base->CH0_MSGA = 0x00000051; + base->CH0_MSGB = 0x00000008; + for(Psi5SChannelId = 0u; Psi5SChannelId < PSI5_S_CH_COUNT; Psi5SChannelId++) + { + /* Control channel registers */ + base->CH[Psi5SChannelId].MSGA = 0x00000000; + base->CH[Psi5SChannelId].MSGB = 0x10842108; + base->CH[Psi5SChannelId].WD_CFGR = 0x00000000; + base->CH[Psi5SChannelId].DDTRIG_OFFR = 0x00000000; + base->CH[Psi5SChannelId].DDTRIG_PERR = 0x00000000; + base->CH[Psi5SChannelId].E2SCR = 0x00000800; + base->CH[Psi5SChannelId].DDSR_L = 0x00000000; + } + + /* Control interrupt registers */ + for(Psi5SChannelId = 0u; Psi5SChannelId < PSI5_S_CH_COUNT; Psi5SChannelId++) + { + base->IRQ[Psi5SChannelId].MBOX_SEL_IRQ = 0x00000000; + base->IRQ[Psi5SChannelId].ERR_SEL_IRQ = 0x00000000; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_IsDataRegisterReady + * Description : Returns Tx register status + * + *END**************************************************************************/ +static boolean Psi5_S_Hw_IsDataRegisterReady(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId) +{ + const uint32 arrayIndex = Psi5_S_UsedConfig->instancesConfig[instanceId].chHwIdToIndexArrayConfig[Psi5SChannelId]; + const Psi5_S_Ip_ChannelConfigType * config = &(Psi5_S_UsedConfig->instancesConfig[instanceId].channelConfig[arrayIndex]); + boolean ret = (boolean)FALSE; + /* Depending on Tx type */ + if(config->txConfig != NULL_PTR) + { + ret = (s_psi5BaseAddresses[instanceId]->CH[(uint8)(Psi5SChannelId-1u)].E2SSR & PSI5_S_E2SSR_DDSR_RDY_MASK) != 0u; + } + return ret; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_IsDirectCommandRegisterReady + * Description : Returns Tx register status + * + *END**************************************************************************/ +static boolean Psi5_S_Hw_IsDirectCommandRegisterReady(const Psi5_S_Ip_InstanceIdType instanceId) +{ + boolean ret = (boolean)FALSE; + ret = ((s_psi5BaseAddresses[instanceId]->GLSR & PSI5_S_GLSR_DIRCMD_RDY_MASK) != 0u); + return ret; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_EnterUartMode + * Description : Enter UART mode. + * + *END**************************************************************************/ +static void Psi5_S_EnterUartMode(const Psi5_S_Ip_InstanceType * instance) +{ + Psi5_S_Hw_EnterUartMode(instance->instanceId); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_EnterConfigMode + * Description : Enter CONFIG mode. + * + *END**************************************************************************/ +static void Psi5_S_EnterConfigMode(const Psi5_S_Ip_InstanceType * instance) +{ + Psi5_S_Hw_EnterConfigMode(instance->instanceId); + if(instance->callback != NULL_PTR) + { + /* Configure interrupts */ + Psi5_S_Hw_EnableGLInterrupts(instance->instanceId, (boolean)TRUE); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_EnterNormalMode + * Description : Enter NORMAL mode. + * + *END**************************************************************************/ +static void Psi5_S_EnterNormalMode(const Psi5_S_Ip_InstanceType * instance) +{ + Psi5_S_Hw_EnterNormalMode(instance->instanceId); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_ConfigureUartMode + * Description : Configures fields in uart mode. + * + *END**************************************************************************/ +static void Psi5_S_ConfigureUartMode(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_UartConfigType *uartConfig) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + /* UART_StandAlone */ + base->LINCR1 &= ~PSI5_S_LINCR1_SLEEP_MASK; /* exit sleep mode */ + base->LINCR1 |= PSI5_S_LINCR1_INIT(0x1U); + if (uartConfig->Uart_loop_back_enable == TRUE) + { + base->LINCR1 |= PSI5_S_LINCR1_LBKM(0x1U); /* Loop Back Mode */ + base->LINCR1 &= ~PSI5_S_LINCR1_INIT_MASK; /* exit initialization mode */ + } + else + { + base->LINCR1 &=~ PSI5_S_LINCR1_LBKM_MASK; /* Loop Back Mode disable */ + base->LINCR1 &= ~PSI5_S_LINCR1_INIT_MASK; /* exit initialization mode */ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_ConfigureUart + * Description : Configures fields in config mode. + * + *END**************************************************************************/ +static void Psi5_S_ConfigureUart(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_UartConfigType * uartConfig) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + uint32 Baudrate; + uint32 integer_baudrate; + uint32 fractional_baudrate; + uint32 frequency_baudrate; + uint32 Frequency = uartConfig->Uart_baud_clock; + uint32 OSR = uartConfig->Uart_over_sampling_rate; + uint32 CSP = uartConfig->Uart_sampling_point; + uint16 PTO = uartConfig->Uart_preset_timeout; + uint8 Tx_TDFBM = ((uartConfig->Uart_transmit_MSB == FALSE) ? 0u : 1u); + uint8 Rx_RDFBM = ((uartConfig->Uart_received_MSB == FALSE) ? 0u : 1u); + uint8 Tx_PCE_TXDTU = ((uartConfig->Uart_tx_parity_enable == FALSE) ? 0u : 1u); + uint8 Rx_PCE_Rx = ((uartConfig->Uart_rx_parity_enable == FALSE) ? 0u : 1u); + uint8 Tx_TDLIS = ((uartConfig->Uart_tx_data_level_inversion == FALSE) ? 0u : 1u); + uint8 Rx_RDLIS = ((uartConfig->Uart_rx_data_level_inversion == FALSE) ? 0u : 1u); + uint8 Tx_IFD_EN = ((uartConfig->Uart_tx_idle_delay_time_enable == FALSE) ? 0u : 1u); + uint8 Tx_IFD = uartConfig->Uart_tx_idle_delay_time; + if (uartConfig->Uart_baud_rate_cus_enable == FALSE) + { + Baudrate = (uint32)(uartConfig->Uart_baud_rate); + } + else + { + Baudrate = (uint32)(uartConfig->Uart_baud_rate_cus); + } + if ((base->GLCR & PSI5_S_GLCR_GLOBAL_MODE_MASK) == 0x4u) + { + /* Psi5_S UART mode config */ + base->UARTCR |= PSI5_S_UARTCR_UART(0x1U); + if (uartConfig->Uart_reduced_over_sampling_enable == FALSE) + { + integer_baudrate = (Frequency) / (Baudrate * 16u); + frequency_baudrate = integer_baudrate * (Baudrate * 16u); + fractional_baudrate = ((Frequency - frequency_baudrate) * 16u) / (Baudrate * 16u); + } + else + { + integer_baudrate = (Frequency) / (Baudrate * OSR); + frequency_baudrate = integer_baudrate * (Baudrate * OSR); + fractional_baudrate = ((Frequency - frequency_baudrate) * OSR) / (Baudrate * OSR); + base->UARTCR |= PSI5_S_UARTCR_ROSE(0x1U); + base->UARTCR |= PSI5_S_UARTCR_OSR(OSR); + base->UARTCR |= PSI5_S_UARTCR_CSP(CSP); + } + base->UARTCR |= PSI5_S_UARTCR_MIS(0x1U); + base->UARTCR |= PSI5_S_UARTCR_WL0(0x1U); + base->LINIBRR |= PSI5_S_LINIBRR_IBR(integer_baudrate); + base->LINFBRR |= PSI5_S_LINFBRR_FBR((uint32)fractional_baudrate); + base->UARTCR |= PSI5_S_UARTCR_TDFLTFC(0x000U); + base->UARTCR |= PSI5_S_UARTCR_RDFLRFC(0x000U); + base->UARTCR |= PSI5_S_UARTCR_PCE_TXDTU((uint32)Tx_PCE_TXDTU); + base->UARTCR |= PSI5_S_UARTCR_PCE_Rx((uint32)Rx_PCE_Rx); + base->UARTCR |= PSI5_S_UARTCR_PC0(0x1U); + base->UARTCR |= PSI5_S_UARTCR_RxEn(0x1U); + base->UARTCR |= PSI5_S_UARTCR_TxEn(0x1U); + /* Psi5_S Global Control config mode */ + base->UARTCR |= PSI5_S_GCR_TDFBM((uint32)Tx_TDFBM); + base->UARTCR |= PSI5_S_GCR_RDFBM((uint32)Rx_RDFBM); + base->UARTCR |= PSI5_S_GCR_TDLIS((uint32)Tx_TDLIS); + base->UARTCR |= PSI5_S_GCR_RDLIS((uint32)Rx_RDLIS); + base->PTD |= PSI5_S_PTD_EN((uint32)Tx_IFD_EN); + base->PTD |= PSI5_S_PTD_IFD((uint32)Tx_IFD); + base->UARTPTO = PSI5_S_UARTPTO_PTO(PTO); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_ConfigureSlots + * Description : Configures a single slot. + * + *END**************************************************************************/ +static void Psi5_S_ConfigureSlots(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * channelConfig) +{ + /* For each slot configuration */ + for (uint32 slotIdx = 0u; slotIdx < channelConfig->rxConfig->numOfSlotConfigs; slotIdx++) + { + const Psi5_S_Ip_SlotConfigType * slotCfg = &(channelConfig->rxConfig->slotConfig[slotIdx]); + /* Configure current slot */ + Psi5_S_Hw_ConfigureSlot(instanceId, channelConfig->channelId, slotCfg); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_ConfigureChannel + * Description : Configures a single channel. + * + *END**************************************************************************/ +static void Psi5_S_ConfigureChannel(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * chCfg) +{ + /* Configure Rx parameters */ + Psi5_S_Hw_ConfigureRx(instanceId, chCfg); + /* Configure Tx mode side */ + Psi5_S_Hw_ConfigureTx(instanceId, chCfg); + if(chCfg->callbackRx != NULL_PTR) + { + /* Configure interrupts */ + Psi5_S_Hw_EnableRxInterrupts(instanceId, chCfg, (boolean)TRUE); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_ConfigureChannels + * Description : Configures all the channels. + * + *END**************************************************************************/ +static void Psi5_S_ConfigureChannels(const Psi5_S_Ip_InstanceType * instance) +{ + /* Configure uart */ + Psi5_S_ConfigureUart(instance->instanceId, instance->uartConfig); +#if (STD_ON == PSI5_S_IP_DMA_IS_USED) + /* Configure DMA */ + Psi5_S_Hw_ConfigureDma(instance->instanceId, instance->dmaConfig); +#endif + /* For each channel configuration */ + for (uint32 chIdx = 0u; chIdx < instance->numOfChannels; chIdx++) + { + const Psi5_S_Ip_ChannelConfigType * chCfg = &(instance->channelConfig[chIdx]); + /* Configure the pulse generator */ + Psi5_S_ConfigureChannel(instance->instanceId, chCfg); + /* Configure the slots */ + Psi5_S_ConfigureSlots(instance->instanceId, chCfg); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_EnableGLInterrupts + * Description : Interrupt enabler + * + *END**************************************************************************/ +static void Psi5_S_Hw_EnableGLInterrupts(const Psi5_S_Ip_InstanceIdType instanceId, + const boolean Enable) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + /* Clear MRU error interrupt flag */ + base->GLSR = PSI5_S_GLSR_MRU_ERR_MASK; + /* Enable MRU error interrupt */ + base->GLCR |= Enable ? PSI5_S_GLCR_MRU_ERR_EN_MASK : 0u; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_EnableRxInterrupts + * Description : Interrupt enabler + * + *END**************************************************************************/ +static void Psi5_S_Hw_EnableRxInterrupts(const Psi5_S_Ip_InstanceIdType instanceId, + const Psi5_S_Ip_ChannelConfigType * chCfg, + const boolean Enable) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[instanceId]; + /* Enable Mailbox interrupts */ + base->IRQ[chCfg->channelId].MBOX_SEL_IRQ |= Enable ? (uint32)((uint32)(PSI5_S_MBOX_SEL_IRQ_MBOX_CH0_SEL_MASK)<<(uint32)(chCfg->channelId)) : (uint32)0u; + /* Clear Error interrupt flag */ + base->ERR_SR_IRQ = PSI5_S_ERR_SR_IRQ_XCRC_ERR_MASK | PSI5_S_ERR_SR_IRQ_CRC_ERR_P_ERR_MASK + | PSI5_S_ERR_SR_IRQ_HD_ERR_MASK | PSI5_S_ERR_SR_IRQ_SCI_P_ERR_MASK + | PSI5_S_ERR_SR_IRQ_SCI_F_ERR_MASK | PSI5_S_ERR_SR_IRQ_SCI_O_ERR_MASK + | PSI5_S_ERR_SR_IRQ_F_WD_ERR_MASK | PSI5_S_ERR_SR_IRQ_R_OVL_ERR_MASK + | PSI5_S_ERR_SR_IRQ_N_ERR_MASK | PSI5_S_ERR_SR_IRQ_R_UVL_ERR_MASK; + /* Enable Error interrupts */ + base->IRQ[0].ERR_SEL_IRQ |= Enable ? (PSI5_S_ERR_SEL_IRQ_XCRC_ERR_SEL_MASK | PSI5_S_ERR_SEL_IRQ_CRC_ERR_SEL_MASK + |PSI5_S_ERR_SEL_IRQ_CRC_ERR_SEL_MASK | PSI5_S_ERR_SEL_IRQ_HD_ERR_SEL_MASK + |PSI5_S_ERR_SEL_IRQ_SCI_P_ERR_SEL_MASK | PSI5_S_ERR_SEL_IRQ_SCI_F_ERR_SEL_MASK + |PSI5_S_ERR_SEL_IRQ_SCI_O_ERR_SEL_MASK | PSI5_S_ERR_SEL_IRQ_F_WD_ERR_SEL_MASK + |PSI5_S_ERR_SEL_IRQ_R_OVL_ERR_SEL_MASK | PSI5_S_ERR_SEL_IRQ_N_ERR_SEL_MASK + |PSI5_S_ERR_SEL_IRQ_R_UVL_ERR_SEL_MASK) : 0u; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Hw_ClearEvents + * Description : Clears all active events + * + *END**************************************************************************/ +static void Psi5_S_Hw_ClearEvents(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[Psi5SInstanceId]; + /* Clear LIN interrupts */ + base->LINIER |= PSI5_S_LINIER_DTIE_MASK | PSI5_S_LINIER_DRIE_MASK + |PSI5_S_LINIER_TOIE_MASK | PSI5_S_LINIER_WUIE_MASK + |PSI5_S_LINIER_BOIE_MASK | PSI5_S_LINIER_FEIE_MASK + |PSI5_S_LINIER_OCIE_MASK | PSI5_S_LINIER_SZIE_MASK; + /* Clear MRU error interrupt flag */ + base->GLSR = PSI5_S_GLSR_MRU_ERR_MASK; + /* Clear Error interrupt flag */ + base->ERR_SR_IRQ = PSI5_S_ERR_SR_IRQ_XCRC_ERR_MASK | PSI5_S_ERR_SR_IRQ_CRC_ERR_P_ERR_MASK + | PSI5_S_ERR_SR_IRQ_HD_ERR_MASK | PSI5_S_ERR_SR_IRQ_SCI_P_ERR_MASK + | PSI5_S_ERR_SR_IRQ_SCI_F_ERR_MASK | PSI5_S_ERR_SR_IRQ_SCI_O_ERR_MASK + | PSI5_S_ERR_SR_IRQ_F_WD_ERR_MASK | PSI5_S_ERR_SR_IRQ_R_OVL_ERR_MASK + | PSI5_S_ERR_SR_IRQ_N_ERR_MASK | PSI5_S_ERR_SR_IRQ_R_UVL_ERR_MASK; + if(Psi5SChannelId == 0u) + { + /* Clear read flag */ + base->CH0_MBOX_SR = PSI5_S_CH0_MBOX_SR_F0_READ_MASK | PSI5_S_CH0_MBOX_SR_F1_READ_MASK; + /* Clear error flag */ + base->CH0_MBOX_SR = PSI5_S_CH0_MBOX_SR_F0_ERR_MASK | PSI5_S_CH0_MBOX_SR_F1_ERR_MASK; + /* Clear overwrite flag */ + base->CH0_MBOX_SR = PSI5_S_CH0_MBOX_SR_F0_OV_MASK | PSI5_S_CH0_MBOX_SR_F1_OV_MASK; + } + else + { + /* Clear read flag */ + base->CH[(uint8)(Psi5SChannelId-1u)].MBOX_SR = PSI5_S_MBOX_SR_F0_READ_MASK | PSI5_S_MBOX_SR_F1_READ_MASK + | PSI5_S_MBOX_SR_F2_READ_MASK | PSI5_S_MBOX_SR_F3_READ_MASK + | PSI5_S_MBOX_SR_F4_READ_MASK | PSI5_S_MBOX_SR_F5_READ_MASK; + /* clear error flag */ + base->CH[(uint8)(Psi5SChannelId-1u)].MBOX_SR = PSI5_S_MBOX_SR_F0_ERR_MASK | PSI5_S_MBOX_SR_F1_ERR_MASK + | PSI5_S_MBOX_SR_F2_ERR_MASK | PSI5_S_MBOX_SR_F3_ERR_MASK + | PSI5_S_MBOX_SR_F4_ERR_MASK | PSI5_S_MBOX_SR_F5_ERR_MASK; + /* Clear overwrite flag */ + base->CH[(uint8)(Psi5SChannelId-1u)].MBOX_SR = PSI5_S_MBOX_SR_F0_OV_MASK | PSI5_S_MBOX_SR_F1_OV_MASK + | PSI5_S_MBOX_SR_F2_OV_MASK | PSI5_S_MBOX_SR_F3_OV_MASK + | PSI5_S_MBOX_SR_F4_OV_MASK | PSI5_S_MBOX_SR_F5_OV_MASK; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_IRQ_Handler_Rx + * Description : Gets called from the low level handler + * with instance and channel as parameter. + * + *END**************************************************************************/ +void Psi5_S_Ip_IRQ_Handler_Rx(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId) +{ + Psi5_S_Ip_Psi5SFrameType Psi5SFramePtr; + + Psi5_S_Hw_GetPsi5SEvents(Psi5SInstanceId, Psi5SChannelId, &Psi5SFramePtr); + if(TRUE == Psi5_S_DriverInitialized) + { + const uint8 arrayIndex = Psi5_S_UsedConfig->instancesConfig[Psi5SInstanceId].chHwIdToIndexArrayConfig[Psi5SChannelId]; + const Psi5_S_Ip_ChannelConfigType * chCfg = &(Psi5_S_UsedConfig->instancesConfig[Psi5SInstanceId].channelConfig[arrayIndex]); + if(NULL_PTR != chCfg->callbackRx) + { + chCfg->callbackRx(Psi5SInstanceId, Psi5SFramePtr); + } + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_IRQ_Handler_Tx + * Description : Gets called from the low level handler + * with instance and channel as parameter. + * + *END**************************************************************************/ +void Psi5_S_Ip_IRQ_Handler_Tx(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId) +{ + Psi5_S_Ip_EventType Events; + /*Clear all values*/ + Events.Psi5S_UartRX = FALSE; + Events.Psi5S_UartTX = FALSE; + Events.Psi5S_UartERR = FALSE; + Events.Psi5S_GlobalTrigger = FALSE; + Events.Psi5S_MessageReceived = FALSE; + Events.Psi5S_MessageOverwrite = FALSE; + Events.Psi5S_MessageErrorsPresent = FALSE; + Events.Psi5S_TxDataOverwrite = FALSE; + Events.Psi5S_ReadyToTransmit = FALSE; + + Psi5_S_Hw_GetEvents(Psi5SInstanceId, Psi5SChannelId, &Events); + if(TRUE == Psi5_S_DriverInitialized) + { + const uint8 arrayIndex = Psi5_S_UsedConfig->instancesConfig[Psi5SInstanceId].chHwIdToIndexArrayConfig[Psi5SChannelId]; + const Psi5_S_Ip_ChannelConfigType * chCfg = &(Psi5_S_UsedConfig->instancesConfig[Psi5SInstanceId].channelConfig[arrayIndex]); + if(NULL_PTR != chCfg->callbackTx) + { + chCfg->callbackTx(Events); + } + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_IRQ_Global_Handler + * Description : Gets called from the low level handler + * with instance and channel as parameter. + * + *END**************************************************************************/ +void Psi5_S_Ip_IRQ_Global_Handler(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId) +{ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[Psi5SInstanceId]; + Psi5_S_Ip_EventType Events; + /* Clear all values */ + Events.Psi5S_UartRX = FALSE; + Events.Psi5S_UartTX = FALSE; + Events.Psi5S_UartERR = FALSE; + Events.Psi5S_GlobalTrigger = FALSE; + Events.Psi5S_MessageReceived = FALSE; + Events.Psi5S_MessageOverwrite = FALSE; + Events.Psi5S_MessageErrorsPresent = FALSE; + Events.Psi5S_TxDataOverwrite = FALSE; + Events.Psi5S_ReadyToTransmit = FALSE; + + /* Call Psi5_S_Hw_GetGLEvents(Psi5SInstanceId, &Events) */ + if ((base->GLSR & PSI5_S_GLSR_DIRCMD_RDY_MASK) != 0u) + { + Events.Psi5S_GlobalTrigger = TRUE; + base->GLCR&=~PSI5_S_GLCR_IE_DIRCMD_RDY_MASK; + } + if(TRUE == Psi5_S_DriverInitialized) + { + const Psi5_S_Ip_InstanceType * chCfg = &(Psi5_S_UsedConfig->instancesConfig[Psi5SInstanceId]); + if(NULL_PTR != chCfg->callback) + { + chCfg->callback(Events); + } + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_GetPsi5SFrame + * Description : Returns the last received PSI5 frame. + * + * Implements : Psi5_S_Ip_GetPsi5SFrame_Activity + *END**************************************************************************/ +Std_ReturnType Psi5_S_Ip_GetPsi5SFrame(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + Psi5_S_Ip_Psi5SFrameType * Psi5SFramePtr) +{ + Std_ReturnType ret; + ret = Psi5_S_Hw_GetPsi5SFrame(Psi5SInstanceId, Psi5SChannelId, Psi5SFramePtr); + return ret; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_Transmit + * Description : Transmits a frame (standard or custom). + * + * Implements : Psi5_S_Ip_Transmit_Activity + *END**************************************************************************/ +Std_ReturnType Psi5_S_Ip_Transmit(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + const uint64 Psi5SData) +{ + Std_ReturnType ret; + const uint8 arrayIndex = Psi5_S_UsedConfig->instancesConfig[Psi5SInstanceId].chHwIdToIndexArrayConfig[Psi5SChannelId]; + const Psi5_S_Ip_ChannelConfigType * config = &(Psi5_S_UsedConfig->instancesConfig[Psi5SInstanceId].channelConfig[arrayIndex]); + /* Only if enabled */ + if (config->txConfig != NULL_PTR) + { + /* Check if ready for Tx */ + if (!Psi5_S_Hw_IsDataRegisterReady(Psi5SInstanceId, Psi5SChannelId)) + { + ret = (Std_ReturnType)E_NOT_OK; + } + else + { + /* Write and trigger */ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[Psi5SInstanceId]; + /* Enter critical region */ + /* SchM_Enter_Psi5S_PSI5_EXCLUSIVE_AREA_00 */ + base->CH[(uint8)(Psi5SChannelId-1u)].E2SCR |= PSI5_S_E2SCR_DDSR_CLR_MASK; + base->CH[(uint8)(Psi5SChannelId-1u)].DDSR_L = (uint32)(Psi5SData & PSI5_S_DDSR_L_DDSR_L2_MASK); + base->CH[(uint8)(Psi5SChannelId-1u)].E2SSR |= PSI5_S_E2SSR_DDSR_RDY_MASK; + if (config->callbackTx != NULL_PTR) + { + base->CH[(uint8)(Psi5SChannelId-1u)].E2SCR |= PSI5_S_E2SCR_DDSR_RDY_IE_MASK | PSI5_S_E2SCR_CMDTR_NWRT_IE_MASK; + } + /* Exit critical region*/ + /* SchM_Exit_Psi5S_PSI5_EXCLUSIVE_AREA_00 */ + ret = (Std_ReturnType)E_OK; + } + } + else + { + ret = (Std_ReturnType)E_NOT_OK; + } + return ret; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_GetTransmissionStatus + * Description : Returns the status of the transmission part of the driver. + * + * Implements : Psi5_S_Ip_GetTransmissionStatus_Activity + *END**************************************************************************/ +boolean Psi5_S_Ip_GetTransmissionStatus(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId) +{ + return Psi5_S_Hw_IsDataRegisterReady(Psi5SInstanceId, Psi5SChannelId); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_SendDirectCommand + * Description : Direct writing for the special Transceiver. + * + * Implements : Psi5_S_Ip_SendDirectCommand_Activity + *END**************************************************************************/ +Std_ReturnType Psi5_S_Ip_SendDirectCommand(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, + const uint32 Psi5SDirCmd, + const uint8 Psi5SDirCmdLen) +{ + Std_ReturnType ret; + const Psi5_S_Ip_InstanceType * config = &(Psi5_S_UsedConfig->instancesConfig[Psi5SInstanceId]); + /* Only if enabled */ + if (((Psi5SDirCmdLen == 1U) || (Psi5SDirCmdLen == 2U) || (Psi5SDirCmdLen == 4U))) + { + /* Check if ready for Tx */ + if (!Psi5_S_Hw_IsDirectCommandRegisterReady(Psi5SInstanceId)) + { + ret = (Std_ReturnType)E_NOT_OK; + } + else + { + /* Write and trigger */ + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[Psi5SInstanceId]; + /* Enter critical region*/ + /* SchM_Enter_Psi5S_PSI5_EXCLUSIVE_AREA_00 */ + /* Provide length of the Direct Command that is transferred to the UART Tx line */ + /* 00: 1 byte */ + /* 01: 2 bytes */ + /* 10-11: 4 bytes */ + /* Clear first */ + base->GLCR &= ~PSI5_S_GLCR_DIRCMD_LEN_MASK; + /* Set length */ + base->GLCR |= PSI5_S_GLCR_DIRCMD_LEN((uint32)((uint32)Psi5SDirCmdLen - (uint32)1u)); + base->DIRCMD = (uint32)(Psi5SDirCmd); + base->GLSR |= PSI5_S_GLSR_DIRCMD_RDY_MASK; + if (config->callback != NULL_PTR) + { + /* IE_DIRCMD_RDY interrupt */ + base->GLCR |= PSI5_S_GLCR_IE_DIRCMD_RDY_MASK; + } + /* Exit critical region*/ + /* SchM_Exit_Psi5S_PSI5_EXCLUSIVE_AREA_00 */ + ret = (Std_ReturnType)E_OK; + } + } + else + { + ret = (Std_ReturnType)E_NOT_OK; + } + return ret; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_SetGlobalSync + * Description : Sets the global Pulse Generator state. + * + * Implements : Psi5_S_Ip_SetGlobalSync_Activity + *END**************************************************************************/ +Std_ReturnType Psi5_S_Ip_SetGlobalSync(const uint8 Psi5SInstanceId, + const boolean Psi5SState) +{ + Std_ReturnType ret = (Std_ReturnType)E_NOT_OK; + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[Psi5SInstanceId]; + uint8 ChIndex; + for (ChIndex = 0u; ChIndex < 7u; ChIndex++) + { + if ((base->CH[ChIndex].E2SCR & PSI5_S_E2SCR_GL_TRIG_SEL_MASK) != 0u) + { + /* Enter critical region */ + /* SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_03 */ + base->GLCR = (base->GLCR & ~PSI5_S_GLCR_GL_DDSR_TRIG_MASK) | PSI5_S_GLCR_GL_DDSR_TRIG(((FALSE == Psi5SState) ? 0U : 1U)); + /* Exit critical region*/ + /* SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_03 */ + ret = (Std_ReturnType)E_OK; + } + } + return ret; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_SetChannelSync + * Description : Sets the local (Psi5SChannelId) Pulse Generator state. + * + * Implements : Psi5_S_Ip_SetChannelSync_Activity + *END**************************************************************************/ +Std_ReturnType Psi5_S_Ip_SetChannelSync(const Psi5_S_Ip_InstanceIdType Psi5SInstanceId, + const Psi5_S_Ip_HwChannelIdType Psi5SChannelId, + const boolean Psi5SState) +{ + Std_ReturnType ret = (Std_ReturnType)E_NOT_OK; + PSI5_S_MemMapPtr base = s_psi5BaseAddresses[Psi5SInstanceId]; + if (Psi5SChannelId > 0u) + { + /* Enter critical region */ + /* SchM_Enter_Psi5S_PSI5_EXCLUSIVE_AREA_04 */ + base->CH[(uint8)(Psi5SChannelId-1u)].E2SCR = Psi5SState ? (base->CH[(uint8)(Psi5SChannelId-1u)].E2SCR | PSI5_S_E2SCR_CH_TRIG_MASK) : (base->CH[(uint8)(Psi5SChannelId-1u)].E2SCR & ~PSI5_S_E2SCR_CH_TRIG_MASK); + + /* Exit critical region*/ + /* SchM_Exit_Psi5S_PSI5_EXCLUSIVE_AREA_04 */ + ret = (Std_ReturnType)E_OK; + } + return ret; +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_Init + * Description : Initializes the driver for a given peripheral + * according to the given configuration structure. + * + * Implements : Psi5_S_Ip_Init_Activity + *END**************************************************************************/ +void Psi5_S_Ip_Init(const Psi5_S_Ip_ConfigType * configPtr) +{ + Psi5_S_UsedConfig = configPtr; + Psi5_S_DriverInitialized = (boolean) TRUE; + + for(uint32 instanceCnt = 0; instanceCnt < Psi5_S_UsedConfig->numOfInstances; instanceCnt++) + { + const Psi5_S_Ip_InstanceType * cfgInstance = &(Psi5_S_UsedConfig->instancesConfig[instanceCnt]); + /* Ente uart mode */ + Psi5_S_EnterUartMode(cfgInstance); + /* Configure uart mode*/ + Psi5_S_ConfigureUartMode(cfgInstance->instanceId, cfgInstance->uartConfig); + /* Enter configuration mode */ + Psi5_S_EnterConfigMode(cfgInstance); + /* Configure channels */ + Psi5_S_ConfigureChannels(cfgInstance); + /* Enter normal mode */ + Psi5_S_EnterNormalMode(cfgInstance); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_Ip_DeInit + * Description : Stops the driver and resets the internal states. + * + * Implements : Psi5_S_Ip_DeInit_Activity + *END**************************************************************************/ +void Psi5_S_Ip_DeInit(void) +{ + Psi5_S_DriverInitialized = (boolean) FALSE; + for(uint32 instanceCnt = 0u; instanceCnt < Psi5_S_UsedConfig->numOfInstances; instanceCnt++) + { + /* Put all channels in configuration mode */ + for (uint8 chIdx = 0u; chIdx < Psi5_S_UsedConfig->instancesConfig[instanceCnt].numOfChannels; chIdx++) + { + const Psi5_S_Ip_ChannelConfigType * chCfg = &(Psi5_S_UsedConfig->instancesConfig[instanceCnt].channelConfig[chIdx]); + /* Enter configuration mode */ + Psi5_S_Hw_EnterConfigMode(Psi5_S_UsedConfig->instancesConfig[instanceCnt].instanceId); + if(Psi5_S_UsedConfig->instancesConfig[instanceCnt].callback != NULL_PTR) + { + /* Disable interrupts */ + Psi5_S_Hw_EnableGLInterrupts(Psi5_S_UsedConfig->instancesConfig[instanceCnt].instanceId, (boolean)FALSE); + } + if(chCfg->callbackRx != NULL_PTR) + { + /* Disable interrupts */ + Psi5_S_Hw_EnableRxInterrupts(Psi5_S_UsedConfig->instancesConfig[instanceCnt].instanceId, chCfg, (boolean)FALSE); + } + Psi5_S_Hw_ClearEvents(Psi5_S_UsedConfig->instancesConfig[instanceCnt].instanceId, chIdx); + } + /* Clear all registers */ + Psi5_S_Hw_ResetRegisters(Psi5_S_UsedConfig->instancesConfig[instanceCnt].instanceId); + /* Disable the instance */ + Psi5_S_Hw_InstanceDisable(Psi5_S_UsedConfig->instancesConfig[instanceCnt].instanceId); + } + Psi5_S_UsedConfig = NULL_PTR; +} + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/s32/drivers/s32ze/Psi5_S/src/Psi5_S_Ip_Irq.c b/s32/drivers/s32ze/Psi5_S/src/Psi5_S_Ip_Irq.c new file mode 100644 index 000000000..acbcca9e1 --- /dev/null +++ b/s32/drivers/s32ze/Psi5_S/src/Psi5_S_Ip_Irq.c @@ -0,0 +1,463 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file Psi5_S_Ip_Irq.c +* +* @addtogroup PSI5_S_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Psi5_S_Ip.h" +#include "Psi5_S_Ip_Irq.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_S_IP_IRQ_VENDOR_ID_C 43 +#define PSI5_S_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C 4 +#define PSI5_S_IP_IRQ_AR_RELEASE_MINOR_VERSION_C 7 +#define PSI5_S_IP_IRQ_AR_RELEASE_REVISION_VERSION_C 0 +#define PSI5_S_IP_IRQ_SW_MAJOR_VERSION_C 2 +#define PSI5_S_IP_IRQ_SW_MINOR_VERSION_C 0 +#define PSI5_S_IP_IRQ_SW_PATCH_VERSION_C 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + +/* Checks against Psi5_S_Ip.h */ +#if (PSI5_S_IP_IRQ_VENDOR_ID_C != PSI5_S_IP_VENDOR_ID) + #error "Psi5_S_Ip_Irq.c and Psi5_S_Ip.h have different vendor ids" +#endif +#if ((PSI5_S_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != PSI5_S_IP_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != PSI5_S_IP_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != PSI5_S_IP_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip_Irq.c and Psi5_S_Ip.h are different" +#endif +#if ((PSI5_S_IP_IRQ_SW_MAJOR_VERSION_C != PSI5_S_IP_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_IRQ_SW_MINOR_VERSION_C != PSI5_S_IP_SW_MINOR_VERSION) || \ + (PSI5_S_IP_IRQ_SW_PATCH_VERSION_C != PSI5_S_IP_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_S_Ip_Irq.c and Psi5_S_Ip.h are different" +#endif + +/* Checks against Psi5_S_Ip_Irq.h */ +#if (PSI5_S_IP_IRQ_VENDOR_ID_C != PSI5_S_IP_IRQ_VENDOR_ID) + #error "Psi5_S_Ip_Irq.c and Psi5_S_Ip_Irq.h have different vendor ids" +#endif +#if ((PSI5_S_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != PSI5_S_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != PSI5_S_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != PSI5_S_IP_IRQ_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AUTOSAR Version Numbers of Psi5_S_Ip_Irq.c and Psi5_S_Ip_Irq.h are different" +#endif +#if ((PSI5_S_IP_IRQ_SW_MAJOR_VERSION_C != PSI5_S_IP_IRQ_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_IRQ_SW_MINOR_VERSION_C != PSI5_S_IP_IRQ_SW_MINOR_VERSION) || \ + (PSI5_S_IP_IRQ_SW_PATCH_VERSION_C != PSI5_S_IP_IRQ_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_S_Ip_Irq.c and Psi5_S_Ip_Irq.h are different" +#endif + +/*================================================================================================== +* LOCAL MACROS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) +==================================================================================================*/ + +/*================================================================================================== +* LOCAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL VARIABLES +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef PSI5_S_IP_ENABLE_GLOBAL_INTERRUPTS_PSI5_S_INSTANCE0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_IRQ_Global_Handle_0 + * Description : Must be mapped to the generic interrupt of global. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Global_Handle_PSI5S_0) +{ + Psi5_S_Ip_IRQ_Global_Handler((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH0 + * Description : Must be mapped to the generic interrupt of instance 0 channel 0. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH0) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH0); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH1 + * Description : Must be mapped to the generic interrupt of instance 0 channel 1. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH1) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH1 + * Description : Must be mapped to the generic interrupt of instance 0 channel 1. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH1) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, PSI5_S_0_CH1); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH2 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH2 + * Description : Must be mapped to the generic interrupt of instance 0 channel 2. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH2) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH2); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH2 + * Description : Must be mapped to the generic interrupt of instance 0 channel 2. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH2) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH2); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH3 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH3 + * Description : Must be mapped to the generic interrupt of instance 0 channel 3. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH3) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH3); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH3 + * Description : Must be mapped to the generic interrupt of instance 0 channel 3. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH3) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH3); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH4 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH4 + * Description : Must be mapped to the generic interrupt of instance 0 channel 4. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH4) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH4); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH4 + * Description : Must be mapped to the generic interrupt of instance 0 channel 4. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH4) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH4); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH5 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH5 + * Description : Must be mapped to the generic interrupt of instance 0 channel 5. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH5) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH5); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH5 + * Description : Must be mapped to the generic interrupt of instance 0 channel 5. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH5) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH5); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH6 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH6 + * Description : Must be mapped to the generic interrupt of instance 0 channel 6. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH6) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH6); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH6 + * Description : Must be mapped to the generic interrupt of instance 0 channel 6. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH6) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH6); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH7 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_0_CH7 + * Description : Must be mapped to the generic interrupt of instance 0 channel 7. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_0_CH7) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH7); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_0_CH7 + * Description : Must be mapped to the generic interrupt of instance 0 channel 7. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_0_CH7) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE0, (Psi5_S_Ip_HwChannelIdType)PSI5_S_0_CH7); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_GLOBAL_INTERRUPTS_PSI5_S_INSTANCE1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5_S_IRQ_Global_Handle_1 + * Description : Must be mapped to the generic interrupt of global. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Global_Handle_PSI5S_1) +{ + Psi5_S_Ip_IRQ_Global_Handler((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH0 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH0 + * Description : Must be mapped to the generic interrupt of instance 1 channel 0. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH0) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH0); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH1 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH1 + * Description : Must be mapped to the generic interrupt of instance 1 channel 1. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH1) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH1 + * Description : Must be mapped to the generic interrupt of instance 1 channel 1. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH1) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH1); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH2 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH2 + * Description : Must be mapped to the generic interrupt of instance 1 channel 2. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH2) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH2); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH2 + * Description : Must be mapped to the generic interrupt of instance 1 channel 2. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH2) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH2); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH3 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH3 + * Description : Must be mapped to the generic interrupt of instance 1 channel 3. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH3) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH2); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH3 + * Description : Must be mapped to the generic interrupt of instance 1 channel 3. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH3) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH2); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH4 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH4 + * Description : Must be mapped to the generic interrupt of instance 1 channel 4. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH4) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH4); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH4 + * Description : Must be mapped to the generic interrupt of instance 1 channel 4. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH4) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH4); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH5 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH5 + * Description : Must be mapped to the generic interrupt of instance 1 channel 5. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH5) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH5); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH5 + * Description : Must be mapped to the generic interrupt of instance 1 channel 5. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH5) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH5); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH6 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH6 + * Description : Must be mapped to the generic interrupt of instance 1 channel 6. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH6) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH6); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH6 + * Description : Must be mapped to the generic interrupt of instance 1 channel 6. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH6) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH6); +} +#endif + +#ifdef PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_1_CH7 +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Rx_PSI5S_1_CH7 + * Description : Must be mapped to the generic interrupt of instance 1 channel 7. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Rx_PSI5S_1_CH7) +{ + Psi5_S_Ip_IRQ_Handler_Rx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH7); +} + +/*FUNCTION********************************************************************** + * + * Function Name : Psi5S_IRQ_Handle_Tx_PSI5S_1_CH7 + * Description : Must be mapped to the generic interrupt of instance 1 channel 7. + *END**************************************************************************/ +ISR(Psi5S_IRQ_Handle_Tx_PSI5S_1_CH7) +{ + Psi5_S_Ip_IRQ_Handler_Tx((Psi5_S_Ip_InstanceIdType)PSI5_S_INSTANCE1, (Psi5_S_Ip_HwChannelIdType)PSI5_S_1_CH7); +} +#endif + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/s32/drivers/s32ze/Rte/CMakeLists.txt b/s32/drivers/s32ze/Rte/CMakeLists.txt index 7ed99c705..81bebf8c3 100644 --- a/s32/drivers/s32ze/Rte/CMakeLists.txt +++ b/s32/drivers/s32ze/Rte/CMakeLists.txt @@ -10,3 +10,5 @@ zephyr_library_sources_ifdef(CONFIG_UART_NXP_S32_LINFLEXD src/SchM_Uart.c) zephyr_library_sources_ifdef(CONFIG_CAN_NXP_S32_CANXL src/SchM_Can_43_CANEXCEL.c) zephyr_library_sources_ifdef(CONFIG_ETH_NXP_S32_NETC src/SchM_Eth_43_NETC.c) zephyr_library_sources_ifdef(CONFIG_ETH_NXP_S32_NETC src/SchM_EthSwt_43_NETC.c) +zephyr_library_sources_ifdef(CONFIG_PSI5_NXP_S32 src/SchM_Psi5.c) +zephyr_library_sources_ifdef(CONFIG_PSI5_S_NXP_S32 src/SchM_Psi5.c) diff --git a/s32/drivers/s32ze/Rte/include/SchM_Psi5.h b/s32/drivers/s32ze/Rte/include/SchM_Psi5.h new file mode 100644 index 000000000..ac1094a6d --- /dev/null +++ b/s32/drivers/s32ze/Rte/include/SchM_Psi5.h @@ -0,0 +1,123 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file SchM_Psi5.h +* @version 2.0.0 +* +* @brief AUTOSAR Rte - module interface +* @details This file contains the functions prototypes and data types of the AUTOSAR Rte. +* This file contains sample code only. It is not part of the production code deliverables. +* +* @addtogroup RTE_MODULE +* @{ +*/ + +#ifndef SCHM_PSI5_H +#define SCHM_PSI5_H + +#ifdef __cplusplus +extern "C" { +#endif +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define SCHM_PSI5_AR_RELEASE_MAJOR_VERSION 4 +#define SCHM_PSI5_AR_RELEASE_MINOR_VERSION 7 +#define SCHM_PSI5_AR_RELEASE_REVISION_VERSION 0 +#define SCHM_PSI5_SW_MAJOR_VERSION 2 +#define SCHM_PSI5_SW_MINOR_VERSION 0 +#define SCHM_PSI5_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +#define NUMBER_OF_CORES (uint8)(14U) + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ +#define RTE_START_SEC_CODE +#include "Rte_MemMap.h" + +#ifdef MCAL_TESTING_ENVIRONMENT +/** +@brief This function checks that all entered exclusive areas were also exited. +@details This function checks that all entered exclusive areas were also exited. The check + is done by verifying that all reentry_guard_* static variables are back to the + zero value. + +@param[in] void No input parameters +@return void This function does not return a value. Test asserts are used instead. + +@pre None +@post None + +@remarks Covers +@remarks Implements +*/ +void SchM_Check_psi5(void); +#endif /*MCAL_TESTING_ENVIRONMENT*/ + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_00(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_00(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_01(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_01(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_02(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_02(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_03(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_03(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_04(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_04(void); + +extern void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_05(void); +extern void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_05(void); + + + + +#define RTE_STOP_SEC_CODE +#include "Rte_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* SCHM_PSI5_H */ diff --git a/s32/drivers/s32ze/Rte/src/SchM_Psi5.c b/s32/drivers/s32ze/Rte/src/SchM_Psi5.c new file mode 100644 index 000000000..9c25e1cae --- /dev/null +++ b/s32/drivers/s32ze/Rte/src/SchM_Psi5.c @@ -0,0 +1,654 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file SchM_Psi5.c +* @version 2.0.0 +* +* @brief AUTOSAR Rte - module implementation +* @details This module implements stubs for the AUTOSAR Rte +* This file contains sample code only. It is not part of the production code deliverables. +* +* @addtogroup RTE_MODULE +* @{ +*/ + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Std_Types.h" +#include "Mcal.h" +#include "OsIf.h" +#include "SchM_Psi5.h" +#ifdef MCAL_TESTING_ENVIRONMENT +#include "EUnit.h" /* EUnit Test Suite */ +#endif + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define SCHM_PSI5_AR_RELEASE_MAJOR_VERSION_C 4 +#define SCHM_PSI5_AR_RELEASE_MINOR_VERSION_C 7 +#define SCHM_PSI5_AR_RELEASE_REVISION_VERSION_C 0 +#define SCHM_PSI5_SW_MAJOR_VERSION_C 2 +#define SCHM_PSI5_SW_MINOR_VERSION_C 0 +#define SCHM_PSI5_SW_PATCH_VERSION_C 0 + +/*================================================================================================== +* LOCAL CONSTANTS +==================================================================================================*/ +#ifdef MCAL_PLATFORM_ARM + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */ + #else + #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */ + #else + #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */ + #endif + #endif +#else + #ifdef MCAL_PLATFORM_S12 + #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */ + #else + #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */ + #endif +#endif +/*================================================================================================== +* LOCAL MACROS +==================================================================================================*/ +#ifdef MCAL_PLATFORM_ARM + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK)) + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK)) + #else + #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0) + #endif +#else + #ifdef MCAL_PLATFORM_S12 + #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0) + #else + #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK)) + #endif +#endif + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + +/*================================================================================================== +* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) +==================================================================================================*/ + + +/*================================================================================================== +* LOCAL VARIABLES +==================================================================================================*/ +#define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE +#include "Rte_MemMap.h" +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_00) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_00[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_00[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_01) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_01[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_01[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_02) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_02[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_02[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_03) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_03[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_03[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_04) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_04[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_04[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(msr_PSI5_EXCLUSIVE_AREA_05) static volatile uint32 msr_PSI5_EXCLUSIVE_AREA_05[NUMBER_OF_CORES]; +VAR_SEC_NOCACHE(reentry_guard_PSI5_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_PSI5_EXCLUSIVE_AREA_05[NUMBER_OF_CORES]; + +#define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE +#include "Rte_MemMap.h" +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + + +/*================================================================================================== +* GLOBAL VARIABLES +==================================================================================================*/ + +/*================================================================================================== +* LOCAL FUNCTION PROTOTYPES +==================================================================================================*/ + +#ifndef _COSMIC_C_S32ZE_ +/*================================================================================================*/ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void); +#endif /*ifndef _COSMIC_C_S32ZE_*/ +/*================================================================================================== +* LOCAL FUNCTIONS +==================================================================================================*/ +#define RTE_START_SEC_CODE +#include "Rte_MemMap.h" + +#if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_)) +/*================================================================================================*/ +/** +* @brief This macro returns the MSR register value (32 bits). +* @details This macro function implementation returns the MSR register value in r3 (32 bits). +* +* @pre None +* @post None +* +*/ +#ifdef MCAL_PLATFORM_ARM +#if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + mrs x0, S3_3_c4_c2_1 +} +#elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + mrs r0, CPSR +} +#else +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ +#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + mrs r0, BASEPRI +#else + mrs r0, PRIMASK +#endif +} +#endif +#else +#ifdef MCAL_PLATFORM_S12 +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + tfr ccr, d6 +} +#else +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + mfmsr r3 +} +#endif +#endif +#endif /*#ifdef GHS||CW*/ + +#ifdef _DIABDATA_C_S32ZE_ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +#ifdef MCAL_PLATFORM_ARM +uint32 Psi5_schm_read_msr(void) +{ + register uint32 reg_tmp; + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) ); + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) ); + #else + #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) ); + #else + __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) ); + #endif + #endif + return (uint32)reg_tmp; +} +#else +ASM_KEYWORD uint32 Psi5_schm_read_msr(void) +{ + mfmsr r3 +} +#endif /* MCAL_PLATFORM_ARM */ + +#endif /* _DIABDATA_C_S32ZE_*/ + +#ifdef _COSMIC_C_S32ZE_ +/*================================================================================================*/ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ + +#ifdef MCAL_PLATFORM_S12 + #define Psi5_schm_read_msr() ASM_KEYWORD("tfr ccr, d6") +#else + #define Psi5_schm_read_msr() ASM_KEYWORD("mfmsr r3") +#endif + +#endif /*Cosmic compiler only*/ + + +#ifdef _HITECH_C_S32ZE_ +/*================================================================================================*/ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void) +{ + uint32 result; + __asm volatile("mfmsr %0" : "=r" (result) :); + return result; +} + +#endif /*HighTec compiler only*/ + /*================================================================================================*/ +#ifdef _GCC_C_S32ZE_ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void) +{ + register uint32 reg_tmp; + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) ); + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) ); + #else + #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) ); + #else + __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) ); + #endif + #endif + return (uint32)reg_tmp; +} +#endif /* _GCC_C_S32ZE_*/ +/*================================================================================================*/ + +#ifdef _ARM_DS5_C_S32ZE_ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void) +{ + register uint32 reg_tmp; + #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64) + __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) ); + #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH) + __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) ); + #else + #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) ); + #else + __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) ); + #endif + #endif + return (uint32)reg_tmp; +} +#endif /* _ARM_DS5_C_S32ZE_ */ + +#ifdef _IAR_C_S32ZE_ +/** +* @brief This function returns the MSR register value (32 bits). +* @details This function returns the MSR register value (32 bits). +* +* @param[in] void No input parameters +* @return uint32 msr This function returns the MSR register value (32 bits). +* +* @pre None +* @post None +* +*/ +uint32 Psi5_schm_read_msr(void) +{ + register uint32 reg_tmp; + +#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS)) + __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) ); +#else + __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) ); +#endif + + return (uint32)reg_tmp; +} +#endif /* _IAR_C_S32ZE_ */ + +#define RTE_STOP_SEC_CODE +#include "Rte_MemMap.h" + +/*================================================================================================== +* GLOBAL FUNCTIONS +==================================================================================================*/ +#define RTE_START_SEC_CODE +#include "Rte_MemMap.h" + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_00(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_00[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_00(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_01(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_01[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_01(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_02(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_02[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_02(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_03(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_03[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_03(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_04(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_04[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_04(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + +void SchM_Enter_Psi5_PSI5_EXCLUSIVE_AREA_05(void) +{ + uint32 msr; + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + if(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId]) + { +#if (defined MCAL_ENABLE_USER_MODE_SUPPORT) + msr = OsIf_Trusted_Call_Return(Psi5_schm_read_msr); +#else + msr = Psi5_schm_read_msr(); /*read MSR (to store interrupts state)*/ +#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */ + if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/ + { + OsIf_SuspendAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } + msr_PSI5_EXCLUSIVE_AREA_05[u32CoreId] = msr; + } + reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId]++; +} + +void SchM_Exit_Psi5_PSI5_EXCLUSIVE_AREA_05(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId]--; + if ((ISR_ON(msr_PSI5_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/ + { + OsIf_ResumeAllInterrupts(); +#ifdef _ARM_DS5_C_S32ZE_ + ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/ +#endif + } +} + + +#ifdef MCAL_TESTING_ENVIRONMENT +/** +@brief This function checks that all entered exclusive areas were also exited. +@details This function checks that all entered exclusive areas were also exited. The check + is done by verifying that all reentry_guard_* static variables are back to the + zero value. + +@param[in] void No input parameters +@return void This function does not return a value. Test asserts are used instead. + +@pre None +@post None + +@remarks Covers +@remarks Implements +*/ +void SchM_Check_psi5(void) +{ + uint32 u32CoreId = (uint32)OsIf_GetCoreID(); + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_00 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_01 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_02 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_03 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_04 for the next test in the suite*/ + + EU_ASSERT(0UL == reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId]); + reentry_guard_PSI5_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_PSI5_EXCLUSIVE_AREA_05 for the next test in the suite*/ + + +} +#endif /*MCAL_TESTING_ENVIRONMENT*/ + +#define RTE_STOP_SEC_CODE +#include "Rte_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ \ No newline at end of file diff --git a/s32/soc/s32z270/include/Psi5_Ip_Cfg.h b/s32/soc/s32z270/include/Psi5_Ip_Cfg.h new file mode 100644 index 000000000..657c71e37 --- /dev/null +++ b/s32/soc/s32z270/include/Psi5_Ip_Cfg.h @@ -0,0 +1,193 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_CFG_H +#define PSI5_IP_CFG_H + +/** +* @file Psi5_Ip_Cfg.h +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C"{ +#endif +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Mcal.h" + +#include "Psi5_Ip_Init_PBcfg.h" + +#include "Psi5_Ip_Types.h" +#include "Psi5_Ip_Cfg_Defines.h" +#if (STD_ON == PSI5_IP_DMA_IS_USED) +#include "CDD_Mcl.h" +#endif +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_CFG_VENDOR_ID 43 +#define PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_CFG_SW_MAJOR_VERSION 2 +#define PSI5_IP_CFG_SW_MINOR_VERSION 0 +#define PSI5_IP_CFG_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Check if Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h header file are of the same vendor */ +#if (PSI5_IP_CFG_VENDOR_ID != PSI5_IP_INIT_PBCFG_VENDOR_ID) + #error "Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h have different vendor ids" +#endif +/* Check if Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h header file are of the same Autosar version */ +#if ((PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION != PSI5_IP_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION != PSI5_IP_INIT_PBCFG_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION != PSI5_IP_INIT_PBCFG_AR_RELEASE_REVISION_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h are different" +#endif +/* Check if Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h header file are of the same software version */ +#if ((PSI5_IP_CFG_SW_MAJOR_VERSION != PSI5_IP_INIT_PBCFG_SW_MAJOR_VERSION) || \ + (PSI5_IP_CFG_SW_MINOR_VERSION != PSI5_IP_INIT_PBCFG_SW_MINOR_VERSION) || \ + (PSI5_IP_CFG_SW_PATCH_VERSION != PSI5_IP_INIT_PBCFG_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Init_PBcfg.h are different" +#endif + +/* Checks against Psi5_Ip_Types.h */ +#if (PSI5_IP_CFG_VENDOR_ID != PSI5_IP_TYPES_VENDOR_ID) + #error "Psi5_Ip_Cfg.h and Psi5_Ip_Types.h have different vendor ids" +#endif +#if ((PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION != PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip.h and Psi5_Ip_Types.h are different" +#endif +#if ((PSI5_IP_CFG_SW_MAJOR_VERSION != PSI5_IP_TYPES_SW_MAJOR_VERSION) || \ + (PSI5_IP_CFG_SW_MINOR_VERSION != PSI5_IP_TYPES_SW_MINOR_VERSION) || \ + (PSI5_IP_CFG_SW_PATCH_VERSION != PSI5_IP_TYPES_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Types.h are different" +#endif + +/* Checks against Psi5_Ip_Cfg_Defines.h */ +#if (PSI5_IP_CFG_VENDOR_ID != PSI5_IP_CFG_DEFINES_VENDOR_ID) + #error "Psi5_Ip_Cfg.h and Psi5_Ip_Cfg_Defines.h have different vendor ids" +#endif +#if ((PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_REVISION_VERSION != PSI5_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) + #error "AUTOSAR Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Cfg_Defines.h are different" +#endif +#if ((PSI5_IP_CFG_SW_MAJOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ + (PSI5_IP_CFG_SW_MINOR_VERSION != PSI5_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ + (PSI5_IP_CFG_SW_PATCH_VERSION != PSI5_IP_CFG_DEFINES_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_Ip_Cfg.h and Psi5_Ip_Cfg_Defines.h are different" +#endif + +#if (STD_ON == PSI5_IP_DMA_IS_USED) +/* Check Psi5_Ip_Cfg.h against CDD_Mcl.h file versions */ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + #if ((PSI5_IP_CFG_AR_RELEASE_MAJOR_VERSION != CDD_MCL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_CFG_AR_RELEASE_MINOR_VERSION != CDD_MCL_AR_RELEASE_MINOR_VERSION)) + #error "AutoSar Version Numbers of Psi5_Ip_Cfg.h and CDD_Mcl.h are different" + #endif +#endif +#endif + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +/** +* @brief Collection of all configuration structures declarations. +*/ +#define PSI5_IP_CONFIG_EXT +/** +* @brief Switches the Psi5_Ip_Transmit() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_TRANSMIT_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_GetTransmissionStatus() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_GET_TRANSMISSION_STATUS_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_GetPsi5Frame() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_GET_PSI5_FRAME_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_GetSmcFrame() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_GET_SMC_FRAME_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_SetGlobalSync() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_SET_GLOBAL_SYNC_API (STD_ON) + +/** +* @brief Switches the Psi5_Ip_SetChannelSync() API ON or OFF. +* +* @api +* +*/ +#define PSI5_IP_SET_CHANNEL_SYNC_API (STD_ON) + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ +#define PSI5_START_SEC_CODE +#include "Psi5_MemMap.h" + +#define PSI5_STOP_SEC_CODE +#include "Psi5_MemMap.h" + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* PSI5_IP_CFG_H */ + diff --git a/s32/soc/s32z270/include/Psi5_Ip_Cfg_Defines.h b/s32/soc/s32z270/include/Psi5_Ip_Cfg_Defines.h new file mode 100644 index 000000000..869d89365 --- /dev/null +++ b/s32/soc/s32z270/include/Psi5_Ip_Cfg_Defines.h @@ -0,0 +1,85 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_CFG_DEFINES_H +#define PSI5_IP_CFG_DEFINES_H + +/** +* @file Psi5_Ip_Cfg_Defines.h +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "S32Z2_PSI5.h" +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_CFG_DEFINES_VENDOR_ID 43 +#define PSI5_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_CFG_DEFINES_SW_MAJOR_VERSION 2 +#define PSI5_IP_CFG_DEFINES_SW_MINOR_VERSION 0 +#define PSI5_IP_CFG_DEFINES_SW_PATCH_VERSION 0 +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +/* @brief Enables / Disables multipartition support */ +#define PSI5_IP_MULTIPARTITION_SUPPORT (STD_OFF) + +#define PSI5_IP_DEV_ERROR_DETECT (STD_OFF) + +/* Define for HW channelId of channel Psi5Channel_0 */ +#define PSI5_0_CH0 (0U) +#define PSI5_IP_ENABLE_INTERRUPTS_PSI5_0_CH0 + + +#define PSI5_IP_DMA_IS_USED (STD_OFF) +#define PSI5_IP_DMA_PSI5_FRAME_IS_USED (STD_OFF) +#define PSI5_IP_DMA_SMC_FRAME_IS_USED (STD_OFF) + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* PSI5_IP_CFG_DEFINES_H */ + diff --git a/s32/soc/s32z270/include/Psi5_Ip_Init_PBcfg.h b/s32/soc/s32z270/include/Psi5_Ip_Init_PBcfg.h new file mode 100644 index 000000000..ebb7d3182 --- /dev/null +++ b/s32/soc/s32z270/include/Psi5_Ip_Init_PBcfg.h @@ -0,0 +1,92 @@ +/* + * Copyright 2021-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSI5_IP_INIT_PBCFG_H +#define PSI5_IP_INIT_PBCFG_H + +/** +* @file Psi5_Ip_Init_PBcfg.h +* +* @addtogroup PSI5_IP PSI5 IPV Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Psi5_Ip_Types.h" + +/*================================================================================================== + SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_IP_INIT_PBCFG_VENDOR_ID 43 +#define PSI5_IP_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_IP_INIT_PBCFG_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_IP_INIT_PBCFG_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_IP_INIT_PBCFG_SW_MAJOR_VERSION 2 +#define PSI5_IP_INIT_PBCFG_SW_MINOR_VERSION 0 +#define PSI5_IP_INIT_PBCFG_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Check if current file and Psi5_Ip_Types.h header file are of the same vendor */ +#if (PSI5_IP_INIT_PBCFG_VENDOR_ID != PSI5_IP_TYPES_VENDOR_ID) + #error "Psi5_Ip_INIT_PBcfg.h and Psi5_Ip_Types.h have different vendor ids" +#endif +/* Check if current file and Psi5_Ip_Types.h header file are of the same Autosar version */ +#if ((PSI5_IP_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_IP_INIT_PBCFG_AR_RELEASE_MINOR_VERSION != PSI5_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_IP_INIT_PBCFG_AR_RELEASE_REVISION_VERSION != PSI5_IP_TYPES_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AutoSar Version Numbers of Psi5_Ip_INIT_PBcfg.h and Psi5_Ip_Types.h are different" +#endif +/* Check if current file and Psi5_Ip_Types.h header file are of the same software version */ +#if ((PSI5_IP_INIT_PBCFG_SW_MAJOR_VERSION != PSI5_IP_TYPES_SW_MAJOR_VERSION) || \ + (PSI5_IP_INIT_PBCFG_SW_MINOR_VERSION != PSI5_IP_TYPES_SW_MINOR_VERSION) || \ + (PSI5_IP_INIT_PBCFG_SW_PATCH_VERSION != PSI5_IP_TYPES_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_Ip_INIT_PBcfg.h and Psi5_Ip_Types.h are different" +#endif +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* PSI5_IP_INIT_PBCFG_H */ + diff --git a/s32/soc/s32z270/include/Psi5_S_Ip_Cfg.h b/s32/soc/s32z270/include/Psi5_S_Ip_Cfg.h new file mode 100644 index 000000000..c26f4c243 --- /dev/null +++ b/s32/soc/s32z270/include/Psi5_S_Ip_Cfg.h @@ -0,0 +1,162 @@ +/*================================================================================================== +* Project : RTD AUTOSAR 4.7 +* Platform : CORTEXM +* Peripheral : +* Dependencies : none +* +* Autosar Version : 4.7.0 +* Autosar Revision : ASR_REL_4_7_REV_0000 +* Autosar Conf.Variant : +* SW Version : 2.0.0 +* Build Version : S32ZE_RTD_2_0_0_D2407_ASR_REL_4_7_REV_0000_20240726 +* +* Copyright 2021-2024 NXP +* +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be +* used strictly in accordance with the applicable license terms. By expressly +* accepting such terms or by downloading, installing, activating and/or otherwise +* using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be +* bound by the applicable license terms, then you may not retain, install, +* activate or otherwise use the software. +==================================================================================================*/ + +#ifndef PSI5_S_IP_CFG_H +#define PSI5_S_IP_CFG_H + +/** +* @file Psi5_S_Ip_Cfg.h +* +* @addtogroup PSI5_S_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Mcal.h" +#include "Psi5_S_Ip_Init_PBcfg.h" + +#include "Psi5_S_Ip_Types.h" +#include "Psi5_S_Ip_Cfg_Defines.h" +#if (STD_ON == PSI5_S_IP_DMA_IS_USED) +#include "CDD_Mcl.h" +#include "CDD_Mcl_Cfg.h" +#endif + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_S_IP_CFG_VENDOR_ID 43 +#define PSI5_S_IP_CFG_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_S_IP_CFG_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_S_IP_CFG_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_S_IP_CFG_SW_MAJOR_VERSION 2 +#define PSI5_S_IP_CFG_SW_MINOR_VERSION 0 +#define PSI5_S_IP_CFG_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Checks current file and Psi5_S_Ip_Init_PBcfg.h header file are of the same vendor */ +#if (PSI5_S_IP_CFG_VENDOR_ID != PSI5_S_IP_INIT_PBCFG_VENDOR_ID) + #error "Psi5_S_Ip_Cfg.h and Psi5_S_Ip_Init_PBcfg.h have different vendor ids" +#endif +/* Check if current file and Psi5_S_Ip_Init_PBcfg.h header file are of the same Autosar version */ +#if ((PSI5_S_IP_CFG_AR_RELEASE_MAJOR_VERSION != PSI5_S_IP_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_CFG_AR_RELEASE_MINOR_VERSION != PSI5_S_IP_INIT_PBCFG_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_CFG_AR_RELEASE_REVISION_VERSION != PSI5_S_IP_INIT_PBCFG_AR_RELEASE_REVISION_VERSION)) + #error "AutoSar Version Numbers of Psi5_S_Ip_Cfg.h and Psi5_S_Ip_Init_PBcfg.h are different" +#endif +/* Check if current file and Psi5_S_Ip_Init_PBcfg.h header file are of the same software version */ +#if ((PSI5_S_IP_CFG_SW_MAJOR_VERSION != PSI5_S_IP_INIT_PBCFG_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_CFG_SW_MINOR_VERSION != PSI5_S_IP_INIT_PBCFG_SW_MINOR_VERSION) || \ + (PSI5_S_IP_CFG_SW_PATCH_VERSION != PSI5_S_IP_INIT_PBCFG_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_S_Ip_Cfg.h and Psi5_S_Ip_Init_PBcfg.h are different" +#endif + +/* Checks against Psi5_S_Ip_Types.h */ +#if (PSI5_S_IP_CFG_VENDOR_ID != PSI5_S_IP_TYPES_VENDOR_ID) + #error "Psi5_S_Ip_Cfg.h and Psi5_S_Ip_Types.h have different vendor ids" +#endif +#if ((PSI5_S_IP_CFG_AR_RELEASE_MAJOR_VERSION != PSI5_S_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_CFG_AR_RELEASE_MINOR_VERSION != PSI5_S_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_CFG_AR_RELEASE_REVISION_VERSION != PSI5_S_IP_TYPES_AR_RELEASE_REVISION_VERSION)) + #error "AutoSar Version Numbers of Psi5_S_Ip.h and Psi5_S_Ip_Types.h are different" +#endif +#if ((PSI5_S_IP_CFG_SW_MAJOR_VERSION != PSI5_S_IP_TYPES_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_CFG_SW_MINOR_VERSION != PSI5_S_IP_TYPES_SW_MINOR_VERSION) || \ + (PSI5_S_IP_CFG_SW_PATCH_VERSION != PSI5_S_IP_TYPES_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_S_Ip_Cfg.h and Psi5_S_Ip_Types.h are different" +#endif + +/* Checks against Psi5_S_Ip_Cfg_Defines.h */ +#if (PSI5_S_IP_CFG_VENDOR_ID != PSI5_S_IP_CFG_DEFINES_VENDOR_ID) + #error "Psi5_S_Ip_Cfg.h and Psi5_S_Ip_Cfg_Defines.h have different vendor ids" +#endif +#if ((PSI5_S_IP_CFG_AR_RELEASE_MAJOR_VERSION != PSI5_S_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_CFG_AR_RELEASE_MINOR_VERSION != PSI5_S_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_CFG_AR_RELEASE_REVISION_VERSION != PSI5_S_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) + #error "AutoSar Version Numbers of Psi5_S_Ip_Cfg.h and Psi5_S_Ip_Cfg_Defines.h are different" +#endif +#if ((PSI5_S_IP_CFG_SW_MAJOR_VERSION != PSI5_S_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_CFG_SW_MINOR_VERSION != PSI5_S_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ + (PSI5_S_IP_CFG_SW_PATCH_VERSION != PSI5_S_IP_CFG_DEFINES_SW_PATCH_VERSION)) + #error "Software Version Numbers of Psi5_S_Ip_Cfg.h and Psi5_S_Ip_Cfg_Defines.h are different" +#endif + +#if (STD_ON == PSI5_S_IP_DMA_IS_USED) +/* Check Psi5_S_Ip_Cfg.h against CDD_Mcl.h file versions */ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + #if ((PSI5_S_IP_CFG_AR_RELEASE_MAJOR_VERSION != CDD_MCL_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_CFG_AR_RELEASE_MINOR_VERSION != CDD_MCL_AR_RELEASE_MINOR_VERSION)) + #error "AutoSar Version Numbers of Psi5_S_Ip_Cfg.h and CDD_Mcl.h are different" + #endif +#endif +#endif + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +/** +* @brief Collection of all configuration structures declarations. +*/ +#define PSI5_S_IP_CONFIG_EXT \ + PSI5_S_IP_CONFIG_INIT_PB + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* PSI5_S_IP_CFG_H */ diff --git a/s32/soc/s32z270/include/Psi5_S_Ip_Cfg_Defines.h b/s32/soc/s32z270/include/Psi5_S_Ip_Cfg_Defines.h new file mode 100644 index 000000000..daf2a48fd --- /dev/null +++ b/s32/soc/s32z270/include/Psi5_S_Ip_Cfg_Defines.h @@ -0,0 +1,108 @@ +/*================================================================================================== +* Project : RTD AUTOSAR 4.7 +* Platform : CORTEXM +* Peripheral : +* Dependencies : none +* +* Autosar Version : 4.7.0 +* Autosar Revision : ASR_REL_4_7_REV_0000 +* Autosar Conf.Variant : +* SW Version : 2.0.0 +* Build Version : S32ZE_RTD_2_0_0_D2407_ASR_REL_4_7_REV_0000_20240726 +* +* Copyright 2021-2024 NXP +* +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be +* used strictly in accordance with the applicable license terms. By expressly +* accepting such terms or by downloading, installing, activating and/or otherwise +* using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be +* bound by the applicable license terms, then you may not retain, install, +* activate or otherwise use the software. +==================================================================================================*/ + +#ifndef PSI5_S_IP_CFG_DEFINES_H +#define PSI5_S_IP_CFG_DEFINES_H + +/** +* @file Psi5_S_Ip_Cfg_Defines.h +* +* @addtogroup PSI5_S_IP PSI5 IPV Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "S32Z2_PSI5_S.h" +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_S_IP_CFG_DEFINES_VENDOR_ID 43 +#define PSI5_S_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_S_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_S_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_S_IP_CFG_DEFINES_SW_MAJOR_VERSION 2 +#define PSI5_S_IP_CFG_DEFINES_SW_MINOR_VERSION 0 +#define PSI5_S_IP_CFG_DEFINES_SW_PATCH_VERSION 0 +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ + +/* Define for HW channelId of channel Psi5SChannel_0 */ +#define PSI5_S_0_CH0 (0U) +#define PSI5_S_IP_ENABLE_INTERRUPTS_PSI5_S_0_CH0 + + +#define PSI5_S_IP_ENABLE_GLOBAL_INTERRUPTS_PSI5_S_INSTANCE0 + + +#define PSI5_S_IP_DMA_IS_USED (STD_OFF) +#define PSI5_S_IP_DEBUG_MODE (STD_OFF) +#define PSI5_S_IP_DEV_ERROR_DETECT (STD_OFF) + +/* @brief Enables / Disables multipartition support */ +#define PSI5_S_IP_MULTIPARTITION_SUPPORT (STD_ON) +/* @brief Psi5S Osif source counter. This parameter is used to select between different OsIf counter implementation */ +#define PSI5_S_IP_TIMEOUT_TYPE (OSIF_COUNTER_DUMMY) +/* @brief Number of loops before returning PSI5_S_STATUS_TIMEOUT */ +#define PSI5_S_IP_TIMEOUT_VALUE_US (0U) + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* PSI5_S_IP_CFG_DEFINES_H */ diff --git a/s32/soc/s32z270/include/Psi5_S_Ip_Init_PBcfg.h b/s32/soc/s32z270/include/Psi5_S_Ip_Init_PBcfg.h new file mode 100644 index 000000000..cc49b8872 --- /dev/null +++ b/s32/soc/s32z270/include/Psi5_S_Ip_Init_PBcfg.h @@ -0,0 +1,116 @@ +/*================================================================================================== +* Project : RTD AUTOSAR 4.7 +* Platform : CORTEXM +* Peripheral : +* Dependencies : none +* +* Autosar Version : 4.7.0 +* Autosar Revision : ASR_REL_4_7_REV_0000 +* Autosar Conf.Variant : +* SW Version : 2.0.0 +* Build Version : S32ZE_RTD_2_0_0_D2407_ASR_REL_4_7_REV_0000_20240726 +* +* Copyright 2021-2024 NXP +* +* NXP Confidential and Proprietary. This software is owned or controlled by NXP and may only be +* used strictly in accordance with the applicable license terms. By expressly +* accepting such terms or by downloading, installing, activating and/or otherwise +* using the software, you are agreeing that you have read, and that you agree to +* comply with and are bound by, such license terms. If you do not agree to be +* bound by the applicable license terms, then you may not retain, install, +* activate or otherwise use the software. +==================================================================================================*/ +#ifndef PSI5_S_IP_INIT_PBCFG_H +#define PSI5_S_IP_INIT_PBCFG_H + +/** +* @file Psi5_S_Ip_PBcfg.h +* +* @addtogroup PSI5_S_IP PSI5 IPV Driver +* @{ +*/ + + +#ifdef __cplusplus +extern "C"{ +#endif + + +/*================================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Psi5_S_Ip_Types.h" + +/*================================================================================================== + SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define PSI5_S_IP_INIT_PBCFG_VENDOR_ID 43 +#define PSI5_S_IP_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION 4 +#define PSI5_S_IP_INIT_PBCFG_AR_RELEASE_MINOR_VERSION 7 +#define PSI5_S_IP_INIT_PBCFG_AR_RELEASE_REVISION_VERSION 0 +#define PSI5_S_IP_INIT_PBCFG_SW_MAJOR_VERSION 2 +#define PSI5_S_IP_INIT_PBCFG_SW_MINOR_VERSION 0 +#define PSI5_S_IP_INIT_PBCFG_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Check if current file and Psi5_S_Ip_Types.h header file are of the same vendor */ +#if (PSI5_S_IP_INIT_PBCFG_VENDOR_ID != PSI5_S_IP_TYPES_VENDOR_ID) + #error "Psi5_S_Ip_INIT_PBcfg.h and Psi5_S_Ip_Types.h have different vendor ids" +#endif +/* Check if current file and Psi5_S_Ip_Types.h header file are of the same Autosar version */ +#if ((PSI5_S_IP_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION != PSI5_S_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \ + (PSI5_S_IP_INIT_PBCFG_AR_RELEASE_MINOR_VERSION != PSI5_S_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \ + (PSI5_S_IP_INIT_PBCFG_AR_RELEASE_REVISION_VERSION != PSI5_S_IP_TYPES_AR_RELEASE_REVISION_VERSION) \ + ) + #error "AutoSar Version Numbers of Psi5_S_Ip_INIT_PBcfg.h and Psi5_S_Ip_Types.h are different" +#endif +/* Check if current file and Psi5_S_Ip_Types.h header file are of the same software version */ +#if ((PSI5_S_IP_INIT_PBCFG_SW_MAJOR_VERSION != PSI5_S_IP_TYPES_SW_MAJOR_VERSION) || \ + (PSI5_S_IP_INIT_PBCFG_SW_MINOR_VERSION != PSI5_S_IP_TYPES_SW_MINOR_VERSION) || \ + (PSI5_S_IP_INIT_PBCFG_SW_PATCH_VERSION != PSI5_S_IP_TYPES_SW_PATCH_VERSION) \ + ) + #error "Software Version Numbers of Psi5_S_Ip_INIT_PBcfg.h and Psi5_S_Ip_Types.h are different" +#endif +/*================================================================================================== + CONSTANTS +==================================================================================================*/ + +/*================================================================================================== + DEFINES AND MACROS +==================================================================================================*/ + +/*================================================================================================== + ENUMS +==================================================================================================*/ + +/*================================================================================================== + STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== + GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +#define PSI5_START_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" +#define PSI5_S_IP_CONFIG_INIT_PB \ + extern const Psi5_S_Ip_ConfigType Psi5_S_Ip_Config_Init; +#define PSI5_STOP_SEC_CONFIG_DATA_UNSPECIFIED +#include "Psi5_MemMap.h" + +/*================================================================================================== + FUNCTION PROTOTYPES +==================================================================================================*/ + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* PSI5_S_IP_INIT_PBCFG_H */