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pfb_fir_1024ch_core.mdl
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pfb_fir_1024ch_core.mdl
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Model {
Name "pfb_fir_1024ch_core"
Version 7.5
MdlSubVersion 0
GraphicalInterface {
NumRootInports 0
NumRootOutports 0
ParameterArgumentNames ""
ComputedModelVersion "1.2"
NumModelReferences 0
NumTestPointedSignals 0
}
SavedCharacterEncoding "UTF-8"
SaveDefaultBlockParams on
ScopeRefreshTime 0.035000
OverrideScopeRefreshTime on
DisableAllScopes off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
MaxMDLFileLineLength 120
Created "Tue May 15 10:15:49 2012"
Creator "zaki"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "zaki"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Tue May 15 10:35:40 2012"
RTWModifiedTimeStamp 258977781
ModelVersionFormat "1.%<AutoIncrement:2>"
ConfigurationManager "None"
SampleTimeColors off
SampleTimeAnnotations off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ShowTestPointIcons on
ShowSignalResolutionIcons on
ShowViewerIcons on
SortedOrder off
ExecutionContextIcon off
ShowLinearizationAnnotations on
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
SimulationMode "normal"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
CovForceBlockReductionOff on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
CovReportOnPause on
CovModelRefEnable "Off"
CovExternalEMLEnable off
ExtModeBatchMode off
ExtModeEnableFloating on
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigDurationFloating "auto"
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
ShowModelReferenceBlockVersion off
ShowModelReferenceBlockIO off
Array {
Type "Handle"
Dimension 1
Simulink.ConfigSet {
$ObjectID 1
Version "1.10.0"
Array {
Type "Handle"
Dimension 9
Simulink.SolverCC {
$ObjectID 2
Version "1.10.0"
StartTime "0.0"
StopTime "10.0"
AbsTol "auto"
FixedStep "auto"
InitialStep "auto"
MaxNumMinSteps "-1"
MaxOrder 5
ZcThreshold "auto"
ConsecutiveZCsStepRelTol "10*128*eps"
MaxConsecutiveZCs "1000"
ExtrapolationOrder 4
NumberNewtonIterations 1
MaxStep "auto"
MinStep "auto"
MaxConsecutiveMinStep "1"
RelTol "1e-3"
SolverMode "Auto"
Solver "ode45"
SolverName "ode45"
SolverJacobianMethodControl "auto"
ShapePreserveControl "DisableAll"
ZeroCrossControl "UseLocalSettings"
ZeroCrossAlgorithm "Nonadaptive"
AlgebraicLoopSolver "TrustRegion"
SolverResetMethod "Fast"
PositivePriorityOrder off
AutoInsertRateTranBlk off
SampleTimeConstraint "Unconstrained"
InsertRTBMode "Whenever possible"
}
Simulink.DataIOCC {
$ObjectID 3
Version "1.10.0"
Decimation "1"
ExternalInput "[t, u]"
FinalStateName "xFinal"
InitialState "xInitial"
LimitDataPoints on
MaxDataPoints "1000"
LoadExternalInput off
LoadInitialState off
SaveFinalState off
SaveCompleteFinalSimState off
SaveFormat "Array"
SaveOutput on
SaveState off
SignalLogging on
DSMLogging on
InspectSignalLogs off
SaveTime on
ReturnWorkspaceOutputs off
StateSaveName "xout"
TimeSaveName "tout"
OutputSaveName "yout"
SignalLoggingName "logsout"
DSMLoggingName "dsmout"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
ReturnWorkspaceOutputsName "out"
Refine "1"
}
Simulink.OptimizationCC {
$ObjectID 4
Version "1.10.0"
Array {
Type "Cell"
Dimension 7
Cell "BooleansAsBitfields"
Cell "PassReuseOutputArgsAs"
Cell "PassReuseOutputArgsThreshold"
Cell "ZeroExternalMemoryAtStartup"
Cell "ZeroInternalMemoryAtStartup"
Cell "OptimizeModelRefInitCode"
Cell "NoFixptDivByZeroProtection"
PropName "DisabledProps"
}
BlockReduction on
BooleanDataType on
ConditionallyExecuteInputs on
InlineParams off
UseIntDivNetSlope off
InlineInvariantSignals off
OptimizeBlockIOStorage on
BufferReuse on
EnhancedBackFolding off
StrengthReduction off
EnforceIntegerDowncast on
ExpressionFolding on
BooleansAsBitfields off
BitfieldContainerType "uint_T"
EnableMemcpy on
MemcpyThreshold 64
PassReuseOutputArgsAs "Structure reference"
ExpressionDepthLimit 2147483647
FoldNonRolledExpr on
LocalBlockOutputs on
RollThreshold 5
SystemCodeInlineAuto off
StateBitsets off
DataBitsets off
UseTempVars off
ZeroExternalMemoryAtStartup on
ZeroInternalMemoryAtStartup on
InitFltsAndDblsToZero off
NoFixptDivByZeroProtection off
EfficientFloat2IntCast off
EfficientMapNaN2IntZero on
OptimizeModelRefInitCode off
LifeSpan "inf"
MaxStackSize "Inherit from target"
BufferReusableBoundary on
SimCompilerOptimization "Off"
AccelVerboseBuild off
}
Simulink.DebuggingCC {
$ObjectID 5
Version "1.10.0"
RTPrefix "error"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
SignalInfNanChecking "none"
SignalRangeChecking "none"
ReadBeforeWriteMsg "UseLocalSettings"
WriteAfterWriteMsg "UseLocalSettings"
WriteAfterReadMsg "UseLocalSettings"
AlgebraicLoopMsg "warning"
ArtificialAlgebraicLoopMsg "warning"
SaveWithDisabledLinksMsg "warning"
SaveWithParameterizedLinksMsg "warning"
CheckSSInitialOutputMsg on
UnderspecifiedInitializationDetection "Classic"
MergeDetectMultiDrivingBlocksExec "none"
CheckExecutionContextPreStartOutputMsg off
CheckExecutionContextRuntimeOutputMsg off
SignalResolutionControl "UseLocalSettings"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
TimeAdjustmentMsg "none"
MaxConsecutiveZCsMsg "error"
SolverPrmCheckMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskDSMMsg "error"
MultiTaskCondExecSysMsg "error"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
TasksWithSamePriorityMsg "warning"
SigSpecEnsureSampleTimeMsg "warning"
CheckMatrixSingularityMsg "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterUnderflowMsg "none"
ParameterPrecisionLossMsg "warning"
ParameterTunabilityLossMsg "warning"
FixptConstUnderflowMsg "none"
FixptConstOverflowMsg "none"
FixptConstPrecisionLossMsg "none"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
FcnCallInpInsideContextMsg "Use local settings"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SFcnCompatibilityMsg "none"
UniqueDataStoreMsg "none"
BusObjectLabelMismatch "warning"
RootOutportRequireBusObject "warning"
AssertControl "UseLocalSettings"
EnableOverflowDetection off
ModelReferenceIOMsg "none"
ModelReferenceVersionMismatchMessage "none"
ModelReferenceIOMismatchMessage "none"
ModelReferenceCSMismatchMessage "none"
UnknownTsInhSupMsg "warning"
ModelReferenceDataLoggingMessage "warning"
ModelReferenceSymbolNameMessage "warning"
ModelReferenceExtraNoncontSigs "error"
StateNameClashWarn "warning"
SimStateInterfaceChecksumMismatchMsg "warning"
StrictBusMsg "ErrorLevel1"
BusNameAdapt "WarnAndRepair"
NonBusSignalsTreatedAsBus "none"
LoggingUnavailableSignals "error"
BlockIODiagnostic "none"
}
Simulink.HardwareCC {
$ObjectID 6
Version "1.10.0"
ProdBitPerChar 8
ProdBitPerShort 16
ProdBitPerInt 32
ProdBitPerLong 32
ProdIntDivRoundTo "Undefined"
ProdEndianess "Unspecified"
ProdWordSize 32
ProdShiftRightIntArith on
ProdHWDeviceType "32-bit Generic"
TargetBitPerChar 8
TargetBitPerShort 16
TargetBitPerInt 32
TargetBitPerLong 32
TargetShiftRightIntArith on
TargetIntDivRoundTo "Undefined"
TargetEndianess "Unspecified"
TargetWordSize 32
TargetTypeEmulationWarnSuppressLevel 0
TargetPreprocMaxBitsSint 32
TargetPreprocMaxBitsUint 32
TargetHWDeviceType "Specified"
TargetUnknown off
ProdEqTarget on
}
Simulink.ModelReferenceCC {
$ObjectID 7
Version "1.10.0"
UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
CheckModelReferenceTargetMessage "error"
EnableParallelModelReferenceBuilds off
ParallelModelReferenceMATLABWorkerInit "None"
ModelReferenceNumInstancesAllowed "Multi"
PropagateVarSize "Infer from blocks in model"
ModelReferencePassRootInputsByReference on
ModelReferenceMinAlgLoopOccurrences off
PropagateSignalLabelsOutOfModel off
SupportModelReferenceSimTargetCustomCode off
}
Simulink.SFSimCC {
$ObjectID 8
Version "1.10.0"
SFSimEnableDebug on
SFSimOverflowDetection on
SFSimEcho on
SimBlas on
SimCtrlC on
SimExtrinsic on
SimIntegrity on
SimUseLocalCustomCode off
SimBuildMode "sf_incremental_build"
}
Simulink.RTWCC {
$BackupClass "Simulink.RTWCC"
$ObjectID 9
Version "1.10.0"
Array {
Type "Cell"
Dimension 6
Cell "IncludeHyperlinkInReport"
Cell "GenerateTraceInfo"
Cell "GenerateTraceReport"
Cell "GenerateTraceReportSl"
Cell "GenerateTraceReportSf"
Cell "GenerateTraceReportEml"
PropName "DisabledProps"
}
SystemTargetFile "grt.tlc"
GenCodeOnly off
MakeCommand "make_rtw"
GenerateMakefile on
TemplateMakefile "grt_default_tmf"
GenerateReport off
SaveLog off
RTWVerbose on
RetainRTWFile off
ProfileTLC off
TLCDebug off
TLCCoverage off
TLCAssert off
ProcessScriptMode "Default"
ConfigurationMode "Optimized"
ConfigAtBuild off
RTWUseLocalCustomCode off
RTWUseSimCustomCode off
IncludeHyperlinkInReport off
LaunchReport off
TargetLang "C"
IncludeBusHierarchyInRTWFileBlockHierarchyMap off
IncludeERTFirstTime off
GenerateTraceInfo off
GenerateTraceReport off
GenerateTraceReportSl off
GenerateTraceReportSf off
GenerateTraceReportEml off
GenerateCodeInfo off
RTWCompilerOptimization "Off"
CheckMdlBeforeBuild "Off"
CustomRebuildMode "OnUpdate"
Array {
Type "Handle"
Dimension 2
Simulink.CodeAppCC {
$ObjectID 10
Version "1.10.0"
Array {
Type "Cell"
Dimension 19
Cell "IgnoreCustomStorageClasses"
Cell "IgnoreTestpoints"
Cell "InsertBlockDesc"
Cell "SFDataObjDesc"
Cell "SimulinkDataObjDesc"
Cell "DefineNamingRule"
Cell "SignalNamingRule"
Cell "ParamNamingRule"
Cell "InlinedPrmAccess"
Cell "CustomSymbolStr"
Cell "CustomSymbolStrGlobalVar"
Cell "CustomSymbolStrType"
Cell "CustomSymbolStrField"
Cell "CustomSymbolStrFcn"
Cell "CustomSymbolStrFcnArg"
Cell "CustomSymbolStrBlkIO"
Cell "CustomSymbolStrTmpVar"
Cell "CustomSymbolStrMacro"
Cell "ReqsInCode"
PropName "DisabledProps"
}
ForceParamTrailComments off
GenerateComments on
IgnoreCustomStorageClasses on
IgnoreTestpoints off
IncHierarchyInIds off
MaxIdLength 31
PreserveName off
PreserveNameWithParent off
ShowEliminatedStatement off
IncAutoGenComments off
SimulinkDataObjDesc off
SFDataObjDesc off
IncDataTypeInIds off
MangleLength 1
CustomSymbolStrGlobalVar "$R$N$M"
CustomSymbolStrType "$N$R$M"
CustomSymbolStrField "$N$M"
CustomSymbolStrFcn "$R$N$M$F"
CustomSymbolStrFcnArg "rt$I$N$M"
CustomSymbolStrBlkIO "rtb_$N$M"
CustomSymbolStrTmpVar "$N$M"
CustomSymbolStrMacro "$R$N$M"
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
UseSimReservedNames off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 11
Version "1.10.0"
Array {
Type "Cell"
Dimension 17
Cell "GeneratePreprocessorConditionals"
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "GenerateTestInterfaces"
Cell "ModelStepFunctionPrototypeControlCompliant"
Cell "CPPClassGenCompliant"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
Cell "PortableWordSizes"
PropName "DisabledProps"
}
TargetFcnLib "ansi_tfl_table_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
TargetFunctionLibrary "ANSI_C"
UtilityFuncGeneration "Auto"
ERTMultiwordTypeDef "System defined"
ERTCodeCoverageTool "None"
ERTMultiwordLength 256
MultiwordLength 2048
GenerateFullHeader on
GenerateSampleERTMain off
GenerateTestInterfaces off
IsPILTarget off
ModelReferenceCompliant on
ParMdlRefBuildCompliant on
CompOptLevelCompliant on
IncludeMdlTerminateFcn on
GeneratePreprocessorConditionals "Disable all"
CombineOutputUpdateFcns off
SuppressErrorStatus off
ERTFirstTimeCompliant off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
SupportVariableSizeSignals off
EnableShiftOperators on
ParenthesesLevel "Nominal"
PortableWordSizes off
ModelStepFunctionPrototypeControlCompliant off
CPPClassGenCompliant off
AutosarCompliant off
UseMalloc off
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
ExtModeIntrfLevel "Level1"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
hdlcoderui.hdlcc {
$ObjectID 12
Version "1.10.0"
Description "HDL Coder custom configuration component"
Name "HDL Coder"
Array {
Type "Cell"
Dimension 1
Cell ""
PropName "HDLConfigFile"
}
HDLCActiveTab "0"
}
PropName "Components"
}
Name "Configuration"
CurrentDlgPage "Solver"
ConfigPrmDlgPosition " [ 72, 69, 952, 699 ] "
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
BlockRotation 0
BlockMirror off
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
BlockParameterDefaults {
Block {
BlockType Constant
Value "1"
VectorParams1D on
SamplingMode "Sample based"
OutMin "[]"
OutMax "[]"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "fixdt(1,16,0)"
ConRadixGroup "Use specified scaling"
OutScaling "[]"
OutDataTypeStr "Inherit: Inherit from 'Constant value'"
LockScale off
SampleTime "inf"
FramePeriod "inf"
PreserveConstantTs off
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
OutMin "[]"
OutMax "[]"
DataType "auto"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchInputForFeedbackSignals off
Interpolate on
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
OutMin "[]"
OutMax "[]"
DataType "auto"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
SignalType "auto"
SamplingMode "auto"
SourceOfInitialOutputValue "Dialog"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
CheckFcnCallInpInsideContextMsg off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Terminator
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
FixptAsFi off
}
}
System {
Name "pfb_fir_1024ch_core"
Location [106, 335, 864, 674]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
SIDHighWatermark 16
Block {
BlockType Reference
Name " System Generator"
SID 1
Tag "genX"
Ports []
Position [112, 15, 163, 65]
ShowName off
AttributesFormatString "System\\nGenerator"
LibraryVersion "1.2"
UserDataPersistent on
UserData "DataTag0"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator Block"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
infoedit " System Generator"
xilinxfamily "virtex5"
part "xc5vsx95t"
speed "-1"
package "ff1136"
synthesis_tool "XST"
clock_wrapper "Clock Enables"
directory "./pfb_fir_1024ch_core"
proj_type "Project Navigator"
Synth_file "XST Defaults"
Impl_file "ISE Defaults"
testbench off
simulink_period "1"
sysclk_period "5"
dcm_input_clock_period "100"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
has_advanced_control "0"
sggui_pos "642,188,464,470"
block_type "sysgen"
block_version "10.1.3"
sg_icon_stat "51,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 51 51 0 0 ],[0 0 50 50 0 ],[1 1 1 ]"
");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1"
"55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3"
"6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15"
"5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15"
"5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph"
"ics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');"
}
Block {
BlockType Reference
Name "Band-Limited\nWhite Noise"
SID 2
Ports [0, 1]
Position [15, 150, 45, 180]
ShowName off
LibraryVersion "1.216"
SourceBlock "simulink/Sources/Band-Limited\nWhite Noise"
SourceType "Band-Limited White Noise."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Cov "(16/128)^2"
Ts "1"
seed "[23341]"
VectorParams1D on
}
Block {
BlockType Constant
Name "Constant1"
SID 3
Position [50, 188, 65, 202]
ShowName off
Value "0"
}
Block {
BlockType Reference
Name "Repeating\nSequence\nStair1"
SID 4
Ports [0, 1]
Position [15, 90, 45, 120]
ShowName off
LibraryVersion "1.216"
SourceBlock "simulink/Sources/Repeating\nSequence\nStair"
SourceType "Repeating Sequence Stair"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
OutValues "[1, zeros(1,2^12-1)]"
tsamp "1"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "float('double')"
OutputDataTypeScalingMode "Specify via dialog"
OutDataType "float('double')"
ConRadixGroup "Best Precision: Vector-wise"
OutScaling "2^-12"
LockScale off
}
Block {
BlockType Terminator
Name "Terminator1"
SID 5
Position [710, 190, 720, 200]
ShowName off
}
Block {
BlockType ToWorkspace
Name "To Workspace"
SID 6
Ports [1]
Position [690, 155, 735, 175]
ShowName off
VariableName "pfbout"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType ToWorkspace
Name "To Workspace1"
SID 7
Ports [1]
Position [690, 125, 735, 145]
ShowName off
VariableName "pfbsync"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType SubSystem
Name "c_to_ri"
SID 8
Ports [1, 2]
Position [485, 151, 525, 209]
AttributesFormatString "18_17 r/i"
AncestorBlock "casper_library/Misc/c_to_ri"
UserDataPersistent on
UserData "DataTag1"
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
MaskType "c_to_ri"
MaskDescription "Outputs real and imaginary components of a complex input.\nUseful for simplifying interco"
"nnects.\nSee also: Real-Imag to Complex (ri_to_c)"
MaskHelp "eval('xlWeb(''http://casper.berkeley.edu/wiki/C_to_ri'')')"
MaskPromptString "Bit Width|Binary Point"
MaskStyleString "edit,edit"
MaskTunableValueString "on,on"
MaskCallbackString "|"
MaskEnableString "on,on"
MaskVisibilityString "on,on"
MaskToolTipString "on,on"
MaskVariables "n_bits=@1;bin_pt=@2;"
MaskInitialization "annotation=sprintf('%d_%d r/i',n_bits,bin_pt);\nset_param(gcb,'AttributesFormatString',"
"annotation);"
MaskSelfModifiable on
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskPortRotate "default"
MaskIconUnits "autoscale"
MaskValueString "18|17"
System {
Name "c_to_ri"
Location [698, 94, 968, 282]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
SIDHighWatermark 7
SIDPrevWatermark 7
Block {
BlockType Inport
Name "c"
SID 1
Position [20, 63, 50, 77]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Reference
Name "force_im"
SID 2
Ports [1, 1]
Position [150, 79, 190, 111]
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Reinterpret"
SourceType "Xilinx Type Reinterpreter Block"
infoedit "Changes signal type without altering the binary representation. You can changed the signal between s"
"igned and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>"
"Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi"
"th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in "
"binary)."
force_arith_type on
arith_type "Signed (2's comp)"
force_bin_pt on
bin_pt "bin_pt"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "reinterpret"
block_version "9.1.01"
sg_icon_stat "40,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.91"
" ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20.44 24.4"
"4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20.44 16.44 ],"
"[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([15."
"1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','"
"COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nfp"
"rintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "force_re"
SID 3
Ports [1, 1]
Position [150, 29, 190, 61]
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Reinterpret"
SourceType "Xilinx Type Reinterpreter Block"
infoedit "Changes signal type without altering the binary representation. You can changed the signal between s"
"igned and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>"
"Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi"
"th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in "
"binary)."
force_arith_type on
arith_type "Signed (2's comp)"
force_bin_pt on
bin_pt "bin_pt"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "reinterpret"
block_version "9.1.01"
sg_icon_stat "40,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.91"
" ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20.44 24.4"
"4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20.44 16.44 ],"
"[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([15."
"1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','"
"COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nfp"
"rintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "slice_im"
SID 4
Ports [1, 1]
Position [80, 81, 125, 109]
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type "
"is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware "
"notes: In hardware this block costs nothing."
nbits "n_bits"
boolean_output off
mode "Lower Bit Location + Width"