-
Notifications
You must be signed in to change notification settings - Fork 4
/
fft_1024ch_core_config.m
132 lines (102 loc) · 4.16 KB
/
fft_1024ch_core_config.m
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
function fft_1024ch_core_config(this_block)
% Revision History:
%
% 15-May-2012 (11:34 hours):
% Original code was machine generated by Xilinx's System Generator after parsing
% /scratch/zaki/workspace/roachfengine/fft_1024ch_core.vhd
%
%
this_block.setTopLevelLanguage('VHDL');
this_block.setEntityName('fft_1024ch_core');
% System Generator has to assume that your entity has a combinational feed through;
% if it doesn't, then comment out the following line:
%this_block.tagAsCombinational;
this_block.addSimulinkInport('sync');
this_block.addSimulinkInport('shift');
this_block.addSimulinkInport('pol0');
this_block.addSimulinkInport('pol1');
this_block.addSimulinkInport('pol2');
this_block.addSimulinkInport('pol3');
this_block.addSimulinkOutport('sync_out');
this_block.addSimulinkOutport('pol02_out');
this_block.addSimulinkOutport('pol13_out');
this_block.addSimulinkOutport('oflow');
oflow_port = this_block.port('oflow');
oflow_port.setType('Bool');
oflow_port.useHDLVector(false);
pol02_out_port = this_block.port('pol02_out');
pol02_out_port.setType('UFix_36_0');
pol13_out_port = this_block.port('pol13_out');
pol13_out_port.setType('UFix_36_0');
sync_out_port = this_block.port('sync_out');
sync_out_port.setType('Bool');
sync_out_port.useHDLVector(false);
% -----------------------------
if (this_block.inputTypesKnown)
% do input type checking, dynamic output type and generic setup in this code block.
if (this_block.port('pol0').width ~= 18);
this_block.setError('Input data type for port "pol0" must have width=18.');
end
if (this_block.port('pol1').width ~= 18);
this_block.setError('Input data type for port "pol1" must have width=18.');
end
if (this_block.port('pol2').width ~= 18);
this_block.setError('Input data type for port "pol2" must have width=18.');
end
if (this_block.port('pol3').width ~= 18);
this_block.setError('Input data type for port "pol3" must have width=18.');
end
if (this_block.port('shift').width ~= 16);
this_block.setError('Input data type for port "shift" must have width=16.');
end
if (this_block.port('sync').width ~= 1);
this_block.setError('Input data type for port "sync" must have width=1.');
end
this_block.port('sync').useHDLVector(false);
end % if(inputTypesKnown)
% -----------------------------
% -----------------------------
if (this_block.inputRatesKnown)
setup_as_single_rate(this_block,'clk_1','ce_1')
end % if(inputRatesKnown)
% -----------------------------
% (!) Set the inout port rate to be the same as the first input
% rate. Change the following code if this is untrue.
uniqueInputRates = unique(this_block.getInputRates);
% Add addtional source files as needed.
% |-------------
% | Add files in the order in which they should be compiled.
% | If two files "a.vhd" and "b.vhd" contain the entities
% | entity_a and entity_b, and entity_a contains a
% | component of type entity_b, the correct sequence of
% | addFile() calls would be:
% | this_block.addFile('b.vhd');
% | this_block.addFile('a.vhd');
% |-------------
% this_block.addFile('');
% this_block.addFile('');
this_block.addFile('fft_1024ch_core.vhd');
return;
% ------------------------------------------------------------
function setup_as_single_rate(block,clkname,cename)
inputRates = block.inputRates;
uniqueInputRates = unique(inputRates);
if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf)
block.addError('The inputs to this block cannot all be constant.');
return;
end
if (uniqueInputRates(end) == Inf)
hasConstantInput = true;
uniqueInputRates = uniqueInputRates(1:end-1);
end
if (length(uniqueInputRates) ~= 1)
block.addError('The inputs to this block must run at a single rate.');
return;
end
theInputRate = uniqueInputRates(1);
for i = 1:block.numSimulinkOutports
block.outport(i).setRate(theInputRate);
end
block.addClkCEPair(clkname,cename,theInputRate);
return;
% ------------------------------------------------------------