Ghidra dsp56k slaspec coverage

[yatli]

• ABS Absolute Value page 13-5
• BRA Branch Always page 13-25
• ADC Add Long With Carry page 13-6
• BRCLR Branch if Bit Clear page 13-26
• ADD Add page 13-7
• BRKcc Exit Current DO Loop Conditionally page 13-28
• ADDL Shift Left and Add Accumulators page 13-9
• BRSET Branch if Bit Set page 13-29
• ADDR Shift Right and Add Accumulators page 13-10
• BScc Branch to Subroutine Conditionally page 13-31
• AND Logical AND page 13-11
• BSCLR Branch to Subroutine if Bit Clear page 13-32
• ANDI AND Immediate With Control Register page 13-13
• BSET Bit Set and Test page 13-34
• ASL Arithmetic Shift Accumulator Left page 13-14
• BSR Branch to Subroutine page 13-37
• ASR Arithmetic Shift Accumulator Right page 13-16
• BSSET Branch to Subroutine if Bit Set page 13-38
• Bcc Branch Conditionally page 13-18
• BTST Bit Test page 13-40
• BCHG Bit Test and Change page 13-19
• CLB Count Leading Bits page 13-42
• BCLR Bit Test and Clear page 13-22
• CLR Clear Accumulator page 13-44
• CMP Compare page 13-45
• INC Increment by One page 13-77
• CMPM Compare Magnitude page 13-47
• INSERT Insert Bit Field page 13-78
• CMPU Compare Unsigned page 13-48
• Jcc Jump Conditionally page 13-80
• DEBUG Enter Debug Mode page 13-49
• JCLR Jump if Bit Clear page 13-81
• DEBUGcc Enter Debug Mode Conditionally page 13-50
• JMP Jump page 13-83
• DEC Decrement by One page 13-51
• JScc Jump to Subroutine Conditionally page 13-84
• DIV Divide Iteration page 13-51
• JSCLR Jump to Subroutine if Bit Clear page 13-85
• DMAC Double-Precision Multiply-Accumulate With Right Shift page 13-55
• JSET Jump if Bit Set page 13-87
• DO Start Hardware Loop page 13-56
• JSR Jump to Subroutine page 13-89
• DO FOREVER Start Infinite Loop page 13-59
• JSSET Jump to Subroutine if Bit Set page 13-90
• DOR Start PC-Relative Hardware Loop page 13-61
• L: Long Memory Data Move
• DOR FOREVER Start PC-Relative Infinite Loop page 13-65
• LRA Load PC-Relative Address page 13-92
• ENDDO End Current DO Loop page 13-67
• LSL Logical Shift Left page 13-93
• EOR Logical Exclusive OR page 13-68
• LSR Logical Shift Right page 13-96
• EXTRACT Extract Bit Field page 13-70
• LUA Load Updated Address page 13-98
• EXTRACTU Extract Unsigned Bit Field page 13-72
• MAC Signed Multiply Accumulate page 13-99
• I Immediate Short Data Move page 13-113
• MAC(su,uu) Mixed Multiply Accumulate page 13-102
• IFcc Execute Conditionally Without CCR Update page 13-74 MACI
• Signed Multiply Accumulate With Immediate Operand page 13-101
• IFcc.U Execute Conditionally With CCR Update page 13-75
• MACR Signed Multiply Accumulate and Round page 13-103
• ILLEGAL Illegal Instruction Interrupt page 13-76
• MACRI Signed Multiply Accumulate and Round With Immediate Operand page 13-105
• MAX Transfer by Signed Value page 13-106
• MPYRI Signed Multiply and Round With Immediate Operand page 13-143
• MAXM Transfer by Magnitude page 13-107
• NEG Negate Accumulator page 13-144
• MERGE Merge Two Half Words page 13-108
• No Parallel Data Move page 13-112
• MOVE Move Data page 13-110
• NOP No Operation page 13-145
• No Parallel Data Move page 13-112
• NORM Norm Accumulator Iteration page 13-147
• I Immediate Short Data Move page 13-113
• NORMF Fast Accumulator Normalization page 13-147
• R Register-to-Register Data Move page 13-115
• NOT Logical Complement page 13-149
• U Address Register Update page 13-117
• OR Logical Inclusive OR page 13-150
• X: X Memory Data Move page 13-118
• ORI OR Immediate With Control Register page 13-152
• X:R X Memory and Register Data Move page 13-120
• PFLUSH Program Cache Flush page 13-153
• Y: Y Memory Data Move page 13-122
• PFLUSHUN Program cache Flush Unlocked Sectors page 13-154
• R:Y Register and Y Memory Data Move page 13-124
• PFREE Program Cache Global Unlock page 13-155
• L: Long Memory Data Move page 13-126
• PLOCK Lock Instruction Cache Sector page 13-156
• X:Y: XY Memory Data Move page 13-123
• PLOCKR Lock Instruction Cache Relative Sector page 13-157
• MOVEC Move Control Register page 13-130
• PUNLOCK Unlock Instruction Cache Sector page 13-158
• MOVEM Move Program Memory page 13-132
• PUNLOCKR Unlock Instruction Cache Relative Sector page 13-159
• MOVEP Move Peripheral Data page 13-134
• R Register-to-Register Data Move page 13-115
• MPY Signed Multiply page 13-137
• REP Repeat Next Instruction page 13-160
• MPY(su,uu) Mixed Multiply page 13-139
• RESET Reset On-Chip Peripheral Devices page 13-162
• MPYI Signed Multiply With Immediate Operand page 13-140
• RND Round Accumulator page 13-163
• MPYR Signed Multiply and Round page 13-141
• ROL Rotate Left page 13-165
• ROR Rotate Right page 13-166
• TRAP Software Interrupt page 13-179
• RTI Return From Interrupt page 13-168
• TRAPcc Conditional Software Interrupt page 13-180
• RTS Return From Subroutine page 13-168
• TST Test Accumulator page 13-181
• R:Y Register and Y Memory Data Move page 13-124
• U Address Register Update page 13-117
• SBC Subtract Long With Carry page 13-169
• VSL Viterbi Shift Left page 13-182
• STOP Stop Instruction Processing page 13-170
• WAIT Wait for Interrupt or DMA Request page 13-183
• SUB Subtract page 13-172
• X: X Memory Data Move page 13-118
• SUBL Shift Left and Subtract Accumulators page 13-174
• X:R X Memory and Register Data Move page 13-120
• SUBR Shift Right and Subtract Accumulators page 13-175
• X:Y: XY Memory Data Move page 13-123
• Tcc Transfer Conditionally page 13-176
• Y: Y Memory Data Move page 13-122
• TFR Transfer Data ALU Register page 13-178