LICENSE

xv6-riscv-fpga (https://gitlab.com/x653/xv6-riscv-fpga/)

xv6-riscv-fpga is an fpga implementation of a RISC-V cpu rv32ia_zicsr based on the Olimex iCE40HX8K-EVB development board capable of running UNIX xv6 (https://pdos.csail.mit.edu/6.828/2022/xv6.html) using only FOSS (free and open source hard- and software)

Copyright 2023 Michael Schröder

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

cube		- 3D printable model of a case for the xv6-riscv-fpga computer
doc			- documentation
fpga		- hardware part: fpga implementation of xv6-riscv-fpga computer
iceprog		- firmware for programmer/bridge Olimexino 324
LICENSE		- this license text
lisp		- c-implementation of a homemade LISP interpreter
README.md	- Readme file
xv6-riscv	- software part: port of xv6-riscv to 32 bit rv32ia_zicsr

The original files in xv6-riscv/ are Copyright 2006-2022 Frans Kaashoek, Robert Morris, and Russ Cox.(https://pdos.csail.mit.edu/6.828/2022/xv6.html)