diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..66e5029
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+
+wcupl/test/wcupl/
diff --git a/WCPLD Examples/6502/W6502SBC.wpld b/WCPLD Examples/6502/W6502SBC.wpld
new file mode 100644
index 0000000..20b6673
--- /dev/null
+++ b/WCPLD Examples/6502/W6502SBC.wpld	
@@ -0,0 +1,77 @@
+header:
+Name     W6502SBC_16 ;
+PartNo   01 ;
+Date     05.08.2022 ;
+Revision 01 ;
+Designer wkla ;
+Company  nn ;
+Assembly None ;
+Location  ;
+Device   G22V10 ;
+
+pld:
+/* *************** INPUT PINS *********************/
+PIN 1   =  PHI2; 
+PIN 2   =  A15;
+PIN 3   =  A14;
+PIN 4   =  A13;
+PIN 5 	=  A12;
+PIN 6 	=  A11;
+PIN 7 	=  A10;
+PIN 8 	=  A9;
+PIN 9   =  A8;
+//PIN 10  =  nn;
+PIN 11  =  RW;
+//PIN 13 	= nn; 
+
+/* *************** OUTPUT PINS *********************/
+PIN 23   =  CSRAM;
+PIN 22   =  CSHIROM;
+PIN 21   =  CSEXTROM;
+PIN 20   =  CSIO;
+PIN 19   =  CSIO0;
+PIN 18   =  CSIO1;
+PIN 17   =  CSIO2;
+PIN 16   =  CSIO3;
+PIN 15   =  MWR;  // /WR only for RAM
+PIN 14   =  MRD;  // goes to all /OE of ROM and RAM
+
+FIELD Addr = [A15..A8];
+
+CSRAM = ! (Addr:[0000..7FFF]); // 32KB
+CSIO = ! (Addr:[B000..BFFF]); // 4KB
+CSIO0 = ! (Addr:[B000..B0FF]);
+CSIO1 = ! (Addr:[B100..B1FF]);
+CSIO2 = ! (Addr:[B200..B2FF]);
+CSIO3 = ! (Addr:[B300..B3FF]);
+CSEXTROM = ! (Addr:[8000..AFFF]); // 12KB
+CSROM = ! (Addr:[C000..FFFF]);  // 16KB
+
+MWR = ! (PHI2 & !RW);
+MRD = ! (PHI2 & RW);
+
+simulator:
+ORDER: A15, A14, A13, A12, A11, A10, A9, A8, RW, PHI2, CSRAM, CSIO, CSIO0, CSIO1, CSIO2, CSIO3, CSEXTROM, CSHIROM, MWR, MRD; 
+
+VECTORS:
+/* RAM */
+0 X X X X X X X 0 0 L H H H H H H H H H
+0 X X X X X X X 0 1 L H H H H H H H L H
+/* IO */
+1 0 1 1 0 0 0 0 X X H L L H H H H H X X
+1 0 1 1 0 0 0 1 X X H L H L H H H H X X
+1 0 1 1 0 0 1 0 X X H L H H L H H H X X
+1 0 1 1 0 0 1 1 X X H L H H H L H H X X
+1 0 1 1 0 1 X X X X H L H H H H H H X X
+1 0 1 1 1 X X X X X H L H H H H H H X X
+
+/* 8000-AFFF external Rom */ 
+1 0 0 0 X X X X X X H H H H H H L H X X
+1 0 0 1 X X X X X X H H H H H H L H X X
+1 0 1 0 X X X X X X H H H H H H L H X X
+
+/* ROM */
+1 1 X X X X X X 1 0 H H H H H H H L H H
+1 1 X X X X X X 1 1 H H H H H H H L H L
+1 1 X X X X X X 0 0 H H H H H H H L H H
+1 1 X X X X X X 0 1 H H H H H H H L L H
diff --git a/WCPLD Examples/6502/W6502SBC_C64.wpld b/WCPLD Examples/6502/W6502SBC_C64.wpld
new file mode 100644
index 0000000..b6b8d0c
--- /dev/null
+++ b/WCPLD Examples/6502/W6502SBC_C64.wpld	
@@ -0,0 +1,63 @@
+header:
+Name     W6502SBC_ADR_C64 ;
+PartNo   01 ;
+Date     20.07.2022 ;
+Revision 01 ;
+Designer wkla ;
+Company  nn ;
+Assembly None ;
+Location  ;
+Device   G16V8AS ;
+
+pld:
+/* *************** INPUT PINS *********************/
+PIN 1   =  A12; 
+PIN 2   =  A13;
+PIN 3   =  A14;
+PIN 4   =  A15;
+PIN 5 	=  ALORAM;
+PIN 6 	=  AHIRAM;
+PIN 7 	=  ALOROM;
+PIN 8 	=  AHIROM;
+PIN 9   =  PHI2;
+PIN 11  =  NOLOROM;
+
+/* *************** OUTPUT PINS *********************/
+PIN 12   =  CSRAM;
+PIN 13   =  CSHIROM;
+PIN 14   =  CSLOROM;
+PIN 15   =  CSIO;
+PIN 16   =  LORAM;
+PIN 17   =  LOROM;
+PIN 18   =  HIRAM;
+PIN 19   =  HIROM;
+
+ 
+CSRAM = (A15 & !A14 & !A13 & !ALORAM) # (A15 & !A14 & A13 & NOLOROM) # (A15 & A14 & !A13 & !A12 & !AHIRAM) # (A15 & A14 & !A13 & A12) # (A15 & A14 & A13) # !PHI2;
+CSHIROM = !(A15 & A14 & A13 & AHIROM);
+CSLOROM = !(A15 & !A14 & A13 & ALOROM & NOLOROM);
+CSIO= !(A15 & A14 & !A13 & A12);
+LORAM= !(A15 & !A14 & !A13 & !ALORAM);
+LOROM= !(A15 & !A14 & A13 & !ALOROM & NOLOROM);
+HIRAM= !(A15 & A14 & !A13 & !A12 & !AHIRAM);
+HIROM= !(A15 & A14 & A13 & !AHIROM);
+
+simulator:
+ORDER: A15, A14, A13, A12, ALORAM, AHIRAM, ALOROM, AHIROM, NOLOROM, PHI2, CSRAM, CSHIROM, CSLOROM, CSIO, LORAM, LOROM, HIRAM, HIROM; 
+
+VECTORS:
+0 X X X X X X X X 0 H H H H H H H H 
+0 X X X X X X X X 1 L H H H H H H H 
+1 0 0 X 1 X X X X 0 H H H H H H H H 
+1 0 0 X 1 X X X X 1 L H H H H H H H 
+1 0 0 X 0 X X X X X H H H H L H H H 
+1 0 1 X X X 1 X 1 X H H L H H H H H 
+1 0 1 X X X 0 X 1 X H H H H H L H H 
+1 0 1 X X X X X 0 0 H H H H H H H H 
+1 0 1 X X X X X 0 1 L H H H H H H H 
+1 1 0 0 X 1 X X X 0 H H H H H H H H 
+1 1 0 0 X 1 X X X 1 L H H H H H H H 
+1 1 0 0 X 0 X X X X H H H H H H L H 
+1 1 0 1 X X X X X X H H H L H H H H 
+1 1 1 X X X X 1 X X H L H H H H H H 
+1 1 1 X X X X 0 X X H H H H H H H L 
diff --git a/WCPLD Examples/6502/adr_simple.wpld b/WCPLD Examples/6502/adr_simple.wpld
new file mode 100644
index 0000000..ebe126f
--- /dev/null
+++ b/WCPLD Examples/6502/adr_simple.wpld	
@@ -0,0 +1,72 @@
+header:
+Name     adr_simple ;
+PartNo   01 ;
+Date     24.07.2022 ;
+Revision 03 ;
+Designer wkla ;
+Company  nn ;
+Assembly None ;
+Location  ;
+Device   G16V8 ;
+
+pld:
+/* *************** INPUT PINS *********************/
+PIN [1..8]   =  [A15..A8]; 
+PIN 9   =  PHI2;
+
+/* *************** OUTPUT PINS *********************/
+PIN 12   =  CSRAM;
+PIN 13   =  CSHIROM;
+PIN 14   =  CSEXTROM;
+PIN 15   =  IOPORT;
+PIN 16   =  CSIO3PORT;
+PIN 17   =  CSIO2PORT;
+PIN 18   =  ACIAPORT;
+PIN 19   =  VIAPORT;
+/* *************** LOGIC *********************/
+
+FIELD Addr = [A15..A8];
+CSRAM_EQU = Addr:[0000..7FFF]; // 32KB
+
+/* IO */
+IOPORT    = ! (Addr:[B000..BFFF]); // 4KB
+VIAPORT   = ! (Addr:[B000..B0FF]);
+ACIAPORT  = ! (Addr:[B100..B1FF]);
+CSIO2PORT = ! (Addr:[B200..B2FF]);
+CSIO3PORT = ! (Addr:[B300..B3FF]);
+
+/* 12KB of external ROM */
+CSEXTROM = ! (Addr:[8000..AFFF]); // 12KB
+/* 8kb of ROM */
+CSHIROM = ! (Addr:[C000..FFFF]);  // 16KB
+
+/* RAM */
+CSRAM = !CSRAM_EQU # !PHI2;
+
+simulator:
+ORDER: A15, A14, A13, A12, A11, A10, A9, A8, PHI2, CSEXTROM, CSRAM, CSHIROM, IOPORT, VIAPORT, ACIAPORT, CSIO2PORT, CSIO3PORT; 
+
+VECTORS:
+/* internal RAM */
+0 X X X X X X X 0 H H H H H H H H 
+0 X X X X X X X 1 H L H H H H H H 
+
+/* 8000-AFFF external Rom */ 
+1 0 0 0 X X X X X L H H H H H H H 
+1 0 0 1 X X X X X L H H H H H H H 
+1 0 1 0 X X X X X L H H H H H H H 
+
+/* IO */ 
+/* CSIO0 */
+1 0 1 1 0 0 0 0 X H H H L L H H H 
+/* CSIO1 */
+1 0 1 1 0 0 0 1 X H H H L H L H H 
+/* CSIO2 */
+1 0 1 1 0 0 1 0 X H H H L H H L H 
+/* CSIO3 */
+1 0 1 1 0 0 1 1 X H H H L H H H L 
+/* nicht direkt benutzt */
+1 0 1 1 0 1 X X X H H H L H H H H 
+1 0 1 1 1 X X X X H H H L H H H H 
+/* ROM */
+1 1 X X X X X X X H H L H H H H H 
diff --git a/WCPLD Examples/6502/adr_simple_v2.wpld b/WCPLD Examples/6502/adr_simple_v2.wpld
new file mode 100644
index 0000000..a6c27f4
--- /dev/null
+++ b/WCPLD Examples/6502/adr_simple_v2.wpld	
@@ -0,0 +1,79 @@
+header:
+Name     adr_simple ;
+PartNo   01 ;
+Date     24.07.2022 ;
+Revision 03 ;
+Designer wkla ;
+Company  nn ;
+Assembly None ;
+Location  ;
+Device   G16V8 ;
+
+pld:
+/* *************** INPUT PINS *********************/
+PIN [1..8]   =  [A15..A8]; 
+PIN 9   =  PHI2;
+PIN 11  = RW;
+
+/* *************** OUTPUT PINS *********************/
+PIN 12   =  CSRAM;
+PIN 13   =  CSHIROM;
+PIN 14   =  CSEXTROM;
+PIN 15   =  CSIO;
+PIN 16   =  MWR;
+PIN 17   =  CSIO2;
+PIN 18   =  CSIO1;
+PIN 19   =  CSIO0;
+/* *************** LOGIC *********************/
+
+FIELD Addr = [A15..A8];
+
+/* RAM 32kb */
+CSRAM = ! (Addr:[0000..7FFF]); 
+
+/* IO 4kb */
+CSIO = ! (Addr:[B000..BFFF]); 
+CSIO0 = ! (Addr:[B000..B0FF]);
+CSIO1 = ! (Addr:[B100..B1FF]);
+CSIO2 = ! (Addr:[B200..B2FF]);
+
+/* 12kb of external ROM */
+CSEXTROM = ! (Addr:[8000..AFFF]); 
+
+/* 16kb of ROM */
+CSHIROM = ! (Addr:[C000..FFFF]);  
+
+MWR = ! (PHI2 & !RW);
+
+simulator:
+ORDER: A15, A14, A13, A12, A11, A10, A9, A8, RW, PHI2, CSRAM, MWR, CSIO, CSIO0, CSIO1, CSIO2, CSEXTROM, CSHIROM; 
+
+VECTORS:
+/* testing /RD /WR */
+X X X X X X X X 0 0 X H X X X X X X 
+X X X X X X X X 0 1 X L X X X X X X 
+X X X X X X X X 1 0 X H X X X X X X 
+X X X X X X X X 1 1 X H X X X X X X 
+
+/* internal RAM */
+0 X X X X X X X X X L X H H H H H H 
+
+/* 8000-AFFF external Rom */ 
+1 0 0 0 X X X X X X H X H H H H L H 
+1 0 0 1 X X X X X X H X H H H H L H 
+1 0 1 0 X X X X X X H X H H H H L H 
+
+/* IO */ 
+/* CSIO0 */
+1 0 1 1 0 0 0 0 X X H X L L H H H H
+/* CSIO1 */
+1 0 1 1 0 0 0 1 X X H X L H L H H H
+/* CSIO2 */
+1 0 1 1 0 0 1 0 X X H X L H H L H H
+
+/* nicht direkt benutzt */
+1 0 1 1 0 1 X X X X H X L H H H H H
+1 0 1 1 1 X X X X X H X L H H H H H
+
+/* ROM */
+1 1 X X X X X X X X H X H H H H H L
diff --git a/WCPLD Examples/7-seg decoder/7segDecoder - Kopie.wpld b/WCPLD Examples/7-seg decoder/7segDecoder - Kopie.wpld
new file mode 100644
index 0000000..3368679
--- /dev/null
+++ b/WCPLD Examples/7-seg decoder/7segDecoder - Kopie.wpld	
@@ -0,0 +1,93 @@
+header:
+Name     7segDecoder ;
+PartNo   00 ;
+Date     8/6/2020 ;
+Revision 02 ;
+Designer Peter Murray ;
+Company  N/A ;
+Assembly None ;
+Location Right here ;
+Device   g16v8ms ;
+
+/*
+  Hex to 7-segment LED display converter
+  Common Cathode Variant
+
+      +----\/----+
+  CLK | 1     20 | Vcc
+   I0 | 2     19 | Segment A
+   I1 | 3     18 | Segment B
+   I2 | 4     17 | Segment C
+   I3 | 5     16 | Segment D
+  N/C | 6     15 | Segment E
+  N/C | 7     14 | Segment F
+  N/C | 8     13 | Segment G
+  N/C | 9     12 | N/C
+  GND | 10    11 | /OE
+      +----------+
+
+  This is designed for the Atmel ATF16V8B (Digikey: ATF16V8B-15PU-ND )
+
+*/
+pld:
+/* *************** INPUT PINS *********************/
+PIN  1   = CLK;
+PIN  2   =  I0;
+PIN  3   =  I1;
+PIN  4   =  I2;
+PIN  5   =  I3;
+/* PIN 11   =  !ENABLE; */
+
+/* *************** OUTPUT PINS ******************** */
+PIN  19 = !A;
+PIN  18 = !B;
+PIN  17 = !C;
+PIN  16 = !D;
+PIN  15 = !E;
+PIN  14 = !F;
+PIN  13 = !G;
+
+/* [A,B,C,D,E,F,G].oe = ENABLE; */
+
+FIELD INPUT = [I0,I1,I2,I3]; /* Defines input array */
+FIELD OUTPUT = [A.d,B.d,C.d,D.d,E.d,F.d,G.d]; /* Defines output array */
+TABLE INPUT => OUTPUT
+{
+  'b'0000 => 'b'0000001;
+  'b'0001 => 'b'1001111;
+  'b'0010 => 'b'0010010;
+  'b'0011 => 'b'0000110;
+  'b'0100 => 'b'1001100;
+  'b'0101 => 'b'0100100;
+  'b'0110 => 'b'0100000;
+  'b'0111 => 'b'0001111;
+  'b'1000 => 'b'0000000;
+  'b'1001 => 'b'0001100;
+  'b'1010 => 'b'0001000;
+  'b'1011 => 'b'1100000;
+  'b'1100 => 'b'0110001;
+  'b'1101 => 'b'1000010;
+  'b'1110 => 'b'0110000;
+  'b'1111 => 'b'0111000;
+}
+/*
+{
+  'b'0000 => 'b'1111110;
+  'b'0001 => 'b'0110000;
+  'b'0010 => 'b'1101101;
+  'b'0011 => 'b'1111001;
+  'b'0100 => 'b'0110011;
+  'b'0101 => 'b'1011011;
+  'b'0110 => 'b'1011111;
+  'b'0111 => 'b'1110000;
+  'b'1000 => 'b'1111111;
+  'b'1001 => 'b'1110011;
+  'b'1010 => 'b'1110111;
+  'b'1011 => 'b'0011111;
+  'b'1100 => 'b'1001110;
+  'b'1101 => 'b'0111101;
+  'b'1110 => 'b'1001111;
+  'b'1111 => 'b'1000111;
+}
+*/
+simulator:
diff --git a/WCPLD Examples/7-seg decoder/7segDecoder_ca_latch.wpld b/WCPLD Examples/7-seg decoder/7segDecoder_ca_latch.wpld
new file mode 100644
index 0000000..2688253
--- /dev/null
+++ b/WCPLD Examples/7-seg decoder/7segDecoder_ca_latch.wpld	
@@ -0,0 +1,58 @@
+header:
+Name     7segDecoder_ca_latch ;
+PartNo   00 ;
+Date     8/6/2020 ;
+Revision 02 ;
+Designer Peter Murray ;
+Company  N/A ;
+Assembly None ;
+Location Right here ;
+Device   g16v8ms ;
+
+/*
+  Hex to 7-segment LED display converter
+  Common Cathode Variant
+
+      +----\/----+
+  CLK | 1     20 | Vcc
+   I0 | 2     19 | Segment A
+   I1 | 3     18 | Segment B
+   I2 | 4     17 | Segment C
+   I3 | 5     16 | Segment D
+  N/C | 6     15 | Segment E
+  N/C | 7     14 | Segment F
+  N/C | 8     13 | Segment G
+  N/C | 9     12 | N/C
+  GND | 10    11 | /OE
+      +----------+
+
+  This is designed for the Atmel ATF16V8B (Digikey: ATF16V8B-15PU-ND )
+
+*/
+pld:
+/* *************** INPUT PINS *********************/
+PIN  1   = CLK;
+PIN  2   =  I0;
+PIN  3   =  I1;
+PIN  4   =  I2;
+PIN  5   =  I3;
+/* PIN 11   =  !ENABLE; */
+
+/* *************** OUTPUT PINS ******************** */
+PIN  19 = A;
+PIN  18 = B;
+PIN  17 = C;
+PIN  16 = D;
+PIN  15 = E;
+PIN  14 = F;
+PIN  13 = G;
+
+/* [A,B,C,D,E,F,G].oe = ENABLE; */
+
+A.d = (!I0 & !I1 & !I2 & I3) # (!I0 & I1 & !I2 & !I3) # (I0 & !I1 & I2 & I3) # (!I0 & I1 & !I2 & !I3);
+B.d = (!I0 & I1 & !I2 & I3) # (!I0 & I1 & I2 & !I3) # (I0 & !I1 & I2 & I3) # (I0 & I1 & !I2 & !I3) # (I0 & I1 & I2 & !I3) # (I0 & I1 & I2 & I3);
+C.d = (!I0 & !I1 & I2 & !I3) # (I0 & I1 & !I2 & !I3) # (I0 & I1 & I2 & !I3) # (I0 & I1 & I2 & I3);
+D.d = (!I0 & !I1 & !I2 & I3) # (!I0 & I1 & !I2 & !I3) # (!I0 & I1 & I2 & I3)# (I0 & !I1 & !I2 & I3) # (I0 & !I1 & I2 & !I3) # (I0 & I1 & I2 & I3);
+E.d = (!I0 & !I1 & !I2 & I3) # (!I0 & !I1 & I2 & I3) # (!I0 & I1 & !I2 & !I3) # (!I0 & I1 & !I2 & I3) # (!I0 & I1 & I2 & I3) # (I0 & !I1 & !I2 & I3);
+F.d = (!I0 & !I1 & !I2 & I3) # (!I0 & !I1 & I2 & !I3) # (!I0 & !I1 & I2 & I3) # (!I0 & I1 & I2 & I3) # (I0 & I1 & !I2 & I3);
+G.d = (!I0 & !I1 & !I2 & !I3) # (!I0 & !I1 & !I2 & I3) # (!I0 & I1 & I2 & I3) # (I0 & I1 & !I2 & !I3) ;
diff --git a/WCPLD Examples/7-seg decoder/7segDecoder_latch.wpld b/WCPLD Examples/7-seg decoder/7segDecoder_latch.wpld
new file mode 100644
index 0000000..19da455
--- /dev/null
+++ b/WCPLD Examples/7-seg decoder/7segDecoder_latch.wpld	
@@ -0,0 +1,58 @@
+header:
+Name     7segDecoder_latch ;
+PartNo   00 ;
+Date     8/6/2020 ;
+Revision 02 ;
+Designer Peter Murray ;
+Company  N/A ;
+Assembly None ;
+Location Right here ;
+Device   g16v8ms ;
+
+/*
+  Hex to 7-segment LED display converter
+  Common Cathode Variant
+
+      +----\/----+
+  CLK | 1     20 | Vcc
+   I0 | 2     19 | Segment A
+   I1 | 3     18 | Segment B
+   I2 | 4     17 | Segment C
+   I3 | 5     16 | Segment D
+  N/C | 6     15 | Segment E
+  N/C | 7     14 | Segment F
+  N/C | 8     13 | Segment G
+  N/C | 9     12 | N/C
+  GND | 10    11 | /OE
+      +----------+
+
+  This is designed for the Atmel ATF16V8B (Digikey: ATF16V8B-15PU-ND )
+
+*/
+pld:
+/* *************** INPUT PINS *********************/
+PIN  1   = CLK;
+PIN  2   =  I0;
+PIN  3   =  I1;
+PIN  4   =  I2;
+PIN  5   =  I3;
+/* PIN 11   =  !ENABLE; */
+
+/* *************** OUTPUT PINS ******************** */
+PIN  19 = !A;
+PIN  18 = !B;
+PIN  17 = !C;
+PIN  16 = !D;
+PIN  15 = !E;
+PIN  14 = !F;
+PIN  13 = !G;
+
+/* [A,B,C,D,E,F,G].oe = ENABLE; */
+
+A.d = (!I0 & !I1 & !I2 & I3) # (!I0 & I1 & !I2 & !I3) # (I0 & !I1 & I2 & I3) # (!I0 & I1 & !I2 & !I3);
+B.d = (!I0 & I1 & !I2 & I3) # (!I0 & I1 & I2 & !I3) # (I0 & !I1 & I2 & I3) # (I0 & I1 & !I2 & !I3) # (I0 & I1 & I2 & !I3) # (I0 & I1 & I2 & I3);
+C.d = (!I0 & !I1 & I2 & !I3) # (I0 & I1 & !I2 & !I3) # (I0 & I1 & I2 & !I3) # (I0 & I1 & I2 & I3);
+D.d = (!I0 & !I1 & !I2 & I3) # (!I0 & I1 & !I2 & !I3) # (!I0 & I1 & I2 & I3)# (I0 & !I1 & !I2 & I3) # (I0 & !I1 & I2 & !I3) # (I0 & I1 & I2 & I3);
+E.d = (!I0 & !I1 & !I2 & I3) # (!I0 & !I1 & I2 & I3) # (!I0 & I1 & !I2 & !I3) # (!I0 & I1 & !I2 & I3) # (!I0 & I1 & I2 & I3) # (I0 & !I1 & !I2 & I3);
+F.d = (!I0 & !I1 & !I2 & I3) # (!I0 & !I1 & I2 & !I3) # (!I0 & !I1 & I2 & I3) # (!I0 & I1 & I2 & I3) # (I0 & I1 & !I2 & I3);
+G.d = (!I0 & !I1 & !I2 & !I3) # (!I0 & !I1 & !I2 & I3) # (!I0 & I1 & I2 & I3) # (I0 & I1 & !I2 & !I3) ;
diff --git a/WCPLD Examples/7-seg decoder/compile.cmd b/WCPLD Examples/7-seg decoder/compile.cmd
new file mode 100644
index 0000000..fc044da
--- /dev/null
+++ b/WCPLD Examples/7-seg decoder/compile.cmd	
@@ -0,0 +1,8 @@
+@echo off
+set LIBCUPL=e:\Wincupl\Shared\atmel.dl
+e:\Wincupl\Shared\wcupl.exe -jaxfsl -m4 %1.wpld
+rem c:\Wincupl\Shared\csim.exe -l g16v8 -u c:\Wincupl\Shared\Atmel.dl TEST
+if errorlevel 1 (
+.\wcupl\%1.lst
+.\wcupl\%1.so
+)
\ No newline at end of file
diff --git a/WCPLD Examples/7-seg decoder/dualhex7seg.wpld b/WCPLD Examples/7-seg decoder/dualhex7seg.wpld
new file mode 100644
index 0000000..3189dd4
--- /dev/null
+++ b/WCPLD Examples/7-seg decoder/dualhex7seg.wpld	
@@ -0,0 +1,107 @@
+header:
+Name     DualHex7Seg ;
+PartNo   1 ;
+Date     08.08.2022 ;
+Revision 01 ;
+Designer WKLA ;
+Company  MCS ;
+Assembly None ;
+Location  ;
+Device   G22V10 ;
+
+/*
+  Dual Hex to 7-segment LED display converter
+  Common Anode Variant
+
+      +----\/----+
+  CLK | 1     24 | Vcc
+  AI0 | 2     23 | OEA
+  AI1 | 3     22 | Segment E
+  AI2 | 4     21 | Segment B
+  AI3 | 5     20 | Segment C
+  BI0 | 6     19 | Segment A
+  BI1 | 7     18 | Segment D
+  BI2 | 8     17 | Segment F
+  BI3 | 9     16 | Segment G
+  DPA | 10    15 | Segmant DP
+  DPB | 11    14 | OEB
+  GND | 12    13 | n.c
+      +----------+
+
+  This is designed for the Atmel ATF22V10
+
+*/
+
+pld:
+/* *************** INPUT PINS *********************/
+PIN  1 = CLK;
+PIN  2 = AIA;
+PIN  3 = AIB;
+PIN  4 = AIC;
+PIN  5 = AID;
+PIN  6 = BIA;
+PIN  7 = BIB;
+PIN  8 = BIC;
+PIN  9 = BID;
+PIN 10 = DPA;
+PIN 11 = DPB;
+
+/* *************** OUTPUT PINS *********************/
+PIN  23 = OEA ; 
+PIN  22 = !E ;
+PIN  21 = !B ;
+PIN  20 = !C ;
+PIN  19 = !A ;
+PIN  18 = !D ;
+PIN  17 = !F ;
+PIN  16 = !G ;
+PIN  14 = OEB ;
+PIN  15 = !DP;
+/* ************* Declarations **********************/
+
+FIELD AADD = [CLK,AID,AIC,AIB,AIA] ;
+FIELD BADD = [CLK,BID,BIC,BIB,BIA] ;
+FIELD OUTPUT = [OEA,A,B,C,D,E,F,G,OEB] ;
+
+/********* EQUATIONS ****************/
+DP = (DPA & !CLK) # (DPB & CLK) ;
+
+/* 7-Segment A */
+TABLE AADD => OUTPUT {
+'b'00000=>'b'011111101 ; /* 0 */ 
+'b'00001=>'b'001100001 ; /* 1 */
+'b'00010=>'b'011011011 ; /* 2 */
+'b'00011=>'b'011110011 ; /* 3 */
+'b'00100=>'b'001100111 ; /* 4 */
+'b'00101=>'b'010110111 ; /* 5 */
+'b'00110=>'b'010111111 ; /* 6 */
+'b'00111=>'b'011100001 ; /* 7 */
+'b'01000=>'b'011111111 ; /* 8 */
+'b'01001=>'b'011100111 ; /* 9 */
+'b'01010=>'b'011101111 ; /* A */
+'b'01011=>'b'000111111 ; /* B */
+'b'01100=>'b'010011101 ; /* C */
+'b'01101=>'b'001111011 ; /* D */
+'b'01110=>'b'010011111 ; /* E */
+'b'01111=>'b'010001111 ; /* F */
+}
+
+/* 7-Segment B */
+TABLE BADD => OUTPUT {
+'b'10000=>'b'111111100 ; /* 0 */
+'b'10001=>'b'101100000 ; /* 1 */
+'b'10010=>'b'111011010 ; /* 2 */
+'b'10011=>'b'111110010 ; /* 3 */
+'b'10100=>'b'101100110 ; /* 4 */
+'b'10101=>'b'110110110 ; /* 5 */
+'b'10110=>'b'110111110 ; /* 6 */
+'b'10111=>'b'111100000 ; /* 7 */
+'b'11000=>'b'111111110 ; /* 8 */
+'b'11001=>'b'111100110 ; /* 9 */
+'b'11010=>'b'111101110 ; /* A */
+'b'11011=>'b'100111110 ; /* B */
+'b'11100=>'b'110011100 ; /* C */
+'b'11101=>'b'101111010 ; /* D */
+'b'11110=>'b'110011110 ; /* E */
+'b'11111=>'b'110001110 ; /* F */
+}
diff --git a/wcupl/3rd_party/7z.exe b/wcupl/3rd_party/7z.exe
new file mode 100644
index 0000000..872133e
Binary files /dev/null and b/wcupl/3rd_party/7z.exe differ
diff --git a/wcupl/3rd_party/GoVersionSetter.exe b/wcupl/3rd_party/GoVersionSetter.exe
new file mode 100644
index 0000000..5e0ab6f
Binary files /dev/null and b/wcupl/3rd_party/GoVersionSetter.exe differ
diff --git a/wcupl/cmd/main.go b/wcupl/cmd/main.go
index e2b5247..23d7691 100644
--- a/wcupl/cmd/main.go
+++ b/wcupl/cmd/main.go
@@ -9,10 +9,15 @@ import (
 	"os/exec"
 	"path/filepath"
 	"strings"
+	"time"
 
 	"log"
+
+	"github.com/aymerick/raymond"
 )
 
+const layoutISO = "2006-01-02"
+
 var (
 	cuplargs []string
 	file     string
@@ -59,11 +64,30 @@ func main() {
 		log.Fatalf("error creating temp dir: %v\n", err)
 	}
 	destfile := filepath.Join(workdir, filepath.Base(file))
-	file, err = copy(file, destfile)
+
+	filename := strings.TrimSuffix(filepath.Base(file), filepath.Ext(file))
+
+	ctx := map[string]string{
+		"filename": filename,
+		"date":     time.Now().Format(layoutISO),
+	}
+
+	b, err := ioutil.ReadFile(file)
+	if err != nil {
+		log.Fatalf("error loading source file: %v\n", err)
+	}
+
+	result, err := raymond.Render(string(b), ctx)
+	if err != nil {
+		log.Fatalf("error render file: %v\n", err)
+	}
+
+	err = ioutil.WriteFile(destfile, []byte(result), 0644)
 	if err != nil {
-		log.Fatalf("error copy source file: %v\n", err)
+		log.Fatalf("error writing file: %v\n", err)
 	}
 
+	file = destfile
 	f, err := os.Open(file)
 	if err != nil {
 		log.Fatalf("error opening file: %v\n", err)
diff --git a/wcupl/deployments/build.cmd b/wcupl/deployments/build.cmd
index 946b986..5f30fcc 100644
--- a/wcupl/deployments/build.cmd
+++ b/wcupl/deployments/build.cmd
@@ -1,3 +1,4 @@
 @echo off
 go build -ldflags="-s -w" -o wcupl.exe cmd/main.go
+.\3rd_party\7z.exe a wcupl.zip wcupl.exe
 copy wcupl.exe e:\WinCupl\shared
\ No newline at end of file
diff --git a/wcupl/go.mod b/wcupl/go.mod
index 9e504e1..e0ea881 100644
--- a/wcupl/go.mod
+++ b/wcupl/go.mod
@@ -1,3 +1,5 @@
 module github.com/willie68/wcupl
 
 go 1.18
+
+require github.com/aymerick/raymond v2.0.2+incompatible // indirect
diff --git a/wcupl/go.sum b/wcupl/go.sum
new file mode 100644
index 0000000..742b034
--- /dev/null
+++ b/wcupl/go.sum
@@ -0,0 +1,2 @@
+github.com/aymerick/raymond v2.0.2+incompatible h1:VEp3GpgdAnv9B2GFyTvqgcKvY+mfKMjPOA3SbKLtnU0=
+github.com/aymerick/raymond v2.0.2+incompatible/go.mod h1:osfaiScAUVup+UC9Nfq76eWqDhXlp+4UYaA8uhTBO6g=
diff --git a/wcupl/readme.md b/wcupl/readme.md
new file mode 100644
index 0000000..d946830
--- /dev/null
+++ b/wcupl/readme.md
@@ -0,0 +1,15 @@
+# wcupl
+
+Since WinCUPL is no longer running on any of my computers, I wrote a batch, directly starting cupl.exe, with which I can generate the JED file and also run the simulator right away. Personally, though, I like having the sources in one place. I personally find the duplication of the headers of the PLD and SI file and the manual synchronization between the two unpleasant. That's why I came up with the simple WPLD format and wrote the WCUPL tool for it. The WCUPL tool is available in my repo (https://github.com/willie68/WCPLD/releases). This eliminates the tedious header matching and logic and test are in one file. 
+
+The tool itself doesn't do much. Any arguments are passed directly to CUPL. 
+
+- macros with {{}} will be exchange with some other data:
+  `{{filename}}`: is the filename without wpld extension
+  `{{date}}`: is the actual date in format yyyy-mm-dd (ISO8601)
+- it will create a subfolder called wcupl and copy the wpld into it. 
+- From this wpld files, `header:` and `pld:` are merged into one #.pld file and `header`: and `simulator:` part into the #.si file. 
+- Then cupl is started from the same directory where wcupl is located. Or if present using environment variable `CUPL_HOME` for trying to find cupl.exe. (So sorry, this version is only for windows users)
+
+
+
diff --git a/wcupl/test/adr_simple.pld b/wcupl/test/adr_simple.pld
deleted file mode 100644
index 7e281cb..0000000
--- a/wcupl/test/adr_simple.pld
+++ /dev/null
@@ -1,33 +0,0 @@
-Name     adr_simple ;
-PartNo   01 ;
-Date     24.07.2022 ;
-Revision 02 ;
-Designer wkla ;
-Company  nn ;
-Assembly None ;
-Location  ;
-Device   G16V8 ;
-
-/* *************** INPUT PINS *********************/
-PIN 1   =  A12; 
-PIN 2   =  A13;
-PIN 3   =  A14;
-PIN 4   =  A15;
-PIN 9   =  PHI2;
-
-/* *************** OUTPUT PINS *********************/
-PIN 12   =  CSRAM;
-PIN 13   =  CSHIROM;
-PIN 15   =  CSIO;
-
-/* *************** LOGIC *********************/
-
-/* RAM */
-CSRAM = A15 # !PHI2;
-
-/* 8kb of ROM */
-CSHIROM = !(A15 & A14 & A13);
-
-/* IO */
-CSIO= !(A15 & A14 & !A13 & A12);
-
diff --git a/wcupl/test/adr_simple.si b/wcupl/test/adr_simple.si
deleted file mode 100644
index 51b0fef..0000000
--- a/wcupl/test/adr_simple.si
+++ /dev/null
@@ -1,20 +0,0 @@
-Name     adr_simple ;
-PartNo   01 ;
-Date     24.07.2022 ;
-Revision 02 ;
-Designer wkla ;
-Company  nn ;
-Assembly None ;
-Location  ;
-Device   G16V8 ;
-
-/* Starting Test description */
-ORDER: A15, A14, A13, A12, PHI2, CSRAM, CSHIROM, CSIO; 
-
-VECTORS:
-0 X X X 0 H H H 
-0 X X X 1 L H H 
-1 0 X X X H H H 
-1 1 0 0 X H H H 
-1 1 0 1 X H H L 
-1 1 1 X X H L H 
diff --git a/wcupl/test/adr_simple.wpld b/wcupl/test/adr_simple.wpld
index 42489c3..78bed14 100644
--- a/wcupl/test/adr_simple.wpld
+++ b/wcupl/test/adr_simple.wpld
@@ -1,7 +1,7 @@
 HEADER:
-Name     adr_simple ;
+Name     {{filename}} ;
 PartNo   01 ;
-Date     24.07.2022 ;
+Date     {{date}} ;
 Revision 02 ;
 Designer wkla ;
 Company  nn ;
diff --git a/wcupl/test/wcupl/adr_simple.abs b/wcupl/test/wcupl/adr_simple.abs
deleted file mode 100644
index 5e678dc..0000000
Binary files a/wcupl/test/wcupl/adr_simple.abs and /dev/null differ
diff --git a/wcupl/test/wcupl/adr_simple.doc b/wcupl/test/wcupl/adr_simple.doc
deleted file mode 100644
index 4ee0785..0000000
--- a/wcupl/test/wcupl/adr_simple.doc
+++ /dev/null
@@ -1,157 +0,0 @@
-
-*******************************************************************************
-                                  adr_simple
-*******************************************************************************
-
-CUPL(WM)        5.0a Serial# MW-10400000
-Device          g16v8s  Library DLIB-h-40-9
-Created         Thu Aug 04 10:19:57 2022
-Name            adr_simple 
-Partno          01 
-Revision        02 
-Date            24.07.2022 
-Designer        wkla 
-Company         nn 
-Assembly        None 
-Location        
-
-===============================================================================
-                            Expanded Product Terms
-===============================================================================
-
-CSHIROM =>
-    A13 & A14 & A15
-
-CSIO =>
-    A12 & !A13 & A14 & A15
-
-CSRAM =>
-    A15
-  # !PHI2
-
-
-===============================================================================
-                                 Symbol Table
-===============================================================================
-
-Pin Variable                                    Pterms   Max     Min    
-Pol   Name              Ext     Pin     Type     Used   Pterms  Level   
---- --------            ---     ---     ----    ------  ------  -----   
-
-    A12                         1        V        -       -       -     
-    A13                         2        V        -       -       -     
-    A14                         3        V        -       -       -     
-    A15                         4        V        -       -       -     
-    CSHIROM                     13       V        1       8       1     
-    CSIO                        15       V        1       8       1     
-    CSRAM                       12       V        2       8       1     
-    PHI2                        9        V        -       -       -     
-
-
-LEGEND    D : default variable         F : field      G : group
-          I : intermediate variable    N : node       M : extended node
-          U : undefined                V : variable   X : extended variable
-          T : function
-
-
-===============================================================================
-                                   Fuse Plot
-===============================================================================
-
-Syn   02192 - Ac0   02193 x 
-
-Pin #19  02048  Pol x  02120  Ac1 - 
- 00000 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00032 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00064 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00096 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
-Pin #18  02049  Pol x  02121  Ac1 - 
- 00256 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00288 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00320 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00352 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00384 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00416 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00448 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00480 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
-Pin #17  02050  Pol x  02122  Ac1 - 
- 00512 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00544 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00576 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00608 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00640 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00672 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00736 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
-Pin #16  02051  Pol x  02123  Ac1 - 
- 00768 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00800 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00832 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00864 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00896 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00928 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
-Pin #15  02052  Pol x  02124  Ac1 x 
- 01024 -xx-x---x----------------------- 
- 01056 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01088 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01120 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01152 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01184 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01248 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
-Pin #14  02053  Pol x  02125  Ac1 - 
- 01280 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01312 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01344 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01376 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01440 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
-Pin #13  02054  Pol x  02126  Ac1 x 
- 01536 x---x---x----------------------- 
- 01568 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01600 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
-Pin #12  02055  Pol -  02127  Ac1 x 
- 01792 --------x----------------------- 
- 01824 -----------------------------x-- 
- 01856 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01888 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01920 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 01984 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
- 02016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 
-
-
-LEGEND    X : fuse not blown 
-          - : fuse blown 
-
-===============================================================================
-                                 Chip Diagram
-===============================================================================
-
-                               ______________
-                              |  adr_simple  |
-                      A12 x---|1           20|---x Vcc                      
-                      A13 x---|2           19|---x                          
-                      A14 x---|3           18|---x                          
-                      A15 x---|4           17|---x                          
-                          x---|5           16|---x                          
-                          x---|6           15|---x CSIO                     
-                          x---|7           14|---x                          
-                          x---|8           13|---x CSHIROM                  
-                     PHI2 x---|9           12|---x CSRAM                    
-                      GND x---|10          11|---x                          
-                              |______________|
-
diff --git a/wcupl/test/wcupl/adr_simple.jed b/wcupl/test/wcupl/adr_simple.jed
deleted file mode 100644
index a3d071f..0000000
--- a/wcupl/test/wcupl/adr_simple.jed
+++ /dev/null
@@ -1,34 +0,0 @@
-
-CUPL(WM)        5.0a  Serial# MW-10400000
-Device          g16v8s  Library DLIB-h-40-9
-Created         Thu Aug 04 10:19:57 2022
-Name            adr_simple 
-Partno          01 
-Revision        02 
-Date            24.07.2022 
-Designer        wkla 
-Company         nn 
-Assembly        None 
-Location        
-*QP20 
-*QF2194 
-*QV6
-*G0 
-*F0 
-*L01024 10010111011111111111111111111111
-*L01536 01110111011111111111111111111111
-*L01792 11111111011111111111111111111111
-*L01824 11111111111111111111111111111011
-*L02048 00000001001100000011000100100000
-*L02112 00000000111101001111111111111111
-*L02144 11111111111111111111111111111111
-*L02176 111111111111111110
-*C18EA
-*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-*V0001 XXX0XXXX0NXHHXHXXXXN
-*V0002 XXX0XXXX1NXLHXHXXXXN
-*V0003 XX01XXXXXNXHHXHXXXXN
-*V0004 0011XXXXXNXHHXHXXXXN
-*V0005 1011XXXXXNXHHXLXXXXN
-*V0006 X111XXXXXNXHLXHXXXXN
-*C3FA
\ No newline at end of file
diff --git a/wcupl/test/wcupl/adr_simple.lst b/wcupl/test/wcupl/adr_simple.lst
deleted file mode 100644
index 35188f6..0000000
--- a/wcupl/test/wcupl/adr_simple.lst
+++ /dev/null
@@ -1,47 +0,0 @@
-LISTING FOR LOGIC DESCRIPTION FILE: adr_simple.pld                   Page 1
-
-CUPL(WM): Universal Compiler for Programmable Logic
-Version 5.0a Serial# MW-10400000
-Copyright (c) 1983, 1998 Logical Devices, Inc.
-Created Thu Aug 04 10:19:57 2022
-
-  1:Name     adr_simple ;
-  2:PartNo   01 ;
-  3:Date     24.07.2022 ;
-  4:Revision 02 ;
-  5:Designer wkla ;
-  6:Company  nn ;
-  7:Assembly None ;
-  8:Location  ;
-  9:Device   G16V8 ;
- 10:
- 11:/* *************** INPUT PINS *********************/
- 12:PIN 1   =  A12; 
- 13:PIN 2   =  A13;
- 14:PIN 3   =  A14;
- 15:PIN 4   =  A15;
- 16:PIN 9   =  PHI2;
- 17:
- 18:/* *************** OUTPUT PINS *********************/
- 19:PIN 12   =  CSRAM;
- 20:PIN 13   =  CSHIROM;
- 21:PIN 15   =  CSIO;
- 22:
- 23:/* *************** LOGIC *********************/
- 24:
- 25:/* RAM */
- 26:CSRAM = A15 # !PHI2;
- 27:
- 28:/* 8kb of ROM */
- 29:CSHIROM = !(A15 & A14 & A13);
- 30:
- 31:/* IO */
- 32:CSIO= !(A15 & A14 & !A13 & A12);
- 33:
- 34:
- 35:
-
-
-
-Jedec Fuse Checksum       (18ea)
-Jedec Transmit Checksum   (8ba0)
diff --git a/wcupl/test/wcupl/adr_simple.pld b/wcupl/test/wcupl/adr_simple.pld
deleted file mode 100644
index 7e281cb..0000000
--- a/wcupl/test/wcupl/adr_simple.pld
+++ /dev/null
@@ -1,33 +0,0 @@
-Name     adr_simple ;
-PartNo   01 ;
-Date     24.07.2022 ;
-Revision 02 ;
-Designer wkla ;
-Company  nn ;
-Assembly None ;
-Location  ;
-Device   G16V8 ;
-
-/* *************** INPUT PINS *********************/
-PIN 1   =  A12; 
-PIN 2   =  A13;
-PIN 3   =  A14;
-PIN 4   =  A15;
-PIN 9   =  PHI2;
-
-/* *************** OUTPUT PINS *********************/
-PIN 12   =  CSRAM;
-PIN 13   =  CSHIROM;
-PIN 15   =  CSIO;
-
-/* *************** LOGIC *********************/
-
-/* RAM */
-CSRAM = A15 # !PHI2;
-
-/* 8kb of ROM */
-CSHIROM = !(A15 & A14 & A13);
-
-/* IO */
-CSIO= !(A15 & A14 & !A13 & A12);
-
diff --git a/wcupl/test/wcupl/adr_simple.si b/wcupl/test/wcupl/adr_simple.si
deleted file mode 100644
index 51b0fef..0000000
--- a/wcupl/test/wcupl/adr_simple.si
+++ /dev/null
@@ -1,20 +0,0 @@
-Name     adr_simple ;
-PartNo   01 ;
-Date     24.07.2022 ;
-Revision 02 ;
-Designer wkla ;
-Company  nn ;
-Assembly None ;
-Location  ;
-Device   G16V8 ;
-
-/* Starting Test description */
-ORDER: A15, A14, A13, A12, PHI2, CSRAM, CSHIROM, CSIO; 
-
-VECTORS:
-0 X X X 0 H H H 
-0 X X X 1 L H H 
-1 0 X X X H H H 
-1 1 0 0 X H H H 
-1 1 0 1 X H H L 
-1 1 1 X X H L H 
diff --git a/wcupl/test/wcupl/adr_simple.sim b/wcupl/test/wcupl/adr_simple.sim
deleted file mode 100644
index ca02aff..0000000
--- a/wcupl/test/wcupl/adr_simple.sim
+++ /dev/null
@@ -1,26 +0,0 @@
-%SIGNAL
-PIN   1 =  A12 
-PIN   2 =  A13 
-PIN   3 =  A14 
-PIN   4 =  A15 
-PIN  13 =  CSHIROM 
-PIN  15 =  CSIO 
-PIN  12 =  CSRAM 
-PIN   9 =  PHI2 
-%END
-
-%FIELD
-%END
-
-%EQUATION
-CSHIROM =>
-    A13 & A14 & A15
-
-CSIO =>
-    A12 & !A13 & A14 & A15
-
-CSRAM =>
-    A15
-  # !PHI2
-
-%END
diff --git a/wcupl/test/wcupl/adr_simple.so b/wcupl/test/wcupl/adr_simple.so
deleted file mode 100644
index a4e65c5..0000000
--- a/wcupl/test/wcupl/adr_simple.so
+++ /dev/null
@@ -1,36 +0,0 @@
-CSIM(WM): CUPL Simulation Program
-Version 5.0a Serial# MW-10400000
-Copyright (c) 1983, 1998 Logical Devices, Inc.
-CREATED Thu Aug 04 10:19:57 2022
-
-LISTING FOR SIMULATION FILE: adr_simple.si
-
-   1: Name     adr_simple ;
-   2: PartNo   01 ;
-   3: Date     24.07.2022 ;
-   4: Revision 02 ;
-   5: Designer wkla ;
-   6: Company  nn ;
-   7: Assembly None ;
-   8: Location  ;
-   9: Device   G16V8 ;
-  10: 
-  11: /* Starting Test description */
-  12: ORDER: A15, A14, A13, A12, PHI2, CSRAM, CSHIROM, CSIO; 
-  13: 
-
-=================
-            C    
-            S    
-           CH    
-          PSIC   
-      AAAAHRRS   
-      1111IAOI   
-      54322MMO   
-=================
-0001: 0XXX0HHH
-0002: 0XXX1LHH
-0003: 10XXXHHH
-0004: 1100XHHH
-0005: 1101XHHL
-0006: 111XXHLH
diff --git a/wcupl/test/wcupl/adr_simple.wo b/wcupl/test/wcupl/adr_simple.wo
deleted file mode 100644
index 4df73fe..0000000
--- a/wcupl/test/wcupl/adr_simple.wo
+++ /dev/null
@@ -1,20 +0,0 @@
-#WAVEFORM
-#H Name     adr_simple ;
-#H PartNo   01 ;
-#H Date     24.07.2022 ;
-#H Revision 02 ;
-#H Designer wkla ;
-#H Company  nn ;
-#H Assembly None ;
-#H Location  ;
-#H Device   G16V8 ;
-#H 
-#H /* Starting Test description */
-#H ORDER: A15, A14, A13, A12, PHI2, CSRAM, CSHIROM, CSIO; 
-#H 
-#V 0001 0XXX0HHH
-#V 0002 0XXX1LHH
-#V 0003 10XXXHHH
-#V 0004 1100XHHH
-#V 0005 1101XHHL
-#V 0006 111XXHLH
diff --git a/wcupl/test/wcupl/adr_simple.wpld b/wcupl/test/wcupl/adr_simple.wpld
deleted file mode 100644
index 42489c3..0000000
--- a/wcupl/test/wcupl/adr_simple.wpld
+++ /dev/null
@@ -1,46 +0,0 @@
-HEADER:
-Name     adr_simple ;
-PartNo   01 ;
-Date     24.07.2022 ;
-Revision 02 ;
-Designer wkla ;
-Company  nn ;
-Assembly None ;
-Location  ;
-Device   G16V8 ;
-
-PLD:
-/* *************** INPUT PINS *********************/
-PIN 1   =  A12; 
-PIN 2   =  A13;
-PIN 3   =  A14;
-PIN 4   =  A15;
-PIN 9   =  PHI2;
-
-/* *************** OUTPUT PINS *********************/
-PIN 12   =  CSRAM;
-PIN 13   =  CSHIROM;
-PIN 15   =  CSIO;
-
-/* *************** LOGIC *********************/
-
-/* RAM */
-CSRAM = A15 # !PHI2;
-
-/* 8kb of ROM */
-CSHIROM = !(A15 & A14 & A13);
-
-/* IO */
-CSIO= !(A15 & A14 & !A13 & A12);
-
-SIMULATOR:
-/* Starting Test description */
-ORDER: A15, A14, A13, A12, PHI2, CSRAM, CSHIROM, CSIO; 
-
-VECTORS:
-0 X X X 0 H H H 
-0 X X X 1 L H H 
-1 0 X X X H H H 
-1 1 0 0 X H H H 
-1 1 0 1 X H H L 
-1 1 1 X X H L H 
diff --git a/wcupl/wcupl.code-workspace b/wcupl/wcupl.code-workspace
new file mode 100644
index 0000000..876a149
--- /dev/null
+++ b/wcupl/wcupl.code-workspace
@@ -0,0 +1,8 @@
+{
+	"folders": [
+		{
+			"path": "."
+		}
+	],
+	"settings": {}
+}
\ No newline at end of file