From 8bf404a9b6a8ee4dab16bdd54746051f8698e167 Mon Sep 17 00:00:00 2001
From: valadaptive <valadaptive@protonmail.com>
Date: Tue, 3 Dec 2024 18:49:14 -0500
Subject: [PATCH] Clean up SIMD code

---
 crates/ntscrs/src/f32x4.rs | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/crates/ntscrs/src/f32x4.rs b/crates/ntscrs/src/f32x4.rs
index a71f8bf..f202fc5 100644
--- a/crates/ntscrs/src/f32x4.rs
+++ b/crates/ntscrs/src/f32x4.rs
@@ -32,6 +32,7 @@ pub trait F32x4:
 
     /// Safety:
     /// You must ensure that whatever flavor of SIMD vector you're creating is supported by the current CPU.
+    #[inline(always)]
     unsafe fn load4(src: &[f32; 4]) -> Self {
         Self::load(src.as_slice())
     }
@@ -43,12 +44,6 @@ pub trait F32x4:
     fn store(self, dst: &mut [f32]);
     fn store1(self, dst: &mut f32);
 
-    /// Safety:
-    /// You must ensure that whatever flavor of SIMD vector you're creating is supported by the current CPU.
-    unsafe fn zero() -> Self {
-        Self::set1(0.0)
-    }
-
     /// Safety:
     /// You must ensure that whatever flavor of SIMD vector you're creating is supported by the current CPU.
     unsafe fn set1(src: f32) -> Self;
@@ -86,10 +81,6 @@ pub mod x86_64 {
     pub type AvxF32x4 = IntelF32x4<true>;
     pub type SseF32x4 = IntelF32x4<false>;
 
-    const fn _mm_shuffle(x: i32, y: i32, z: i32, w: i32) -> i32 {
-        (x << 0) | (y << 2) | (z << 4) | (w << 6)
-    }
-
     impl<const USE_AVX2: bool> From<__m128> for IntelF32x4<USE_AVX2> {
         #[inline(always)]
         fn from(src: __m128) -> Self {